drivers/gpu/drm/amd/powerplay/inc/smu74.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24
  25 #ifndef SMU74_H
  26 #define SMU74_H
  27
  28 #pragma pack(push, 1)
  29
  30 #define SMU__DGPU_ONLY
  31
  32 #define SMU__NUM_SCLK_DPM_STATE  8
  33 #define SMU__NUM_MCLK_DPM_LEVELS 4
  34 #define SMU__NUM_LCLK_DPM_LEVELS 8
  35 #define SMU__NUM_PCIE_DPM_LEVELS 8
  36
  37 enum SID_OPTION {
  38         SID_OPTION_HI,
  39         SID_OPTION_LO,
  40         SID_OPTION_COUNT
  41 };
  42
  43 enum Poly3rdOrderCoeff {
  44         LEAKAGE_TEMPERATURE_SCALAR,
  45         LEAKAGE_VOLTAGE_SCALAR,
  46         DYNAMIC_VOLTAGE_SCALAR,
  47         POLY_3RD_ORDER_COUNT
  48 };
  49
  50 struct SMU7_Poly3rdOrder_Data {
  51         int32_t a;
  52         int32_t b;
  53         int32_t c;
  54         int32_t d;
  55         uint8_t a_shift;
  56         uint8_t b_shift;
  57         uint8_t c_shift;
  58         uint8_t x_shift;
  59 };
  60
  61 typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
  62
  63 struct Power_Calculator_Data {
  64         uint16_t NoLoadVoltage;
  65         uint16_t LoadVoltage;
  66         uint16_t Resistance;
  67         uint16_t Temperature;
  68         uint16_t BaseLeakage;
  69         uint16_t LkgTempScalar;
  70         uint16_t LkgVoltScalar;
  71         uint16_t LkgAreaScalar;
  72         uint16_t LkgPower;
  73         uint16_t DynVoltScalar;
  74         uint32_t Cac;
  75         uint32_t DynPower;
  76         uint32_t TotalCurrent;
  77         uint32_t TotalPower;
  78 };
  79
  80 typedef struct Power_Calculator_Data PowerCalculatorData_t;
  81
  82 struct Gc_Cac_Weight_Data {
  83         uint8_t index;
  84         uint32_t value;
  85 };
  86
  87 typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
  88
  89
  90 typedef struct {
  91         uint32_t high;
  92         uint32_t low;
  93 } data_64_t;
  94
  95 typedef struct {
  96         data_64_t high;
  97         data_64_t low;
  98 } data_128_t;
  99
 100 #define SMU7_CONTEXT_ID_SMC        1
 101 #define SMU7_CONTEXT_ID_VBIOS      2
 102
 103 #define SMU74_MAX_LEVELS_VDDC            16
 104 #define SMU74_MAX_LEVELS_VDDGFX          16
 105 #define SMU74_MAX_LEVELS_VDDCI           8
 106 #define SMU74_MAX_LEVELS_MVDD            4
 107
 108 #define SMU_MAX_SMIO_LEVELS              4
 109
 110 #define SMU74_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   /* SCLK + SQ DPM + ULV */
 111 #define SMU74_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   /* MCLK Levels DPM */
 112 #define SMU74_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  /* LCLK Levels */
 113 #define SMU74_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  /* PCIe speed and number of lanes */
 114 #define SMU74_MAX_LEVELS_UVD             8   /* VCLK/DCLK levels for UVD */
 115 #define SMU74_MAX_LEVELS_VCE             8   /* ECLK levels for VCE */
 116 #define SMU74_MAX_LEVELS_ACP             8   /* ACLK levels for ACP */
 117 #define SMU74_MAX_LEVELS_SAMU            8   /* SAMCLK levels for SAMU */
 118 #define SMU74_MAX_ENTRIES_SMIO           32  /* Number of entries in SMIO table */
 119
 120 #define DPM_NO_LIMIT 0
 121 #define DPM_NO_UP 1
 122 #define DPM_GO_DOWN 2
 123 #define DPM_GO_UP 3
 124
 125 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
 126 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
 127
 128 #define GPIO_CLAMP_MODE_VRHOT      1
 129 #define GPIO_CLAMP_MODE_THERM      2
 130 #define GPIO_CLAMP_MODE_DC         4
 131
 132 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
 133 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
 134 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
 135 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
 136 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
 137 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
 138 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
 139 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
 140 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
 141 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
 142 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
 143 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
 144 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
 145 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
 146 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
 147 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
 148 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
 149 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
 150 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
 151 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
 152
 153 /* Virtualization Defines */
 154 #define CG_XDMA_MASK  0x1
 155 #define CG_XDMA_SHIFT 0
 156 #define CG_UVD_MASK   0x2
 157 #define CG_UVD_SHIFT  1
 158 #define CG_VCE_MASK   0x4
 159 #define CG_VCE_SHIFT  2
 160 #define CG_SAMU_MASK  0x8
 161 #define CG_SAMU_SHIFT 3
 162 #define CG_GFX_MASK   0x10
 163 #define CG_GFX_SHIFT  4
 164 #define CG_SDMA_MASK  0x20
 165 #define CG_SDMA_SHIFT 5
 166 #define CG_HDP_MASK   0x40
 167 #define CG_HDP_SHIFT  6
 168 #define CG_MC_MASK    0x80
 169 #define CG_MC_SHIFT   7
 170 #define CG_DRM_MASK   0x100
 171 #define CG_DRM_SHIFT  8
 172 #define CG_ROM_MASK   0x200
 173 #define CG_ROM_SHIFT  9
 174 #define CG_BIF_MASK   0x400
 175 #define CG_BIF_SHIFT  10
 176
 177
 178 #define SMU74_DTE_ITERATIONS 5
 179 #define SMU74_DTE_SOURCES 3
 180 #define SMU74_DTE_SINKS 1
 181 #define SMU74_NUM_CPU_TES 0
 182 #define SMU74_NUM_GPU_TES 1
 183 #define SMU74_NUM_NON_TES 2
 184 #define SMU74_DTE_FAN_SCALAR_MIN 0x100
 185 #define SMU74_DTE_FAN_SCALAR_MAX 0x166
 186 #define SMU74_DTE_FAN_TEMP_MAX 93
 187 #define SMU74_DTE_FAN_TEMP_MIN 83
 188
 189
 190 #if defined SMU__FUSION_ONLY
 191 #define SMU7_DTE_ITERATIONS 5
 192 #define SMU7_DTE_SOURCES 5
 193 #define SMU7_DTE_SINKS 3
 194 #define SMU7_NUM_CPU_TES 2
 195 #define SMU7_NUM_GPU_TES 1
 196 #define SMU7_NUM_NON_TES 2
 197 #endif
 198
 199 struct SMU7_HystController_Data {
 200         uint8_t waterfall_up;
 201         uint8_t waterfall_down;
 202         uint8_t waterfall_limit;
 203         uint8_t spare;
 204         uint16_t release_cnt;
 205         uint16_t release_limit;
 206 };
 207
 208 typedef struct SMU7_HystController_Data SMU7_HystController_Data;
 209
 210 struct SMU74_PIDController {
 211         uint32_t Ki;
 212         int32_t LFWindupUpperLim;
 213         int32_t LFWindupLowerLim;
 214         uint32_t StatePrecision;
 215         uint32_t LfPrecision;
 216         uint32_t LfOffset;
 217         uint32_t MaxState;
 218         uint32_t MaxLfFraction;
 219         uint32_t StateShift;
 220 };
 221
 222 typedef struct SMU74_PIDController SMU74_PIDController;
 223
 224 struct SMU7_LocalDpmScoreboard {
 225         uint32_t PercentageBusy;
 226
 227         int32_t  PIDError;
 228         int32_t  PIDIntegral;
 229         int32_t  PIDOutput;
 230
 231         uint32_t SigmaDeltaAccum;
 232         uint32_t SigmaDeltaOutput;
 233         uint32_t SigmaDeltaLevel;
 234
 235         uint32_t UtilizationSetpoint;
 236
 237         uint8_t  TdpClampMode;
 238         uint8_t  TdcClampMode;
 239         uint8_t  ThermClampMode;
 240         uint8_t  VoltageBusy;
 241
 242         int8_t   CurrLevel;
 243         int8_t   TargLevel;
 244         uint8_t  LevelChangeInProgress;
 245         uint8_t  UpHyst;
 246
 247         uint8_t  DownHyst;
 248         uint8_t  VoltageDownHyst;
 249         uint8_t  DpmEnable;
 250         uint8_t  DpmRunning;
 251
 252         uint8_t  DpmForce;
 253         uint8_t  DpmForceLevel;
 254         uint8_t  DisplayWatermark;
 255         uint8_t  McArbIndex;
 256
 257         uint32_t MinimumPerfSclk;
 258
 259         uint8_t  AcpiReq;
 260         uint8_t  AcpiAck;
 261         uint8_t  GfxClkSlow;
 262         uint8_t  GpioClampMode;
 263
 264         uint8_t  spare2;
 265         uint8_t  EnabledLevelsChange;
 266         uint8_t  DteClampMode;
 267         uint8_t  FpsClampMode;
 268
 269         uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_GRAPHICS];
 270         uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_GRAPHICS];
 271
 272         void     (*TargetStateCalculator)(uint8_t);
 273         void     (*SavedTargetStateCalculator)(uint8_t);
 274
 275         uint16_t AutoDpmInterval;
 276         uint16_t AutoDpmRange;
 277
 278         uint8_t  FpsEnabled;
 279         uint8_t  MaxPerfLevel;
 280         uint8_t  AllowLowClkInterruptToHost;
 281         uint8_t  FpsRunning;
 282
 283         uint32_t MaxAllowedFrequency;
 284
 285         uint32_t FilteredSclkFrequency;
 286         uint32_t LastSclkFrequency;
 287         uint32_t FilteredSclkFrequencyCnt;
 288
 289         uint8_t MinPerfLevel;
 290         uint8_t padding[3];
 291
 292         uint16_t FpsAlpha;
 293         uint16_t DeltaTime;
 294         uint32_t CurrentFps;
 295         uint32_t FilteredFps;
 296         uint32_t FrameCount;
 297         uint32_t FrameCountLast;
 298         uint16_t FpsTargetScalar;
 299         uint16_t FpsWaterfallLimitScalar;
 300         uint16_t FpsAlphaScalar;
 301         uint16_t spare8;
 302         SMU7_HystController_Data HystControllerData;
 303 };
 304
 305 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
 306
 307 #define SMU7_MAX_VOLTAGE_CLIENTS 12
 308
 309 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
 310
 311 #define VDDC_MASK    0x00007FFF
 312 #define VDDC_SHIFT   0
 313 #define VDDCI_MASK   0x3FFF8000
 314 #define VDDCI_SHIFT  15
 315 #define PHASES_MASK  0xC0000000
 316 #define PHASES_SHIFT 30
 317
 318 typedef uint32_t SMU_VoltageLevel;
 319
 320 struct SMU7_VoltageScoreboard {
 321
 322         SMU_VoltageLevel TargetVoltage;
 323         uint16_t MaxVid;
 324         uint8_t  HighestVidOffset;
 325         uint8_t  CurrentVidOffset;
 326
 327         uint16_t CurrentVddc;
 328         uint16_t CurrentVddci;
 329
 330
 331         uint8_t  ControllerBusy;
 332         uint8_t  CurrentVid;
 333         uint8_t  CurrentVddciVid;
 334         uint8_t  padding;
 335
 336         SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
 337         SMU_VoltageLevel TargetVoltageState;
 338         uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
 339
 340         uint8_t  padding2;
 341         uint8_t  padding3;
 342         uint8_t  ControllerEnable;
 343         uint8_t  ControllerRunning;
 344         uint16_t CurrentStdVoltageHiSidd;
 345         uint16_t CurrentStdVoltageLoSidd;
 346         uint8_t  OverrideVoltage;
 347         uint8_t  padding4;
 348         uint8_t  padding5;
 349         uint8_t  CurrentPhases;
 350
 351         VoltageChangeHandler_t ChangeVddc;
 352
 353         VoltageChangeHandler_t ChangeVddci;
 354         VoltageChangeHandler_t ChangePhase;
 355         VoltageChangeHandler_t ChangeMvdd;
 356
 357         VoltageChangeHandler_t functionLinks[6];
 358
 359         uint16_t *VddcFollower1;
 360
 361         int16_t  Driver_OD_RequestedVidOffset1;
 362         int16_t  Driver_OD_RequestedVidOffset2;
 363 };
 364
 365 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
 366
 367 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
 368
 369 struct SMU7_PCIeLinkSpeedScoreboard {
 370         uint8_t     DpmEnable;
 371         uint8_t     DpmRunning;
 372         uint8_t     DpmForce;
 373         uint8_t     DpmForceLevel;
 374
 375         uint8_t     CurrentLinkSpeed;
 376         uint8_t     EnabledLevelsChange;
 377         uint16_t    AutoDpmInterval;
 378
 379         uint16_t    AutoDpmRange;
 380         uint16_t    AutoDpmCount;
 381
 382         uint8_t     DpmMode;
 383         uint8_t     AcpiReq;
 384         uint8_t     AcpiAck;
 385         uint8_t     CurrentLinkLevel;
 386
 387 };
 388
 389 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
 390
 391 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
 392 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
 393
 394 #define SMU7_SCALE_I  7
 395 #define SMU7_SCALE_R 12
 396
 397 struct SMU7_PowerScoreboard {
 398         PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
 399
 400         uint32_t TotalGpuPower;
 401         uint32_t TdcCurrent;
 402
 403         uint16_t   VddciTotalPower;
 404         uint16_t   sparesasfsdfd;
 405         uint16_t   Vddr1Power;
 406         uint16_t   RocPower;
 407
 408         uint16_t   CalcMeasPowerBlend;
 409         uint8_t    SidOptionPower;
 410         uint8_t    SidOptionCurrent;
 411
 412         uint32_t   WinTime;
 413
 414         uint16_t Telemetry_1_slope;
 415         uint16_t Telemetry_2_slope;
 416         int32_t Telemetry_1_offset;
 417         int32_t Telemetry_2_offset;
 418
 419         uint32_t VddcCurrentTelemetry;
 420         uint32_t VddGfxCurrentTelemetry;
 421         uint32_t VddcPowerTelemetry;
 422         uint32_t VddGfxPowerTelemetry;
 423         uint32_t VddciPowerTelemetry;
 424
 425         uint32_t VddcPower;
 426         uint32_t VddGfxPower;
 427         uint32_t VddciPower;
 428
 429         uint32_t TelemetryCurrent[2];
 430         uint32_t TelemetryVoltage[2];
 431         uint32_t TelemetryPower[2];
 432 };
 433
 434 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
 435
 436 struct SMU7_ThermalScoreboard {
 437         int16_t  GpuLimit;
 438         int16_t  GpuHyst;
 439         uint16_t CurrGnbTemp;
 440         uint16_t FilteredGnbTemp;
 441
 442         uint8_t  ControllerEnable;
 443         uint8_t  ControllerRunning;
 444         uint8_t  AutoTmonCalInterval;
 445         uint8_t  AutoTmonCalEnable;
 446
 447         uint8_t  ThermalDpmEnabled;
 448         uint8_t  SclkEnabledMask;
 449         uint8_t  spare[2];
 450         int32_t  temperature_gradient;
 451
 452         SMU7_HystController_Data HystControllerData;
 453         int32_t  WeightedSensorTemperature;
 454         uint16_t TemperatureLimit[SMU74_MAX_LEVELS_GRAPHICS];
 455         uint32_t Alpha;
 456 };
 457
 458 typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
 459
 460 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
 461 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
 462 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
 463 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
 464 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
 465 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
 466 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
 467 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
 468 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
 469
 470 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
 471 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
 472 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
 473 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
 474 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
 475 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
 476
 477 /* All 'soft registers' should be uint32_t. */
 478 struct SMU74_SoftRegisters {
 479         uint32_t        RefClockFrequency;
 480         uint32_t        PmTimerPeriod;
 481         uint32_t        FeatureEnables;
 482
 483         uint32_t        PreVBlankGap;
 484         uint32_t        VBlankTimeout;
 485         uint32_t        TrainTimeGap;
 486
 487         uint32_t        MvddSwitchTime;
 488         uint32_t        LongestAcpiTrainTime;
 489         uint32_t        AcpiDelay;
 490         uint32_t        G5TrainTime;
 491         uint32_t        DelayMpllPwron;
 492         uint32_t        VoltageChangeTimeout;
 493
 494         uint32_t        HandshakeDisables;
 495
 496         uint8_t         DisplayPhy1Config;
 497         uint8_t         DisplayPhy2Config;
 498         uint8_t         DisplayPhy3Config;
 499         uint8_t         DisplayPhy4Config;
 500
 501         uint8_t         DisplayPhy5Config;
 502         uint8_t         DisplayPhy6Config;
 503         uint8_t         DisplayPhy7Config;
 504         uint8_t         DisplayPhy8Config;
 505
 506         uint32_t        AverageGraphicsActivity;
 507         uint32_t        AverageMemoryActivity;
 508         uint32_t        AverageGioActivity;
 509
 510         uint8_t         SClkDpmEnabledLevels;
 511         uint8_t         MClkDpmEnabledLevels;
 512         uint8_t         LClkDpmEnabledLevels;
 513         uint8_t         PCIeDpmEnabledLevels;
 514
 515         uint8_t         UVDDpmEnabledLevels;
 516         uint8_t         SAMUDpmEnabledLevels;
 517         uint8_t         ACPDpmEnabledLevels;
 518         uint8_t         VCEDpmEnabledLevels;
 519
 520         uint32_t        DRAM_LOG_ADDR_H;
 521         uint32_t        DRAM_LOG_ADDR_L;
 522         uint32_t        DRAM_LOG_PHY_ADDR_H;
 523         uint32_t        DRAM_LOG_PHY_ADDR_L;
 524         uint32_t        DRAM_LOG_BUFF_SIZE;
 525         uint32_t        UlvEnterCount;
 526         uint32_t        UlvTime;
 527         uint32_t        UcodeLoadStatus;
 528         uint32_t        AllowMvddSwitch;
 529         uint8_t         Activity_Weight;
 530         uint8_t         Reserved8[3];
 531 };
 532
 533 typedef struct SMU74_SoftRegisters SMU74_SoftRegisters;
 534
 535 struct SMU74_Firmware_Header {
 536         uint32_t Digest[5];
 537         uint32_t Version;
 538         uint32_t HeaderSize;
 539         uint32_t Flags;
 540         uint32_t EntryPoint;
 541         uint32_t CodeSize;
 542         uint32_t ImageSize;
 543
 544         uint32_t Rtos;
 545         uint32_t SoftRegisters;
 546         uint32_t DpmTable;
 547         uint32_t FanTable;
 548         uint32_t CacConfigTable;
 549         uint32_t CacStatusTable;
 550
 551
 552         uint32_t mcRegisterTable;
 553
 554
 555         uint32_t mcArbDramTimingTable;
 556
 557
 558
 559
 560         uint32_t PmFuseTable;
 561         uint32_t Globals;
 562         uint32_t ClockStretcherTable;
 563         uint32_t VftTable;
 564         uint32_t Reserved[21];
 565         uint32_t Signature;
 566 };
 567
 568 typedef struct SMU74_Firmware_Header SMU74_Firmware_Header;
 569
 570 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
 571
 572 enum  DisplayConfig {
 573         PowerDown = 1,
 574         DP54x4,
 575         DP54x2,
 576         DP54x1,
 577         DP27x4,
 578         DP27x2,
 579         DP27x1,
 580         HDMI297,
 581         HDMI162,
 582         LVDS,
 583         DP324x4,
 584         DP324x2,
 585         DP324x1
 586 };
 587
 588
 589 #define MC_BLOCK_COUNT 1
 590 #define CPL_BLOCK_COUNT 5
 591 #define SE_BLOCK_COUNT 15
 592 #define GC_BLOCK_COUNT 24
 593
 594 struct SMU7_Local_Cac {
 595         uint8_t BlockId;
 596         uint8_t SignalId;
 597         uint8_t Threshold;
 598         uint8_t Padding;
 599 };
 600
 601 typedef struct SMU7_Local_Cac SMU7_Local_Cac;
 602
 603 struct SMU7_Local_Cac_Table {
 604
 605         SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
 606         SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
 607         SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
 608         SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
 609 };
 610
 611 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
 612
 613 #pragma pack(pop)
 614
 615 /* Description of Clock Gating bitmask for Tonga:
 616  * System Clock Gating
 617  */
 618 #define CG_SYS_BITMASK_FIRST_BIT      0  /* First bit of Sys CG bitmask */
 619 #define CG_SYS_BITMASK_LAST_BIT       9  /* Last bit of Sys CG bitmask */
 620 #define CG_SYS_BIF_MGLS_SHIFT         0
 621 #define CG_SYS_ROM_SHIFT              1
 622 #define CG_SYS_MC_MGCG_SHIFT          2
 623 #define CG_SYS_MC_MGLS_SHIFT          3
 624 #define CG_SYS_SDMA_MGCG_SHIFT        4
 625 #define CG_SYS_SDMA_MGLS_SHIFT        5
 626 #define CG_SYS_DRM_MGCG_SHIFT         6
 627 #define CG_SYS_HDP_MGCG_SHIFT         7
 628 #define CG_SYS_HDP_MGLS_SHIFT         8
 629 #define CG_SYS_DRM_MGLS_SHIFT         9
 630 #define CG_SYS_BIF_MGCG_SHIFT         10
 631
 632 #define CG_SYS_BIF_MGLS_MASK          0x1
 633 #define CG_SYS_ROM_MASK               0x2
 634 #define CG_SYS_MC_MGCG_MASK           0x4
 635 #define CG_SYS_MC_MGLS_MASK           0x8
 636 #define CG_SYS_SDMA_MGCG_MASK         0x10
 637 #define CG_SYS_SDMA_MGLS_MASK         0x20
 638 #define CG_SYS_DRM_MGCG_MASK          0x40
 639 #define CG_SYS_HDP_MGCG_MASK          0x80
 640 #define CG_SYS_HDP_MGLS_MASK          0x100
 641 #define CG_SYS_DRM_MGLS_MASK          0x200
 642 #define CG_SYS_BIF_MGCG_MASK          0x400
 643
 644 /* Graphics Clock Gating */
 645 #define CG_GFX_BITMASK_FIRST_BIT      16 /* First bit of Gfx CG bitmask */
 646 #define CG_GFX_BITMASK_LAST_BIT       24 /* Last bit of Gfx CG bitmask */
 647
 648 #define CG_GFX_CGCG_SHIFT             16
 649 #define CG_GFX_CGLS_SHIFT             17
 650 #define CG_CPF_MGCG_SHIFT             18
 651 #define CG_RLC_MGCG_SHIFT             19
 652 #define CG_GFX_OTHERS_MGCG_SHIFT      20
 653 #define CG_GFX_3DCG_SHIFT             21
 654 #define CG_GFX_3DLS_SHIFT             22
 655 #define CG_GFX_RLC_LS_SHIFT           23
 656 #define CG_GFX_CP_LS_SHIFT            24
 657
 658 #define CG_GFX_CGCG_MASK              0x00010000
 659 #define CG_GFX_CGLS_MASK              0x00020000
 660 #define CG_CPF_MGCG_MASK              0x00040000
 661 #define CG_RLC_MGCG_MASK              0x00080000
 662 #define CG_GFX_OTHERS_MGCG_MASK       0x00100000
 663 #define CG_GFX_3DCG_MASK              0x00200000
 664 #define CG_GFX_3DLS_MASK              0x00400000
 665 #define CG_GFX_RLC_LS_MASK            0x00800000
 666 #define CG_GFX_CP_LS_MASK             0x01000000
 667
 668
 669 /* Voltage Regulator Configuration
 670 VR Config info is contained in dpmTable.VRConfig */
 671
 672 #define VRCONF_VDDC_MASK         0x000000FF
 673 #define VRCONF_VDDC_SHIFT        0
 674 #define VRCONF_VDDGFX_MASK       0x0000FF00
 675 #define VRCONF_VDDGFX_SHIFT      8
 676 #define VRCONF_VDDCI_MASK        0x00FF0000
 677 #define VRCONF_VDDCI_SHIFT       16
 678 #define VRCONF_MVDD_MASK         0xFF000000
 679 #define VRCONF_MVDD_SHIFT        24
 680
 681 #define VR_MERGED_WITH_VDDC      0
 682 #define VR_SVI2_PLANE_1          1
 683 #define VR_SVI2_PLANE_2          2
 684 #define VR_SMIO_PATTERN_1        3
 685 #define VR_SMIO_PATTERN_2        4
 686 #define VR_STATIC_VOLTAGE        5
 687
 688 /* Clock Stretcher Configuration */
 689
 690 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4
 691 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4
 692
 693 /* The 'settings' field is subdivided in the following way: */
 694 #define CLOCK_STRETCHER_SETTING_DDT_MASK             0x01
 695 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT            0x0
 696 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK  0x1E
 697 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
 698 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK          0x80
 699 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT         0x7
 700
 701 struct SMU_ClockStretcherDataTableEntry {
 702         uint8_t minVID;
 703         uint8_t maxVID;
 704
 705
 706         uint16_t setting;
 707 };
 708 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
 709
 710 struct SMU_ClockStretcherDataTable {
 711         SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
 712 };
 713 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
 714
 715 struct SMU_CKS_LOOKUPTableEntry {
 716         uint16_t minFreq;
 717         uint16_t maxFreq;
 718
 719         uint8_t setting;
 720         uint8_t padding[3];
 721 };
 722 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
 723
 724 struct SMU_CKS_LOOKUPTable {
 725         SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
 726 };
 727 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
 728
 729 struct AgmAvfsData_t {
 730         uint16_t avgPsmCount[28];
 731         uint16_t minPsmCount[28];
 732 };
 733
 734 typedef struct AgmAvfsData_t AgmAvfsData_t;
 735
 736 enum VFT_COLUMNS {
 737         SCLK0,
 738         SCLK1,
 739         SCLK2,
 740         SCLK3,
 741         SCLK4,
 742         SCLK5,
 743         SCLK6,
 744         SCLK7,
 745
 746         NUM_VFT_COLUMNS
 747 };
 748
 749 #define VFT_TABLE_DEFINED
 750
 751 #define TEMP_RANGE_MAXSTEPS 12
 752
 753 struct VFT_CELL_t {
 754         uint16_t Voltage;
 755 };
 756
 757 typedef struct VFT_CELL_t VFT_CELL_t;
 758
 759 struct VFT_TABLE_t {
 760         VFT_CELL_t    Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
 761         uint16_t      AvfsGbv[NUM_VFT_COLUMNS];
 762         uint16_t      BtcGbv[NUM_VFT_COLUMNS];
 763         uint16_t      Temperature[TEMP_RANGE_MAXSTEPS];
 764
 765         uint8_t       NumTemperatureSteps;
 766         uint8_t       padding[3];
 767 };
 768
 769 typedef struct VFT_TABLE_t VFT_TABLE_t;
 770
 771
 772 #endif
 773
 774