drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "smumgr.h"
  25 #include "smu73.h"
  26 #include "smu_ucode_xfer_vi.h"
  27 #include "fiji_smumgr.h"
  28 #include "fiji_ppsmc.h"
  29 #include "smu73_discrete.h"
  30 #include "ppatomctrl.h"
  31 #include "smu/smu_7_1_3_d.h"
  32 #include "smu/smu_7_1_3_sh_mask.h"
  33 #include "gmc/gmc_8_1_d.h"
  34 #include "gmc/gmc_8_1_sh_mask.h"
  35 #include "oss/oss_3_0_d.h"
  36 #include "gca/gfx_8_0_d.h"
  37 #include "bif/bif_5_0_d.h"
  38 #include "bif/bif_5_0_sh_mask.h"
  39 #include "pp_debug.h"
  40 #include "fiji_pwrvirus.h"
  41 #include "fiji_smc.h"
  42
  43 #define AVFS_EN_MSB                                        1568
  44 #define AVFS_EN_LSB                                        1568
  45
  46 #define FIJI_SMC_SIZE 0x20000
  47
  48 static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
  49                 /*  Min        Sclk       pcie     DeepSleep Activity  CgSpll      CgSpll    spllSpread  SpllSpread   CcPwr  CcPwr  Sclk   Display     Enabled     Enabled                       Voltage    Power */
  50                 /* Voltage,  Frequency,  DpmLevel,  DivId,    Level,  FuncCntl3,  FuncCntl4,  Spectrum,   Spectrum2,  DynRm, DynRm1  Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
  51                 { 0x3c0fd047, 0x30750000,   0x00,     0x03,   0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000,   0,      0,   0x16,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  52                 { 0xa00fd047, 0x409c0000,   0x01,     0x04,   0x1e00, 0x00800510, 0x87020000, 0x21680000, 0x11000000,   0,      0,   0x16,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  53                 { 0x0410d047, 0x50c30000,   0x01,     0x00,   0x1e00, 0x00600410, 0x87020000, 0x21680000, 0x0d000000,   0,      0,   0x0e,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  54                 { 0x6810d047, 0x60ea0000,   0x01,     0x00,   0x1e00, 0x00800410, 0x87020000, 0x21680000, 0x0e000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  55                 { 0xcc10d047, 0xe8fd0000,   0x01,     0x00,   0x1e00, 0x00e00410, 0x87020000, 0x21680000, 0x0f000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  56                 { 0x3011d047, 0x70110100,   0x01,     0x00,   0x1e00, 0x00400510, 0x87020000, 0x21680000, 0x10000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  57                 { 0x9411d047, 0xf8240100,   0x01,     0x00,   0x1e00, 0x00a00510, 0x87020000, 0x21680000, 0x11000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
  58                 { 0xf811d047, 0x80380100,   0x01,     0x00,   0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000,   0,      0,   0x0c,   0x01,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 }
  59 };
  60
  61 static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
  62 {
  63         int result = 0;
  64
  65         /* Wait for smc boot up */
  66         /* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
  67                 RCU_UC_EVENTS, boot_seq_done, 0); */
  68
  69         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
  70                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
  71
  72         result = smu7_upload_smu_firmware_image(smumgr);
  73         if (result)
  74                 return result;
  75
  76         /* Clear status */
  77         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
  78                         ixSMU_STATUS, 0);
  79
  80         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
  81                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
  82
  83         /* De-assert reset */
  84         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
  85                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
  86
  87         /* Wait for ROM firmware to initialize interrupt hendler */
  88         /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
  89                         SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
  90
  91         /* Set SMU Auto Start */
  92         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
  93                         SMU_INPUT_DATA, AUTO_START, 1);
  94
  95         /* Clear firmware interrupt enable flag */
  96         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
  97                         ixFIRMWARE_FLAGS, 0);
  98
  99         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS,
 100                         INTERRUPTS_ENABLED, 1);
 101
 102         cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
 103         cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
 104         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 105
 106         /* Wait for done bit to be set */
 107         SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
 108                         SMU_STATUS, SMU_DONE, 0);
 109
 110         /* Check pass/failed indicator */
 111         if (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 112                         SMU_STATUS, SMU_PASS) != 1) {
 113                 PP_ASSERT_WITH_CODE(false,
 114                                 "SMU Firmware start failed!", return -1);
 115         }
 116
 117         /* Wait for firmware to initialize */
 118         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
 119                         FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 120
 121         return result;
 122 }
 123
 124 static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
 125 {
 126         int result = 0;
 127
 128         /* wait for smc boot up */
 129         SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
 130                         RCU_UC_EVENTS, boot_seq_done, 0);
 131
 132         /* Clear firmware interrupt enable flag */
 133         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
 134                         ixFIRMWARE_FLAGS, 0);
 135
 136         /* Assert reset */
 137         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 138                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 139
 140         result = smu7_upload_smu_firmware_image(smumgr);
 141         if (result)
 142                 return result;
 143
 144         /* Set smc instruct start point at 0x0 */
 145         smu7_program_jump_on_start(smumgr);
 146
 147         /* Enable clock */
 148         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 149                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 150
 151         /* De-assert reset */
 152         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 153                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 154
 155         /* Wait for firmware to initialize */
 156         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
 157                         FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 158
 159         return result;
 160 }
 161
 162 int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
 163 {
 164         int i, result = -1;
 165         uint32_t reg, data;
 166         const PWR_Command_Table *virus = PwrVirusTable;
 167         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 168
 169         priv->avfs.AvfsBtcStatus = AVFS_LOAD_VIRUS;
 170         for (i = 0; (i < PWR_VIRUS_TABLE_SIZE); i++) {
 171                 switch (virus->command) {
 172                 case PwrCmdWrite:
 173                         reg  = virus->reg;
 174                         data = virus->data;
 175                         cgs_write_register(smumgr->device, reg, data);
 176                         break;
 177                 case PwrCmdEnd:
 178                         priv->avfs.AvfsBtcStatus = AVFS_BTC_VIRUS_LOADED;
 179                         result = 0;
 180                         break;
 181                 default:
 182                         printk(KERN_ERR "Table Exit with Invalid Command!");
 183                         priv->avfs.AvfsBtcStatus = AVFS_BTC_VIRUS_FAIL;
 184                         result = -1;
 185                         break;
 186                 }
 187                 virus++;
 188         }
 189         return result;
 190 }
 191
 192 static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
 193 {
 194         int result = 0;
 195         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 196
 197         priv->avfs.AvfsBtcStatus = AVFS_BTC_STARTED;
 198         if (priv->avfs.AvfsBtcParam) {
 199                 if (!smum_send_msg_to_smc_with_parameter(smumgr,
 200                                 PPSMC_MSG_PerformBtc, priv->avfs.AvfsBtcParam)) {
 201                         if (!smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs)) {
 202                                 priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_UNSAVED;
 203                                 result = 0;
 204                         } else {
 205                                 printk(KERN_ERR "[AVFS][fiji_start_avfs_btc] Attempt"
 206                                                 " to Enable AVFS Failed!");
 207                                 smum_send_msg_to_smc(smumgr, PPSMC_MSG_DisableAvfs);
 208                                 result = -1;
 209                         }
 210                 } else {
 211                         printk(KERN_ERR "[AVFS][fiji_start_avfs_btc] "
 212                                         "PerformBTC SMU msg failed");
 213                         result = -1;
 214                 }
 215         }
 216         /* Soft-Reset to reset the engine before loading uCode */
 217          /* halt */
 218         cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
 219         /* reset everything */
 220         cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
 221         /* clear reset */
 222         cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
 223
 224         return result;
 225 }
 226
 227 int fiji_setup_pm_fuse_for_avfs(struct pp_smumgr *smumgr)
 228 {
 229         int result = 0;
 230         uint32_t table_start;
 231         uint32_t charz_freq_addr, inversion_voltage_addr, charz_freq;
 232         uint16_t inversion_voltage;
 233
 234         charz_freq = 0x30750000; /* In 10KHz units 0x00007530 Actual value */
 235         inversion_voltage = 0x1A04; /* mV Q14.2 0x41A Actual value */
 236
 237         PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
 238                         SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU73_Firmware_Header,
 239                                         PmFuseTable), &table_start, 0x40000),
 240                         "[AVFS][Fiji_SetupGfxLvlStruct] SMU could not communicate "
 241                         "starting address of PmFuse structure",
 242                         return -1;);
 243
 244         charz_freq_addr = table_start +
 245                         offsetof(struct SMU73_Discrete_PmFuses, PsmCharzFreq);
 246         inversion_voltage_addr = table_start +
 247                         offsetof(struct SMU73_Discrete_PmFuses, InversionVoltage);
 248
 249         result = smu7_copy_bytes_to_smc(smumgr, charz_freq_addr,
 250                         (uint8_t *)(&charz_freq), sizeof(charz_freq), 0x40000);
 251         PP_ASSERT_WITH_CODE(0 == result,
 252                         "[AVFS][fiji_setup_pm_fuse_for_avfs] charz_freq could not "
 253                         "be populated.", return -1;);
 254
 255         result = smu7_copy_bytes_to_smc(smumgr, inversion_voltage_addr,
 256                         (uint8_t *)(&inversion_voltage), sizeof(inversion_voltage), 0x40000);
 257         PP_ASSERT_WITH_CODE(0 == result, "[AVFS][fiji_setup_pm_fuse_for_avfs] "
 258                         "charz_freq could not be populated.", return -1;);
 259
 260         return result;
 261 }
 262
 263 int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
 264 {
 265         int32_t vr_config;
 266         uint32_t table_start;
 267         uint32_t level_addr, vr_config_addr;
 268         uint32_t level_size = sizeof(avfs_graphics_level);
 269
 270         PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
 271                         SMU7_FIRMWARE_HEADER_LOCATION +
 272                         offsetof(SMU73_Firmware_Header, DpmTable),
 273                         &table_start, 0x40000),
 274                         "[AVFS][Fiji_SetupGfxLvlStruct] SMU could not "
 275                         "communicate starting address of DPM table",
 276                         return -1;);
 277
 278         /* Default value for vr_config =
 279          * VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
 280         vr_config = 0x01000500;   /* Real value:0x50001 */
 281
 282         vr_config_addr = table_start +
 283                         offsetof(SMU73_Discrete_DpmTable, VRConfig);
 284
 285         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_addr,
 286                         (uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
 287                         "[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
 288                         "vr_config value over to SMC",
 289                         return -1;);
 290
 291         level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
 292
 293         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, level_addr,
 294                         (uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
 295                         "[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
 296                         return -1;);
 297
 298         return 0;
 299 }
 300
 301 /* Work in Progress */
 302 int fiji_restore_vft_table(struct pp_smumgr *smumgr)
 303 {
 304         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 305
 306         if (AVFS_BTC_COMPLETED_SAVED == priv->avfs.AvfsBtcStatus) {
 307                 priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_RESTORED;
 308                 return 0;
 309         } else
 310                 return -EINVAL;
 311 }
 312
 313 /* Work in Progress */
 314 int fiji_save_vft_table(struct pp_smumgr *smumgr)
 315 {
 316         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 317
 318         if (AVFS_BTC_COMPLETED_SAVED == priv->avfs.AvfsBtcStatus) {
 319                 priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_RESTORED;
 320                 return 0;
 321         } else
 322                 return -EINVAL;
 323 }
 324
 325 int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
 326 {
 327         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 328
 329         switch (priv->avfs.AvfsBtcStatus) {
 330         case AVFS_BTC_COMPLETED_SAVED: /*S3 State - Pre SMU Start */
 331                 priv->avfs.AvfsBtcStatus = AVFS_BTC_RESTOREVFT_FAILED;
 332                 PP_ASSERT_WITH_CODE(0 == fiji_restore_vft_table(smumgr),
 333                                 "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics "
 334                                 "Level table over to SMU",
 335                                 return -1;);
 336                 priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_RESTORED;
 337                 break;
 338         case AVFS_BTC_COMPLETED_RESTORED: /*S3 State - Post SMU Start*/
 339                 priv->avfs.AvfsBtcStatus = AVFS_BTC_SMUMSG_ERROR;
 340                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(smumgr,
 341                                 0x666),
 342                                 "[AVFS][fiji_avfs_event_mgr] SMU did not respond "
 343                                 "correctly to VftTableIsValid Msg",
 344                                 return -1;);
 345                 priv->avfs.AvfsBtcStatus = AVFS_BTC_SMUMSG_ERROR;
 346                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(smumgr,
 347                                 PPSMC_MSG_EnableAvfs),
 348                                 "[AVFS][fiji_avfs_event_mgr] SMU did not respond "
 349                                 "correctly to EnableAvfs Message Msg",
 350                                 return -1;);
 351                 priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_SAVED;
 352                 break;
 353         case AVFS_BTC_BOOT: /*Cold Boot State - Post SMU Start*/
 354                 if (!smu_started)
 355                         break;
 356                 priv->avfs.AvfsBtcStatus = AVFS_BTC_FAILED;
 357                 PP_ASSERT_WITH_CODE(0 == fiji_setup_pm_fuse_for_avfs(smumgr),
 358                                 "[AVFS][fiji_avfs_event_mgr] Failure at "
 359                                 "fiji_setup_pm_fuse_for_avfs",
 360                                 return -1;);
 361                 priv->avfs.AvfsBtcStatus = AVFS_BTC_DPMTABLESETUP_FAILED;
 362                 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(smumgr),
 363                                 "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
 364                                 " table over to SMU",
 365                                 return -1;);
 366                 priv->avfs.AvfsBtcStatus = AVFS_BTC_VIRUS_FAIL;
 367                 PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(smumgr),
 368                                 "[AVFS][fiji_avfs_event_mgr] Could not setup "
 369                                 "Pwr Virus for AVFS ",
 370                                 return -1;);
 371                 priv->avfs.AvfsBtcStatus = AVFS_BTC_FAILED;
 372                 PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(smumgr),
 373                                 "[AVFS][fiji_avfs_event_mgr] Failure at "
 374                                 "fiji_start_avfs_btc. AVFS Disabled",
 375                                 return -1;);
 376                 priv->avfs.AvfsBtcStatus = AVFS_BTC_SAVEVFT_FAILED;
 377                 PP_ASSERT_WITH_CODE(0 == fiji_save_vft_table(smumgr),
 378                                 "[AVFS][fiji_avfs_event_mgr] Could not save VFT Table",
 379                                 return -1;);
 380                 priv->avfs.AvfsBtcStatus = AVFS_BTC_COMPLETED_SAVED;
 381                 break;
 382         case AVFS_BTC_DISABLED: /* Do nothing */
 383                 break;
 384         case AVFS_BTC_NOTSUPPORTED: /* Do nothing */
 385                 break;
 386         default:
 387                 printk(KERN_ERR "[AVFS] Something is broken. See log!");
 388                 break;
 389         }
 390         return 0;
 391 }
 392
 393 static int fiji_start_smu(struct pp_smumgr *smumgr)
 394 {
 395         int result = 0;
 396         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 397
 398         /* Only start SMC if SMC RAM is not running */
 399         if (!smu7_is_smc_ram_running(smumgr)) {
 400                 fiji_avfs_event_mgr(smumgr, false);
 401
 402                 /* Check if SMU is running in protected mode */
 403                 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
 404                                 CGS_IND_REG__SMC,
 405                                 SMU_FIRMWARE, SMU_MODE)) {
 406                         result = fiji_start_smu_in_non_protection_mode(smumgr);
 407                         if (result)
 408                                 return result;
 409                 } else {
 410                         result = fiji_start_smu_in_protection_mode(smumgr);
 411                         if (result)
 412                                 return result;
 413                 }
 414                 fiji_avfs_event_mgr(smumgr, true);
 415         }
 416
 417         /* To initialize all clock gating before RLC loaded and running.*/
 418         cgs_set_clockgating_state(smumgr->device,
 419                         AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
 420         cgs_set_clockgating_state(smumgr->device,
 421                         AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
 422         cgs_set_clockgating_state(smumgr->device,
 423                         AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
 424         cgs_set_clockgating_state(smumgr->device,
 425                         AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
 426
 427         /* Setup SoftRegsStart here for register lookup in case
 428          * DummyBackEnd is used and ProcessFirmwareHeader is not executed
 429          */
 430         smu7_read_smc_sram_dword(smumgr,
 431                         SMU7_FIRMWARE_HEADER_LOCATION +
 432                         offsetof(SMU73_Firmware_Header, SoftRegisters),
 433                         &(priv->smu7_data.soft_regs_start), 0x40000);
 434
 435         result = smu7_request_smu_load_fw(smumgr);
 436
 437         return result;
 438 }
 439
 440 static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
 441 {
 442
 443         uint32_t efuse = 0;
 444         uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
 445
 446         if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
 447                         mask, &efuse)) {
 448                 if (efuse)
 449                         return true;
 450         }
 451         return false;
 452 }
 453
 454 /**
 455 * Write a 32bit value to the SMC SRAM space.
 456 * ALL PARAMETERS ARE IN HOST BYTE ORDER.
 457 * @param    smumgr  the address of the powerplay hardware manager.
 458 * @param    smc_addr the address in the SMC RAM to access.
 459 * @param    value to write to the SMC SRAM.
 460 */
 461 static int fiji_smu_init(struct pp_smumgr *smumgr)
 462 {
 463         struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
 464         int i;
 465
 466         if (smu7_init(smumgr))
 467                 return -EINVAL;
 468
 469         priv->avfs.AvfsBtcStatus = AVFS_BTC_BOOT;
 470         if (fiji_is_hw_avfs_present(smumgr))
 471                 /* AVFS Parameter
 472                  * 0 - BTC DC disabled, BTC AC disabled
 473                  * 1 - BTC DC enabled,  BTC AC disabled
 474                  * 2 - BTC DC disabled, BTC AC enabled
 475                  * 3 - BTC DC enabled,  BTC AC enabled
 476                  * Default is 0 - BTC DC disabled, BTC AC disabled
 477                  */
 478                 priv->avfs.AvfsBtcParam = 0;
 479         else
 480                 priv->avfs.AvfsBtcStatus = AVFS_BTC_NOTSUPPORTED;
 481
 482         for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
 483                 priv->activity_target[i] = 30;
 484
 485         return 0;
 486 }
 487
 488
 489 static const struct pp_smumgr_func fiji_smu_funcs = {
 490         .smu_init = &fiji_smu_init,
 491         .smu_fini = &smu7_smu_fini,
 492         .start_smu = &fiji_start_smu,
 493         .check_fw_load_finish = &smu7_check_fw_load_finish,
 494         .request_smu_load_fw = &smu7_reload_firmware,
 495         .request_smu_load_specific_fw = NULL,
 496         .send_msg_to_smc = &smu7_send_msg_to_smc,
 497         .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
 498         .download_pptable_settings = NULL,
 499         .upload_pptable_settings = NULL,
 500         .update_smc_table = fiji_update_smc_table,
 501         .get_offsetof = fiji_get_offsetof,
 502         .process_firmware_header = fiji_process_firmware_header,
 503         .init_smc_table = fiji_init_smc_table,
 504         .update_sclk_threshold = fiji_update_sclk_threshold,
 505         .thermal_setup_fan_table = fiji_thermal_setup_fan_table,
 506         .populate_all_graphic_levels = fiji_populate_all_graphic_levels,
 507         .populate_all_memory_levels = fiji_populate_all_memory_levels,
 508         .get_mac_definition = fiji_get_mac_definition,
 509         .initialize_mc_reg_table = fiji_initialize_mc_reg_table,
 510         .is_dpm_running = fiji_is_dpm_running,
 511 };
 512
 513 int fiji_smum_init(struct pp_smumgr *smumgr)
 514 {
 515         struct fiji_smumgr *fiji_smu = NULL;
 516
 517         fiji_smu = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL);
 518
 519         if (fiji_smu == NULL)
 520                 return -ENOMEM;
 521
 522         smumgr->backend = fiji_smu;
 523         smumgr->smumgr_funcs = &fiji_smu_funcs;
 524
 525         return 0;
 526 }