drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include "smumgr.h"
  26 #include "smu74.h"
  27 #include "smu_ucode_xfer_vi.h"
  28 #include "polaris10_smumgr.h"
  29 #include "smu74_discrete.h"
  30 #include "smu/smu_7_1_3_d.h"
  31 #include "smu/smu_7_1_3_sh_mask.h"
  32 #include "gmc/gmc_8_1_d.h"
  33 #include "gmc/gmc_8_1_sh_mask.h"
  34 #include "oss/oss_3_0_d.h"
  35 #include "gca/gfx_8_0_d.h"
  36 #include "bif/bif_5_0_d.h"
  37 #include "bif/bif_5_0_sh_mask.h"
  38 #include "polaris10_pwrvirus.h"
  39 #include "ppatomctrl.h"
  40 #include "cgs_common.h"
  41 #include "polaris10_smc.h"
  42 #include "smu7_ppsmc.h"
  43 #include "smu7_smumgr.h"
  44
  45 #define PPPOLARIS10_TARGETACTIVITY_DFLT                     50
  46
  47 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
  48         /*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
  49         /* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
  50         { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
  51         { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
  52         { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
  53         { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
  54         { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
  55         { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
  56         { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
  57         { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
  58 };
  59
  60 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
  61         0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
  62
  63 static int polaris10_setup_pwr_virus(struct pp_hwmgr *hwmgr)
  64 {
  65         int i;
  66         int result = -EINVAL;
  67         uint32_t reg, data;
  68
  69         const PWR_Command_Table *pvirus = pwr_virus_table;
  70
  71         for (i = 0; i < ARRAY_SIZE(pwr_virus_table); i++) {
  72                 reg  = pvirus->reg;
  73                 data = pvirus->data;
  74                 if (reg != 0xffffffff) {
  75                         cgs_write_register(hwmgr->device, reg, data);
  76                 } else {
  77                         result = 0;
  78                         break;
  79                 }
  80                 pvirus++;
  81         }
  82
  83         return result;
  84 }
  85
  86 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
  87 {
  88         int result = 0;
  89         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
  90
  91         if (0 != smu_data->avfs.avfs_btc_param) {
  92                 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
  93                         pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
  94                         result = -1;
  95                 }
  96         }
  97         if (smu_data->avfs.avfs_btc_param > 1) {
  98                 /* Soft-Reset to reset the engine before loading uCode */
  99                 /* halt */
 100                 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
 101                 /* reset everything */
 102                 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
 103                 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
 104         }
 105         return result;
 106 }
 107
 108
 109 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
 110 {
 111         uint32_t vr_config;
 112         uint32_t dpm_table_start;
 113
 114         uint16_t u16_boot_mvdd;
 115         uint32_t graphics_level_address, vr_config_address, graphics_level_size;
 116
 117         graphics_level_size = sizeof(avfs_graphics_level_polaris10);
 118         u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
 119
 120         PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
 121                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
 122                                 &dpm_table_start, 0x40000),
 123                         "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
 124                         return -1);
 125
 126         /*  Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
 127         vr_config = 0x01000500; /* Real value:0x50001 */
 128
 129         vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
 130
 131         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
 132                                 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
 133                         "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
 134                         return -1);
 135
 136         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
 137
 138         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
 139                                 (uint8_t *)(&avfs_graphics_level_polaris10),
 140                                 graphics_level_size, 0x40000),
 141                         "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
 142                         return -1);
 143
 144         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
 145
 146         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
 147                                 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
 148                                 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
 149                         return -1);
 150
 151         /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
 152
 153         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
 154
 155         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
 156                         (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
 157                         "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
 158                         return -1);
 159
 160         return 0;
 161 }
 162
 163
 164 static int
 165 polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT)
 166 {
 167         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 168
 169         switch (smu_data->avfs.avfs_btc_status) {
 170         case AVFS_BTC_COMPLETED_PREVIOUSLY:
 171                 break;
 172
 173         case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
 174
 175                 smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
 176                 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
 177                         "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
 178                         return -EINVAL);
 179
 180                 if (smu_data->avfs.avfs_btc_param > 1) {
 181                         pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
 182                         smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
 183                         PP_ASSERT_WITH_CODE(0 == polaris10_setup_pwr_virus(hwmgr),
 184                         "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
 185                         return -EINVAL);
 186                 }
 187
 188                 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
 189                 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
 190                                         "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
 191                                  return -EINVAL);
 192                 smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS;
 193                 break;
 194
 195         case AVFS_BTC_DISABLED:
 196         case AVFS_BTC_ENABLEAVFS:
 197         case AVFS_BTC_NOTSUPPORTED:
 198                 break;
 199
 200         default:
 201                 pr_err("AVFS failed status is %x!\n", smu_data->avfs.avfs_btc_status);
 202                 break;
 203         }
 204
 205         return 0;
 206 }
 207
 208 static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
 209 {
 210         int result = 0;
 211
 212         /* Wait for smc boot up */
 213         /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
 214
 215         /* Assert reset */
 216         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 217                                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 218
 219         result = smu7_upload_smu_firmware_image(hwmgr);
 220         if (result != 0)
 221                 return result;
 222
 223         /* Clear status */
 224         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
 225
 226         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 227                                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 228
 229         /* De-assert reset */
 230         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 231                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 232
 233
 234         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
 235
 236
 237         /* Call Test SMU message with 0x20000 offset to trigger SMU start */
 238         smu7_send_msg_to_smc_offset(hwmgr);
 239
 240         /* Wait done bit to be set */
 241         /* Check pass/failed indicator */
 242
 243         PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
 244
 245         if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 246                                                 SMU_STATUS, SMU_PASS))
 247                 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
 248
 249         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
 250
 251         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 252                                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 253
 254         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 255                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 256
 257         /* Wait for firmware to initialize */
 258         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 259
 260         return result;
 261 }
 262
 263 static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
 264 {
 265         int result = 0;
 266
 267         /* wait for smc boot up */
 268         PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
 269
 270         /* Clear firmware interrupt enable flag */
 271         /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
 272         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 273                                 ixFIRMWARE_FLAGS, 0);
 274
 275         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 276                                         SMC_SYSCON_RESET_CNTL,
 277                                         rst_reg, 1);
 278
 279         result = smu7_upload_smu_firmware_image(hwmgr);
 280         if (result != 0)
 281                 return result;
 282
 283         /* Set smc instruct start point at 0x0 */
 284         smu7_program_jump_on_start(hwmgr);
 285
 286         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 287                                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 288
 289         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 290                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 291
 292         /* Wait for firmware to initialize */
 293
 294         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
 295                                         FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 296
 297         return result;
 298 }
 299
 300 static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
 301 {
 302         int result = 0;
 303         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 304         bool SMU_VFT_INTACT;
 305
 306         /* Only start SMC if SMC RAM is not running */
 307         if (!smu7_is_smc_ram_running(hwmgr)) {
 308                 SMU_VFT_INTACT = false;
 309                 smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
 310                 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
 311
 312                 /* Check if SMU is running in protected mode */
 313                 if (smu_data->protected_mode == 0) {
 314                         result = polaris10_start_smu_in_non_protection_mode(hwmgr);
 315                 } else {
 316                         result = polaris10_start_smu_in_protection_mode(hwmgr);
 317
 318                         /* If failed, try with different security Key. */
 319                         if (result != 0) {
 320                                 smu_data->smu7_data.security_hard_key ^= 1;
 321                                 cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
 322                                 result = polaris10_start_smu_in_protection_mode(hwmgr);
 323                         }
 324                 }
 325
 326                 if (result != 0)
 327                         PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
 328
 329                 polaris10_avfs_event_mgr(hwmgr, true);
 330         } else
 331                 SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
 332
 333         polaris10_avfs_event_mgr(hwmgr, SMU_VFT_INTACT);
 334         /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
 335         smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
 336                                         &(smu_data->smu7_data.soft_regs_start), 0x40000);
 337
 338         result = smu7_request_smu_load_fw(hwmgr);
 339
 340         return result;
 341 }
 342
 343 static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
 344 {
 345         uint32_t efuse;
 346
 347         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
 348         efuse &= 0x00000001;
 349         if (efuse)
 350                 return true;
 351
 352         return false;
 353 }
 354
 355 static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
 356 {
 357         struct polaris10_smumgr *smu_data;
 358         int i;
 359
 360         smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
 361         if (smu_data == NULL)
 362                 return -ENOMEM;
 363
 364         hwmgr->smu_backend = smu_data;
 365
 366         if (smu7_init(hwmgr))
 367                 return -EINVAL;
 368
 369         for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
 370                 smu_data->activity_target[i] = PPPOLARIS10_TARGETACTIVITY_DFLT;
 371
 372         return 0;
 373 }
 374
 375 const struct pp_smumgr_func polaris10_smu_funcs = {
 376         .smu_init = polaris10_smu_init,
 377         .smu_fini = smu7_smu_fini,
 378         .start_smu = polaris10_start_smu,
 379         .check_fw_load_finish = smu7_check_fw_load_finish,
 380         .request_smu_load_fw = smu7_reload_firmware,
 381         .request_smu_load_specific_fw = NULL,
 382         .send_msg_to_smc = smu7_send_msg_to_smc,
 383         .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
 384         .download_pptable_settings = NULL,
 385         .upload_pptable_settings = NULL,
 386         .update_smc_table = polaris10_update_smc_table,
 387         .get_offsetof = polaris10_get_offsetof,
 388         .process_firmware_header = polaris10_process_firmware_header,
 389         .init_smc_table = polaris10_init_smc_table,
 390         .update_sclk_threshold = polaris10_update_sclk_threshold,
 391         .thermal_avfs_enable = polaris10_thermal_avfs_enable,
 392         .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
 393         .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
 394         .populate_all_memory_levels = polaris10_populate_all_memory_levels,
 395         .get_mac_definition = polaris10_get_mac_definition,
 396         .is_dpm_running = polaris10_is_dpm_running,
 397         .populate_requested_graphic_levels = polaris10_populate_requested_graphic_levels,
 398         .is_hw_avfs_present = polaris10_is_hw_avfs_present,
 399 };