drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include "pp_instance.h"
  27 #include "smumgr.h"
  28 #include "cgs_common.h"
  29 #include "linux/delay.h"
  30 #include "cz_smumgr.h"
  31 #include "tonga_smumgr.h"
  32 #include "fiji_smumgr.h"
  33
  34 int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
  35 {
  36         struct pp_smumgr *smumgr;
  37
  38         if ((handle == NULL) || (pp_init == NULL))
  39                 return -EINVAL;
  40
  41         smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
  42         if (smumgr == NULL)
  43                 return -ENOMEM;
  44
  45         smumgr->device = pp_init->device;
  46         smumgr->chip_family = pp_init->chip_family;
  47         smumgr->chip_id = pp_init->chip_id;
  48         smumgr->hw_revision = pp_init->rev_id;
  49         smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  50         smumgr->reload_fw = 1;
  51         handle->smu_mgr = smumgr;
  52
  53         switch (smumgr->chip_family) {
  54         case AMD_FAMILY_CZ:
  55                 cz_smum_init(smumgr);
  56                 break;
  57         case AMD_FAMILY_VI:
  58                 switch (smumgr->chip_id) {
  59                 case CHIP_TONGA:
  60                         tonga_smum_init(smumgr);
  61                         break;
  62                 case CHIP_FIJI:
  63                         fiji_smum_init(smumgr);
  64                         break;
  65                 default:
  66                         return -EINVAL;
  67                 }
  68                 break;
  69         default:
  70                 kfree(smumgr);
  71                 return -EINVAL;
  72         }
  73
  74         return 0;
  75 }
  76
  77 int smum_fini(struct pp_smumgr *smumgr)
  78 {
  79         kfree(smumgr);
  80         return 0;
  81 }
  82
  83 int smum_get_argument(struct pp_smumgr *smumgr)
  84 {
  85         if (NULL != smumgr->smumgr_funcs->get_argument)
  86                 return smumgr->smumgr_funcs->get_argument(smumgr);
  87
  88         return 0;
  89 }
  90
  91 int smum_download_powerplay_table(struct pp_smumgr *smumgr,
  92                                                                 void **table)
  93 {
  94         if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
  95                 return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
  96                                                                         table);
  97
  98         return 0;
  99 }
 100
 101 int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
 102 {
 103         if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
 104                 return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
 105
 106         return 0;
 107 }
 108
 109 int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 110 {
 111         if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
 112                 return -EINVAL;
 113
 114         return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
 115 }
 116
 117 int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
 118                                         uint16_t msg, uint32_t parameter)
 119 {
 120         if (smumgr == NULL ||
 121                 smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
 122                 return -EINVAL;
 123         return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
 124                                                 smumgr, msg, parameter);
 125 }
 126
 127 /*
 128  * Returns once the part of the register indicated by the mask has
 129  * reached the given value.
 130  */
 131 int smum_wait_on_register(struct pp_smumgr *smumgr,
 132                                 uint32_t index,
 133                                 uint32_t value, uint32_t mask)
 134 {
 135         uint32_t i;
 136         uint32_t cur_value;
 137
 138         if (smumgr == NULL || smumgr->device == NULL)
 139                 return -EINVAL;
 140
 141         for (i = 0; i < smumgr->usec_timeout; i++) {
 142                 cur_value = cgs_read_register(smumgr->device, index);
 143                 if ((cur_value & mask) == (value & mask))
 144                         break;
 145                 udelay(1);
 146         }
 147
 148         /* timeout means wrong logic*/
 149         if (i == smumgr->usec_timeout)
 150                 return -1;
 151
 152         return 0;
 153 }
 154
 155 int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
 156                                         uint32_t index,
 157                                         uint32_t value, uint32_t mask)
 158 {
 159         uint32_t i;
 160         uint32_t cur_value;
 161
 162         if (smumgr == NULL)
 163                 return -EINVAL;
 164
 165         for (i = 0; i < smumgr->usec_timeout; i++) {
 166                 cur_value = cgs_read_register(smumgr->device,
 167                                                                         index);
 168                 if ((cur_value & mask) != (value & mask))
 169                         break;
 170                 udelay(1);
 171         }
 172
 173         /* timeout means wrong logic */
 174         if (i == smumgr->usec_timeout)
 175                 return -1;
 176
 177         return 0;
 178 }
 179
 180
 181 /*
 182  * Returns once the part of the register indicated by the mask
 183  * has reached the given value.The indirect space is described by
 184  * giving the memory-mapped index of the indirect index register.
 185  */
 186 int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
 187                                         uint32_t indirect_port,
 188                                         uint32_t index,
 189                                         uint32_t value,
 190                                         uint32_t mask)
 191 {
 192         if (smumgr == NULL || smumgr->device == NULL)
 193                 return -EINVAL;
 194
 195         cgs_write_register(smumgr->device, indirect_port, index);
 196         return smum_wait_on_register(smumgr, indirect_port + 1,
 197                                                 mask, value);
 198 }
 199
 200 void smum_wait_for_indirect_register_unequal(
 201                                                 struct pp_smumgr *smumgr,
 202                                                 uint32_t indirect_port,
 203                                                 uint32_t index,
 204                                                 uint32_t value,
 205                                                 uint32_t mask)
 206 {
 207         if (smumgr == NULL || smumgr->device == NULL)
 208                 return;
 209         cgs_write_register(smumgr->device, indirect_port, index);
 210         smum_wait_for_register_unequal(smumgr, indirect_port + 1,
 211                                                 value, mask);
 212 }
 213
 214 int smu_allocate_memory(void *device, uint32_t size,
 215                          enum cgs_gpu_mem_type type,
 216                          uint32_t byte_align, uint64_t *mc_addr,
 217                          void **kptr, void *handle)
 218 {
 219         int ret = 0;
 220         cgs_handle_t cgs_handle;
 221
 222         if (device == NULL || handle == NULL ||
 223             mc_addr == NULL || kptr == NULL)
 224                 return -EINVAL;
 225
 226         ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
 227                                 0, 0, (cgs_handle_t *)handle);
 228         if (ret)
 229                 return -ENOMEM;
 230
 231         cgs_handle = *(cgs_handle_t *)handle;
 232
 233         ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
 234         if (ret)
 235                 goto error_gmap;
 236
 237         ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
 238         if (ret)
 239                 goto error_kmap;
 240
 241         return 0;
 242
 243 error_kmap:
 244         cgs_gunmap_gpu_mem(device, cgs_handle);
 245
 246 error_gmap:
 247         cgs_free_gpu_mem(device, cgs_handle);
 248         return ret;
 249 }
 250
 251 int smu_free_memory(void *device, void *handle)
 252 {
 253         cgs_handle_t cgs_handle = (cgs_handle_t)handle;
 254
 255         if (device == NULL || handle == NULL)
 256                 return -EINVAL;
 257
 258         cgs_kunmap_gpu_mem(device, cgs_handle);
 259         cgs_gunmap_gpu_mem(device, cgs_handle);
 260         cgs_free_gpu_mem(device, cgs_handle);
 261
 262         return 0;
 263 }