drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "pp_instance.h"
  31 #include "smumgr.h"
  32 #include "cgs_common.h"
  33
  34 MODULE_FIRMWARE("amdgpu/topaz_smc.bin");
  35 MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin");
  36 MODULE_FIRMWARE("amdgpu/tonga_smc.bin");
  37 MODULE_FIRMWARE("amdgpu/tonga_k_smc.bin");
  38 MODULE_FIRMWARE("amdgpu/fiji_smc.bin");
  39 MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
  40 MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
  41 MODULE_FIRMWARE("amdgpu/polaris10_k_smc.bin");
  42 MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
  43 MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
  44 MODULE_FIRMWARE("amdgpu/polaris11_k_smc.bin");
  45 MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
  46
  47
  48 int smum_early_init(struct pp_instance *handle)
  49 {
  50         struct pp_smumgr *smumgr;
  51
  52         if (handle == NULL)
  53                 return -EINVAL;
  54
  55         smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
  56         if (smumgr == NULL)
  57                 return -ENOMEM;
  58
  59         smumgr->device = handle->device;
  60         smumgr->chip_family = handle->chip_family;
  61         smumgr->chip_id = handle->chip_id;
  62         smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  63         smumgr->reload_fw = 1;
  64         handle->smu_mgr = smumgr;
  65
  66         switch (smumgr->chip_family) {
  67         case AMDGPU_FAMILY_CZ:
  68                 smumgr->smumgr_funcs = &cz_smu_funcs;
  69                 break;
  70         case AMDGPU_FAMILY_VI:
  71                 switch (smumgr->chip_id) {
  72                 case CHIP_TOPAZ:
  73                         smumgr->smumgr_funcs = &iceland_smu_funcs;
  74                         break;
  75                 case CHIP_TONGA:
  76                         smumgr->smumgr_funcs = &tonga_smu_funcs;
  77                         break;
  78                 case CHIP_FIJI:
  79                         smumgr->smumgr_funcs = &fiji_smu_funcs;
  80                         break;
  81                 case CHIP_POLARIS11:
  82                 case CHIP_POLARIS10:
  83                 case CHIP_POLARIS12:
  84                         smumgr->smumgr_funcs = &polaris10_smu_funcs;
  85                         break;
  86                 default:
  87                         return -EINVAL;
  88                 }
  89                 break;
  90         case AMDGPU_FAMILY_AI:
  91                 switch (smumgr->chip_id) {
  92                 case CHIP_VEGA10:
  93                         smumgr->smumgr_funcs = &vega10_smu_funcs;
  94                         break;
  95                 default:
  96                         return -EINVAL;
  97                 }
  98                 break;
  99         default:
 100                 kfree(smumgr);
 101                 return -EINVAL;
 102         }
 103
 104         return 0;
 105 }
 106
 107 int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
 108                 void *input, void *output, void *storage, int result)
 109 {
 110         if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable)
 111                 return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
 112
 113         return 0;
 114 }
 115
 116 int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
 117                 void *input, void *output, void *storage, int result)
 118 {
 119         if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table)
 120                 return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
 121
 122         return 0;
 123 }
 124
 125 int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
 126 {
 127
 128         if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold)
 129                 return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr);
 130
 131         return 0;
 132 }
 133
 134 int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
 135 {
 136
 137         if (NULL != hwmgr->smumgr->smumgr_funcs->update_smc_table)
 138                 return hwmgr->smumgr->smumgr_funcs->update_smc_table(hwmgr, type);
 139
 140         return 0;
 141 }
 142
 143 uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, uint32_t type, uint32_t member)
 144 {
 145         if (NULL != smumgr->smumgr_funcs->get_offsetof)
 146                 return smumgr->smumgr_funcs->get_offsetof(type, member);
 147
 148         return 0;
 149 }
 150
 151 int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
 152 {
 153         if (NULL != hwmgr->smumgr->smumgr_funcs->process_firmware_header)
 154                 return hwmgr->smumgr->smumgr_funcs->process_firmware_header(hwmgr);
 155         return 0;
 156 }
 157
 158 int smum_get_argument(struct pp_smumgr *smumgr)
 159 {
 160         if (NULL != smumgr->smumgr_funcs->get_argument)
 161                 return smumgr->smumgr_funcs->get_argument(smumgr);
 162
 163         return 0;
 164 }
 165
 166 uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value)
 167 {
 168         if (NULL != smumgr->smumgr_funcs->get_mac_definition)
 169                 return smumgr->smumgr_funcs->get_mac_definition(value);
 170
 171         return 0;
 172 }
 173
 174 int smum_download_powerplay_table(struct pp_smumgr *smumgr,
 175                                                                 void **table)
 176 {
 177         if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
 178                 return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
 179                                                                         table);
 180         return 0;
 181 }
 182
 183 int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
 184 {
 185         if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
 186                 return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
 187
 188         return 0;
 189 }
 190
 191 int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 192 {
 193         if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
 194                 return -EINVAL;
 195
 196         return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
 197 }
 198
 199 int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
 200                                         uint16_t msg, uint32_t parameter)
 201 {
 202         if (smumgr == NULL ||
 203                 smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
 204                 return -EINVAL;
 205         return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
 206                                                 smumgr, msg, parameter);
 207 }
 208
 209 /*
 210  * Returns once the part of the register indicated by the mask has
 211  * reached the given value.
 212  */
 213 int smum_wait_on_register(struct pp_smumgr *smumgr,
 214                                 uint32_t index,
 215                                 uint32_t value, uint32_t mask)
 216 {
 217         uint32_t i;
 218         uint32_t cur_value;
 219
 220         if (smumgr == NULL || smumgr->device == NULL)
 221                 return -EINVAL;
 222
 223         for (i = 0; i < smumgr->usec_timeout; i++) {
 224                 cur_value = cgs_read_register(smumgr->device, index);
 225                 if ((cur_value & mask) == (value & mask))
 226                         break;
 227                 udelay(1);
 228         }
 229
 230         /* timeout means wrong logic*/
 231         if (i == smumgr->usec_timeout)
 232                 return -1;
 233
 234         return 0;
 235 }
 236
 237 int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
 238                                         uint32_t index,
 239                                         uint32_t value, uint32_t mask)
 240 {
 241         uint32_t i;
 242         uint32_t cur_value;
 243
 244         if (smumgr == NULL)
 245                 return -EINVAL;
 246
 247         for (i = 0; i < smumgr->usec_timeout; i++) {
 248                 cur_value = cgs_read_register(smumgr->device,
 249                                                                         index);
 250                 if ((cur_value & mask) != (value & mask))
 251                         break;
 252                 udelay(1);
 253         }
 254
 255         /* timeout means wrong logic */
 256         if (i == smumgr->usec_timeout)
 257                 return -1;
 258
 259         return 0;
 260 }
 261
 262
 263 /*
 264  * Returns once the part of the register indicated by the mask
 265  * has reached the given value.The indirect space is described by
 266  * giving the memory-mapped index of the indirect index register.
 267  */
 268 int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
 269                                         uint32_t indirect_port,
 270                                         uint32_t index,
 271                                         uint32_t value,
 272                                         uint32_t mask)
 273 {
 274         if (smumgr == NULL || smumgr->device == NULL)
 275                 return -EINVAL;
 276
 277         cgs_write_register(smumgr->device, indirect_port, index);
 278         return smum_wait_on_register(smumgr, indirect_port + 1,
 279                                                 mask, value);
 280 }
 281
 282 void smum_wait_for_indirect_register_unequal(
 283                                                 struct pp_smumgr *smumgr,
 284                                                 uint32_t indirect_port,
 285                                                 uint32_t index,
 286                                                 uint32_t value,
 287                                                 uint32_t mask)
 288 {
 289         if (smumgr == NULL || smumgr->device == NULL)
 290                 return;
 291         cgs_write_register(smumgr->device, indirect_port, index);
 292         smum_wait_for_register_unequal(smumgr, indirect_port + 1,
 293                                                 value, mask);
 294 }
 295
 296 int smu_allocate_memory(void *device, uint32_t size,
 297                          enum cgs_gpu_mem_type type,
 298                          uint32_t byte_align, uint64_t *mc_addr,
 299                          void **kptr, void *handle)
 300 {
 301         int ret = 0;
 302         cgs_handle_t cgs_handle;
 303
 304         if (device == NULL || handle == NULL ||
 305             mc_addr == NULL || kptr == NULL)
 306                 return -EINVAL;
 307
 308         ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
 309                                 0, 0, (cgs_handle_t *)handle);
 310         if (ret)
 311                 return -ENOMEM;
 312
 313         cgs_handle = *(cgs_handle_t *)handle;
 314
 315         ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
 316         if (ret)
 317                 goto error_gmap;
 318
 319         ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
 320         if (ret)
 321                 goto error_kmap;
 322
 323         return 0;
 324
 325 error_kmap:
 326         cgs_gunmap_gpu_mem(device, cgs_handle);
 327
 328 error_gmap:
 329         cgs_free_gpu_mem(device, cgs_handle);
 330         return ret;
 331 }
 332
 333 int smu_free_memory(void *device, void *handle)
 334 {
 335         cgs_handle_t cgs_handle = (cgs_handle_t)handle;
 336
 337         if (device == NULL || handle == NULL)
 338                 return -EINVAL;
 339
 340         cgs_kunmap_gpu_mem(device, cgs_handle);
 341         cgs_gunmap_gpu_mem(device, cgs_handle);
 342         cgs_free_gpu_mem(device, cgs_handle);
 343
 344         return 0;
 345 }
 346
 347 int smum_init_smc_table(struct pp_hwmgr *hwmgr)
 348 {
 349         if (NULL != hwmgr->smumgr->smumgr_funcs->init_smc_table)
 350                 return hwmgr->smumgr->smumgr_funcs->init_smc_table(hwmgr);
 351
 352         return 0;
 353 }
 354
 355 int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
 356 {
 357         if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels)
 358                 return hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
 359
 360         return 0;
 361 }
 362
 363 int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
 364 {
 365         if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels)
 366                 return hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
 367
 368         return 0;
 369 }
 370
 371 /*this interface is needed by island ci/vi */
 372 int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
 373 {
 374         if (NULL != hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table)
 375                 return hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
 376
 377         return 0;
 378 }
 379
 380 bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
 381 {
 382         if (NULL != hwmgr->smumgr->smumgr_funcs->is_dpm_running)
 383                 return hwmgr->smumgr->smumgr_funcs->is_dpm_running(hwmgr);
 384
 385         return true;
 386 }
 387
 388 int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
 389                 struct amd_pp_profile *request)
 390 {
 391         if (hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels)
 392                 return hwmgr->smumgr->smumgr_funcs->populate_requested_graphic_levels(
 393                                 hwmgr, request);
 394
 395         return 0;
 396 }