drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "smumgr.h"
  25 #include "vega10_inc.h"
  26 #include "pp_soc15.h"
  27 #include "vega10_smumgr.h"
  28 #include "vega10_ppsmc.h"
  29 #include "smu9_driver_if.h"
  30
  31 #include "ppatomctrl.h"
  32 #include "pp_debug.h"
  33 #include "smu_ucode_xfer_vi.h"
  34 #include "smu7_smumgr.h"
  35
  36 #define AVFS_EN_MSB             1568
  37 #define AVFS_EN_LSB             1568
  38
  39 #define VOLTAGE_SCALE   4
  40
  41 /* Microcode file is stored in this buffer */
  42 #define BUFFER_SIZE                 80000
  43 #define MAX_STRING_SIZE             15
  44 #define BUFFER_SIZETWO              131072 /* 128 *1024 */
  45
  46 /* MP Apertures */
  47 #define MP0_Public                  0x03800000
  48 #define MP0_SRAM                    0x03900000
  49 #define MP1_Public                  0x03b00000
  50 #define MP1_SRAM                    0x03c00004
  51
  52 #define smnMP1_FIRMWARE_FLAGS                                                                           0x3010028
  53 #define smnMP0_FW_INTF                                                                                  0x3010104
  54 #define smnMP1_PUB_CTRL                                                                                 0x3010b14
  55
  56 static bool vega10_is_smc_ram_running(struct pp_smumgr *smumgr)
  57 {
  58         uint32_t mp1_fw_flags, reg;
  59
  60         reg = soc15_get_register_offset(NBIF_HWID, 0,
  61                         mmPCIE_INDEX2_BASE_IDX, mmPCIE_INDEX2);
  62
  63         cgs_write_register(smumgr->device, reg,
  64                         (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
  65
  66         reg = soc15_get_register_offset(NBIF_HWID, 0,
  67                         mmPCIE_DATA2_BASE_IDX, mmPCIE_DATA2);
  68
  69         mp1_fw_flags = cgs_read_register(smumgr->device, reg);
  70
  71         if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
  72                 return true;
  73
  74         return false;
  75 }
  76
  77 /*
  78  * Check if SMC has responded to previous message.
  79  *
  80  * @param    smumgr  the address of the powerplay hardware manager.
  81  * @return   TRUE    SMC has responded, FALSE otherwise.
  82  */
  83 static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr)
  84 {
  85         uint32_t reg;
  86
  87         if (!vega10_is_smc_ram_running(smumgr))
  88                 return -EINVAL;
  89
  90         reg = soc15_get_register_offset(MP1_HWID, 0,
  91                         mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
  92
  93         smum_wait_for_register_unequal(smumgr, reg,
  94                         0, MP1_C2PMSG_90__CONTENT_MASK);
  95
  96         return cgs_read_register(smumgr->device, reg);
  97 }
  98
  99 /*
 100  * Send a message to the SMC, and do not wait for its response.
 101  * @param    smumgr  the address of the powerplay hardware manager.
 102  * @param    msg the message to send.
 103  * @return   Always return 0.
 104  */
 105 int vega10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
 106                 uint16_t msg)
 107 {
 108         uint32_t reg;
 109
 110         if (!vega10_is_smc_ram_running(smumgr))
 111                 return -EINVAL;
 112
 113         reg = soc15_get_register_offset(MP1_HWID, 0,
 114                         mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
 115         cgs_write_register(smumgr->device, reg, msg);
 116
 117         return 0;
 118 }
 119
 120 /*
 121  * Send a message to the SMC, and wait for its response.
 122  * @param    smumgr  the address of the powerplay hardware manager.
 123  * @param    msg the message to send.
 124  * @return   Always return 0.
 125  */
 126 int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 127 {
 128         uint32_t reg;
 129
 130         if (!vega10_is_smc_ram_running(smumgr))
 131                 return -EINVAL;
 132
 133         vega10_wait_for_response(smumgr);
 134
 135         reg = soc15_get_register_offset(MP1_HWID, 0,
 136                         mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
 137         cgs_write_register(smumgr->device, reg, 0);
 138
 139         vega10_send_msg_to_smc_without_waiting(smumgr, msg);
 140
 141         if (vega10_wait_for_response(smumgr) != 1)
 142                 pr_err("Failed to send message: 0x%x\n", msg);
 143
 144         return 0;
 145 }
 146
 147 /*
 148  * Send a message to the SMC with parameter
 149  * @param    smumgr:  the address of the powerplay hardware manager.
 150  * @param    msg: the message to send.
 151  * @param    parameter: the parameter to send
 152  * @return   Always return 0.
 153  */
 154 int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
 155                 uint16_t msg, uint32_t parameter)
 156 {
 157         uint32_t reg;
 158
 159         if (!vega10_is_smc_ram_running(smumgr))
 160                 return -EINVAL;
 161
 162         vega10_wait_for_response(smumgr);
 163
 164         reg = soc15_get_register_offset(MP1_HWID, 0,
 165                         mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
 166         cgs_write_register(smumgr->device, reg, 0);
 167
 168         reg = soc15_get_register_offset(MP1_HWID, 0,
 169                         mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
 170         cgs_write_register(smumgr->device, reg, parameter);
 171
 172         vega10_send_msg_to_smc_without_waiting(smumgr, msg);
 173
 174         if (vega10_wait_for_response(smumgr) != 1)
 175                 pr_err("Failed to send message: 0x%x\n", msg);
 176
 177         return 0;
 178 }
 179
 180
 181 /*
 182  * Send a message to the SMC with parameter, do not wait for response
 183  * @param    smumgr:  the address of the powerplay hardware manager.
 184  * @param    msg: the message to send.
 185  * @param    parameter: the parameter to send
 186  * @return   The response that came from the SMC.
 187  */
 188 int vega10_send_msg_to_smc_with_parameter_without_waiting(
 189                 struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter)
 190 {
 191         uint32_t reg;
 192
 193         reg = soc15_get_register_offset(MP1_HWID, 0,
 194                         mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
 195         cgs_write_register(smumgr->device, reg, parameter);
 196
 197         return vega10_send_msg_to_smc_without_waiting(smumgr, msg);
 198 }
 199
 200 /*
 201  * Retrieve an argument from SMC.
 202  * @param    smumgr  the address of the powerplay hardware manager.
 203  * @param    arg     pointer to store the argument from SMC.
 204  * @return   Always return 0.
 205  */
 206 int vega10_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg)
 207 {
 208         uint32_t reg;
 209
 210         reg = soc15_get_register_offset(MP1_HWID, 0,
 211                         mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
 212
 213         *arg = cgs_read_register(smumgr->device, reg);
 214
 215         return 0;
 216 }
 217
 218 /*
 219  * Copy table from SMC into driver FB
 220  * @param   smumgr    the address of the SMC manager
 221  * @param   table_id    the driver's table ID to copy from
 222  */
 223 int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
 224                 uint8_t *table, int16_t table_id)
 225 {
 226         struct vega10_smumgr *priv =
 227                         (struct vega10_smumgr *)(smumgr->backend);
 228
 229         PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
 230                         "Invalid SMU Table ID!", return -EINVAL);
 231         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 232                         "Invalid SMU Table version!", return -EINVAL);
 233         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 234                         "Invalid SMU Table Length!", return -EINVAL);
 235         PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
 236                         PPSMC_MSG_SetDriverDramAddrHigh,
 237                         priv->smu_tables.entry[table_id].table_addr_high) == 0,
 238                         "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL);
 239         PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
 240                         PPSMC_MSG_SetDriverDramAddrLow,
 241                         priv->smu_tables.entry[table_id].table_addr_low) == 0,
 242                         "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
 243                         return -EINVAL);
 244         PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
 245                         PPSMC_MSG_TransferTableSmu2Dram,
 246                         priv->smu_tables.entry[table_id].table_id) == 0,
 247                         "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
 248                         return -EINVAL);
 249
 250         memcpy(table, priv->smu_tables.entry[table_id].table,
 251                         priv->smu_tables.entry[table_id].size);
 252
 253         return 0;
 254 }
 255
 256 /*
 257  * Copy table from Driver FB into SMC
 258  * @param   smumgr    the address of the SMC manager
 259  * @param   table_id    the table to copy from
 260  */
 261 int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
 262                 uint8_t *table, int16_t table_id)
 263 {
 264         struct vega10_smumgr *priv =
 265                         (struct vega10_smumgr *)(smumgr->backend);
 266
 267         PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
 268                         "Invalid SMU Table ID!", return -EINVAL);
 269         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
 270                         "Invalid SMU Table version!", return -EINVAL);
 271         PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
 272                         "Invalid SMU Table Length!", return -EINVAL);
 273
 274         memcpy(priv->smu_tables.entry[table_id].table, table,
 275                         priv->smu_tables.entry[table_id].size);
 276
 277         PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
 278                         PPSMC_MSG_SetDriverDramAddrHigh,
 279                         priv->smu_tables.entry[table_id].table_addr_high) == 0,
 280                         "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
 281                         return -EINVAL;);
 282         PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
 283                         PPSMC_MSG_SetDriverDramAddrLow,
 284                         priv->smu_tables.entry[table_id].table_addr_low) == 0,
 285                         "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
 286                         return -EINVAL);
 287         PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
 288                         PPSMC_MSG_TransferTableDram2Smu,
 289                         priv->smu_tables.entry[table_id].table_id) == 0,
 290                         "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
 291                         return -EINVAL);
 292
 293         return 0;
 294 }
 295
 296 int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
 297 {
 298         PP_ASSERT_WITH_CODE(avfs_table,
 299                         "No access to SMC AVFS Table",
 300                         return -EINVAL);
 301
 302         return vega10_copy_table_from_smc(smumgr, avfs_table, AVFSTABLE);
 303 }
 304
 305 int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
 306 {
 307         PP_ASSERT_WITH_CODE(avfs_table,
 308                         "No access to SMC AVFS Table",
 309                         return -EINVAL);
 310
 311         return vega10_copy_table_to_smc(smumgr, avfs_table, AVFSTABLE);
 312 }
 313
 314 int vega10_enable_smc_features(struct pp_smumgr *smumgr,
 315                 bool enable, uint32_t feature_mask)
 316 {
 317         int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
 318                         PPSMC_MSG_DisableSmuFeatures;
 319
 320         return vega10_send_msg_to_smc_with_parameter(smumgr,
 321                         msg, feature_mask);
 322 }
 323
 324 int vega10_get_smc_features(struct pp_smumgr *smumgr,
 325                 uint32_t *features_enabled)
 326 {
 327         if (features_enabled == NULL)
 328                 return -EINVAL;
 329
 330         if (!vega10_send_msg_to_smc(smumgr,
 331                         PPSMC_MSG_GetEnabledSmuFeatures)) {
 332                 vega10_read_arg_from_smc(smumgr, features_enabled);
 333                 return 0;
 334         }
 335
 336         return -EINVAL;
 337 }
 338
 339 int vega10_set_tools_address(struct pp_smumgr *smumgr)
 340 {
 341         struct vega10_smumgr *priv =
 342                         (struct vega10_smumgr *)(smumgr->backend);
 343
 344         if (priv->smu_tables.entry[TOOLSTABLE].table_addr_high ||
 345                         priv->smu_tables.entry[TOOLSTABLE].table_addr_low) {
 346                 if (!vega10_send_msg_to_smc_with_parameter(smumgr,
 347                                 PPSMC_MSG_SetToolsDramAddrHigh,
 348                                 priv->smu_tables.entry[TOOLSTABLE].table_addr_high))
 349                         vega10_send_msg_to_smc_with_parameter(smumgr,
 350                                         PPSMC_MSG_SetToolsDramAddrLow,
 351                                         priv->smu_tables.entry[TOOLSTABLE].table_addr_low);
 352         }
 353         return 0;
 354 }
 355
 356 static int vega10_verify_smc_interface(struct pp_smumgr *smumgr)
 357 {
 358         uint32_t smc_driver_if_version;
 359
 360         PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(smumgr,
 361                         PPSMC_MSG_GetDriverIfVersion),
 362                         "Attempt to get SMC IF Version Number Failed!",
 363                         return -EINVAL);
 364         vega10_read_arg_from_smc(smumgr, &smc_driver_if_version);
 365
 366         if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) {
 367                 pr_err("Your firmware(0x%x) doesn't match \
 368                         SMU9_DRIVER_IF_VERSION(0x%x). \
 369                         Please update your firmware!\n",
 370                         smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
 371                 return -EINVAL;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static int vega10_smu_init(struct pp_smumgr *smumgr)
 378 {
 379         struct vega10_smumgr *priv;
 380         uint64_t mc_addr;
 381         void *kaddr = NULL;
 382         unsigned long handle, tools_size;
 383         int ret;
 384         struct cgs_firmware_info info = {0};
 385
 386         ret = cgs_get_firmware_info(smumgr->device,
 387                                     smu7_convert_fw_type_to_cgs(UCODE_ID_SMU),
 388                                     &info);
 389         if (ret || !info.kptr)
 390                 return -EINVAL;
 391
 392         priv = kzalloc(sizeof(struct vega10_smumgr), GFP_KERNEL);
 393
 394         if (!priv)
 395                 return -ENOMEM;
 396
 397         smumgr->backend = priv;
 398
 399         /* allocate space for pptable */
 400         smu_allocate_memory(smumgr->device,
 401                         sizeof(PPTable_t),
 402                         CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 403                         PAGE_SIZE,
 404                         &mc_addr,
 405                         &kaddr,
 406                         &handle);
 407
 408         PP_ASSERT_WITH_CODE(kaddr,
 409                         "[vega10_smu_init] Out of memory for pptable.",
 410                         kfree(smumgr->backend);
 411                         cgs_free_gpu_mem(smumgr->device,
 412                         (cgs_handle_t)handle);
 413                         return -EINVAL);
 414
 415         priv->smu_tables.entry[PPTABLE].version = 0x01;
 416         priv->smu_tables.entry[PPTABLE].size = sizeof(PPTable_t);
 417         priv->smu_tables.entry[PPTABLE].table_id = TABLE_PPTABLE;
 418         priv->smu_tables.entry[PPTABLE].table_addr_high =
 419                         smu_upper_32_bits(mc_addr);
 420         priv->smu_tables.entry[PPTABLE].table_addr_low =
 421                         smu_lower_32_bits(mc_addr);
 422         priv->smu_tables.entry[PPTABLE].table = kaddr;
 423         priv->smu_tables.entry[PPTABLE].handle = handle;
 424
 425         /* allocate space for watermarks table */
 426         smu_allocate_memory(smumgr->device,
 427                         sizeof(Watermarks_t),
 428                         CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 429                         PAGE_SIZE,
 430                         &mc_addr,
 431                         &kaddr,
 432                         &handle);
 433
 434         PP_ASSERT_WITH_CODE(kaddr,
 435                         "[vega10_smu_init] Out of memory for wmtable.",
 436                         kfree(smumgr->backend);
 437                         cgs_free_gpu_mem(smumgr->device,
 438                         (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
 439                         cgs_free_gpu_mem(smumgr->device,
 440                         (cgs_handle_t)handle);
 441                         return -EINVAL);
 442
 443         priv->smu_tables.entry[WMTABLE].version = 0x01;
 444         priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
 445         priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
 446         priv->smu_tables.entry[WMTABLE].table_addr_high =
 447                         smu_upper_32_bits(mc_addr);
 448         priv->smu_tables.entry[WMTABLE].table_addr_low =
 449                         smu_lower_32_bits(mc_addr);
 450         priv->smu_tables.entry[WMTABLE].table = kaddr;
 451         priv->smu_tables.entry[WMTABLE].handle = handle;
 452
 453         /* allocate space for AVFS table */
 454         smu_allocate_memory(smumgr->device,
 455                         sizeof(AvfsTable_t),
 456                         CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 457                         PAGE_SIZE,
 458                         &mc_addr,
 459                         &kaddr,
 460                         &handle);
 461
 462         PP_ASSERT_WITH_CODE(kaddr,
 463                         "[vega10_smu_init] Out of memory for avfs table.",
 464                         kfree(smumgr->backend);
 465                         cgs_free_gpu_mem(smumgr->device,
 466                         (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
 467                         cgs_free_gpu_mem(smumgr->device,
 468                         (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
 469                         cgs_free_gpu_mem(smumgr->device,
 470                         (cgs_handle_t)handle);
 471                         return -EINVAL);
 472
 473         priv->smu_tables.entry[AVFSTABLE].version = 0x01;
 474         priv->smu_tables.entry[AVFSTABLE].size = sizeof(AvfsTable_t);
 475         priv->smu_tables.entry[AVFSTABLE].table_id = TABLE_AVFS;
 476         priv->smu_tables.entry[AVFSTABLE].table_addr_high =
 477                         smu_upper_32_bits(mc_addr);
 478         priv->smu_tables.entry[AVFSTABLE].table_addr_low =
 479                         smu_lower_32_bits(mc_addr);
 480         priv->smu_tables.entry[AVFSTABLE].table = kaddr;
 481         priv->smu_tables.entry[AVFSTABLE].handle = handle;
 482
 483         tools_size = 0x19000;
 484         if (tools_size) {
 485                 smu_allocate_memory(smumgr->device,
 486                                 tools_size,
 487                                 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 488                                 PAGE_SIZE,
 489                                 &mc_addr,
 490                                 &kaddr,
 491                                 &handle);
 492
 493                 if (kaddr) {
 494                         priv->smu_tables.entry[TOOLSTABLE].version = 0x01;
 495                         priv->smu_tables.entry[TOOLSTABLE].size = tools_size;
 496                         priv->smu_tables.entry[TOOLSTABLE].table_id = TABLE_PMSTATUSLOG;
 497                         priv->smu_tables.entry[TOOLSTABLE].table_addr_high =
 498                                         smu_upper_32_bits(mc_addr);
 499                         priv->smu_tables.entry[TOOLSTABLE].table_addr_low =
 500                                         smu_lower_32_bits(mc_addr);
 501                         priv->smu_tables.entry[TOOLSTABLE].table = kaddr;
 502                         priv->smu_tables.entry[TOOLSTABLE].handle = handle;
 503                         vega10_set_tools_address(smumgr);
 504                 }
 505         }
 506
 507         /* allocate space for AVFS Fuse table */
 508         smu_allocate_memory(smumgr->device,
 509                         sizeof(AvfsFuseOverride_t),
 510                         CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 511                         PAGE_SIZE,
 512                         &mc_addr,
 513                         &kaddr,
 514                         &handle);
 515
 516         PP_ASSERT_WITH_CODE(kaddr,
 517                         "[vega10_smu_init] Out of memory for avfs fuse table.",
 518                         kfree(smumgr->backend);
 519                         cgs_free_gpu_mem(smumgr->device,
 520                         (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
 521                         cgs_free_gpu_mem(smumgr->device,
 522                         (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
 523                         cgs_free_gpu_mem(smumgr->device,
 524                         (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
 525                         cgs_free_gpu_mem(smumgr->device,
 526                         (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
 527                         cgs_free_gpu_mem(smumgr->device,
 528                         (cgs_handle_t)handle);
 529                         return -EINVAL);
 530
 531         priv->smu_tables.entry[AVFSFUSETABLE].version = 0x01;
 532         priv->smu_tables.entry[AVFSFUSETABLE].size = sizeof(AvfsFuseOverride_t);
 533         priv->smu_tables.entry[AVFSFUSETABLE].table_id = TABLE_AVFS_FUSE_OVERRIDE;
 534         priv->smu_tables.entry[AVFSFUSETABLE].table_addr_high =
 535                         smu_upper_32_bits(mc_addr);
 536         priv->smu_tables.entry[AVFSFUSETABLE].table_addr_low =
 537                         smu_lower_32_bits(mc_addr);
 538         priv->smu_tables.entry[AVFSFUSETABLE].table = kaddr;
 539         priv->smu_tables.entry[AVFSFUSETABLE].handle = handle;
 540
 541         return 0;
 542 }
 543
 544 static int vega10_smu_fini(struct pp_smumgr *smumgr)
 545 {
 546         struct vega10_smumgr *priv =
 547                         (struct vega10_smumgr *)(smumgr->backend);
 548
 549         if (priv) {
 550                 cgs_free_gpu_mem(smumgr->device,
 551                                 (cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
 552                 cgs_free_gpu_mem(smumgr->device,
 553                                 (cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
 554                 cgs_free_gpu_mem(smumgr->device,
 555                                 (cgs_handle_t)priv->smu_tables.entry[AVFSTABLE].handle);
 556                 if (priv->smu_tables.entry[TOOLSTABLE].table)
 557                         cgs_free_gpu_mem(smumgr->device,
 558                                         (cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
 559                 cgs_free_gpu_mem(smumgr->device,
 560                                 (cgs_handle_t)priv->smu_tables.entry[AVFSFUSETABLE].handle);
 561                 kfree(smumgr->backend);
 562                 smumgr->backend = NULL;
 563         }
 564         return 0;
 565 }
 566
 567 static int vega10_start_smu(struct pp_smumgr *smumgr)
 568 {
 569         PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr),
 570                         "Failed to verify SMC interface!",
 571                         return -EINVAL);
 572         return 0;
 573 }
 574
 575 const struct pp_smumgr_func vega10_smu_funcs = {
 576         .smu_init = &vega10_smu_init,
 577         .smu_fini = &vega10_smu_fini,
 578         .start_smu = &vega10_start_smu,
 579         .request_smu_load_specific_fw = NULL,
 580         .send_msg_to_smc = &vega10_send_msg_to_smc,
 581         .send_msg_to_smc_with_parameter = &vega10_send_msg_to_smc_with_parameter,
 582         .download_pptable_settings = NULL,
 583         .upload_pptable_settings = NULL,
 584 };