drivers/gpu/drm/arc/arcpgu_crtc.c

   1 /*
   2  * ARC PGU DRM driver.
   3  *
   4  * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_fb_cma_helper.h>
  20 #include <drm/drm_gem_cma_helper.h>
  21 #include <drm/drm_plane_helper.h>
  22 #include <linux/clk.h>
  23 #include <linux/platform_data/simplefb.h>
  24
  25 #include "arcpgu.h"
  26 #include "arcpgu_regs.h"
  27
  28 #define ENCODE_PGU_XY(x, y)     ((((x) - 1) << 16) | ((y) - 1))
  29
  30 static struct simplefb_format supported_formats[] = {
  31         { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
  32         { "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
  33 };
  34
  35 static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
  36 {
  37         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  38         const struct drm_framebuffer *fb = crtc->primary->state->fb;
  39         uint32_t pixel_format = fb->format->format;
  40         struct simplefb_format *format = NULL;
  41         int i;
  42
  43         for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
  44                 if (supported_formats[i].fourcc == pixel_format)
  45                         format = &supported_formats[i];
  46         }
  47
  48         if (WARN_ON(!format))
  49                 return;
  50
  51         if (format->fourcc == DRM_FORMAT_RGB888)
  52                 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
  53                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
  54                                            ARCPGU_MODE_RGB888_MASK);
  55
  56 }
  57
  58 static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
  59         .destroy = drm_crtc_cleanup,
  60         .set_config = drm_atomic_helper_set_config,
  61         .page_flip = drm_atomic_helper_page_flip,
  62         .reset = drm_atomic_helper_crtc_reset,
  63         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  64         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  65 };
  66
  67 static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
  68                                                     const struct drm_display_mode *mode)
  69 {
  70         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  71         long rate, clk_rate = mode->clock * 1000;
  72
  73         rate = clk_round_rate(arcpgu->clk, clk_rate);
  74         if (rate != clk_rate)
  75                 return MODE_NOCLOCK;
  76
  77         return MODE_OK;
  78 }
  79
  80 static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
  81 {
  82         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  83         struct drm_display_mode *m = &crtc->state->adjusted_mode;
  84         u32 val;
  85
  86         arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
  87                       ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
  88
  89         arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
  90                       ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
  91                                     m->crtc_hsync_end - m->crtc_hdisplay));
  92
  93         arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
  94                       ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
  95                                     m->crtc_vsync_end - m->crtc_vdisplay));
  96
  97         arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
  98                       ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
  99                                     m->crtc_vblank_end - m->crtc_vblank_start));
 100
 101         val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
 102
 103         if (m->flags & DRM_MODE_FLAG_PVSYNC)
 104                 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
 105         else
 106                 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
 107
 108         if (m->flags & DRM_MODE_FLAG_PHSYNC)
 109                 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
 110         else
 111                 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
 112
 113         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
 114         arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
 115         arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
 116
 117         arc_pgu_set_pxl_fmt(crtc);
 118
 119         clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
 120 }
 121
 122 static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
 123                                        struct drm_crtc_state *old_state)
 124 {
 125         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 126
 127         clk_prepare_enable(arcpgu->clk);
 128         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 129                       arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
 130                       ARCPGU_CTRL_ENABLE_MASK);
 131 }
 132
 133 static void arc_pgu_crtc_disable(struct drm_crtc *crtc)
 134 {
 135         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 136
 137         if (!crtc->primary->fb)
 138                 return;
 139
 140         clk_disable_unprepare(arcpgu->clk);
 141         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 142                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
 143                               ~ARCPGU_CTRL_ENABLE_MASK);
 144 }
 145
 146 static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
 147                                       struct drm_crtc_state *state)
 148 {
 149         struct drm_pending_vblank_event *event = crtc->state->event;
 150
 151         if (event) {
 152                 crtc->state->event = NULL;
 153
 154                 spin_lock_irq(&crtc->dev->event_lock);
 155                 drm_crtc_send_vblank_event(crtc, event);
 156                 spin_unlock_irq(&crtc->dev->event_lock);
 157         }
 158 }
 159
 160 static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
 161         .mode_valid     = arc_pgu_crtc_mode_valid,
 162         .mode_set       = drm_helper_crtc_mode_set,
 163         .mode_set_base  = drm_helper_crtc_mode_set_base,
 164         .mode_set_nofb  = arc_pgu_crtc_mode_set_nofb,
 165         .disable        = arc_pgu_crtc_disable,
 166         .atomic_begin   = arc_pgu_crtc_atomic_begin,
 167         .atomic_enable  = arc_pgu_crtc_atomic_enable,
 168 };
 169
 170 static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
 171                                         struct drm_plane_state *state)
 172 {
 173         struct arcpgu_drm_private *arcpgu;
 174         struct drm_gem_cma_object *gem;
 175
 176         if (!plane->state->crtc || !plane->state->fb)
 177                 return;
 178
 179         arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
 180         gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
 181         arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
 182 }
 183
 184 static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
 185         .atomic_update = arc_pgu_plane_atomic_update,
 186 };
 187
 188 static void arc_pgu_plane_destroy(struct drm_plane *plane)
 189 {
 190         drm_plane_helper_disable(plane);
 191         drm_plane_cleanup(plane);
 192 }
 193
 194 static const struct drm_plane_funcs arc_pgu_plane_funcs = {
 195         .update_plane           = drm_atomic_helper_update_plane,
 196         .disable_plane          = drm_atomic_helper_disable_plane,
 197         .destroy                = arc_pgu_plane_destroy,
 198         .reset                  = drm_atomic_helper_plane_reset,
 199         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 200         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 201 };
 202
 203 static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
 204 {
 205         struct arcpgu_drm_private *arcpgu = drm->dev_private;
 206         struct drm_plane *plane = NULL;
 207         u32 formats[ARRAY_SIZE(supported_formats)], i;
 208         int ret;
 209
 210         plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
 211         if (!plane)
 212                 return ERR_PTR(-ENOMEM);
 213
 214         for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
 215                 formats[i] = supported_formats[i].fourcc;
 216
 217         ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
 218                                        formats, ARRAY_SIZE(formats),
 219                                        DRM_PLANE_TYPE_PRIMARY, NULL);
 220         if (ret)
 221                 return ERR_PTR(ret);
 222
 223         drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
 224         arcpgu->plane = plane;
 225
 226         return plane;
 227 }
 228
 229 int arc_pgu_setup_crtc(struct drm_device *drm)
 230 {
 231         struct arcpgu_drm_private *arcpgu = drm->dev_private;
 232         struct drm_plane *primary;
 233         int ret;
 234
 235         primary = arc_pgu_plane_init(drm);
 236         if (IS_ERR(primary))
 237                 return PTR_ERR(primary);
 238
 239         ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
 240                                         &arc_pgu_crtc_funcs, NULL);
 241         if (ret) {
 242                 arc_pgu_plane_destroy(primary);
 243                 return ret;
 244         }
 245
 246         drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
 247         return 0;
 248 }