drivers/gpu/drm/arm/hdlcd_crtc.c

   1 /*
   2  * Copyright (C) 2013-2015 ARM Limited
   3  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive
   7  * for more details.
   8  *
   9  *  Implementation of a CRTC class for the HDLCD driver.
  10  */
  11
  12 #include <drm/drmP.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_crtc.h>
  15 #include <drm/drm_crtc_helper.h>
  16 #include <drm/drm_fb_helper.h>
  17 #include <drm/drm_fb_cma_helper.h>
  18 #include <drm/drm_gem_cma_helper.h>
  19 #include <drm/drm_of.h>
  20 #include <drm/drm_plane_helper.h>
  21 #include <linux/clk.h>
  22 #include <linux/of_graph.h>
  23 #include <linux/platform_data/simplefb.h>
  24 #include <video/videomode.h>
  25
  26 #include "hdlcd_drv.h"
  27 #include "hdlcd_regs.h"
  28
  29 /*
  30  * The HDLCD controller is a dumb RGB streamer that gets connected to
  31  * a single HDMI transmitter or in the case of the ARM Models it gets
  32  * emulated by the software that does the actual rendering.
  33  *
  34  */
  35
  36 static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
  37 {
  38         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
  39
  40         /* stop the controller on cleanup */
  41         hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
  42         drm_crtc_cleanup(crtc);
  43 }
  44
  45 static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc)
  46 {
  47         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
  48         unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
  49
  50         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
  51
  52         return 0;
  53 }
  54
  55 static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc)
  56 {
  57         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
  58         unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
  59
  60         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
  61 }
  62
  63 static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
  64         .destroy = hdlcd_crtc_cleanup,
  65         .set_config = drm_atomic_helper_set_config,
  66         .page_flip = drm_atomic_helper_page_flip,
  67         .reset = drm_atomic_helper_crtc_reset,
  68         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  69         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  70         .enable_vblank = hdlcd_crtc_enable_vblank,
  71         .disable_vblank = hdlcd_crtc_disable_vblank,
  72 };
  73
  74 static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS;
  75
  76 /*
  77  * Setup the HDLCD registers for decoding the pixels out of the framebuffer
  78  */
  79 static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
  80 {
  81         unsigned int btpp;
  82         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
  83         const struct drm_framebuffer *fb = crtc->primary->state->fb;
  84         uint32_t pixel_format;
  85         struct simplefb_format *format = NULL;
  86         int i;
  87
  88         pixel_format = fb->format->format;
  89
  90         for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
  91                 if (supported_formats[i].fourcc == pixel_format)
  92                         format = &supported_formats[i];
  93         }
  94
  95         if (WARN_ON(!format))
  96                 return 0;
  97
  98         /* HDLCD uses 'bytes per pixel', zero means 1 byte */
  99         btpp = (format->bits_per_pixel + 7) / 8;
 100         hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
 101
 102         /*
 103          * The format of the HDLCD_REG_<color>_SELECT register is:
 104          *   - bits[23:16] - default value for that color component
 105          *   - bits[11:8]  - number of bits to extract for each color component
 106          *   - bits[4:0]   - index of the lowest bit to extract
 107          *
 108          * The default color value is used when bits[11:8] are zero, when the
 109          * pixel is outside the visible frame area or when there is a
 110          * buffer underrun.
 111          */
 112         hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
 113 #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
 114                     0x00ff0000 |        /* show underruns in red */
 115 #endif
 116                     ((format->red.length & 0xf) << 8));
 117         hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
 118                     ((format->green.length & 0xf) << 8));
 119         hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
 120                     ((format->blue.length & 0xf) << 8));
 121
 122         return 0;
 123 }
 124
 125 static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
 126 {
 127         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
 128         struct drm_display_mode *m = &crtc->state->adjusted_mode;
 129         struct videomode vm;
 130         unsigned int polarities, err;
 131
 132         vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
 133         vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
 134         vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
 135         vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
 136         vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
 137         vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
 138
 139         polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA;
 140
 141         if (m->flags & DRM_MODE_FLAG_PHSYNC)
 142                 polarities |= HDLCD_POLARITY_HSYNC;
 143         if (m->flags & DRM_MODE_FLAG_PVSYNC)
 144                 polarities |= HDLCD_POLARITY_VSYNC;
 145
 146         /* Allow max number of outstanding requests and largest burst size */
 147         hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
 148                     HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);
 149
 150         hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
 151         hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
 152         hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
 153         hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
 154         hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
 155         hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
 156         hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
 157         hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
 158         hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
 159
 160         err = hdlcd_set_pxl_fmt(crtc);
 161         if (err)
 162                 return;
 163
 164         clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
 165 }
 166
 167 static void hdlcd_crtc_enable(struct drm_crtc *crtc)
 168 {
 169         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
 170
 171         clk_prepare_enable(hdlcd->clk);
 172         hdlcd_crtc_mode_set_nofb(crtc);
 173         hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
 174         drm_crtc_vblank_on(crtc);
 175 }
 176
 177 static void hdlcd_crtc_disable(struct drm_crtc *crtc)
 178 {
 179         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
 180
 181         drm_crtc_vblank_off(crtc);
 182         hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
 183         clk_disable_unprepare(hdlcd->clk);
 184 }
 185
 186 static int hdlcd_crtc_atomic_check(struct drm_crtc *crtc,
 187                                    struct drm_crtc_state *state)
 188 {
 189         struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
 190         struct drm_display_mode *mode = &state->adjusted_mode;
 191         long rate, clk_rate = mode->clock * 1000;
 192
 193         rate = clk_round_rate(hdlcd->clk, clk_rate);
 194         if (rate != clk_rate) {
 195                 /* clock required by mode not supported by hardware */
 196                 return -EINVAL;
 197         }
 198
 199         return 0;
 200 }
 201
 202 static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
 203                                     struct drm_crtc_state *state)
 204 {
 205         struct drm_pending_vblank_event *event = crtc->state->event;
 206
 207         if (event) {
 208                 crtc->state->event = NULL;
 209
 210                 spin_lock_irq(&crtc->dev->event_lock);
 211                 if (drm_crtc_vblank_get(crtc) == 0)
 212                         drm_crtc_arm_vblank_event(crtc, event);
 213                 else
 214                         drm_crtc_send_vblank_event(crtc, event);
 215                 spin_unlock_irq(&crtc->dev->event_lock);
 216         }
 217 }
 218
 219 static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
 220         .enable         = hdlcd_crtc_enable,
 221         .disable        = hdlcd_crtc_disable,
 222         .atomic_check   = hdlcd_crtc_atomic_check,
 223         .atomic_begin   = hdlcd_crtc_atomic_begin,
 224 };
 225
 226 static int hdlcd_plane_atomic_check(struct drm_plane *plane,
 227                                     struct drm_plane_state *state)
 228 {
 229         u32 src_w, src_h;
 230
 231         src_w = state->src_w >> 16;
 232         src_h = state->src_h >> 16;
 233
 234         /* we can't do any scaling of the plane source */
 235         if ((src_w != state->crtc_w) || (src_h != state->crtc_h))
 236                 return -EINVAL;
 237
 238         return 0;
 239 }
 240
 241 static void hdlcd_plane_atomic_update(struct drm_plane *plane,
 242                                       struct drm_plane_state *state)
 243 {
 244         struct drm_framebuffer *fb = plane->state->fb;
 245         struct hdlcd_drm_private *hdlcd;
 246         struct drm_gem_cma_object *gem;
 247         u32 src_w, src_h, dest_w, dest_h;
 248         dma_addr_t scanout_start;
 249
 250         if (!fb)
 251                 return;
 252
 253         src_w = plane->state->src_w >> 16;
 254         src_h = plane->state->src_h >> 16;
 255         dest_w = plane->state->crtc_w;
 256         dest_h = plane->state->crtc_h;
 257         gem = drm_fb_cma_get_gem_obj(fb, 0);
 258         scanout_start = gem->paddr + fb->offsets[0] +
 259                 plane->state->crtc_y * fb->pitches[0] +
 260                 plane->state->crtc_x *
 261                 fb->format->cpp[0];
 262
 263         hdlcd = plane->dev->dev_private;
 264         hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
 265         hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
 266         hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
 267         hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
 268 }
 269
 270 static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
 271         .atomic_check = hdlcd_plane_atomic_check,
 272         .atomic_update = hdlcd_plane_atomic_update,
 273 };
 274
 275 static void hdlcd_plane_destroy(struct drm_plane *plane)
 276 {
 277         drm_plane_helper_disable(plane);
 278         drm_plane_cleanup(plane);
 279 }
 280
 281 static const struct drm_plane_funcs hdlcd_plane_funcs = {
 282         .update_plane           = drm_atomic_helper_update_plane,
 283         .disable_plane          = drm_atomic_helper_disable_plane,
 284         .destroy                = hdlcd_plane_destroy,
 285         .reset                  = drm_atomic_helper_plane_reset,
 286         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 287         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 288 };
 289
 290 static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
 291 {
 292         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 293         struct drm_plane *plane = NULL;
 294         u32 formats[ARRAY_SIZE(supported_formats)], i;
 295         int ret;
 296
 297         plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
 298         if (!plane)
 299                 return ERR_PTR(-ENOMEM);
 300
 301         for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
 302                 formats[i] = supported_formats[i].fourcc;
 303
 304         ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs,
 305                                        formats, ARRAY_SIZE(formats),
 306                                        DRM_PLANE_TYPE_PRIMARY, NULL);
 307         if (ret) {
 308                 devm_kfree(drm->dev, plane);
 309                 return ERR_PTR(ret);
 310         }
 311
 312         drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
 313         hdlcd->plane = plane;
 314
 315         return plane;
 316 }
 317
 318 int hdlcd_setup_crtc(struct drm_device *drm)
 319 {
 320         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 321         struct drm_plane *primary;
 322         int ret;
 323
 324         primary = hdlcd_plane_init(drm);
 325         if (IS_ERR(primary))
 326                 return PTR_ERR(primary);
 327
 328         ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
 329                                         &hdlcd_crtc_funcs, NULL);
 330         if (ret) {
 331                 hdlcd_plane_destroy(primary);
 332                 devm_kfree(drm->dev, primary);
 333                 return ret;
 334         }
 335
 336         drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
 337         return 0;
 338 }