drivers/gpu/drm/arm/malidp_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   4  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   5  *
   6  * ARM Mali DP500/DP550/DP650 registers definition.
   7  */
   8
   9 #ifndef __MALIDP_REGS_H__
  10 #define __MALIDP_REGS_H__
  11
  12 /*
  13  * abbreviations used:
  14  *    - DC - display core (general settings)
  15  *    - DE - display engine
  16  *    - SE - scaling engine
  17  */
  18
  19 /* interrupt bit masks */
  20 #define MALIDP_DE_IRQ_UNDERRUN                  (1 << 0)
  21
  22 #define MALIDP500_DE_IRQ_AXI_ERR                (1 << 4)
  23 #define MALIDP500_DE_IRQ_VSYNC                  (1 << 5)
  24 #define MALIDP500_DE_IRQ_PROG_LINE              (1 << 6)
  25 #define MALIDP500_DE_IRQ_SATURATION             (1 << 7)
  26 #define MALIDP500_DE_IRQ_CONF_VALID             (1 << 8)
  27 #define MALIDP500_DE_IRQ_CONF_MODE              (1 << 11)
  28 #define MALIDP500_DE_IRQ_CONF_ACTIVE            (1 << 17)
  29 #define MALIDP500_DE_IRQ_PM_ACTIVE              (1 << 18)
  30 #define MALIDP500_DE_IRQ_TESTMODE_ACTIVE        (1 << 19)
  31 #define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE      (1 << 24)
  32 #define MALIDP500_DE_IRQ_AXI_BUSY               (1 << 28)
  33 #define MALIDP500_DE_IRQ_GLOBAL                 (1 << 31)
  34 #define MALIDP500_SE_IRQ_CONF_MODE              (1 << 0)
  35 #define MALIDP500_SE_IRQ_CONF_VALID             (1 << 4)
  36 #define MALIDP500_SE_IRQ_INIT_BUSY              (1 << 5)
  37 #define MALIDP500_SE_IRQ_AXI_ERROR              (1 << 8)
  38 #define MALIDP500_SE_IRQ_OVERRUN                (1 << 9)
  39 #define MALIDP500_SE_IRQ_PROG_LINE1             (1 << 12)
  40 #define MALIDP500_SE_IRQ_PROG_LINE2             (1 << 13)
  41 #define MALIDP500_SE_IRQ_CONF_ACTIVE            (1 << 17)
  42 #define MALIDP500_SE_IRQ_PM_ACTIVE              (1 << 18)
  43 #define MALIDP500_SE_IRQ_AXI_BUSY               (1 << 28)
  44 #define MALIDP500_SE_IRQ_GLOBAL                 (1 << 31)
  45
  46 #define MALIDP550_DE_IRQ_SATURATION             (1 << 8)
  47 #define MALIDP550_DE_IRQ_VSYNC                  (1 << 12)
  48 #define MALIDP550_DE_IRQ_PROG_LINE              (1 << 13)
  49 #define MALIDP550_DE_IRQ_AXI_ERR                (1 << 16)
  50 #define MALIDP550_SE_IRQ_EOW                    (1 << 0)
  51 #define MALIDP550_SE_IRQ_AXI_ERR                (1 << 16)
  52 #define MALIDP550_SE_IRQ_OVR                    (1 << 17)
  53 #define MALIDP550_SE_IRQ_IBSY                   (1 << 18)
  54 #define MALIDP550_DC_IRQ_CONF_VALID             (1 << 0)
  55 #define MALIDP550_DC_IRQ_CONF_MODE              (1 << 4)
  56 #define MALIDP550_DC_IRQ_CONF_ACTIVE            (1 << 16)
  57 #define MALIDP550_DC_IRQ_DE                     (1 << 20)
  58 #define MALIDP550_DC_IRQ_SE                     (1 << 24)
  59
  60 #define MALIDP650_DE_IRQ_DRIFT                  (1 << 4)
  61 #define MALIDP650_DE_IRQ_ACEV1                  (1 << 17)
  62 #define MALIDP650_DE_IRQ_ACEV2                  (1 << 18)
  63 #define MALIDP650_DE_IRQ_ACEG                   (1 << 19)
  64 #define MALIDP650_DE_IRQ_AXIEP                  (1 << 28)
  65
  66 /* bit masks that are common between products */
  67 #define   MALIDP_CFG_VALID              (1 << 0)
  68 #define   MALIDP_DISP_FUNC_GAMMA        (1 << 0)
  69 #define   MALIDP_DISP_FUNC_CADJ         (1 << 4)
  70 #define   MALIDP_DISP_FUNC_ILACED       (1 << 8)
  71 #define   MALIDP_SCALE_ENGINE_EN        (1 << 16)
  72 #define   MALIDP_SE_MEMWRITE_EN         (2 << 5)
  73
  74 /* register offsets for IRQ management */
  75 #define MALIDP_REG_STATUS               0x00000
  76 #define MALIDP_REG_SETIRQ               0x00004
  77 #define MALIDP_REG_MASKIRQ              0x00008
  78 #define MALIDP_REG_CLEARIRQ             0x0000c
  79
  80 /* register offsets */
  81 #define MALIDP_DE_CORE_ID               0x00018
  82 #define MALIDP_DE_DISPLAY_FUNC          0x00020
  83
  84 /* these offsets are relative to MALIDP5x0_TIMINGS_BASE */
  85 #define MALIDP_DE_H_TIMINGS             0x0
  86 #define MALIDP_DE_V_TIMINGS             0x4
  87 #define MALIDP_DE_SYNC_WIDTH            0x8
  88 #define MALIDP_DE_HV_ACTIVE             0xc
  89
  90 /* Stride register offsets relative to Lx_BASE */
  91 #define MALIDP_DE_LG_STRIDE             0x18
  92 #define MALIDP_DE_LV_STRIDE0            0x18
  93 #define MALIDP550_DE_LS_R1_STRIDE       0x28
  94
  95 /* macros to set values into registers */
  96 #define MALIDP_DE_H_FRONTPORCH(x)       (((x) & 0xfff) << 0)
  97 #define MALIDP_DE_H_BACKPORCH(x)        (((x) & 0x3ff) << 16)
  98 #define MALIDP500_DE_V_FRONTPORCH(x)    (((x) & 0xff) << 0)
  99 #define MALIDP550_DE_V_FRONTPORCH(x)    (((x) & 0xfff) << 0)
 100 #define MALIDP_DE_V_BACKPORCH(x)        (((x) & 0xff) << 16)
 101 #define MALIDP_DE_H_SYNCWIDTH(x)        (((x) & 0x3ff) << 0)
 102 #define MALIDP_DE_V_SYNCWIDTH(x)        (((x) & 0xff) << 16)
 103 #define MALIDP_DE_H_ACTIVE(x)           (((x) & 0x1fff) << 0)
 104 #define MALIDP_DE_V_ACTIVE(x)           (((x) & 0x1fff) << 16)
 105
 106 #define MALIDP_PRODUCT_ID(__core_id) ((u32)(__core_id) >> 16)
 107
 108 /* register offsets relative to MALIDP5x0_COEFFS_BASE */
 109 #define MALIDP_COLOR_ADJ_COEF           0x00000
 110 #define MALIDP_COEF_TABLE_ADDR          0x00030
 111 #define MALIDP_COEF_TABLE_DATA          0x00034
 112
 113 /* Scaling engine registers and masks. */
 114 #define   MALIDP_SE_SCALING_EN                  (1 << 0)
 115 #define   MALIDP_SE_ALPHA_EN                    (1 << 1)
 116 #define   MALIDP_SE_ENH_MASK                    3
 117 #define   MALIDP_SE_ENH(x)                      (((x) & MALIDP_SE_ENH_MASK) << 2)
 118 #define   MALIDP_SE_RGBO_IF_EN                  (1 << 4)
 119 #define   MALIDP550_SE_CTL_SEL_MASK             7
 120 #define   MALIDP550_SE_CTL_VCSEL(x) \
 121                 (((x) & MALIDP550_SE_CTL_SEL_MASK) << 20)
 122 #define   MALIDP550_SE_CTL_HCSEL(x) \
 123                 (((x) & MALIDP550_SE_CTL_SEL_MASK) << 16)
 124
 125 /* Blocks with offsets from SE_CONTROL register. */
 126 #define MALIDP_SE_LAYER_CONTROL                 0x14
 127 #define   MALIDP_SE_L0_IN_SIZE                  0x00
 128 #define   MALIDP_SE_L0_OUT_SIZE                 0x04
 129 #define   MALIDP_SE_SET_V_SIZE(x)               (((x) & 0x1fff) << 16)
 130 #define   MALIDP_SE_SET_H_SIZE(x)               (((x) & 0x1fff) << 0)
 131 #define MALIDP_SE_SCALING_CONTROL               0x24
 132 #define   MALIDP_SE_H_INIT_PH                   0x00
 133 #define   MALIDP_SE_H_DELTA_PH                  0x04
 134 #define   MALIDP_SE_V_INIT_PH                   0x08
 135 #define   MALIDP_SE_V_DELTA_PH                  0x0c
 136 #define   MALIDP_SE_COEFFTAB_ADDR               0x10
 137 #define     MALIDP_SE_COEFFTAB_ADDR_MASK        0x7f
 138 #define     MALIDP_SE_V_COEFFTAB                (1 << 8)
 139 #define     MALIDP_SE_H_COEFFTAB                (1 << 9)
 140 #define     MALIDP_SE_SET_V_COEFFTAB_ADDR(x) \
 141                 (MALIDP_SE_V_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK))
 142 #define     MALIDP_SE_SET_H_COEFFTAB_ADDR(x) \
 143                 (MALIDP_SE_H_COEFFTAB | ((x) & MALIDP_SE_COEFFTAB_ADDR_MASK))
 144 #define   MALIDP_SE_COEFFTAB_DATA               0x14
 145 #define     MALIDP_SE_COEFFTAB_DATA_MASK        0x3fff
 146 #define     MALIDP_SE_SET_COEFFTAB_DATA(x) \
 147                 ((x) & MALIDP_SE_COEFFTAB_DATA_MASK)
 148 /* Enhance coeffents reigster offset */
 149 #define MALIDP_SE_IMAGE_ENH                     0x3C
 150 /* ENH_LIMITS offset 0x0 */
 151 #define     MALIDP_SE_ENH_LOW_LEVEL             24
 152 #define     MALIDP_SE_ENH_HIGH_LEVEL            63
 153 #define     MALIDP_SE_ENH_LIMIT_MASK            0xfff
 154 #define     MALIDP_SE_SET_ENH_LIMIT_LOW(x) \
 155                 ((x) & MALIDP_SE_ENH_LIMIT_MASK)
 156 #define     MALIDP_SE_SET_ENH_LIMIT_HIGH(x) \
 157                 (((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16)
 158 #define   MALIDP_SE_ENH_COEFF0                  0x04
 159
 160
 161 /* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */
 162 #define MALIDP_MW_FORMAT                0x00000
 163 #define MALIDP_MW_P1_STRIDE             0x00004
 164 #define MALIDP_MW_P2_STRIDE             0x00008
 165 #define MALIDP_MW_P1_PTR_LOW            0x0000c
 166 #define MALIDP_MW_P1_PTR_HIGH           0x00010
 167 #define MALIDP_MW_P2_PTR_LOW            0x0002c
 168 #define MALIDP_MW_P2_PTR_HIGH           0x00030
 169
 170 /* register offsets and bits specific to DP500 */
 171 #define MALIDP500_ADDR_SPACE_SIZE       0x01000
 172 #define MALIDP500_DC_BASE               0x00000
 173 #define MALIDP500_DC_CONTROL            0x0000c
 174 #define   MALIDP500_DC_CONFIG_REQ       (1 << 17)
 175 #define   MALIDP500_HSYNCPOL            (1 << 20)
 176 #define   MALIDP500_VSYNCPOL            (1 << 21)
 177 #define   MALIDP500_DC_CLEAR_MASK       0x300fff
 178 #define MALIDP500_DE_LINE_COUNTER       0x00010
 179 #define MALIDP500_DE_AXI_CONTROL        0x00014
 180 #define MALIDP500_DE_SECURE_CTRL        0x0001c
 181 #define MALIDP500_DE_CHROMA_KEY         0x00024
 182 #define MALIDP500_TIMINGS_BASE          0x00028
 183
 184 #define MALIDP500_CONFIG_3D             0x00038
 185 #define MALIDP500_BGND_COLOR            0x0003c
 186 #define MALIDP500_OUTPUT_DEPTH          0x00044
 187 #define MALIDP500_COEFFS_BASE           0x00078
 188
 189 /*
 190  * The YUV2RGB coefficients on the DP500 are not in the video layer's register
 191  * block. They belong in a separate block above the layer's registers, hence
 192  * the negative offset.
 193  */
 194 #define MALIDP500_LV_YUV2RGB            ((s16)(-0xB8))
 195 #define MALIDP500_DE_LV_BASE            0x00100
 196 #define MALIDP500_DE_LV_PTR_BASE        0x00124
 197 #define MALIDP500_DE_LV_AD_CTRL         0x00400
 198 #define MALIDP500_DE_LG1_BASE           0x00200
 199 #define MALIDP500_DE_LG1_PTR_BASE       0x0021c
 200 #define MALIDP500_DE_LG1_AD_CTRL        0x0040c
 201 #define MALIDP500_DE_LG2_BASE           0x00300
 202 #define MALIDP500_DE_LG2_PTR_BASE       0x0031c
 203 #define MALIDP500_DE_LG2_AD_CTRL        0x00418
 204 #define MALIDP500_SE_BASE               0x00c00
 205 #define MALIDP500_SE_CONTROL            0x00c0c
 206 #define MALIDP500_SE_MEMWRITE_OUT_SIZE  0x00c2c
 207 #define MALIDP500_SE_RGB_YUV_COEFFS     0x00C74
 208 #define MALIDP500_SE_MEMWRITE_BASE      0x00e00
 209 #define MALIDP500_DC_IRQ_BASE           0x00f00
 210 #define MALIDP500_CONFIG_VALID          0x00f00
 211 #define MALIDP500_CONFIG_ID             0x00fd4
 212
 213 /* register offsets and bits specific to DP550/DP650 */
 214 #define MALIDP550_ADDR_SPACE_SIZE       0x10000
 215 #define MALIDP550_DE_CONTROL            0x00010
 216 #define MALIDP550_DE_LINE_COUNTER       0x00014
 217 #define MALIDP550_DE_AXI_CONTROL        0x00018
 218 #define MALIDP550_DE_QOS                0x0001c
 219 #define MALIDP550_TIMINGS_BASE          0x00030
 220 #define MALIDP550_HSYNCPOL              (1 << 12)
 221 #define MALIDP550_VSYNCPOL              (1 << 28)
 222
 223 #define MALIDP550_DE_DISP_SIDEBAND      0x00040
 224 #define MALIDP550_DE_BGND_COLOR         0x00044
 225 #define MALIDP550_DE_OUTPUT_DEPTH       0x0004c
 226 #define MALIDP550_COEFFS_BASE           0x00050
 227 #define MALIDP550_LV_YUV2RGB            0x00084
 228 #define MALIDP550_DE_LV1_BASE           0x00100
 229 #define MALIDP550_DE_LV1_PTR_BASE       0x00124
 230 #define MALIDP550_DE_LV1_AD_CTRL        0x001B8
 231 #define MALIDP550_DE_LV2_BASE           0x00200
 232 #define MALIDP550_DE_LV2_PTR_BASE       0x00224
 233 #define MALIDP550_DE_LV2_AD_CTRL        0x002B8
 234 #define MALIDP550_DE_LG_BASE            0x00300
 235 #define MALIDP550_DE_LG_PTR_BASE        0x0031c
 236 #define MALIDP550_DE_LG_AD_CTRL         0x00330
 237 #define MALIDP550_DE_LS_BASE            0x00400
 238 #define MALIDP550_DE_LS_PTR_BASE        0x0042c
 239 #define MALIDP550_DE_PERF_BASE          0x00500
 240 #define MALIDP550_SE_BASE               0x08000
 241 #define MALIDP550_SE_CONTROL            0x08010
 242 #define   MALIDP550_SE_MEMWRITE_ONESHOT (1 << 7)
 243 #define MALIDP550_SE_MEMWRITE_OUT_SIZE  0x08030
 244 #define MALIDP550_SE_RGB_YUV_COEFFS     0x08078
 245 #define MALIDP550_SE_MEMWRITE_BASE      0x08100
 246 #define MALIDP550_DC_BASE               0x0c000
 247 #define MALIDP550_DC_CONTROL            0x0c010
 248 #define   MALIDP550_DC_CONFIG_REQ       (1 << 16)
 249 #define MALIDP550_CONFIG_VALID          0x0c014
 250 #define MALIDP550_CONFIG_ID             0x0ffd4
 251
 252 /* register offsets specific to DP650 */
 253 #define MALIDP650_DE_LV_MMU_CTRL        0x000D0
 254 #define MALIDP650_DE_LG_MMU_CTRL        0x00048
 255 #define MALIDP650_DE_LS_MMU_CTRL        0x00078
 256
 257 /* bit masks to set the MMU control register */
 258 #define MALIDP_MMU_CTRL_EN              (1 << 0)
 259 #define MALIDP_MMU_CTRL_MODE            (1 << 4)
 260 #define MALIDP_MMU_CTRL_PX_PS(x)        (1 << (8 + (x)))
 261 #define MALIDP_MMU_CTRL_PP_NUM_REQ(x)   (((x) & 0x7f) << 12)
 262
 263 /* AFBC register offsets relative to MALIDPXXX_DE_LX_AD_CTRL */
 264 /* The following register offsets are common for DP500, DP550 and DP650 */
 265 #define MALIDP_AD_CROP_H                0x4
 266 #define MALIDP_AD_CROP_V                0x8
 267 #define MALIDP_AD_END_PTR_LOW           0xc
 268 #define MALIDP_AD_END_PTR_HIGH          0x10
 269
 270 /* AFBC decoder Registers */
 271 #define MALIDP_AD_EN                    BIT(0)
 272 #define MALIDP_AD_YTR                   BIT(4)
 273 #define MALIDP_AD_BS                    BIT(8)
 274 #define MALIDP_AD_CROP_RIGHT_OFFSET     16
 275 #define MALIDP_AD_CROP_BOTTOM_OFFSET    16
 276
 277 /*
 278  * Starting with DP550 the register map blocks has been standardised to the
 279  * following layout:
 280  *
 281  *   Offset            Block registers
 282  *  0x00000            Display Engine
 283  *  0x08000            Scaling Engine
 284  *  0x0c000            Display Core
 285  *  0x10000            Secure control
 286  *
 287  * The old DP500 IP mixes some DC with the DE registers, hence the need
 288  * for a mapping structure.
 289  */
 290
 291 #endif /* __MALIDP_REGS_H__ */