2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/component.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_plane_helper.h>
16 #include "armada_crtc.h"
17 #include "armada_drm.h"
18 #include "armada_fb.h"
19 #include "armada_gem.h"
20 #include "armada_hw.h"
21 #include "armada_trace.h"
23 struct armada_frame_work
{
24 struct armada_plane_work work
;
25 struct drm_pending_vblank_event
*event
;
26 struct armada_regs regs
[4];
27 struct drm_framebuffer
*old_fb
;
38 static const uint32_t armada_primary_formats
[] = {
56 * A note about interlacing. Let's consider HDMI 1920x1080i.
57 * The timing parameters we have from X are:
58 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
59 * 1920 2448 2492 2640 1080 1084 1094 1125
60 * Which get translated to:
61 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
62 * 1920 2448 2492 2640 540 542 547 562
64 * This is how it is defined by CEA-861-D - line and pixel numbers are
65 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
66 * line: 2640. The odd frame, the first active line is at line 21, and
67 * the even frame, the first active line is 584.
69 * LN: 560 561 562 563 567 568 569
70 * DE: ~~~|____________________________//__________________________
71 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
72 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
73 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
75 * LN: 1123 1124 1125 1 5 6 7
76 * DE: ~~~|____________________________//__________________________
77 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
78 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
81 * The Armada LCD Controller line and pixel numbers are, like X timings,
82 * referenced to the top left of the active frame.
84 * So, translating these to our LCD controller:
85 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
86 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
87 * Note: Vsync front porch remains constant!
90 * vtotal = mode->crtc_vtotal + 1;
91 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
92 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
94 * vtotal = mode->crtc_vtotal;
95 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
96 * vhorizpos = mode->crtc_hsync_start;
98 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
100 * So, we need to reprogram these registers on each vsync event:
101 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
103 * Note: we do not use the frame done interrupts because these appear
104 * to happen too early, and lead to jitter on the display (presumably
105 * they occur at the end of the last active line, before the vsync back
106 * porch, which we're reprogramming.)
110 armada_drm_crtc_update_regs(struct armada_crtc
*dcrtc
, struct armada_regs
*regs
)
112 while (regs
->offset
!= ~0) {
113 void __iomem
*reg
= dcrtc
->base
+ regs
->offset
;
118 val
&= readl_relaxed(reg
);
119 writel_relaxed(val
| regs
->val
, reg
);
124 #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
126 static void armada_drm_crtc_update(struct armada_crtc
*dcrtc
)
130 dumb_ctrl
= dcrtc
->cfg_dumb_ctrl
;
132 if (!dpms_blanked(dcrtc
->dpms
))
133 dumb_ctrl
|= CFG_DUMB_ENA
;
136 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
137 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
138 * force LCD_D[23:0] to output blank color, overriding the GPIO or
139 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
141 if (dpms_blanked(dcrtc
->dpms
) &&
142 (dumb_ctrl
& DUMB_MASK
) == DUMB24_RGB888_0
) {
143 dumb_ctrl
&= ~DUMB_MASK
;
144 dumb_ctrl
|= DUMB_BLANK
;
148 * The documentation doesn't indicate what the normal state of
149 * the sync signals are. Sebastian Hesselbart kindly probed
150 * these signals on his board to determine their state.
152 * The non-inverted state of the sync signals is active high.
153 * Setting these bits makes the appropriate signal active low.
155 if (dcrtc
->crtc
.mode
.flags
& DRM_MODE_FLAG_NCSYNC
)
156 dumb_ctrl
|= CFG_INV_CSYNC
;
157 if (dcrtc
->crtc
.mode
.flags
& DRM_MODE_FLAG_NHSYNC
)
158 dumb_ctrl
|= CFG_INV_HSYNC
;
159 if (dcrtc
->crtc
.mode
.flags
& DRM_MODE_FLAG_NVSYNC
)
160 dumb_ctrl
|= CFG_INV_VSYNC
;
162 if (dcrtc
->dumb_ctrl
!= dumb_ctrl
) {
163 dcrtc
->dumb_ctrl
= dumb_ctrl
;
164 writel_relaxed(dumb_ctrl
, dcrtc
->base
+ LCD_SPU_DUMB_CTRL
);
168 void armada_drm_plane_calc_addrs(u32
*addrs
, struct drm_framebuffer
*fb
,
171 u32 addr
= drm_fb_obj(fb
)->dev_addr
;
172 int num_planes
= fb
->format
->num_planes
;
178 for (i
= 0; i
< num_planes
; i
++)
179 addrs
[i
] = addr
+ fb
->offsets
[i
] + y
* fb
->pitches
[i
] +
180 x
* fb
->format
->cpp
[i
];
185 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer
*fb
,
186 int x
, int y
, struct armada_regs
*regs
, bool interlaced
)
188 unsigned pitch
= fb
->pitches
[0];
189 u32 addrs
[3], addr_odd
, addr_even
;
192 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
193 pitch
, x
, y
, fb
->format
->cpp
[0] * 8);
195 armada_drm_plane_calc_addrs(addrs
, fb
, x
, y
);
197 addr_odd
= addr_even
= addrs
[0];
204 /* write offset, base, and pitch */
205 armada_reg_queue_set(regs
, i
, addr_odd
, LCD_CFG_GRA_START_ADDR0
);
206 armada_reg_queue_set(regs
, i
, addr_even
, LCD_CFG_GRA_START_ADDR1
);
207 armada_reg_queue_mod(regs
, i
, pitch
, 0xffff, LCD_CFG_GRA_PITCH
);
212 static void armada_drm_plane_work_run(struct armada_crtc
*dcrtc
,
213 struct drm_plane
*plane
)
215 struct armada_plane
*dplane
= drm_to_armada_plane(plane
);
216 struct armada_plane_work
*work
= xchg(&dplane
->work
, NULL
);
218 /* Handle any pending frame work. */
220 work
->fn(dcrtc
, dplane
, work
);
221 drm_crtc_vblank_put(&dcrtc
->crtc
);
224 wake_up(&dplane
->frame_wait
);
227 int armada_drm_plane_work_queue(struct armada_crtc
*dcrtc
,
228 struct armada_plane
*plane
, struct armada_plane_work
*work
)
232 ret
= drm_crtc_vblank_get(&dcrtc
->crtc
);
234 DRM_ERROR("failed to acquire vblank counter\n");
238 ret
= cmpxchg(&plane
->work
, NULL
, work
) ? -EBUSY
: 0;
240 drm_crtc_vblank_put(&dcrtc
->crtc
);
245 int armada_drm_plane_work_wait(struct armada_plane
*plane
, long timeout
)
247 return wait_event_timeout(plane
->frame_wait
, !plane
->work
, timeout
);
250 struct armada_plane_work
*armada_drm_plane_work_cancel(
251 struct armada_crtc
*dcrtc
, struct armada_plane
*plane
)
253 struct armada_plane_work
*work
= xchg(&plane
->work
, NULL
);
256 drm_crtc_vblank_put(&dcrtc
->crtc
);
261 static int armada_drm_crtc_queue_frame_work(struct armada_crtc
*dcrtc
,
262 struct armada_frame_work
*work
)
264 struct armada_plane
*plane
= drm_to_armada_plane(dcrtc
->crtc
.primary
);
266 return armada_drm_plane_work_queue(dcrtc
, plane
, &work
->work
);
269 static void armada_drm_crtc_complete_frame_work(struct armada_crtc
*dcrtc
,
270 struct armada_plane
*plane
, struct armada_plane_work
*work
)
272 struct armada_frame_work
*fwork
= container_of(work
, struct armada_frame_work
, work
);
273 struct drm_device
*dev
= dcrtc
->crtc
.dev
;
276 spin_lock_irqsave(&dcrtc
->irq_lock
, flags
);
277 armada_drm_crtc_update_regs(dcrtc
, fwork
->regs
);
278 spin_unlock_irqrestore(&dcrtc
->irq_lock
, flags
);
281 spin_lock_irqsave(&dev
->event_lock
, flags
);
282 drm_crtc_send_vblank_event(&dcrtc
->crtc
, fwork
->event
);
283 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
286 /* Finally, queue the process-half of the cleanup. */
287 __armada_drm_queue_unref_work(dcrtc
->crtc
.dev
, fwork
->old_fb
);
291 static void armada_drm_crtc_finish_fb(struct armada_crtc
*dcrtc
,
292 struct drm_framebuffer
*fb
, bool force
)
294 struct armada_frame_work
*work
;
300 /* Display is disabled, so just drop the old fb */
301 drm_framebuffer_put(fb
);
305 work
= kmalloc(sizeof(*work
), GFP_KERNEL
);
308 work
->work
.fn
= armada_drm_crtc_complete_frame_work
;
311 armada_reg_queue_end(work
->regs
, i
);
313 if (armada_drm_crtc_queue_frame_work(dcrtc
, work
) == 0)
320 * Oops - just drop the reference immediately and hope for
321 * the best. The worst that will happen is the buffer gets
322 * reused before it has finished being displayed.
324 drm_framebuffer_put(fb
);
327 static void armada_drm_vblank_off(struct armada_crtc
*dcrtc
)
330 * Tell the DRM core that vblank IRQs aren't going to happen for
331 * a while. This cleans up any pending vblank events for us.
333 drm_crtc_vblank_off(&dcrtc
->crtc
);
334 armada_drm_plane_work_run(dcrtc
, dcrtc
->crtc
.primary
);
337 /* The mode_config.mutex will be held for this call */
338 static void armada_drm_crtc_dpms(struct drm_crtc
*crtc
, int dpms
)
340 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
342 if (dpms_blanked(dcrtc
->dpms
) != dpms_blanked(dpms
)) {
343 if (dpms_blanked(dpms
))
344 armada_drm_vblank_off(dcrtc
);
345 else if (!IS_ERR(dcrtc
->clk
))
346 WARN_ON(clk_prepare_enable(dcrtc
->clk
));
348 armada_drm_crtc_update(dcrtc
);
349 if (!dpms_blanked(dpms
))
350 drm_crtc_vblank_on(&dcrtc
->crtc
);
351 else if (!IS_ERR(dcrtc
->clk
))
352 clk_disable_unprepare(dcrtc
->clk
);
353 } else if (dcrtc
->dpms
!= dpms
) {
359 * Prepare for a mode set. Turn off overlay to ensure that we don't end
360 * up with the overlay size being bigger than the active screen size.
361 * We rely upon X refreshing this state after the mode set has completed.
363 * The mode_config.mutex will be held for this call
365 static void armada_drm_crtc_prepare(struct drm_crtc
*crtc
)
367 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
368 struct drm_plane
*plane
;
371 * If we have an overlay plane associated with this CRTC, disable
372 * it before the modeset to avoid its coordinates being outside
373 * the new mode parameters.
375 plane
= dcrtc
->plane
;
377 drm_plane_force_disable(plane
);
380 /* The mode_config.mutex will be held for this call */
381 static void armada_drm_crtc_commit(struct drm_crtc
*crtc
)
383 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
385 if (dcrtc
->dpms
!= DRM_MODE_DPMS_ON
) {
386 dcrtc
->dpms
= DRM_MODE_DPMS_ON
;
387 armada_drm_crtc_update(dcrtc
);
391 /* The mode_config.mutex will be held for this call */
392 static bool armada_drm_crtc_mode_fixup(struct drm_crtc
*crtc
,
393 const struct drm_display_mode
*mode
, struct drm_display_mode
*adj
)
395 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
398 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
399 if (!dcrtc
->variant
->has_spu_adv_reg
&&
400 adj
->flags
& DRM_MODE_FLAG_INTERLACE
)
403 /* Check whether the display mode is possible */
404 ret
= dcrtc
->variant
->compute_clock(dcrtc
, adj
, NULL
);
411 /* These are locked by dev->vbl_lock */
412 static void armada_drm_crtc_disable_irq(struct armada_crtc
*dcrtc
, u32 mask
)
414 if (dcrtc
->irq_ena
& mask
) {
415 dcrtc
->irq_ena
&= ~mask
;
416 writel(dcrtc
->irq_ena
, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
420 static void armada_drm_crtc_enable_irq(struct armada_crtc
*dcrtc
, u32 mask
)
422 if ((dcrtc
->irq_ena
& mask
) != mask
) {
423 dcrtc
->irq_ena
|= mask
;
424 writel(dcrtc
->irq_ena
, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
425 if (readl_relaxed(dcrtc
->base
+ LCD_SPU_IRQ_ISR
) & mask
)
426 writel(0, dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
430 static void armada_drm_crtc_irq(struct armada_crtc
*dcrtc
, u32 stat
)
432 void __iomem
*base
= dcrtc
->base
;
433 struct drm_plane
*ovl_plane
;
435 if (stat
& DMA_FF_UNDERFLOW
)
436 DRM_ERROR("video underflow on crtc %u\n", dcrtc
->num
);
437 if (stat
& GRA_FF_UNDERFLOW
)
438 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc
->num
);
440 if (stat
& VSYNC_IRQ
)
441 drm_crtc_handle_vblank(&dcrtc
->crtc
);
443 spin_lock(&dcrtc
->irq_lock
);
444 ovl_plane
= dcrtc
->plane
;
446 armada_drm_plane_work_run(dcrtc
, ovl_plane
);
448 if (stat
& GRA_FRAME_IRQ
&& dcrtc
->interlaced
) {
449 int i
= stat
& GRA_FRAME_IRQ0
? 0 : 1;
452 writel_relaxed(dcrtc
->v
[i
].spu_v_porch
, base
+ LCD_SPU_V_PORCH
);
453 writel_relaxed(dcrtc
->v
[i
].spu_v_h_total
,
454 base
+ LCD_SPUT_V_H_TOTAL
);
456 val
= readl_relaxed(base
+ LCD_SPU_ADV_REG
);
457 val
&= ~(ADV_VSYNC_L_OFF
| ADV_VSYNC_H_OFF
| ADV_VSYNCOFFEN
);
458 val
|= dcrtc
->v
[i
].spu_adv_reg
;
459 writel_relaxed(val
, base
+ LCD_SPU_ADV_REG
);
462 if (stat
& DUMB_FRAMEDONE
&& dcrtc
->cursor_update
) {
463 writel_relaxed(dcrtc
->cursor_hw_pos
,
464 base
+ LCD_SPU_HWC_OVSA_HPXL_VLN
);
465 writel_relaxed(dcrtc
->cursor_hw_sz
,
466 base
+ LCD_SPU_HWC_HPXL_VLN
);
467 armada_updatel(CFG_HWC_ENA
,
468 CFG_HWC_ENA
| CFG_HWC_1BITMOD
| CFG_HWC_1BITENA
,
469 base
+ LCD_SPU_DMA_CTRL0
);
470 dcrtc
->cursor_update
= false;
471 armada_drm_crtc_disable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
474 spin_unlock(&dcrtc
->irq_lock
);
476 if (stat
& GRA_FRAME_IRQ
)
477 armada_drm_plane_work_run(dcrtc
, dcrtc
->crtc
.primary
);
480 static irqreturn_t
armada_drm_irq(int irq
, void *arg
)
482 struct armada_crtc
*dcrtc
= arg
;
483 u32 v
, stat
= readl_relaxed(dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
486 * This is rediculous - rather than writing bits to clear, we
487 * have to set the actual status register value. This is racy.
489 writel_relaxed(0, dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
491 trace_armada_drm_irq(&dcrtc
->crtc
, stat
);
493 /* Mask out those interrupts we haven't enabled */
494 v
= stat
& dcrtc
->irq_ena
;
496 if (v
& (VSYNC_IRQ
|GRA_FRAME_IRQ
|DUMB_FRAMEDONE
)) {
497 armada_drm_crtc_irq(dcrtc
, stat
);
503 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc
*dcrtc
)
505 struct drm_display_mode
*adj
= &dcrtc
->crtc
.mode
;
508 if (dcrtc
->csc_yuv_mode
== CSC_YUV_CCIR709
)
509 val
|= CFG_CSC_YUV_CCIR709
;
510 if (dcrtc
->csc_rgb_mode
== CSC_RGB_STUDIO
)
511 val
|= CFG_CSC_RGB_STUDIO
;
514 * In auto mode, set the colorimetry, based upon the HDMI spec.
515 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
516 * ITU601. It may be more appropriate to set this depending on
517 * the source - but what if the graphic frame is YUV and the
518 * video frame is RGB?
520 if ((adj
->hdisplay
== 1280 && adj
->vdisplay
== 720 &&
521 !(adj
->flags
& DRM_MODE_FLAG_INTERLACE
)) ||
522 (adj
->hdisplay
== 1920 && adj
->vdisplay
== 1080)) {
523 if (dcrtc
->csc_yuv_mode
== CSC_AUTO
)
524 val
|= CFG_CSC_YUV_CCIR709
;
528 * We assume we're connected to a TV-like device, so the YUV->RGB
529 * conversion should produce a limited range. We should set this
530 * depending on the connectors attached to this CRTC, and what
531 * kind of device they report being connected.
533 if (dcrtc
->csc_rgb_mode
== CSC_AUTO
)
534 val
|= CFG_CSC_RGB_STUDIO
;
539 static void armada_drm_primary_set(struct drm_crtc
*crtc
,
540 struct drm_plane
*plane
, int x
, int y
)
542 struct armada_plane_state
*state
= &drm_to_armada_plane(plane
)->state
;
543 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
544 struct armada_regs regs
[8];
545 bool interlaced
= dcrtc
->interlaced
;
549 i
= armada_drm_crtc_calc_fb(plane
->fb
, x
, y
, regs
, interlaced
);
551 armada_reg_queue_set(regs
, i
, state
->dst_yx
, LCD_SPU_GRA_OVSA_HPXL_VLN
);
552 armada_reg_queue_set(regs
, i
, state
->src_hw
, LCD_SPU_GRA_HPXL_VLN
);
553 armada_reg_queue_set(regs
, i
, state
->dst_hw
, LCD_SPU_GZM_HPXL_VLN
);
555 ctrl0
= state
->ctrl0
;
557 ctrl0
|= CFG_GRA_FTOGGLE
;
559 armada_reg_queue_mod(regs
, i
, ctrl0
, CFG_GRAFORMAT
|
560 CFG_GRA_MOD(CFG_SWAPRB
| CFG_SWAPUV
|
561 CFG_SWAPYU
| CFG_YUV2RGB
) |
562 CFG_PALETTE_ENA
| CFG_GRA_FTOGGLE
,
564 armada_reg_queue_end(regs
, i
);
565 armada_drm_crtc_update_regs(dcrtc
, regs
);
568 /* The mode_config.mutex will be held for this call */
569 static int armada_drm_crtc_mode_set(struct drm_crtc
*crtc
,
570 struct drm_display_mode
*mode
, struct drm_display_mode
*adj
,
571 int x
, int y
, struct drm_framebuffer
*old_fb
)
573 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
574 struct armada_regs regs
[17];
575 uint32_t lm
, rm
, tm
, bm
, val
, sclk
;
580 drm_framebuffer_get(crtc
->primary
->fb
);
582 interlaced
= !!(adj
->flags
& DRM_MODE_FLAG_INTERLACE
);
584 val
= CFG_GRA_ENA
| CFG_GRA_HSMOOTH
;
585 val
|= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc
->crtc
.primary
->fb
)->fmt
);
586 val
|= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc
->crtc
.primary
->fb
)->mod
);
588 if (drm_fb_to_armada_fb(dcrtc
->crtc
.primary
->fb
)->fmt
> CFG_420
)
589 val
|= CFG_PALETTE_ENA
;
591 drm_to_armada_plane(crtc
->primary
)->state
.ctrl0
= val
;
592 drm_to_armada_plane(crtc
->primary
)->state
.src_hw
=
593 drm_to_armada_plane(crtc
->primary
)->state
.dst_hw
=
594 adj
->crtc_vdisplay
<< 16 | adj
->crtc_hdisplay
;
595 drm_to_armada_plane(crtc
->primary
)->state
.dst_yx
= 0;
598 rm
= adj
->crtc_hsync_start
- adj
->crtc_hdisplay
;
599 lm
= adj
->crtc_htotal
- adj
->crtc_hsync_end
;
600 bm
= adj
->crtc_vsync_start
- adj
->crtc_vdisplay
;
601 tm
= adj
->crtc_vtotal
- adj
->crtc_vsync_end
;
603 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
605 adj
->crtc_hsync_start
,
607 adj
->crtc_htotal
, lm
, rm
);
608 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
610 adj
->crtc_vsync_start
,
612 adj
->crtc_vtotal
, tm
, bm
);
614 /* Wait for pending flips to complete */
615 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc
->crtc
.primary
),
616 MAX_SCHEDULE_TIMEOUT
);
618 drm_crtc_vblank_off(crtc
);
620 val
= dcrtc
->dumb_ctrl
& ~CFG_DUMB_ENA
;
621 if (val
!= dcrtc
->dumb_ctrl
) {
622 dcrtc
->dumb_ctrl
= val
;
623 writel_relaxed(val
, dcrtc
->base
+ LCD_SPU_DUMB_CTRL
);
627 * If we are blanked, we would have disabled the clock. Re-enable
628 * it so that compute_clock() does the right thing.
630 if (!IS_ERR(dcrtc
->clk
) && dpms_blanked(dcrtc
->dpms
))
631 WARN_ON(clk_prepare_enable(dcrtc
->clk
));
633 /* Now compute the divider for real */
634 dcrtc
->variant
->compute_clock(dcrtc
, adj
, &sclk
);
636 /* Ensure graphic fifo is enabled */
637 armada_reg_queue_mod(regs
, i
, 0, CFG_PDWN64x66
, LCD_SPU_SRAM_PARA1
);
638 armada_reg_queue_set(regs
, i
, sclk
, LCD_CFG_SCLK_DIV
);
640 if (interlaced
^ dcrtc
->interlaced
) {
641 if (adj
->flags
& DRM_MODE_FLAG_INTERLACE
)
642 drm_crtc_vblank_get(&dcrtc
->crtc
);
644 drm_crtc_vblank_put(&dcrtc
->crtc
);
645 dcrtc
->interlaced
= interlaced
;
648 spin_lock_irqsave(&dcrtc
->irq_lock
, flags
);
650 /* Even interlaced/progressive frame */
651 dcrtc
->v
[1].spu_v_h_total
= adj
->crtc_vtotal
<< 16 |
653 dcrtc
->v
[1].spu_v_porch
= tm
<< 16 | bm
;
654 val
= adj
->crtc_hsync_start
;
655 dcrtc
->v
[1].spu_adv_reg
= val
<< 20 | val
| ADV_VSYNCOFFEN
|
656 dcrtc
->variant
->spu_adv_reg
;
659 /* Odd interlaced frame */
660 dcrtc
->v
[0].spu_v_h_total
= dcrtc
->v
[1].spu_v_h_total
+
662 dcrtc
->v
[0].spu_v_porch
= dcrtc
->v
[1].spu_v_porch
+ 1;
663 val
= adj
->crtc_hsync_start
- adj
->crtc_htotal
/ 2;
664 dcrtc
->v
[0].spu_adv_reg
= val
<< 20 | val
| ADV_VSYNCOFFEN
|
665 dcrtc
->variant
->spu_adv_reg
;
667 dcrtc
->v
[0] = dcrtc
->v
[1];
670 val
= adj
->crtc_vdisplay
<< 16 | adj
->crtc_hdisplay
;
672 armada_reg_queue_set(regs
, i
, val
, LCD_SPU_V_H_ACTIVE
);
673 armada_reg_queue_set(regs
, i
, (lm
<< 16) | rm
, LCD_SPU_H_PORCH
);
674 armada_reg_queue_set(regs
, i
, dcrtc
->v
[0].spu_v_porch
, LCD_SPU_V_PORCH
);
675 armada_reg_queue_set(regs
, i
, dcrtc
->v
[0].spu_v_h_total
,
678 if (dcrtc
->variant
->has_spu_adv_reg
) {
679 armada_reg_queue_mod(regs
, i
, dcrtc
->v
[0].spu_adv_reg
,
680 ADV_VSYNC_L_OFF
| ADV_VSYNC_H_OFF
|
681 ADV_VSYNCOFFEN
, LCD_SPU_ADV_REG
);
684 val
= adj
->flags
& DRM_MODE_FLAG_NVSYNC
? CFG_VSYNC_INV
: 0;
685 armada_reg_queue_mod(regs
, i
, val
, CFG_VSYNC_INV
, LCD_SPU_DMA_CTRL1
);
687 val
= dcrtc
->spu_iopad_ctrl
| armada_drm_crtc_calculate_csc(dcrtc
);
688 armada_reg_queue_set(regs
, i
, val
, LCD_SPU_IOPAD_CONTROL
);
689 armada_reg_queue_end(regs
, i
);
691 armada_drm_crtc_update_regs(dcrtc
, regs
);
693 armada_drm_primary_set(crtc
, crtc
->primary
, x
, y
);
694 spin_unlock_irqrestore(&dcrtc
->irq_lock
, flags
);
696 armada_drm_crtc_update(dcrtc
);
698 drm_crtc_vblank_on(crtc
);
699 armada_drm_crtc_finish_fb(dcrtc
, old_fb
, dpms_blanked(dcrtc
->dpms
));
704 /* The mode_config.mutex will be held for this call */
705 static int armada_drm_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
706 struct drm_framebuffer
*old_fb
)
708 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
709 struct armada_regs regs
[4];
712 i
= armada_drm_crtc_calc_fb(crtc
->primary
->fb
, crtc
->x
, crtc
->y
, regs
,
714 armada_reg_queue_end(regs
, i
);
716 /* Wait for pending flips to complete */
717 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc
->crtc
.primary
),
718 MAX_SCHEDULE_TIMEOUT
);
720 /* Take a reference to the new fb as we're using it */
721 drm_framebuffer_get(crtc
->primary
->fb
);
723 /* Update the base in the CRTC */
724 armada_drm_crtc_update_regs(dcrtc
, regs
);
726 /* Drop our previously held reference */
727 armada_drm_crtc_finish_fb(dcrtc
, old_fb
, dpms_blanked(dcrtc
->dpms
));
732 void armada_drm_crtc_plane_disable(struct armada_crtc
*dcrtc
,
733 struct drm_plane
*plane
)
735 u32 sram_para1
, dma_ctrl0_mask
;
738 * Drop our reference on any framebuffer attached to this plane.
739 * We don't need to NULL this out as drm_plane_force_disable(),
740 * and __setplane_internal() will do so for an overlay plane, and
741 * __drm_helper_disable_unused_functions() will do so for the
745 drm_framebuffer_put(plane
->fb
);
747 /* Power down the Y/U/V FIFOs */
748 sram_para1
= CFG_PDWN16x66
| CFG_PDWN32x66
;
750 /* Power down most RAMs and FIFOs if this is the primary plane */
751 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
) {
752 sram_para1
|= CFG_PDWN256x32
| CFG_PDWN256x24
| CFG_PDWN256x8
|
753 CFG_PDWN32x32
| CFG_PDWN64x66
;
754 dma_ctrl0_mask
= CFG_GRA_ENA
;
756 dma_ctrl0_mask
= CFG_DMA_ENA
;
759 spin_lock_irq(&dcrtc
->irq_lock
);
760 armada_updatel(0, dma_ctrl0_mask
, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
761 spin_unlock_irq(&dcrtc
->irq_lock
);
763 armada_updatel(sram_para1
, 0, dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
766 /* The mode_config.mutex will be held for this call */
767 static void armada_drm_crtc_disable(struct drm_crtc
*crtc
)
769 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
771 armada_drm_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
772 armada_drm_crtc_plane_disable(dcrtc
, crtc
->primary
);
775 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs
= {
776 .dpms
= armada_drm_crtc_dpms
,
777 .prepare
= armada_drm_crtc_prepare
,
778 .commit
= armada_drm_crtc_commit
,
779 .mode_fixup
= armada_drm_crtc_mode_fixup
,
780 .mode_set
= armada_drm_crtc_mode_set
,
781 .mode_set_base
= armada_drm_crtc_mode_set_base
,
782 .disable
= armada_drm_crtc_disable
,
785 static void armada_load_cursor_argb(void __iomem
*base
, uint32_t *pix
,
786 unsigned stride
, unsigned width
, unsigned height
)
791 addr
= SRAM_HWC32_RAM1
;
792 for (y
= 0; y
< height
; y
++) {
793 uint32_t *p
= &pix
[y
* stride
];
796 for (x
= 0; x
< width
; x
++, p
++) {
799 val
= (val
& 0xff00ff00) |
800 (val
& 0x000000ff) << 16 |
801 (val
& 0x00ff0000) >> 16;
804 base
+ LCD_SPU_SRAM_WRDAT
);
805 writel_relaxed(addr
| SRAM_WRITE
,
806 base
+ LCD_SPU_SRAM_CTRL
);
807 readl_relaxed(base
+ LCD_SPU_HWC_OVSA_HPXL_VLN
);
809 if ((addr
& 0x00ff) == 0)
811 if ((addr
& 0x30ff) == 0)
812 addr
= SRAM_HWC32_RAM2
;
817 static void armada_drm_crtc_cursor_tran(void __iomem
*base
)
821 for (addr
= 0; addr
< 256; addr
++) {
822 /* write the default value */
823 writel_relaxed(0x55555555, base
+ LCD_SPU_SRAM_WRDAT
);
824 writel_relaxed(addr
| SRAM_WRITE
| SRAM_HWC32_TRAN
,
825 base
+ LCD_SPU_SRAM_CTRL
);
829 static int armada_drm_crtc_cursor_update(struct armada_crtc
*dcrtc
, bool reload
)
831 uint32_t xoff
, xscr
, w
= dcrtc
->cursor_w
, s
;
832 uint32_t yoff
, yscr
, h
= dcrtc
->cursor_h
;
836 * Calculate the visible width and height of the cursor,
837 * screen position, and the position in the cursor bitmap.
839 if (dcrtc
->cursor_x
< 0) {
840 xoff
= -dcrtc
->cursor_x
;
843 } else if (dcrtc
->cursor_x
+ w
> dcrtc
->crtc
.mode
.hdisplay
) {
845 xscr
= dcrtc
->cursor_x
;
846 w
= max_t(int, dcrtc
->crtc
.mode
.hdisplay
- dcrtc
->cursor_x
, 0);
849 xscr
= dcrtc
->cursor_x
;
852 if (dcrtc
->cursor_y
< 0) {
853 yoff
= -dcrtc
->cursor_y
;
856 } else if (dcrtc
->cursor_y
+ h
> dcrtc
->crtc
.mode
.vdisplay
) {
858 yscr
= dcrtc
->cursor_y
;
859 h
= max_t(int, dcrtc
->crtc
.mode
.vdisplay
- dcrtc
->cursor_y
, 0);
862 yscr
= dcrtc
->cursor_y
;
865 /* On interlaced modes, the vertical cursor size must be halved */
867 if (dcrtc
->interlaced
) {
873 if (!dcrtc
->cursor_obj
|| !h
|| !w
) {
874 spin_lock_irq(&dcrtc
->irq_lock
);
875 armada_drm_crtc_disable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
876 dcrtc
->cursor_update
= false;
877 armada_updatel(0, CFG_HWC_ENA
, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
878 spin_unlock_irq(&dcrtc
->irq_lock
);
882 para1
= readl_relaxed(dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
883 armada_updatel(CFG_CSB_256x32
, CFG_CSB_256x32
| CFG_PDWN256x32
,
884 dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
887 * Initialize the transparency if the SRAM was powered down.
888 * We must also reload the cursor data as well.
890 if (!(para1
& CFG_CSB_256x32
)) {
891 armada_drm_crtc_cursor_tran(dcrtc
->base
);
895 if (dcrtc
->cursor_hw_sz
!= (h
<< 16 | w
)) {
896 spin_lock_irq(&dcrtc
->irq_lock
);
897 armada_drm_crtc_disable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
898 dcrtc
->cursor_update
= false;
899 armada_updatel(0, CFG_HWC_ENA
, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
900 spin_unlock_irq(&dcrtc
->irq_lock
);
904 struct armada_gem_object
*obj
= dcrtc
->cursor_obj
;
906 /* Set the top-left corner of the cursor image */
908 pix
+= yoff
* s
+ xoff
;
909 armada_load_cursor_argb(dcrtc
->base
, pix
, s
, w
, h
);
912 /* Reload the cursor position, size and enable in the IRQ handler */
913 spin_lock_irq(&dcrtc
->irq_lock
);
914 dcrtc
->cursor_hw_pos
= yscr
<< 16 | xscr
;
915 dcrtc
->cursor_hw_sz
= h
<< 16 | w
;
916 dcrtc
->cursor_update
= true;
917 armada_drm_crtc_enable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
918 spin_unlock_irq(&dcrtc
->irq_lock
);
923 static void cursor_update(void *data
)
925 armada_drm_crtc_cursor_update(data
, true);
928 static int armada_drm_crtc_cursor_set(struct drm_crtc
*crtc
,
929 struct drm_file
*file
, uint32_t handle
, uint32_t w
, uint32_t h
)
931 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
932 struct armada_gem_object
*obj
= NULL
;
935 /* If no cursor support, replicate drm's return value */
936 if (!dcrtc
->variant
->has_spu_adv_reg
)
939 if (handle
&& w
> 0 && h
> 0) {
940 /* maximum size is 64x32 or 32x64 */
941 if (w
> 64 || h
> 64 || (w
> 32 && h
> 32))
944 obj
= armada_gem_object_lookup(file
, handle
);
948 /* Must be a kernel-mapped object */
950 drm_gem_object_put_unlocked(&obj
->obj
);
954 if (obj
->obj
.size
< w
* h
* 4) {
955 DRM_ERROR("buffer is too small\n");
956 drm_gem_object_put_unlocked(&obj
->obj
);
961 if (dcrtc
->cursor_obj
) {
962 dcrtc
->cursor_obj
->update
= NULL
;
963 dcrtc
->cursor_obj
->update_data
= NULL
;
964 drm_gem_object_put_unlocked(&dcrtc
->cursor_obj
->obj
);
966 dcrtc
->cursor_obj
= obj
;
969 ret
= armada_drm_crtc_cursor_update(dcrtc
, true);
971 obj
->update_data
= dcrtc
;
972 obj
->update
= cursor_update
;
978 static int armada_drm_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
980 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
983 /* If no cursor support, replicate drm's return value */
984 if (!dcrtc
->variant
->has_spu_adv_reg
)
989 ret
= armada_drm_crtc_cursor_update(dcrtc
, false);
994 static void armada_drm_crtc_destroy(struct drm_crtc
*crtc
)
996 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
997 struct armada_private
*priv
= crtc
->dev
->dev_private
;
999 if (dcrtc
->cursor_obj
)
1000 drm_gem_object_put_unlocked(&dcrtc
->cursor_obj
->obj
);
1002 priv
->dcrtc
[dcrtc
->num
] = NULL
;
1003 drm_crtc_cleanup(&dcrtc
->crtc
);
1005 if (!IS_ERR(dcrtc
->clk
))
1006 clk_disable_unprepare(dcrtc
->clk
);
1008 writel_relaxed(0, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
1010 of_node_put(dcrtc
->crtc
.port
);
1016 * The mode_config lock is held here, to prevent races between this
1019 static int armada_drm_crtc_page_flip(struct drm_crtc
*crtc
,
1020 struct drm_framebuffer
*fb
, struct drm_pending_vblank_event
*event
, uint32_t page_flip_flags
,
1021 struct drm_modeset_acquire_ctx
*ctx
)
1023 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1024 struct armada_frame_work
*work
;
1028 /* We don't support changing the pixel format */
1029 if (fb
->format
!= crtc
->primary
->fb
->format
)
1032 work
= kmalloc(sizeof(*work
), GFP_KERNEL
);
1036 work
->work
.fn
= armada_drm_crtc_complete_frame_work
;
1037 work
->event
= event
;
1038 work
->old_fb
= dcrtc
->crtc
.primary
->fb
;
1040 i
= armada_drm_crtc_calc_fb(fb
, crtc
->x
, crtc
->y
, work
->regs
,
1042 armada_reg_queue_end(work
->regs
, i
);
1045 * Ensure that we hold a reference on the new framebuffer.
1046 * This has to match the behaviour in mode_set.
1048 drm_framebuffer_get(fb
);
1050 ret
= armada_drm_crtc_queue_frame_work(dcrtc
, work
);
1052 /* Undo our reference above */
1053 drm_framebuffer_put(fb
);
1059 * Don't take a reference on the new framebuffer;
1060 * drm_mode_page_flip_ioctl() has already grabbed a reference and
1061 * will _not_ drop that reference on successful return from this
1062 * function. Simply mark this new framebuffer as the current one.
1064 dcrtc
->crtc
.primary
->fb
= fb
;
1067 * Finally, if the display is blanked, we won't receive an
1068 * interrupt, so complete it now.
1070 if (dpms_blanked(dcrtc
->dpms
))
1071 armada_drm_plane_work_run(dcrtc
, dcrtc
->crtc
.primary
);
1077 armada_drm_crtc_set_property(struct drm_crtc
*crtc
,
1078 struct drm_property
*property
, uint64_t val
)
1080 struct armada_private
*priv
= crtc
->dev
->dev_private
;
1081 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1082 bool update_csc
= false;
1084 if (property
== priv
->csc_yuv_prop
) {
1085 dcrtc
->csc_yuv_mode
= val
;
1087 } else if (property
== priv
->csc_rgb_prop
) {
1088 dcrtc
->csc_rgb_mode
= val
;
1095 val
= dcrtc
->spu_iopad_ctrl
|
1096 armada_drm_crtc_calculate_csc(dcrtc
);
1097 writel_relaxed(val
, dcrtc
->base
+ LCD_SPU_IOPAD_CONTROL
);
1103 /* These are called under the vbl_lock. */
1104 static int armada_drm_crtc_enable_vblank(struct drm_crtc
*crtc
)
1106 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1108 armada_drm_crtc_enable_irq(dcrtc
, VSYNC_IRQ_ENA
);
1112 static void armada_drm_crtc_disable_vblank(struct drm_crtc
*crtc
)
1114 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1116 armada_drm_crtc_disable_irq(dcrtc
, VSYNC_IRQ_ENA
);
1119 static const struct drm_crtc_funcs armada_crtc_funcs
= {
1120 .cursor_set
= armada_drm_crtc_cursor_set
,
1121 .cursor_move
= armada_drm_crtc_cursor_move
,
1122 .destroy
= armada_drm_crtc_destroy
,
1123 .set_config
= drm_crtc_helper_set_config
,
1124 .page_flip
= armada_drm_crtc_page_flip
,
1125 .set_property
= armada_drm_crtc_set_property
,
1126 .enable_vblank
= armada_drm_crtc_enable_vblank
,
1127 .disable_vblank
= armada_drm_crtc_disable_vblank
,
1130 static const struct drm_plane_funcs armada_primary_plane_funcs
= {
1131 .update_plane
= drm_primary_helper_update
,
1132 .disable_plane
= drm_primary_helper_disable
,
1133 .destroy
= drm_primary_helper_destroy
,
1136 int armada_drm_plane_init(struct armada_plane
*plane
)
1138 init_waitqueue_head(&plane
->frame_wait
);
1143 static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list
[] = {
1144 { CSC_AUTO
, "Auto" },
1145 { CSC_YUV_CCIR601
, "CCIR601" },
1146 { CSC_YUV_CCIR709
, "CCIR709" },
1149 static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list
[] = {
1150 { CSC_AUTO
, "Auto" },
1151 { CSC_RGB_COMPUTER
, "Computer system" },
1152 { CSC_RGB_STUDIO
, "Studio" },
1155 static int armada_drm_crtc_create_properties(struct drm_device
*dev
)
1157 struct armada_private
*priv
= dev
->dev_private
;
1159 if (priv
->csc_yuv_prop
)
1162 priv
->csc_yuv_prop
= drm_property_create_enum(dev
, 0,
1163 "CSC_YUV", armada_drm_csc_yuv_enum_list
,
1164 ARRAY_SIZE(armada_drm_csc_yuv_enum_list
));
1165 priv
->csc_rgb_prop
= drm_property_create_enum(dev
, 0,
1166 "CSC_RGB", armada_drm_csc_rgb_enum_list
,
1167 ARRAY_SIZE(armada_drm_csc_rgb_enum_list
));
1169 if (!priv
->csc_yuv_prop
|| !priv
->csc_rgb_prop
)
1175 static int armada_drm_crtc_create(struct drm_device
*drm
, struct device
*dev
,
1176 struct resource
*res
, int irq
, const struct armada_variant
*variant
,
1177 struct device_node
*port
)
1179 struct armada_private
*priv
= drm
->dev_private
;
1180 struct armada_crtc
*dcrtc
;
1181 struct armada_plane
*primary
;
1185 ret
= armada_drm_crtc_create_properties(drm
);
1189 base
= devm_ioremap_resource(dev
, res
);
1191 return PTR_ERR(base
);
1193 dcrtc
= kzalloc(sizeof(*dcrtc
), GFP_KERNEL
);
1195 DRM_ERROR("failed to allocate Armada crtc\n");
1199 if (dev
!= drm
->dev
)
1200 dev_set_drvdata(dev
, dcrtc
);
1202 dcrtc
->variant
= variant
;
1204 dcrtc
->num
= drm
->mode_config
.num_crtc
;
1205 dcrtc
->clk
= ERR_PTR(-EINVAL
);
1206 dcrtc
->csc_yuv_mode
= CSC_AUTO
;
1207 dcrtc
->csc_rgb_mode
= CSC_AUTO
;
1208 dcrtc
->cfg_dumb_ctrl
= DUMB24_RGB888_0
;
1209 dcrtc
->spu_iopad_ctrl
= CFG_VSCALE_LN_EN
| CFG_IOPAD_DUMB24
;
1210 spin_lock_init(&dcrtc
->irq_lock
);
1211 dcrtc
->irq_ena
= CLEAN_SPU_IRQ_ISR
;
1213 /* Initialize some registers which we don't otherwise set */
1214 writel_relaxed(0x00000001, dcrtc
->base
+ LCD_CFG_SCLK_DIV
);
1215 writel_relaxed(0x00000000, dcrtc
->base
+ LCD_SPU_BLANKCOLOR
);
1216 writel_relaxed(dcrtc
->spu_iopad_ctrl
,
1217 dcrtc
->base
+ LCD_SPU_IOPAD_CONTROL
);
1218 writel_relaxed(0x00000000, dcrtc
->base
+ LCD_SPU_SRAM_PARA0
);
1219 writel_relaxed(CFG_PDWN256x32
| CFG_PDWN256x24
| CFG_PDWN256x8
|
1220 CFG_PDWN32x32
| CFG_PDWN16x66
| CFG_PDWN32x66
|
1221 CFG_PDWN64x66
, dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
1222 writel_relaxed(0x2032ff81, dcrtc
->base
+ LCD_SPU_DMA_CTRL1
);
1223 writel_relaxed(dcrtc
->irq_ena
, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
1224 writel_relaxed(0, dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
1226 ret
= devm_request_irq(dev
, irq
, armada_drm_irq
, 0, "armada_drm_crtc",
1233 if (dcrtc
->variant
->init
) {
1234 ret
= dcrtc
->variant
->init(dcrtc
, dev
);
1241 /* Ensure AXI pipeline is enabled */
1242 armada_updatel(CFG_ARBFAST_ENA
, 0, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
1244 priv
->dcrtc
[dcrtc
->num
] = dcrtc
;
1246 dcrtc
->crtc
.port
= port
;
1248 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
1252 ret
= armada_drm_plane_init(primary
);
1258 ret
= drm_universal_plane_init(drm
, &primary
->base
, 0,
1259 &armada_primary_plane_funcs
,
1260 armada_primary_formats
,
1261 ARRAY_SIZE(armada_primary_formats
),
1263 DRM_PLANE_TYPE_PRIMARY
, NULL
);
1269 ret
= drm_crtc_init_with_planes(drm
, &dcrtc
->crtc
, &primary
->base
, NULL
,
1270 &armada_crtc_funcs
, NULL
);
1274 drm_crtc_helper_add(&dcrtc
->crtc
, &armada_crtc_helper_funcs
);
1276 drm_object_attach_property(&dcrtc
->crtc
.base
, priv
->csc_yuv_prop
,
1277 dcrtc
->csc_yuv_mode
);
1278 drm_object_attach_property(&dcrtc
->crtc
.base
, priv
->csc_rgb_prop
,
1279 dcrtc
->csc_rgb_mode
);
1281 return armada_overlay_plane_create(drm
, 1 << dcrtc
->num
);
1284 primary
->base
.funcs
->destroy(&primary
->base
);
1289 armada_lcd_bind(struct device
*dev
, struct device
*master
, void *data
)
1291 struct platform_device
*pdev
= to_platform_device(dev
);
1292 struct drm_device
*drm
= data
;
1293 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1294 int irq
= platform_get_irq(pdev
, 0);
1295 const struct armada_variant
*variant
;
1296 struct device_node
*port
= NULL
;
1301 if (!dev
->of_node
) {
1302 const struct platform_device_id
*id
;
1304 id
= platform_get_device_id(pdev
);
1308 variant
= (const struct armada_variant
*)id
->driver_data
;
1310 const struct of_device_id
*match
;
1311 struct device_node
*np
, *parent
= dev
->of_node
;
1313 match
= of_match_device(dev
->driver
->of_match_table
, dev
);
1317 np
= of_get_child_by_name(parent
, "ports");
1320 port
= of_get_child_by_name(parent
, "port");
1323 dev_err(dev
, "no port node found in %pOF\n", parent
);
1327 variant
= match
->data
;
1330 return armada_drm_crtc_create(drm
, dev
, res
, irq
, variant
, port
);
1334 armada_lcd_unbind(struct device
*dev
, struct device
*master
, void *data
)
1336 struct armada_crtc
*dcrtc
= dev_get_drvdata(dev
);
1338 armada_drm_crtc_destroy(&dcrtc
->crtc
);
1341 static const struct component_ops armada_lcd_ops
= {
1342 .bind
= armada_lcd_bind
,
1343 .unbind
= armada_lcd_unbind
,
1346 static int armada_lcd_probe(struct platform_device
*pdev
)
1348 return component_add(&pdev
->dev
, &armada_lcd_ops
);
1351 static int armada_lcd_remove(struct platform_device
*pdev
)
1353 component_del(&pdev
->dev
, &armada_lcd_ops
);
1357 static const struct of_device_id armada_lcd_of_match
[] = {
1359 .compatible
= "marvell,dove-lcd",
1360 .data
= &armada510_ops
,
1364 MODULE_DEVICE_TABLE(of
, armada_lcd_of_match
);
1366 static const struct platform_device_id armada_lcd_platform_ids
[] = {
1368 .name
= "armada-lcd",
1369 .driver_data
= (unsigned long)&armada510_ops
,
1371 .name
= "armada-510-lcd",
1372 .driver_data
= (unsigned long)&armada510_ops
,
1376 MODULE_DEVICE_TABLE(platform
, armada_lcd_platform_ids
);
1378 struct platform_driver armada_lcd_platform_driver
= {
1379 .probe
= armada_lcd_probe
,
1380 .remove
= armada_lcd_remove
,
1382 .name
= "armada-lcd",
1383 .owner
= THIS_MODULE
,
1384 .of_match_table
= armada_lcd_of_match
,
1386 .id_table
= armada_lcd_platform_ids
,