2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/component.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_plane_helper.h>
16 #include "armada_crtc.h"
17 #include "armada_drm.h"
18 #include "armada_fb.h"
19 #include "armada_gem.h"
20 #include "armada_hw.h"
21 #include "armada_trace.h"
23 struct armada_frame_work
{
24 struct armada_plane_work work
;
25 struct drm_pending_vblank_event
*event
;
26 struct armada_regs regs
[4];
27 struct drm_framebuffer
*old_fb
;
38 static const uint32_t armada_primary_formats
[] = {
56 * A note about interlacing. Let's consider HDMI 1920x1080i.
57 * The timing parameters we have from X are:
58 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
59 * 1920 2448 2492 2640 1080 1084 1094 1125
60 * Which get translated to:
61 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
62 * 1920 2448 2492 2640 540 542 547 562
64 * This is how it is defined by CEA-861-D - line and pixel numbers are
65 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
66 * line: 2640. The odd frame, the first active line is at line 21, and
67 * the even frame, the first active line is 584.
69 * LN: 560 561 562 563 567 568 569
70 * DE: ~~~|____________________________//__________________________
71 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
72 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
73 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
75 * LN: 1123 1124 1125 1 5 6 7
76 * DE: ~~~|____________________________//__________________________
77 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
78 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
81 * The Armada LCD Controller line and pixel numbers are, like X timings,
82 * referenced to the top left of the active frame.
84 * So, translating these to our LCD controller:
85 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
86 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
87 * Note: Vsync front porch remains constant!
90 * vtotal = mode->crtc_vtotal + 1;
91 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
92 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
94 * vtotal = mode->crtc_vtotal;
95 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
96 * vhorizpos = mode->crtc_hsync_start;
98 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
100 * So, we need to reprogram these registers on each vsync event:
101 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
103 * Note: we do not use the frame done interrupts because these appear
104 * to happen too early, and lead to jitter on the display (presumably
105 * they occur at the end of the last active line, before the vsync back
106 * porch, which we're reprogramming.)
110 armada_drm_crtc_update_regs(struct armada_crtc
*dcrtc
, struct armada_regs
*regs
)
112 while (regs
->offset
!= ~0) {
113 void __iomem
*reg
= dcrtc
->base
+ regs
->offset
;
118 val
&= readl_relaxed(reg
);
119 writel_relaxed(val
| regs
->val
, reg
);
124 #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
126 static void armada_drm_crtc_update(struct armada_crtc
*dcrtc
)
130 dumb_ctrl
= dcrtc
->cfg_dumb_ctrl
;
132 if (!dpms_blanked(dcrtc
->dpms
))
133 dumb_ctrl
|= CFG_DUMB_ENA
;
136 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
137 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
138 * force LCD_D[23:0] to output blank color, overriding the GPIO or
139 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
141 if (dpms_blanked(dcrtc
->dpms
) &&
142 (dumb_ctrl
& DUMB_MASK
) == DUMB24_RGB888_0
) {
143 dumb_ctrl
&= ~DUMB_MASK
;
144 dumb_ctrl
|= DUMB_BLANK
;
148 * The documentation doesn't indicate what the normal state of
149 * the sync signals are. Sebastian Hesselbart kindly probed
150 * these signals on his board to determine their state.
152 * The non-inverted state of the sync signals is active high.
153 * Setting these bits makes the appropriate signal active low.
155 if (dcrtc
->crtc
.mode
.flags
& DRM_MODE_FLAG_NCSYNC
)
156 dumb_ctrl
|= CFG_INV_CSYNC
;
157 if (dcrtc
->crtc
.mode
.flags
& DRM_MODE_FLAG_NHSYNC
)
158 dumb_ctrl
|= CFG_INV_HSYNC
;
159 if (dcrtc
->crtc
.mode
.flags
& DRM_MODE_FLAG_NVSYNC
)
160 dumb_ctrl
|= CFG_INV_VSYNC
;
162 if (dcrtc
->dumb_ctrl
!= dumb_ctrl
) {
163 dcrtc
->dumb_ctrl
= dumb_ctrl
;
164 writel_relaxed(dumb_ctrl
, dcrtc
->base
+ LCD_SPU_DUMB_CTRL
);
168 void armada_drm_plane_calc_addrs(u32
*addrs
, struct drm_framebuffer
*fb
,
171 const struct drm_format_info
*format
= fb
->format
;
172 unsigned int num_planes
= format
->num_planes
;
173 u32 addr
= drm_fb_obj(fb
)->dev_addr
;
179 addrs
[0] = addr
+ fb
->offsets
[0] + y
* fb
->pitches
[0] +
185 for (i
= 1; i
< num_planes
; i
++)
186 addrs
[i
] = addr
+ fb
->offsets
[i
] + y
* fb
->pitches
[i
] +
192 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer
*fb
,
193 int x
, int y
, struct armada_regs
*regs
, bool interlaced
)
195 unsigned pitch
= fb
->pitches
[0];
196 u32 addrs
[3], addr_odd
, addr_even
;
199 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
200 pitch
, x
, y
, fb
->format
->cpp
[0] * 8);
202 armada_drm_plane_calc_addrs(addrs
, fb
, x
, y
);
204 addr_odd
= addr_even
= addrs
[0];
211 /* write offset, base, and pitch */
212 armada_reg_queue_set(regs
, i
, addr_odd
, LCD_CFG_GRA_START_ADDR0
);
213 armada_reg_queue_set(regs
, i
, addr_even
, LCD_CFG_GRA_START_ADDR1
);
214 armada_reg_queue_mod(regs
, i
, pitch
, 0xffff, LCD_CFG_GRA_PITCH
);
219 static void armada_drm_plane_work_run(struct armada_crtc
*dcrtc
,
220 struct drm_plane
*plane
)
222 struct armada_plane
*dplane
= drm_to_armada_plane(plane
);
223 struct armada_plane_work
*work
= xchg(&dplane
->work
, NULL
);
225 /* Handle any pending frame work. */
227 work
->fn(dcrtc
, dplane
, work
);
228 drm_crtc_vblank_put(&dcrtc
->crtc
);
231 wake_up(&dplane
->frame_wait
);
234 int armada_drm_plane_work_queue(struct armada_crtc
*dcrtc
,
235 struct armada_plane
*plane
, struct armada_plane_work
*work
)
239 ret
= drm_crtc_vblank_get(&dcrtc
->crtc
);
241 DRM_ERROR("failed to acquire vblank counter\n");
245 ret
= cmpxchg(&plane
->work
, NULL
, work
) ? -EBUSY
: 0;
247 drm_crtc_vblank_put(&dcrtc
->crtc
);
252 int armada_drm_plane_work_wait(struct armada_plane
*plane
, long timeout
)
254 return wait_event_timeout(plane
->frame_wait
, !plane
->work
, timeout
);
257 struct armada_plane_work
*armada_drm_plane_work_cancel(
258 struct armada_crtc
*dcrtc
, struct armada_plane
*plane
)
260 struct armada_plane_work
*work
= xchg(&plane
->work
, NULL
);
263 drm_crtc_vblank_put(&dcrtc
->crtc
);
268 static int armada_drm_crtc_queue_frame_work(struct armada_crtc
*dcrtc
,
269 struct armada_frame_work
*work
)
271 struct armada_plane
*plane
= drm_to_armada_plane(dcrtc
->crtc
.primary
);
273 return armada_drm_plane_work_queue(dcrtc
, plane
, &work
->work
);
276 static void armada_drm_crtc_complete_frame_work(struct armada_crtc
*dcrtc
,
277 struct armada_plane
*plane
, struct armada_plane_work
*work
)
279 struct armada_frame_work
*fwork
= container_of(work
, struct armada_frame_work
, work
);
280 struct drm_device
*dev
= dcrtc
->crtc
.dev
;
283 spin_lock_irqsave(&dcrtc
->irq_lock
, flags
);
284 armada_drm_crtc_update_regs(dcrtc
, fwork
->regs
);
285 spin_unlock_irqrestore(&dcrtc
->irq_lock
, flags
);
288 spin_lock_irqsave(&dev
->event_lock
, flags
);
289 drm_crtc_send_vblank_event(&dcrtc
->crtc
, fwork
->event
);
290 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
293 /* Finally, queue the process-half of the cleanup. */
294 __armada_drm_queue_unref_work(dcrtc
->crtc
.dev
, fwork
->old_fb
);
298 static void armada_drm_crtc_finish_fb(struct armada_crtc
*dcrtc
,
299 struct drm_framebuffer
*fb
, bool force
)
301 struct armada_frame_work
*work
;
307 /* Display is disabled, so just drop the old fb */
308 drm_framebuffer_put(fb
);
312 work
= kmalloc(sizeof(*work
), GFP_KERNEL
);
315 work
->work
.fn
= armada_drm_crtc_complete_frame_work
;
318 armada_reg_queue_end(work
->regs
, i
);
320 if (armada_drm_crtc_queue_frame_work(dcrtc
, work
) == 0)
327 * Oops - just drop the reference immediately and hope for
328 * the best. The worst that will happen is the buffer gets
329 * reused before it has finished being displayed.
331 drm_framebuffer_put(fb
);
334 static void armada_drm_vblank_off(struct armada_crtc
*dcrtc
)
337 * Tell the DRM core that vblank IRQs aren't going to happen for
338 * a while. This cleans up any pending vblank events for us.
340 drm_crtc_vblank_off(&dcrtc
->crtc
);
341 armada_drm_plane_work_run(dcrtc
, dcrtc
->crtc
.primary
);
344 /* The mode_config.mutex will be held for this call */
345 static void armada_drm_crtc_dpms(struct drm_crtc
*crtc
, int dpms
)
347 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
349 if (dpms_blanked(dcrtc
->dpms
) != dpms_blanked(dpms
)) {
350 if (dpms_blanked(dpms
))
351 armada_drm_vblank_off(dcrtc
);
352 else if (!IS_ERR(dcrtc
->clk
))
353 WARN_ON(clk_prepare_enable(dcrtc
->clk
));
355 armada_drm_crtc_update(dcrtc
);
356 if (!dpms_blanked(dpms
))
357 drm_crtc_vblank_on(&dcrtc
->crtc
);
358 else if (!IS_ERR(dcrtc
->clk
))
359 clk_disable_unprepare(dcrtc
->clk
);
360 } else if (dcrtc
->dpms
!= dpms
) {
366 * Prepare for a mode set. Turn off overlay to ensure that we don't end
367 * up with the overlay size being bigger than the active screen size.
368 * We rely upon X refreshing this state after the mode set has completed.
370 * The mode_config.mutex will be held for this call
372 static void armada_drm_crtc_prepare(struct drm_crtc
*crtc
)
374 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
375 struct drm_plane
*plane
;
378 * If we have an overlay plane associated with this CRTC, disable
379 * it before the modeset to avoid its coordinates being outside
380 * the new mode parameters.
382 plane
= dcrtc
->plane
;
384 drm_plane_force_disable(plane
);
387 /* The mode_config.mutex will be held for this call */
388 static void armada_drm_crtc_commit(struct drm_crtc
*crtc
)
390 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
392 if (dcrtc
->dpms
!= DRM_MODE_DPMS_ON
) {
393 dcrtc
->dpms
= DRM_MODE_DPMS_ON
;
394 armada_drm_crtc_update(dcrtc
);
398 /* The mode_config.mutex will be held for this call */
399 static bool armada_drm_crtc_mode_fixup(struct drm_crtc
*crtc
,
400 const struct drm_display_mode
*mode
, struct drm_display_mode
*adj
)
402 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
405 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
406 if (!dcrtc
->variant
->has_spu_adv_reg
&&
407 adj
->flags
& DRM_MODE_FLAG_INTERLACE
)
410 /* Check whether the display mode is possible */
411 ret
= dcrtc
->variant
->compute_clock(dcrtc
, adj
, NULL
);
418 /* These are locked by dev->vbl_lock */
419 static void armada_drm_crtc_disable_irq(struct armada_crtc
*dcrtc
, u32 mask
)
421 if (dcrtc
->irq_ena
& mask
) {
422 dcrtc
->irq_ena
&= ~mask
;
423 writel(dcrtc
->irq_ena
, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
427 static void armada_drm_crtc_enable_irq(struct armada_crtc
*dcrtc
, u32 mask
)
429 if ((dcrtc
->irq_ena
& mask
) != mask
) {
430 dcrtc
->irq_ena
|= mask
;
431 writel(dcrtc
->irq_ena
, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
432 if (readl_relaxed(dcrtc
->base
+ LCD_SPU_IRQ_ISR
) & mask
)
433 writel(0, dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
437 static void armada_drm_crtc_irq(struct armada_crtc
*dcrtc
, u32 stat
)
439 void __iomem
*base
= dcrtc
->base
;
440 struct drm_plane
*ovl_plane
;
442 if (stat
& DMA_FF_UNDERFLOW
)
443 DRM_ERROR("video underflow on crtc %u\n", dcrtc
->num
);
444 if (stat
& GRA_FF_UNDERFLOW
)
445 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc
->num
);
447 if (stat
& VSYNC_IRQ
)
448 drm_crtc_handle_vblank(&dcrtc
->crtc
);
450 spin_lock(&dcrtc
->irq_lock
);
451 ovl_plane
= dcrtc
->plane
;
453 armada_drm_plane_work_run(dcrtc
, ovl_plane
);
455 if (stat
& GRA_FRAME_IRQ
&& dcrtc
->interlaced
) {
456 int i
= stat
& GRA_FRAME_IRQ0
? 0 : 1;
459 writel_relaxed(dcrtc
->v
[i
].spu_v_porch
, base
+ LCD_SPU_V_PORCH
);
460 writel_relaxed(dcrtc
->v
[i
].spu_v_h_total
,
461 base
+ LCD_SPUT_V_H_TOTAL
);
463 val
= readl_relaxed(base
+ LCD_SPU_ADV_REG
);
464 val
&= ~(ADV_VSYNC_L_OFF
| ADV_VSYNC_H_OFF
| ADV_VSYNCOFFEN
);
465 val
|= dcrtc
->v
[i
].spu_adv_reg
;
466 writel_relaxed(val
, base
+ LCD_SPU_ADV_REG
);
469 if (stat
& DUMB_FRAMEDONE
&& dcrtc
->cursor_update
) {
470 writel_relaxed(dcrtc
->cursor_hw_pos
,
471 base
+ LCD_SPU_HWC_OVSA_HPXL_VLN
);
472 writel_relaxed(dcrtc
->cursor_hw_sz
,
473 base
+ LCD_SPU_HWC_HPXL_VLN
);
474 armada_updatel(CFG_HWC_ENA
,
475 CFG_HWC_ENA
| CFG_HWC_1BITMOD
| CFG_HWC_1BITENA
,
476 base
+ LCD_SPU_DMA_CTRL0
);
477 dcrtc
->cursor_update
= false;
478 armada_drm_crtc_disable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
481 spin_unlock(&dcrtc
->irq_lock
);
483 if (stat
& GRA_FRAME_IRQ
)
484 armada_drm_plane_work_run(dcrtc
, dcrtc
->crtc
.primary
);
487 static irqreturn_t
armada_drm_irq(int irq
, void *arg
)
489 struct armada_crtc
*dcrtc
= arg
;
490 u32 v
, stat
= readl_relaxed(dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
493 * This is rediculous - rather than writing bits to clear, we
494 * have to set the actual status register value. This is racy.
496 writel_relaxed(0, dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
498 trace_armada_drm_irq(&dcrtc
->crtc
, stat
);
500 /* Mask out those interrupts we haven't enabled */
501 v
= stat
& dcrtc
->irq_ena
;
503 if (v
& (VSYNC_IRQ
|GRA_FRAME_IRQ
|DUMB_FRAMEDONE
)) {
504 armada_drm_crtc_irq(dcrtc
, stat
);
510 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc
*dcrtc
)
512 struct drm_display_mode
*adj
= &dcrtc
->crtc
.mode
;
515 if (dcrtc
->csc_yuv_mode
== CSC_YUV_CCIR709
)
516 val
|= CFG_CSC_YUV_CCIR709
;
517 if (dcrtc
->csc_rgb_mode
== CSC_RGB_STUDIO
)
518 val
|= CFG_CSC_RGB_STUDIO
;
521 * In auto mode, set the colorimetry, based upon the HDMI spec.
522 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
523 * ITU601. It may be more appropriate to set this depending on
524 * the source - but what if the graphic frame is YUV and the
525 * video frame is RGB?
527 if ((adj
->hdisplay
== 1280 && adj
->vdisplay
== 720 &&
528 !(adj
->flags
& DRM_MODE_FLAG_INTERLACE
)) ||
529 (adj
->hdisplay
== 1920 && adj
->vdisplay
== 1080)) {
530 if (dcrtc
->csc_yuv_mode
== CSC_AUTO
)
531 val
|= CFG_CSC_YUV_CCIR709
;
535 * We assume we're connected to a TV-like device, so the YUV->RGB
536 * conversion should produce a limited range. We should set this
537 * depending on the connectors attached to this CRTC, and what
538 * kind of device they report being connected.
540 if (dcrtc
->csc_rgb_mode
== CSC_AUTO
)
541 val
|= CFG_CSC_RGB_STUDIO
;
546 static void armada_drm_primary_set(struct drm_crtc
*crtc
,
547 struct drm_plane
*plane
, int x
, int y
)
549 struct armada_plane_state
*state
= &drm_to_armada_plane(plane
)->state
;
550 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
551 struct armada_regs regs
[8];
552 bool interlaced
= dcrtc
->interlaced
;
556 i
= armada_drm_crtc_calc_fb(plane
->fb
, x
, y
, regs
, interlaced
);
558 armada_reg_queue_set(regs
, i
, state
->dst_yx
, LCD_SPU_GRA_OVSA_HPXL_VLN
);
559 armada_reg_queue_set(regs
, i
, state
->src_hw
, LCD_SPU_GRA_HPXL_VLN
);
560 armada_reg_queue_set(regs
, i
, state
->dst_hw
, LCD_SPU_GZM_HPXL_VLN
);
562 ctrl0
= state
->ctrl0
;
564 ctrl0
|= CFG_GRA_FTOGGLE
;
566 armada_reg_queue_mod(regs
, i
, ctrl0
, CFG_GRAFORMAT
|
567 CFG_GRA_MOD(CFG_SWAPRB
| CFG_SWAPUV
|
568 CFG_SWAPYU
| CFG_YUV2RGB
) |
569 CFG_PALETTE_ENA
| CFG_GRA_FTOGGLE
,
571 armada_reg_queue_end(regs
, i
);
572 armada_drm_crtc_update_regs(dcrtc
, regs
);
575 /* The mode_config.mutex will be held for this call */
576 static int armada_drm_crtc_mode_set(struct drm_crtc
*crtc
,
577 struct drm_display_mode
*mode
, struct drm_display_mode
*adj
,
578 int x
, int y
, struct drm_framebuffer
*old_fb
)
580 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
581 struct armada_regs regs
[17];
582 uint32_t lm
, rm
, tm
, bm
, val
, sclk
;
587 drm_framebuffer_get(crtc
->primary
->fb
);
589 interlaced
= !!(adj
->flags
& DRM_MODE_FLAG_INTERLACE
);
591 val
= CFG_GRA_ENA
| CFG_GRA_HSMOOTH
;
592 val
|= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc
->crtc
.primary
->fb
)->fmt
);
593 val
|= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc
->crtc
.primary
->fb
)->mod
);
595 if (drm_fb_to_armada_fb(dcrtc
->crtc
.primary
->fb
)->fmt
> CFG_420
)
596 val
|= CFG_PALETTE_ENA
;
598 drm_to_armada_plane(crtc
->primary
)->state
.ctrl0
= val
;
599 drm_to_armada_plane(crtc
->primary
)->state
.src_hw
=
600 drm_to_armada_plane(crtc
->primary
)->state
.dst_hw
=
601 adj
->crtc_vdisplay
<< 16 | adj
->crtc_hdisplay
;
602 drm_to_armada_plane(crtc
->primary
)->state
.dst_yx
= 0;
605 rm
= adj
->crtc_hsync_start
- adj
->crtc_hdisplay
;
606 lm
= adj
->crtc_htotal
- adj
->crtc_hsync_end
;
607 bm
= adj
->crtc_vsync_start
- adj
->crtc_vdisplay
;
608 tm
= adj
->crtc_vtotal
- adj
->crtc_vsync_end
;
610 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
612 adj
->crtc_hsync_start
,
614 adj
->crtc_htotal
, lm
, rm
);
615 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
617 adj
->crtc_vsync_start
,
619 adj
->crtc_vtotal
, tm
, bm
);
621 /* Wait for pending flips to complete */
622 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc
->crtc
.primary
),
623 MAX_SCHEDULE_TIMEOUT
);
625 drm_crtc_vblank_off(crtc
);
627 val
= dcrtc
->dumb_ctrl
& ~CFG_DUMB_ENA
;
628 if (val
!= dcrtc
->dumb_ctrl
) {
629 dcrtc
->dumb_ctrl
= val
;
630 writel_relaxed(val
, dcrtc
->base
+ LCD_SPU_DUMB_CTRL
);
634 * If we are blanked, we would have disabled the clock. Re-enable
635 * it so that compute_clock() does the right thing.
637 if (!IS_ERR(dcrtc
->clk
) && dpms_blanked(dcrtc
->dpms
))
638 WARN_ON(clk_prepare_enable(dcrtc
->clk
));
640 /* Now compute the divider for real */
641 dcrtc
->variant
->compute_clock(dcrtc
, adj
, &sclk
);
643 /* Ensure graphic fifo is enabled */
644 armada_reg_queue_mod(regs
, i
, 0, CFG_PDWN64x66
, LCD_SPU_SRAM_PARA1
);
645 armada_reg_queue_set(regs
, i
, sclk
, LCD_CFG_SCLK_DIV
);
647 if (interlaced
^ dcrtc
->interlaced
) {
648 if (adj
->flags
& DRM_MODE_FLAG_INTERLACE
)
649 drm_crtc_vblank_get(&dcrtc
->crtc
);
651 drm_crtc_vblank_put(&dcrtc
->crtc
);
652 dcrtc
->interlaced
= interlaced
;
655 spin_lock_irqsave(&dcrtc
->irq_lock
, flags
);
657 /* Even interlaced/progressive frame */
658 dcrtc
->v
[1].spu_v_h_total
= adj
->crtc_vtotal
<< 16 |
660 dcrtc
->v
[1].spu_v_porch
= tm
<< 16 | bm
;
661 val
= adj
->crtc_hsync_start
;
662 dcrtc
->v
[1].spu_adv_reg
= val
<< 20 | val
| ADV_VSYNCOFFEN
|
663 dcrtc
->variant
->spu_adv_reg
;
666 /* Odd interlaced frame */
667 dcrtc
->v
[0].spu_v_h_total
= dcrtc
->v
[1].spu_v_h_total
+
669 dcrtc
->v
[0].spu_v_porch
= dcrtc
->v
[1].spu_v_porch
+ 1;
670 val
= adj
->crtc_hsync_start
- adj
->crtc_htotal
/ 2;
671 dcrtc
->v
[0].spu_adv_reg
= val
<< 20 | val
| ADV_VSYNCOFFEN
|
672 dcrtc
->variant
->spu_adv_reg
;
674 dcrtc
->v
[0] = dcrtc
->v
[1];
677 val
= adj
->crtc_vdisplay
<< 16 | adj
->crtc_hdisplay
;
679 armada_reg_queue_set(regs
, i
, val
, LCD_SPU_V_H_ACTIVE
);
680 armada_reg_queue_set(regs
, i
, (lm
<< 16) | rm
, LCD_SPU_H_PORCH
);
681 armada_reg_queue_set(regs
, i
, dcrtc
->v
[0].spu_v_porch
, LCD_SPU_V_PORCH
);
682 armada_reg_queue_set(regs
, i
, dcrtc
->v
[0].spu_v_h_total
,
685 if (dcrtc
->variant
->has_spu_adv_reg
) {
686 armada_reg_queue_mod(regs
, i
, dcrtc
->v
[0].spu_adv_reg
,
687 ADV_VSYNC_L_OFF
| ADV_VSYNC_H_OFF
|
688 ADV_VSYNCOFFEN
, LCD_SPU_ADV_REG
);
691 val
= adj
->flags
& DRM_MODE_FLAG_NVSYNC
? CFG_VSYNC_INV
: 0;
692 armada_reg_queue_mod(regs
, i
, val
, CFG_VSYNC_INV
, LCD_SPU_DMA_CTRL1
);
694 val
= dcrtc
->spu_iopad_ctrl
| armada_drm_crtc_calculate_csc(dcrtc
);
695 armada_reg_queue_set(regs
, i
, val
, LCD_SPU_IOPAD_CONTROL
);
696 armada_reg_queue_end(regs
, i
);
698 armada_drm_crtc_update_regs(dcrtc
, regs
);
700 armada_drm_primary_set(crtc
, crtc
->primary
, x
, y
);
701 spin_unlock_irqrestore(&dcrtc
->irq_lock
, flags
);
703 armada_drm_crtc_update(dcrtc
);
705 drm_crtc_vblank_on(crtc
);
706 armada_drm_crtc_finish_fb(dcrtc
, old_fb
, dpms_blanked(dcrtc
->dpms
));
711 /* The mode_config.mutex will be held for this call */
712 static int armada_drm_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
713 struct drm_framebuffer
*old_fb
)
715 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
716 struct armada_regs regs
[4];
719 i
= armada_drm_crtc_calc_fb(crtc
->primary
->fb
, crtc
->x
, crtc
->y
, regs
,
721 armada_reg_queue_end(regs
, i
);
723 /* Wait for pending flips to complete */
724 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc
->crtc
.primary
),
725 MAX_SCHEDULE_TIMEOUT
);
727 /* Take a reference to the new fb as we're using it */
728 drm_framebuffer_get(crtc
->primary
->fb
);
730 /* Update the base in the CRTC */
731 armada_drm_crtc_update_regs(dcrtc
, regs
);
733 /* Drop our previously held reference */
734 armada_drm_crtc_finish_fb(dcrtc
, old_fb
, dpms_blanked(dcrtc
->dpms
));
739 void armada_drm_crtc_plane_disable(struct armada_crtc
*dcrtc
,
740 struct drm_plane
*plane
)
742 u32 sram_para1
, dma_ctrl0_mask
;
745 * Drop our reference on any framebuffer attached to this plane.
746 * We don't need to NULL this out as drm_plane_force_disable(),
747 * and __setplane_internal() will do so for an overlay plane, and
748 * __drm_helper_disable_unused_functions() will do so for the
752 drm_framebuffer_put(plane
->fb
);
754 /* Power down most RAMs and FIFOs if this is the primary plane */
755 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
) {
756 sram_para1
= CFG_PDWN256x32
| CFG_PDWN256x24
| CFG_PDWN256x8
|
757 CFG_PDWN32x32
| CFG_PDWN64x66
;
758 dma_ctrl0_mask
= CFG_GRA_ENA
;
760 /* Power down the Y/U/V FIFOs */
761 sram_para1
= CFG_PDWN16x66
| CFG_PDWN32x66
;
762 dma_ctrl0_mask
= CFG_DMA_ENA
;
765 spin_lock_irq(&dcrtc
->irq_lock
);
766 armada_updatel(0, dma_ctrl0_mask
, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
767 spin_unlock_irq(&dcrtc
->irq_lock
);
769 armada_updatel(sram_para1
, 0, dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
772 /* The mode_config.mutex will be held for this call */
773 static void armada_drm_crtc_disable(struct drm_crtc
*crtc
)
775 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
777 armada_drm_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
778 armada_drm_crtc_plane_disable(dcrtc
, crtc
->primary
);
781 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs
= {
782 .dpms
= armada_drm_crtc_dpms
,
783 .prepare
= armada_drm_crtc_prepare
,
784 .commit
= armada_drm_crtc_commit
,
785 .mode_fixup
= armada_drm_crtc_mode_fixup
,
786 .mode_set
= armada_drm_crtc_mode_set
,
787 .mode_set_base
= armada_drm_crtc_mode_set_base
,
788 .disable
= armada_drm_crtc_disable
,
791 static void armada_load_cursor_argb(void __iomem
*base
, uint32_t *pix
,
792 unsigned stride
, unsigned width
, unsigned height
)
797 addr
= SRAM_HWC32_RAM1
;
798 for (y
= 0; y
< height
; y
++) {
799 uint32_t *p
= &pix
[y
* stride
];
802 for (x
= 0; x
< width
; x
++, p
++) {
805 val
= (val
& 0xff00ff00) |
806 (val
& 0x000000ff) << 16 |
807 (val
& 0x00ff0000) >> 16;
810 base
+ LCD_SPU_SRAM_WRDAT
);
811 writel_relaxed(addr
| SRAM_WRITE
,
812 base
+ LCD_SPU_SRAM_CTRL
);
813 readl_relaxed(base
+ LCD_SPU_HWC_OVSA_HPXL_VLN
);
815 if ((addr
& 0x00ff) == 0)
817 if ((addr
& 0x30ff) == 0)
818 addr
= SRAM_HWC32_RAM2
;
823 static void armada_drm_crtc_cursor_tran(void __iomem
*base
)
827 for (addr
= 0; addr
< 256; addr
++) {
828 /* write the default value */
829 writel_relaxed(0x55555555, base
+ LCD_SPU_SRAM_WRDAT
);
830 writel_relaxed(addr
| SRAM_WRITE
| SRAM_HWC32_TRAN
,
831 base
+ LCD_SPU_SRAM_CTRL
);
835 static int armada_drm_crtc_cursor_update(struct armada_crtc
*dcrtc
, bool reload
)
837 uint32_t xoff
, xscr
, w
= dcrtc
->cursor_w
, s
;
838 uint32_t yoff
, yscr
, h
= dcrtc
->cursor_h
;
842 * Calculate the visible width and height of the cursor,
843 * screen position, and the position in the cursor bitmap.
845 if (dcrtc
->cursor_x
< 0) {
846 xoff
= -dcrtc
->cursor_x
;
849 } else if (dcrtc
->cursor_x
+ w
> dcrtc
->crtc
.mode
.hdisplay
) {
851 xscr
= dcrtc
->cursor_x
;
852 w
= max_t(int, dcrtc
->crtc
.mode
.hdisplay
- dcrtc
->cursor_x
, 0);
855 xscr
= dcrtc
->cursor_x
;
858 if (dcrtc
->cursor_y
< 0) {
859 yoff
= -dcrtc
->cursor_y
;
862 } else if (dcrtc
->cursor_y
+ h
> dcrtc
->crtc
.mode
.vdisplay
) {
864 yscr
= dcrtc
->cursor_y
;
865 h
= max_t(int, dcrtc
->crtc
.mode
.vdisplay
- dcrtc
->cursor_y
, 0);
868 yscr
= dcrtc
->cursor_y
;
871 /* On interlaced modes, the vertical cursor size must be halved */
873 if (dcrtc
->interlaced
) {
879 if (!dcrtc
->cursor_obj
|| !h
|| !w
) {
880 spin_lock_irq(&dcrtc
->irq_lock
);
881 armada_drm_crtc_disable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
882 dcrtc
->cursor_update
= false;
883 armada_updatel(0, CFG_HWC_ENA
, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
884 spin_unlock_irq(&dcrtc
->irq_lock
);
888 para1
= readl_relaxed(dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
889 armada_updatel(CFG_CSB_256x32
, CFG_CSB_256x32
| CFG_PDWN256x32
,
890 dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
893 * Initialize the transparency if the SRAM was powered down.
894 * We must also reload the cursor data as well.
896 if (!(para1
& CFG_CSB_256x32
)) {
897 armada_drm_crtc_cursor_tran(dcrtc
->base
);
901 if (dcrtc
->cursor_hw_sz
!= (h
<< 16 | w
)) {
902 spin_lock_irq(&dcrtc
->irq_lock
);
903 armada_drm_crtc_disable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
904 dcrtc
->cursor_update
= false;
905 armada_updatel(0, CFG_HWC_ENA
, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
906 spin_unlock_irq(&dcrtc
->irq_lock
);
910 struct armada_gem_object
*obj
= dcrtc
->cursor_obj
;
912 /* Set the top-left corner of the cursor image */
914 pix
+= yoff
* s
+ xoff
;
915 armada_load_cursor_argb(dcrtc
->base
, pix
, s
, w
, h
);
918 /* Reload the cursor position, size and enable in the IRQ handler */
919 spin_lock_irq(&dcrtc
->irq_lock
);
920 dcrtc
->cursor_hw_pos
= yscr
<< 16 | xscr
;
921 dcrtc
->cursor_hw_sz
= h
<< 16 | w
;
922 dcrtc
->cursor_update
= true;
923 armada_drm_crtc_enable_irq(dcrtc
, DUMB_FRAMEDONE_ENA
);
924 spin_unlock_irq(&dcrtc
->irq_lock
);
929 static void cursor_update(void *data
)
931 armada_drm_crtc_cursor_update(data
, true);
934 static int armada_drm_crtc_cursor_set(struct drm_crtc
*crtc
,
935 struct drm_file
*file
, uint32_t handle
, uint32_t w
, uint32_t h
)
937 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
938 struct armada_gem_object
*obj
= NULL
;
941 /* If no cursor support, replicate drm's return value */
942 if (!dcrtc
->variant
->has_spu_adv_reg
)
945 if (handle
&& w
> 0 && h
> 0) {
946 /* maximum size is 64x32 or 32x64 */
947 if (w
> 64 || h
> 64 || (w
> 32 && h
> 32))
950 obj
= armada_gem_object_lookup(file
, handle
);
954 /* Must be a kernel-mapped object */
956 drm_gem_object_put_unlocked(&obj
->obj
);
960 if (obj
->obj
.size
< w
* h
* 4) {
961 DRM_ERROR("buffer is too small\n");
962 drm_gem_object_put_unlocked(&obj
->obj
);
967 if (dcrtc
->cursor_obj
) {
968 dcrtc
->cursor_obj
->update
= NULL
;
969 dcrtc
->cursor_obj
->update_data
= NULL
;
970 drm_gem_object_put_unlocked(&dcrtc
->cursor_obj
->obj
);
972 dcrtc
->cursor_obj
= obj
;
975 ret
= armada_drm_crtc_cursor_update(dcrtc
, true);
977 obj
->update_data
= dcrtc
;
978 obj
->update
= cursor_update
;
984 static int armada_drm_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
986 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
989 /* If no cursor support, replicate drm's return value */
990 if (!dcrtc
->variant
->has_spu_adv_reg
)
995 ret
= armada_drm_crtc_cursor_update(dcrtc
, false);
1000 static void armada_drm_crtc_destroy(struct drm_crtc
*crtc
)
1002 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1003 struct armada_private
*priv
= crtc
->dev
->dev_private
;
1005 if (dcrtc
->cursor_obj
)
1006 drm_gem_object_put_unlocked(&dcrtc
->cursor_obj
->obj
);
1008 priv
->dcrtc
[dcrtc
->num
] = NULL
;
1009 drm_crtc_cleanup(&dcrtc
->crtc
);
1011 if (!IS_ERR(dcrtc
->clk
))
1012 clk_disable_unprepare(dcrtc
->clk
);
1014 writel_relaxed(0, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
1016 of_node_put(dcrtc
->crtc
.port
);
1022 * The mode_config lock is held here, to prevent races between this
1025 static int armada_drm_crtc_page_flip(struct drm_crtc
*crtc
,
1026 struct drm_framebuffer
*fb
, struct drm_pending_vblank_event
*event
, uint32_t page_flip_flags
,
1027 struct drm_modeset_acquire_ctx
*ctx
)
1029 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1030 struct armada_frame_work
*work
;
1034 /* We don't support changing the pixel format */
1035 if (fb
->format
!= crtc
->primary
->fb
->format
)
1038 work
= kmalloc(sizeof(*work
), GFP_KERNEL
);
1042 work
->work
.fn
= armada_drm_crtc_complete_frame_work
;
1043 work
->event
= event
;
1044 work
->old_fb
= dcrtc
->crtc
.primary
->fb
;
1046 i
= armada_drm_crtc_calc_fb(fb
, crtc
->x
, crtc
->y
, work
->regs
,
1048 armada_reg_queue_end(work
->regs
, i
);
1051 * Ensure that we hold a reference on the new framebuffer.
1052 * This has to match the behaviour in mode_set.
1054 drm_framebuffer_get(fb
);
1056 ret
= armada_drm_crtc_queue_frame_work(dcrtc
, work
);
1058 /* Undo our reference above */
1059 drm_framebuffer_put(fb
);
1065 * Don't take a reference on the new framebuffer;
1066 * drm_mode_page_flip_ioctl() has already grabbed a reference and
1067 * will _not_ drop that reference on successful return from this
1068 * function. Simply mark this new framebuffer as the current one.
1070 dcrtc
->crtc
.primary
->fb
= fb
;
1073 * Finally, if the display is blanked, we won't receive an
1074 * interrupt, so complete it now.
1076 if (dpms_blanked(dcrtc
->dpms
))
1077 armada_drm_plane_work_run(dcrtc
, dcrtc
->crtc
.primary
);
1083 armada_drm_crtc_set_property(struct drm_crtc
*crtc
,
1084 struct drm_property
*property
, uint64_t val
)
1086 struct armada_private
*priv
= crtc
->dev
->dev_private
;
1087 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1088 bool update_csc
= false;
1090 if (property
== priv
->csc_yuv_prop
) {
1091 dcrtc
->csc_yuv_mode
= val
;
1093 } else if (property
== priv
->csc_rgb_prop
) {
1094 dcrtc
->csc_rgb_mode
= val
;
1101 val
= dcrtc
->spu_iopad_ctrl
|
1102 armada_drm_crtc_calculate_csc(dcrtc
);
1103 writel_relaxed(val
, dcrtc
->base
+ LCD_SPU_IOPAD_CONTROL
);
1109 /* These are called under the vbl_lock. */
1110 static int armada_drm_crtc_enable_vblank(struct drm_crtc
*crtc
)
1112 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1114 armada_drm_crtc_enable_irq(dcrtc
, VSYNC_IRQ_ENA
);
1118 static void armada_drm_crtc_disable_vblank(struct drm_crtc
*crtc
)
1120 struct armada_crtc
*dcrtc
= drm_to_armada_crtc(crtc
);
1122 armada_drm_crtc_disable_irq(dcrtc
, VSYNC_IRQ_ENA
);
1125 static const struct drm_crtc_funcs armada_crtc_funcs
= {
1126 .cursor_set
= armada_drm_crtc_cursor_set
,
1127 .cursor_move
= armada_drm_crtc_cursor_move
,
1128 .destroy
= armada_drm_crtc_destroy
,
1129 .set_config
= drm_crtc_helper_set_config
,
1130 .page_flip
= armada_drm_crtc_page_flip
,
1131 .set_property
= armada_drm_crtc_set_property
,
1132 .enable_vblank
= armada_drm_crtc_enable_vblank
,
1133 .disable_vblank
= armada_drm_crtc_disable_vblank
,
1136 static const struct drm_plane_funcs armada_primary_plane_funcs
= {
1137 .update_plane
= drm_primary_helper_update
,
1138 .disable_plane
= drm_primary_helper_disable
,
1139 .destroy
= drm_primary_helper_destroy
,
1142 int armada_drm_plane_init(struct armada_plane
*plane
)
1144 init_waitqueue_head(&plane
->frame_wait
);
1149 static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list
[] = {
1150 { CSC_AUTO
, "Auto" },
1151 { CSC_YUV_CCIR601
, "CCIR601" },
1152 { CSC_YUV_CCIR709
, "CCIR709" },
1155 static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list
[] = {
1156 { CSC_AUTO
, "Auto" },
1157 { CSC_RGB_COMPUTER
, "Computer system" },
1158 { CSC_RGB_STUDIO
, "Studio" },
1161 static int armada_drm_crtc_create_properties(struct drm_device
*dev
)
1163 struct armada_private
*priv
= dev
->dev_private
;
1165 if (priv
->csc_yuv_prop
)
1168 priv
->csc_yuv_prop
= drm_property_create_enum(dev
, 0,
1169 "CSC_YUV", armada_drm_csc_yuv_enum_list
,
1170 ARRAY_SIZE(armada_drm_csc_yuv_enum_list
));
1171 priv
->csc_rgb_prop
= drm_property_create_enum(dev
, 0,
1172 "CSC_RGB", armada_drm_csc_rgb_enum_list
,
1173 ARRAY_SIZE(armada_drm_csc_rgb_enum_list
));
1175 if (!priv
->csc_yuv_prop
|| !priv
->csc_rgb_prop
)
1181 static int armada_drm_crtc_create(struct drm_device
*drm
, struct device
*dev
,
1182 struct resource
*res
, int irq
, const struct armada_variant
*variant
,
1183 struct device_node
*port
)
1185 struct armada_private
*priv
= drm
->dev_private
;
1186 struct armada_crtc
*dcrtc
;
1187 struct armada_plane
*primary
;
1191 ret
= armada_drm_crtc_create_properties(drm
);
1195 base
= devm_ioremap_resource(dev
, res
);
1197 return PTR_ERR(base
);
1199 dcrtc
= kzalloc(sizeof(*dcrtc
), GFP_KERNEL
);
1201 DRM_ERROR("failed to allocate Armada crtc\n");
1205 if (dev
!= drm
->dev
)
1206 dev_set_drvdata(dev
, dcrtc
);
1208 dcrtc
->variant
= variant
;
1210 dcrtc
->num
= drm
->mode_config
.num_crtc
;
1211 dcrtc
->clk
= ERR_PTR(-EINVAL
);
1212 dcrtc
->csc_yuv_mode
= CSC_AUTO
;
1213 dcrtc
->csc_rgb_mode
= CSC_AUTO
;
1214 dcrtc
->cfg_dumb_ctrl
= DUMB24_RGB888_0
;
1215 dcrtc
->spu_iopad_ctrl
= CFG_VSCALE_LN_EN
| CFG_IOPAD_DUMB24
;
1216 spin_lock_init(&dcrtc
->irq_lock
);
1217 dcrtc
->irq_ena
= CLEAN_SPU_IRQ_ISR
;
1219 /* Initialize some registers which we don't otherwise set */
1220 writel_relaxed(0x00000001, dcrtc
->base
+ LCD_CFG_SCLK_DIV
);
1221 writel_relaxed(0x00000000, dcrtc
->base
+ LCD_SPU_BLANKCOLOR
);
1222 writel_relaxed(dcrtc
->spu_iopad_ctrl
,
1223 dcrtc
->base
+ LCD_SPU_IOPAD_CONTROL
);
1224 writel_relaxed(0x00000000, dcrtc
->base
+ LCD_SPU_SRAM_PARA0
);
1225 writel_relaxed(CFG_PDWN256x32
| CFG_PDWN256x24
| CFG_PDWN256x8
|
1226 CFG_PDWN32x32
| CFG_PDWN16x66
| CFG_PDWN32x66
|
1227 CFG_PDWN64x66
, dcrtc
->base
+ LCD_SPU_SRAM_PARA1
);
1228 writel_relaxed(0x2032ff81, dcrtc
->base
+ LCD_SPU_DMA_CTRL1
);
1229 writel_relaxed(dcrtc
->irq_ena
, dcrtc
->base
+ LCD_SPU_IRQ_ENA
);
1230 writel_relaxed(0, dcrtc
->base
+ LCD_SPU_IRQ_ISR
);
1232 ret
= devm_request_irq(dev
, irq
, armada_drm_irq
, 0, "armada_drm_crtc",
1237 if (dcrtc
->variant
->init
) {
1238 ret
= dcrtc
->variant
->init(dcrtc
, dev
);
1243 /* Ensure AXI pipeline is enabled */
1244 armada_updatel(CFG_ARBFAST_ENA
, 0, dcrtc
->base
+ LCD_SPU_DMA_CTRL0
);
1246 priv
->dcrtc
[dcrtc
->num
] = dcrtc
;
1248 dcrtc
->crtc
.port
= port
;
1250 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
1256 ret
= armada_drm_plane_init(primary
);
1262 ret
= drm_universal_plane_init(drm
, &primary
->base
, 0,
1263 &armada_primary_plane_funcs
,
1264 armada_primary_formats
,
1265 ARRAY_SIZE(armada_primary_formats
),
1267 DRM_PLANE_TYPE_PRIMARY
, NULL
);
1273 ret
= drm_crtc_init_with_planes(drm
, &dcrtc
->crtc
, &primary
->base
, NULL
,
1274 &armada_crtc_funcs
, NULL
);
1278 drm_crtc_helper_add(&dcrtc
->crtc
, &armada_crtc_helper_funcs
);
1280 drm_object_attach_property(&dcrtc
->crtc
.base
, priv
->csc_yuv_prop
,
1281 dcrtc
->csc_yuv_mode
);
1282 drm_object_attach_property(&dcrtc
->crtc
.base
, priv
->csc_rgb_prop
,
1283 dcrtc
->csc_rgb_mode
);
1285 return armada_overlay_plane_create(drm
, 1 << dcrtc
->num
);
1288 primary
->base
.funcs
->destroy(&primary
->base
);
1296 armada_lcd_bind(struct device
*dev
, struct device
*master
, void *data
)
1298 struct platform_device
*pdev
= to_platform_device(dev
);
1299 struct drm_device
*drm
= data
;
1300 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1301 int irq
= platform_get_irq(pdev
, 0);
1302 const struct armada_variant
*variant
;
1303 struct device_node
*port
= NULL
;
1308 if (!dev
->of_node
) {
1309 const struct platform_device_id
*id
;
1311 id
= platform_get_device_id(pdev
);
1315 variant
= (const struct armada_variant
*)id
->driver_data
;
1317 const struct of_device_id
*match
;
1318 struct device_node
*np
, *parent
= dev
->of_node
;
1320 match
= of_match_device(dev
->driver
->of_match_table
, dev
);
1324 np
= of_get_child_by_name(parent
, "ports");
1327 port
= of_get_child_by_name(parent
, "port");
1330 dev_err(dev
, "no port node found in %pOF\n", parent
);
1334 variant
= match
->data
;
1337 return armada_drm_crtc_create(drm
, dev
, res
, irq
, variant
, port
);
1341 armada_lcd_unbind(struct device
*dev
, struct device
*master
, void *data
)
1343 struct armada_crtc
*dcrtc
= dev_get_drvdata(dev
);
1345 armada_drm_crtc_destroy(&dcrtc
->crtc
);
1348 static const struct component_ops armada_lcd_ops
= {
1349 .bind
= armada_lcd_bind
,
1350 .unbind
= armada_lcd_unbind
,
1353 static int armada_lcd_probe(struct platform_device
*pdev
)
1355 return component_add(&pdev
->dev
, &armada_lcd_ops
);
1358 static int armada_lcd_remove(struct platform_device
*pdev
)
1360 component_del(&pdev
->dev
, &armada_lcd_ops
);
1364 static const struct of_device_id armada_lcd_of_match
[] = {
1366 .compatible
= "marvell,dove-lcd",
1367 .data
= &armada510_ops
,
1371 MODULE_DEVICE_TABLE(of
, armada_lcd_of_match
);
1373 static const struct platform_device_id armada_lcd_platform_ids
[] = {
1375 .name
= "armada-lcd",
1376 .driver_data
= (unsigned long)&armada510_ops
,
1378 .name
= "armada-510-lcd",
1379 .driver_data
= (unsigned long)&armada510_ops
,
1383 MODULE_DEVICE_TABLE(platform
, armada_lcd_platform_ids
);
1385 struct platform_driver armada_lcd_platform_driver
= {
1386 .probe
= armada_lcd_probe
,
1387 .remove
= armada_lcd_remove
,
1389 .name
= "armada-lcd",
1390 .owner
= THIS_MODULE
,
1391 .of_match_table
= armada_lcd_of_match
,
1393 .id_table
= armada_lcd_platform_ids
,