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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / ast / ast_post.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29 #include <drm/drmP.h>
30 #include "ast_drv.h"
31
32 #include "ast_dram_tables.h"
33
34 static void ast_init_dram_2300(struct drm_device *dev);
35
36 void ast_enable_vga(struct drm_device *dev)
37 {
38 struct ast_private *ast = dev->dev_private;
39
40 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
41 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01);
42 }
43
44 void ast_enable_mmio(struct drm_device *dev)
45 {
46 struct ast_private *ast = dev->dev_private;
47
48 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
49 }
50
51
52 bool ast_is_vga_enabled(struct drm_device *dev)
53 {
54 struct ast_private *ast = dev->dev_private;
55 u8 ch;
56
57 if (ast->chip == AST1180) {
58 /* TODO 1180 */
59 } else {
60 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
61 if (ch) {
62 ast_open_key(ast);
63 ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff);
64 return ch & 0x04;
65 }
66 }
67 return 0;
68 }
69
70 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
71 static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
72 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
73
74 static void
75 ast_set_def_ext_reg(struct drm_device *dev)
76 {
77 struct ast_private *ast = dev->dev_private;
78 u8 i, index, reg;
79 const u8 *ext_reg_info;
80
81 /* reset scratch */
82 for (i = 0x81; i <= 0x8f; i++)
83 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
84
85 if (ast->chip == AST2300 || ast->chip == AST2400) {
86 if (dev->pdev->revision >= 0x20)
87 ext_reg_info = extreginfo_ast2300;
88 else
89 ext_reg_info = extreginfo_ast2300a0;
90 } else
91 ext_reg_info = extreginfo;
92
93 index = 0xa0;
94 while (*ext_reg_info != 0xff) {
95 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
96 index++;
97 ext_reg_info++;
98 }
99
100 /* disable standard IO/MEM decode if secondary */
101 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
102
103 /* Set Ext. Default */
104 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
105 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
106
107 /* Enable RAMDAC for A1 */
108 reg = 0x04;
109 if (ast->chip == AST2300 || ast->chip == AST2400)
110 reg |= 0x20;
111 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
112 }
113
114 u32 ast_mindwm(struct ast_private *ast, u32 r)
115 {
116 uint32_t data;
117
118 ast_write32(ast, 0xf004, r & 0xffff0000);
119 ast_write32(ast, 0xf000, 0x1);
120
121 do {
122 data = ast_read32(ast, 0xf004) & 0xffff0000;
123 } while (data != (r & 0xffff0000));
124 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
125 }
126
127 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
128 {
129 uint32_t data;
130 ast_write32(ast, 0xf004, r & 0xffff0000);
131 ast_write32(ast, 0xf000, 0x1);
132 do {
133 data = ast_read32(ast, 0xf004) & 0xffff0000;
134 } while (data != (r & 0xffff0000));
135 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
136 }
137
138 /*
139 * AST2100/2150 DLL CBR Setting
140 */
141 #define CBR_SIZE_AST2150 ((16 << 10) - 1)
142 #define CBR_PASSNUM_AST2150 5
143 #define CBR_THRESHOLD_AST2150 10
144 #define CBR_THRESHOLD2_AST2150 10
145 #define TIMEOUT_AST2150 5000000
146
147 #define CBR_PATNUM_AST2150 8
148
149 static const u32 pattern_AST2150[14] = {
150 0xFF00FF00,
151 0xCC33CC33,
152 0xAA55AA55,
153 0xFFFE0001,
154 0x683501FE,
155 0x0F1929B0,
156 0x2D0B4346,
157 0x60767F02,
158 0x6FBE36A6,
159 0x3A253035,
160 0x3019686D,
161 0x41C6167E,
162 0x620152BF,
163 0x20F050E0
164 };
165
166 static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
167 {
168 u32 data, timeout;
169
170 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
171 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
172 timeout = 0;
173 do {
174 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
175 if (++timeout > TIMEOUT_AST2150) {
176 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
177 return 0xffffffff;
178 }
179 } while (!data);
180 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
181 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
182 timeout = 0;
183 do {
184 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
185 if (++timeout > TIMEOUT_AST2150) {
186 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
187 return 0xffffffff;
188 }
189 } while (!data);
190 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
191 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
192 return data;
193 }
194
195 #if 0 /* unused in DDX driver - here for completeness */
196 static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
197 {
198 u32 data, timeout;
199
200 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
201 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
202 timeout = 0;
203 do {
204 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
205 if (++timeout > TIMEOUT_AST2150) {
206 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
207 return 0xffffffff;
208 }
209 } while (!data);
210 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
211 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
212 return data;
213 }
214 #endif
215
216 static int cbrtest_ast2150(struct ast_private *ast)
217 {
218 int i;
219
220 for (i = 0; i < 8; i++)
221 if (mmctestburst2_ast2150(ast, i))
222 return 0;
223 return 1;
224 }
225
226 static int cbrscan_ast2150(struct ast_private *ast, int busw)
227 {
228 u32 patcnt, loop;
229
230 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
231 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
232 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
233 if (cbrtest_ast2150(ast))
234 break;
235 }
236 if (loop == CBR_PASSNUM_AST2150)
237 return 0;
238 }
239 return 1;
240 }
241
242
243 static void cbrdlli_ast2150(struct ast_private *ast, int busw)
244 {
245 u32 dll_min[4], dll_max[4], dlli, data, passcnt;
246
247 cbr_start:
248 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
249 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
250 passcnt = 0;
251
252 for (dlli = 0; dlli < 100; dlli++) {
253 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
254 data = cbrscan_ast2150(ast, busw);
255 if (data != 0) {
256 if (data & 0x1) {
257 if (dll_min[0] > dlli)
258 dll_min[0] = dlli;
259 if (dll_max[0] < dlli)
260 dll_max[0] = dlli;
261 }
262 passcnt++;
263 } else if (passcnt >= CBR_THRESHOLD_AST2150)
264 goto cbr_start;
265 }
266 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
267 goto cbr_start;
268
269 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
270 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
271 }
272
273
274
275 static void ast_init_dram_reg(struct drm_device *dev)
276 {
277 struct ast_private *ast = dev->dev_private;
278 u8 j;
279 u32 data, temp, i;
280 const struct ast_dramstruct *dram_reg_info;
281
282 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
283
284 if ((j & 0x80) == 0) { /* VGA only */
285 if (ast->chip == AST2000) {
286 dram_reg_info = ast2000_dram_table_data;
287 ast_write32(ast, 0xf004, 0x1e6e0000);
288 ast_write32(ast, 0xf000, 0x1);
289 ast_write32(ast, 0x10100, 0xa8);
290
291 do {
292 ;
293 } while (ast_read32(ast, 0x10100) != 0xa8);
294 } else {/* AST2100/1100 */
295 if (ast->chip == AST2100 || ast->chip == 2200)
296 dram_reg_info = ast2100_dram_table_data;
297 else
298 dram_reg_info = ast1100_dram_table_data;
299
300 ast_write32(ast, 0xf004, 0x1e6e0000);
301 ast_write32(ast, 0xf000, 0x1);
302 ast_write32(ast, 0x12000, 0x1688A8A8);
303 do {
304 ;
305 } while (ast_read32(ast, 0x12000) != 0x01);
306
307 ast_write32(ast, 0x10000, 0xfc600309);
308 do {
309 ;
310 } while (ast_read32(ast, 0x10000) != 0x01);
311 }
312
313 while (dram_reg_info->index != 0xffff) {
314 if (dram_reg_info->index == 0xff00) {/* delay fn */
315 for (i = 0; i < 15; i++)
316 udelay(dram_reg_info->data);
317 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
318 data = dram_reg_info->data;
319 if (ast->dram_type == AST_DRAM_1Gx16)
320 data = 0x00000d89;
321 else if (ast->dram_type == AST_DRAM_1Gx32)
322 data = 0x00000c8d;
323
324 temp = ast_read32(ast, 0x12070);
325 temp &= 0xc;
326 temp <<= 2;
327 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
328 } else
329 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
330 dram_reg_info++;
331 }
332
333 /* AST 2100/2150 DRAM calibration */
334 data = ast_read32(ast, 0x10120);
335 if (data == 0x5061) { /* 266Mhz */
336 data = ast_read32(ast, 0x10004);
337 if (data & 0x40)
338 cbrdlli_ast2150(ast, 16); /* 16 bits */
339 else
340 cbrdlli_ast2150(ast, 32); /* 32 bits */
341 }
342
343 switch (ast->chip) {
344 case AST2000:
345 temp = ast_read32(ast, 0x10140);
346 ast_write32(ast, 0x10140, temp | 0x40);
347 break;
348 case AST1100:
349 case AST2100:
350 case AST2200:
351 case AST2150:
352 temp = ast_read32(ast, 0x1200c);
353 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
354 temp = ast_read32(ast, 0x12040);
355 ast_write32(ast, 0x12040, temp | 0x40);
356 break;
357 default:
358 break;
359 }
360 }
361
362 /* wait ready */
363 do {
364 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
365 } while ((j & 0x40) == 0);
366 }
367
368 void ast_post_gpu(struct drm_device *dev)
369 {
370 u32 reg;
371 struct ast_private *ast = dev->dev_private;
372
373 pci_read_config_dword(ast->dev->pdev, 0x04, &reg);
374 reg |= 0x3;
375 pci_write_config_dword(ast->dev->pdev, 0x04, reg);
376
377 ast_enable_vga(dev);
378 ast_enable_mmio(dev);
379 ast_open_key(ast);
380 ast_set_def_ext_reg(dev);
381
382 if (ast->config_mode == ast_use_p2a) {
383 if (ast->chip == AST2300 || ast->chip == AST2400)
384 ast_init_dram_2300(dev);
385 else
386 ast_init_dram_reg(dev);
387
388 ast_init_3rdtx(dev);
389 } else {
390 if (ast->tx_chip_type != AST_TX_NONE)
391 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */
392 }
393 }
394
395 /* AST 2300 DRAM settings */
396 #define AST_DDR3 0
397 #define AST_DDR2 1
398
399 struct ast2300_dram_param {
400 u32 dram_type;
401 u32 dram_chipid;
402 u32 dram_freq;
403 u32 vram_size;
404 u32 odt;
405 u32 wodt;
406 u32 rodt;
407 u32 dram_config;
408 u32 reg_PERIOD;
409 u32 reg_MADJ;
410 u32 reg_SADJ;
411 u32 reg_MRS;
412 u32 reg_EMRS;
413 u32 reg_AC1;
414 u32 reg_AC2;
415 u32 reg_DQSIC;
416 u32 reg_DRV;
417 u32 reg_IOZ;
418 u32 reg_DQIDLY;
419 u32 reg_FREQ;
420 u32 madj_max;
421 u32 dll2_finetune_step;
422 };
423
424 /*
425 * DQSI DLL CBR Setting
426 */
427 #define CBR_SIZE0 ((1 << 10) - 1)
428 #define CBR_SIZE1 ((4 << 10) - 1)
429 #define CBR_SIZE2 ((64 << 10) - 1)
430 #define CBR_PASSNUM 5
431 #define CBR_PASSNUM2 5
432 #define CBR_THRESHOLD 10
433 #define CBR_THRESHOLD2 10
434 #define TIMEOUT 5000000
435 #define CBR_PATNUM 8
436
437 static const u32 pattern[8] = {
438 0xFF00FF00,
439 0xCC33CC33,
440 0xAA55AA55,
441 0x88778877,
442 0x92CC4D6E,
443 0x543D3CDE,
444 0xF1E843C7,
445 0x7C61D253
446 };
447
448 static int mmc_test_burst(struct ast_private *ast, u32 datagen)
449 {
450 u32 data, timeout;
451
452 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
453 ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
454 timeout = 0;
455 do {
456 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
457 if (data & 0x2000) {
458 return 0;
459 }
460 if (++timeout > TIMEOUT) {
461 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
462 return 0;
463 }
464 } while (!data);
465 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
466 return 1;
467 }
468
469 static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
470 {
471 u32 data, timeout;
472
473 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
474 ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
475 timeout = 0;
476 do {
477 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
478 if (++timeout > TIMEOUT) {
479 ast_moutdwm(ast, 0x1e6e0070, 0x0);
480 return -1;
481 }
482 } while (!data);
483 data = ast_mindwm(ast, 0x1e6e0078);
484 data = (data | (data >> 16)) & 0xffff;
485 ast_moutdwm(ast, 0x1e6e0070, 0x0);
486 return data;
487 }
488
489 static int mmc_test_single(struct ast_private *ast, u32 datagen)
490 {
491 u32 data, timeout;
492
493 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
494 ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
495 timeout = 0;
496 do {
497 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
498 if (data & 0x2000)
499 return 0;
500 if (++timeout > TIMEOUT) {
501 ast_moutdwm(ast, 0x1e6e0070, 0x0);
502 return 0;
503 }
504 } while (!data);
505 ast_moutdwm(ast, 0x1e6e0070, 0x0);
506 return 1;
507 }
508
509 static int mmc_test_single2(struct ast_private *ast, u32 datagen)
510 {
511 u32 data, timeout;
512
513 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
514 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
515 timeout = 0;
516 do {
517 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
518 if (++timeout > TIMEOUT) {
519 ast_moutdwm(ast, 0x1e6e0070, 0x0);
520 return -1;
521 }
522 } while (!data);
523 data = ast_mindwm(ast, 0x1e6e0078);
524 data = (data | (data >> 16)) & 0xffff;
525 ast_moutdwm(ast, 0x1e6e0070, 0x0);
526 return data;
527 }
528
529 static int cbr_test(struct ast_private *ast)
530 {
531 u32 data;
532 int i;
533 data = mmc_test_single2(ast, 0);
534 if ((data & 0xff) && (data & 0xff00))
535 return 0;
536 for (i = 0; i < 8; i++) {
537 data = mmc_test_burst2(ast, i);
538 if ((data & 0xff) && (data & 0xff00))
539 return 0;
540 }
541 if (!data)
542 return 3;
543 else if (data & 0xff)
544 return 2;
545 return 1;
546 }
547
548 static int cbr_scan(struct ast_private *ast)
549 {
550 u32 data, data2, patcnt, loop;
551
552 data2 = 3;
553 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
554 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
555 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
556 if ((data = cbr_test(ast)) != 0) {
557 data2 &= data;
558 if (!data2)
559 return 0;
560 break;
561 }
562 }
563 if (loop == CBR_PASSNUM2)
564 return 0;
565 }
566 return data2;
567 }
568
569 static u32 cbr_test2(struct ast_private *ast)
570 {
571 u32 data;
572
573 data = mmc_test_burst2(ast, 0);
574 if (data == 0xffff)
575 return 0;
576 data |= mmc_test_single2(ast, 0);
577 if (data == 0xffff)
578 return 0;
579
580 return ~data & 0xffff;
581 }
582
583 static u32 cbr_scan2(struct ast_private *ast)
584 {
585 u32 data, data2, patcnt, loop;
586
587 data2 = 0xffff;
588 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
589 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
590 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
591 if ((data = cbr_test2(ast)) != 0) {
592 data2 &= data;
593 if (!data2)
594 return 0;
595 break;
596 }
597 }
598 if (loop == CBR_PASSNUM2)
599 return 0;
600 }
601 return data2;
602 }
603
604 static u32 cbr_test3(struct ast_private *ast)
605 {
606 if (!mmc_test_burst(ast, 0))
607 return 0;
608 if (!mmc_test_single(ast, 0))
609 return 0;
610 return 1;
611 }
612
613 static u32 cbr_scan3(struct ast_private *ast)
614 {
615 u32 patcnt, loop;
616
617 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
618 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
619 for (loop = 0; loop < 2; loop++) {
620 if (cbr_test3(ast))
621 break;
622 }
623 if (loop == 2)
624 return 0;
625 }
626 return 1;
627 }
628
629 static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
630 {
631 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
632 bool status = false;
633 FINETUNE_START:
634 for (cnt = 0; cnt < 16; cnt++) {
635 dllmin[cnt] = 0xff;
636 dllmax[cnt] = 0x0;
637 }
638 passcnt = 0;
639 for (dlli = 0; dlli < 76; dlli++) {
640 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
641 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
642 data = cbr_scan2(ast);
643 if (data != 0) {
644 mask = 0x00010001;
645 for (cnt = 0; cnt < 16; cnt++) {
646 if (data & mask) {
647 if (dllmin[cnt] > dlli) {
648 dllmin[cnt] = dlli;
649 }
650 if (dllmax[cnt] < dlli) {
651 dllmax[cnt] = dlli;
652 }
653 }
654 mask <<= 1;
655 }
656 passcnt++;
657 } else if (passcnt >= CBR_THRESHOLD2) {
658 break;
659 }
660 }
661 gold_sadj[0] = 0x0;
662 passcnt = 0;
663 for (cnt = 0; cnt < 16; cnt++) {
664 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
665 gold_sadj[0] += dllmin[cnt];
666 passcnt++;
667 }
668 }
669 if (retry++ > 10)
670 goto FINETUNE_DONE;
671 if (passcnt != 16) {
672 goto FINETUNE_START;
673 }
674 status = true;
675 FINETUNE_DONE:
676 gold_sadj[0] = gold_sadj[0] >> 4;
677 gold_sadj[1] = gold_sadj[0];
678
679 data = 0;
680 for (cnt = 0; cnt < 8; cnt++) {
681 data >>= 3;
682 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
683 dlli = dllmin[cnt];
684 if (gold_sadj[0] >= dlli) {
685 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
686 if (dlli > 3) {
687 dlli = 3;
688 }
689 } else {
690 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
691 if (dlli > 4) {
692 dlli = 4;
693 }
694 dlli = (8 - dlli) & 0x7;
695 }
696 data |= dlli << 21;
697 }
698 }
699 ast_moutdwm(ast, 0x1E6E0080, data);
700
701 data = 0;
702 for (cnt = 8; cnt < 16; cnt++) {
703 data >>= 3;
704 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
705 dlli = dllmin[cnt];
706 if (gold_sadj[1] >= dlli) {
707 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
708 if (dlli > 3) {
709 dlli = 3;
710 } else {
711 dlli = (dlli - 1) & 0x7;
712 }
713 } else {
714 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
715 dlli += 1;
716 if (dlli > 4) {
717 dlli = 4;
718 }
719 dlli = (8 - dlli) & 0x7;
720 }
721 data |= dlli << 21;
722 }
723 }
724 ast_moutdwm(ast, 0x1E6E0084, data);
725 return status;
726 } /* finetuneDQI_L */
727
728 static void finetuneDQSI(struct ast_private *ast)
729 {
730 u32 dlli, dqsip, dqidly;
731 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
732 u32 g_dqidly, g_dqsip, g_margin, g_side;
733 u16 pass[32][2][2];
734 char tag[2][76];
735
736 /* Disable DQI CBR */
737 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
738 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
739 reg_mcr18 &= 0x0000ffff;
740 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
741
742 for (dlli = 0; dlli < 76; dlli++) {
743 tag[0][dlli] = 0x0;
744 tag[1][dlli] = 0x0;
745 }
746 for (dqidly = 0; dqidly < 32; dqidly++) {
747 pass[dqidly][0][0] = 0xff;
748 pass[dqidly][0][1] = 0x0;
749 pass[dqidly][1][0] = 0xff;
750 pass[dqidly][1][1] = 0x0;
751 }
752 for (dqidly = 0; dqidly < 32; dqidly++) {
753 passcnt[0] = passcnt[1] = 0;
754 for (dqsip = 0; dqsip < 2; dqsip++) {
755 ast_moutdwm(ast, 0x1E6E000C, 0);
756 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
757 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
758 for (dlli = 0; dlli < 76; dlli++) {
759 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
760 ast_moutdwm(ast, 0x1E6E0070, 0);
761 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
762 if (cbr_scan3(ast)) {
763 if (dlli == 0)
764 break;
765 passcnt[dqsip]++;
766 tag[dqsip][dlli] = 'P';
767 if (dlli < pass[dqidly][dqsip][0])
768 pass[dqidly][dqsip][0] = (u16) dlli;
769 if (dlli > pass[dqidly][dqsip][1])
770 pass[dqidly][dqsip][1] = (u16) dlli;
771 } else if (passcnt[dqsip] >= 5)
772 break;
773 else {
774 pass[dqidly][dqsip][0] = 0xff;
775 pass[dqidly][dqsip][1] = 0x0;
776 }
777 }
778 }
779 if (passcnt[0] == 0 && passcnt[1] == 0)
780 dqidly++;
781 }
782 /* Search margin */
783 g_dqidly = g_dqsip = g_margin = g_side = 0;
784
785 for (dqidly = 0; dqidly < 32; dqidly++) {
786 for (dqsip = 0; dqsip < 2; dqsip++) {
787 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
788 continue;
789 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
790 if ((diff+2) < g_margin)
791 continue;
792 passcnt[0] = passcnt[1] = 0;
793 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
794 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
795 if (passcnt[0] > passcnt[1])
796 passcnt[0] = passcnt[1];
797 passcnt[1] = 0;
798 if (passcnt[0] > g_side)
799 passcnt[1] = passcnt[0] - g_side;
800 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
801 g_margin = diff;
802 g_dqidly = dqidly;
803 g_dqsip = dqsip;
804 g_side = passcnt[0];
805 } else if (passcnt[1] > 1 && g_side < 8) {
806 if (diff > g_margin)
807 g_margin = diff;
808 g_dqidly = dqidly;
809 g_dqsip = dqsip;
810 g_side = passcnt[0];
811 }
812 }
813 }
814 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
815 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
816
817 }
818 static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
819 {
820 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
821 bool status = false;
822
823 finetuneDQSI(ast);
824 if (finetuneDQI_L(ast, param) == false)
825 return status;
826
827 CBR_START2:
828 dllmin[0] = dllmin[1] = 0xff;
829 dllmax[0] = dllmax[1] = 0x0;
830 passcnt = 0;
831 for (dlli = 0; dlli < 76; dlli++) {
832 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
833 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
834 data = cbr_scan(ast);
835 if (data != 0) {
836 if (data & 0x1) {
837 if (dllmin[0] > dlli) {
838 dllmin[0] = dlli;
839 }
840 if (dllmax[0] < dlli) {
841 dllmax[0] = dlli;
842 }
843 }
844 if (data & 0x2) {
845 if (dllmin[1] > dlli) {
846 dllmin[1] = dlli;
847 }
848 if (dllmax[1] < dlli) {
849 dllmax[1] = dlli;
850 }
851 }
852 passcnt++;
853 } else if (passcnt >= CBR_THRESHOLD) {
854 break;
855 }
856 }
857 if (retry++ > 10)
858 goto CBR_DONE2;
859 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
860 goto CBR_START2;
861 }
862 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
863 goto CBR_START2;
864 }
865 status = true;
866 CBR_DONE2:
867 dlli = (dllmin[1] + dllmax[1]) >> 1;
868 dlli <<= 8;
869 dlli += (dllmin[0] + dllmax[0]) >> 1;
870 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
871 return status;
872 } /* CBRDLL2 */
873
874 static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
875 {
876 u32 trap, trap_AC2, trap_MRS;
877
878 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
879
880 /* Ger trap info */
881 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
882 trap_AC2 = 0x00020000 + (trap << 16);
883 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
884 trap_MRS = 0x00000010 + (trap << 4);
885 trap_MRS |= ((trap & 0x2) << 18);
886
887 param->reg_MADJ = 0x00034C4C;
888 param->reg_SADJ = 0x00001800;
889 param->reg_DRV = 0x000000F0;
890 param->reg_PERIOD = param->dram_freq;
891 param->rodt = 0;
892
893 switch (param->dram_freq) {
894 case 336:
895 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
896 param->wodt = 0;
897 param->reg_AC1 = 0x22202725;
898 param->reg_AC2 = 0xAA007613 | trap_AC2;
899 param->reg_DQSIC = 0x000000BA;
900 param->reg_MRS = 0x04001400 | trap_MRS;
901 param->reg_EMRS = 0x00000000;
902 param->reg_IOZ = 0x00000023;
903 param->reg_DQIDLY = 0x00000074;
904 param->reg_FREQ = 0x00004DC0;
905 param->madj_max = 96;
906 param->dll2_finetune_step = 3;
907 switch (param->dram_chipid) {
908 default:
909 case AST_DRAM_512Mx16:
910 case AST_DRAM_1Gx16:
911 param->reg_AC2 = 0xAA007613 | trap_AC2;
912 break;
913 case AST_DRAM_2Gx16:
914 param->reg_AC2 = 0xAA00761C | trap_AC2;
915 break;
916 case AST_DRAM_4Gx16:
917 param->reg_AC2 = 0xAA007636 | trap_AC2;
918 break;
919 }
920 break;
921 default:
922 case 396:
923 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
924 param->wodt = 1;
925 param->reg_AC1 = 0x33302825;
926 param->reg_AC2 = 0xCC009617 | trap_AC2;
927 param->reg_DQSIC = 0x000000E2;
928 param->reg_MRS = 0x04001600 | trap_MRS;
929 param->reg_EMRS = 0x00000000;
930 param->reg_IOZ = 0x00000034;
931 param->reg_DRV = 0x000000FA;
932 param->reg_DQIDLY = 0x00000089;
933 param->reg_FREQ = 0x00005040;
934 param->madj_max = 96;
935 param->dll2_finetune_step = 4;
936
937 switch (param->dram_chipid) {
938 default:
939 case AST_DRAM_512Mx16:
940 case AST_DRAM_1Gx16:
941 param->reg_AC2 = 0xCC009617 | trap_AC2;
942 break;
943 case AST_DRAM_2Gx16:
944 param->reg_AC2 = 0xCC009622 | trap_AC2;
945 break;
946 case AST_DRAM_4Gx16:
947 param->reg_AC2 = 0xCC00963F | trap_AC2;
948 break;
949 }
950 break;
951
952 case 408:
953 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
954 param->wodt = 1;
955 param->reg_AC1 = 0x33302825;
956 param->reg_AC2 = 0xCC009617 | trap_AC2;
957 param->reg_DQSIC = 0x000000E2;
958 param->reg_MRS = 0x04001600 | trap_MRS;
959 param->reg_EMRS = 0x00000000;
960 param->reg_IOZ = 0x00000023;
961 param->reg_DRV = 0x000000FA;
962 param->reg_DQIDLY = 0x00000089;
963 param->reg_FREQ = 0x000050C0;
964 param->madj_max = 96;
965 param->dll2_finetune_step = 4;
966
967 switch (param->dram_chipid) {
968 default:
969 case AST_DRAM_512Mx16:
970 case AST_DRAM_1Gx16:
971 param->reg_AC2 = 0xCC009617 | trap_AC2;
972 break;
973 case AST_DRAM_2Gx16:
974 param->reg_AC2 = 0xCC009622 | trap_AC2;
975 break;
976 case AST_DRAM_4Gx16:
977 param->reg_AC2 = 0xCC00963F | trap_AC2;
978 break;
979 }
980
981 break;
982 case 456:
983 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
984 param->wodt = 0;
985 param->reg_AC1 = 0x33302926;
986 param->reg_AC2 = 0xCD44961A;
987 param->reg_DQSIC = 0x000000FC;
988 param->reg_MRS = 0x00081830;
989 param->reg_EMRS = 0x00000000;
990 param->reg_IOZ = 0x00000045;
991 param->reg_DQIDLY = 0x00000097;
992 param->reg_FREQ = 0x000052C0;
993 param->madj_max = 88;
994 param->dll2_finetune_step = 4;
995 break;
996 case 504:
997 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
998 param->wodt = 1;
999 param->reg_AC1 = 0x33302926;
1000 param->reg_AC2 = 0xDE44A61D;
1001 param->reg_DQSIC = 0x00000117;
1002 param->reg_MRS = 0x00081A30;
1003 param->reg_EMRS = 0x00000000;
1004 param->reg_IOZ = 0x070000BB;
1005 param->reg_DQIDLY = 0x000000A0;
1006 param->reg_FREQ = 0x000054C0;
1007 param->madj_max = 79;
1008 param->dll2_finetune_step = 4;
1009 break;
1010 case 528:
1011 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
1012 param->wodt = 1;
1013 param->rodt = 1;
1014 param->reg_AC1 = 0x33302926;
1015 param->reg_AC2 = 0xEF44B61E;
1016 param->reg_DQSIC = 0x00000125;
1017 param->reg_MRS = 0x00081A30;
1018 param->reg_EMRS = 0x00000040;
1019 param->reg_DRV = 0x000000F5;
1020 param->reg_IOZ = 0x00000023;
1021 param->reg_DQIDLY = 0x00000088;
1022 param->reg_FREQ = 0x000055C0;
1023 param->madj_max = 76;
1024 param->dll2_finetune_step = 3;
1025 break;
1026 case 576:
1027 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1028 param->reg_MADJ = 0x00136868;
1029 param->reg_SADJ = 0x00004534;
1030 param->wodt = 1;
1031 param->rodt = 1;
1032 param->reg_AC1 = 0x33302A37;
1033 param->reg_AC2 = 0xEF56B61E;
1034 param->reg_DQSIC = 0x0000013F;
1035 param->reg_MRS = 0x00101A50;
1036 param->reg_EMRS = 0x00000040;
1037 param->reg_DRV = 0x000000FA;
1038 param->reg_IOZ = 0x00000023;
1039 param->reg_DQIDLY = 0x00000078;
1040 param->reg_FREQ = 0x000057C0;
1041 param->madj_max = 136;
1042 param->dll2_finetune_step = 3;
1043 break;
1044 case 600:
1045 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1046 param->reg_MADJ = 0x00136868;
1047 param->reg_SADJ = 0x00004534;
1048 param->wodt = 1;
1049 param->rodt = 1;
1050 param->reg_AC1 = 0x32302A37;
1051 param->reg_AC2 = 0xDF56B61F;
1052 param->reg_DQSIC = 0x0000014D;
1053 param->reg_MRS = 0x00101A50;
1054 param->reg_EMRS = 0x00000004;
1055 param->reg_DRV = 0x000000F5;
1056 param->reg_IOZ = 0x00000023;
1057 param->reg_DQIDLY = 0x00000078;
1058 param->reg_FREQ = 0x000058C0;
1059 param->madj_max = 132;
1060 param->dll2_finetune_step = 3;
1061 break;
1062 case 624:
1063 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1064 param->reg_MADJ = 0x00136868;
1065 param->reg_SADJ = 0x00004534;
1066 param->wodt = 1;
1067 param->rodt = 1;
1068 param->reg_AC1 = 0x32302A37;
1069 param->reg_AC2 = 0xEF56B621;
1070 param->reg_DQSIC = 0x0000015A;
1071 param->reg_MRS = 0x02101A50;
1072 param->reg_EMRS = 0x00000004;
1073 param->reg_DRV = 0x000000F5;
1074 param->reg_IOZ = 0x00000034;
1075 param->reg_DQIDLY = 0x00000078;
1076 param->reg_FREQ = 0x000059C0;
1077 param->madj_max = 128;
1078 param->dll2_finetune_step = 3;
1079 break;
1080 } /* switch freq */
1081
1082 switch (param->dram_chipid) {
1083 case AST_DRAM_512Mx16:
1084 param->dram_config = 0x130;
1085 break;
1086 default:
1087 case AST_DRAM_1Gx16:
1088 param->dram_config = 0x131;
1089 break;
1090 case AST_DRAM_2Gx16:
1091 param->dram_config = 0x132;
1092 break;
1093 case AST_DRAM_4Gx16:
1094 param->dram_config = 0x133;
1095 break;
1096 } /* switch size */
1097
1098 switch (param->vram_size) {
1099 default:
1100 case AST_VIDMEM_SIZE_8M:
1101 param->dram_config |= 0x00;
1102 break;
1103 case AST_VIDMEM_SIZE_16M:
1104 param->dram_config |= 0x04;
1105 break;
1106 case AST_VIDMEM_SIZE_32M:
1107 param->dram_config |= 0x08;
1108 break;
1109 case AST_VIDMEM_SIZE_64M:
1110 param->dram_config |= 0x0c;
1111 break;
1112 }
1113
1114 }
1115
1116 static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1117 {
1118 u32 data, data2, retry = 0;
1119
1120 ddr3_init_start:
1121 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1122 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1123 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1124 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1125 udelay(10);
1126 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1127 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1128 udelay(10);
1129 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1130 udelay(10);
1131
1132 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1133 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1134 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1135 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1136 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1137 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1138 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1139 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1140 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1141 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1142 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1143 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1144 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1145 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1146 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1147 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1148 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1149 ast_moutdwm(ast, 0x1E6E0054, 0);
1150 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1151 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1152 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1153 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1154 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1155 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1156 /* Wait MCLK2X lock to MCLK */
1157 do {
1158 data = ast_mindwm(ast, 0x1E6E001C);
1159 } while (!(data & 0x08000000));
1160 data = ast_mindwm(ast, 0x1E6E001C);
1161 data = (data >> 8) & 0xff;
1162 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1163 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1164 if ((data2 & 0xff) > param->madj_max) {
1165 break;
1166 }
1167 ast_moutdwm(ast, 0x1E6E0064, data2);
1168 if (data2 & 0x00100000) {
1169 data2 = ((data2 & 0xff) >> 3) + 3;
1170 } else {
1171 data2 = ((data2 & 0xff) >> 2) + 5;
1172 }
1173 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1174 data2 += data & 0xff;
1175 data = data | (data2 << 8);
1176 ast_moutdwm(ast, 0x1E6E0068, data);
1177 udelay(10);
1178 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1179 udelay(10);
1180 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1181 ast_moutdwm(ast, 0x1E6E0018, data);
1182 data = data | 0x200;
1183 ast_moutdwm(ast, 0x1E6E0018, data);
1184 do {
1185 data = ast_mindwm(ast, 0x1E6E001C);
1186 } while (!(data & 0x08000000));
1187
1188 data = ast_mindwm(ast, 0x1E6E001C);
1189 data = (data >> 8) & 0xff;
1190 }
1191 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1192 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1193 ast_moutdwm(ast, 0x1E6E0018, data);
1194
1195 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1196 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1197 udelay(50);
1198 /* Mode Register Setting */
1199 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1200 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1201 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1202 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1203 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1204 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1205 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1206 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1207 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1208
1209 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1210 data = 0;
1211 if (param->wodt) {
1212 data = 0x300;
1213 }
1214 if (param->rodt) {
1215 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1216 }
1217 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1218
1219 /* Calibrate the DQSI delay */
1220 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1221 goto ddr3_init_start;
1222
1223 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1224 /* ECC Memory Initialization */
1225 #ifdef ECC
1226 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1227 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1228 do {
1229 data = ast_mindwm(ast, 0x1E6E0070);
1230 } while (!(data & 0x00001000));
1231 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1232 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1233 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1234 #endif
1235
1236
1237 }
1238
1239 static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
1240 {
1241 u32 trap, trap_AC2, trap_MRS;
1242
1243 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1244
1245 /* Ger trap info */
1246 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1247 trap_AC2 = (trap << 20) | (trap << 16);
1248 trap_AC2 += 0x00110000;
1249 trap_MRS = 0x00000040 | (trap << 4);
1250
1251
1252 param->reg_MADJ = 0x00034C4C;
1253 param->reg_SADJ = 0x00001800;
1254 param->reg_DRV = 0x000000F0;
1255 param->reg_PERIOD = param->dram_freq;
1256 param->rodt = 0;
1257
1258 switch (param->dram_freq) {
1259 case 264:
1260 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1261 param->wodt = 0;
1262 param->reg_AC1 = 0x11101513;
1263 param->reg_AC2 = 0x78117011;
1264 param->reg_DQSIC = 0x00000092;
1265 param->reg_MRS = 0x00000842;
1266 param->reg_EMRS = 0x00000000;
1267 param->reg_DRV = 0x000000F0;
1268 param->reg_IOZ = 0x00000034;
1269 param->reg_DQIDLY = 0x0000005A;
1270 param->reg_FREQ = 0x00004AC0;
1271 param->madj_max = 138;
1272 param->dll2_finetune_step = 3;
1273 break;
1274 case 336:
1275 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1276 param->wodt = 1;
1277 param->reg_AC1 = 0x22202613;
1278 param->reg_AC2 = 0xAA009016 | trap_AC2;
1279 param->reg_DQSIC = 0x000000BA;
1280 param->reg_MRS = 0x00000A02 | trap_MRS;
1281 param->reg_EMRS = 0x00000040;
1282 param->reg_DRV = 0x000000FA;
1283 param->reg_IOZ = 0x00000034;
1284 param->reg_DQIDLY = 0x00000074;
1285 param->reg_FREQ = 0x00004DC0;
1286 param->madj_max = 96;
1287 param->dll2_finetune_step = 3;
1288 switch (param->dram_chipid) {
1289 default:
1290 case AST_DRAM_512Mx16:
1291 param->reg_AC2 = 0xAA009012 | trap_AC2;
1292 break;
1293 case AST_DRAM_1Gx16:
1294 param->reg_AC2 = 0xAA009016 | trap_AC2;
1295 break;
1296 case AST_DRAM_2Gx16:
1297 param->reg_AC2 = 0xAA009023 | trap_AC2;
1298 break;
1299 case AST_DRAM_4Gx16:
1300 param->reg_AC2 = 0xAA00903B | trap_AC2;
1301 break;
1302 }
1303 break;
1304 default:
1305 case 396:
1306 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1307 param->wodt = 1;
1308 param->rodt = 0;
1309 param->reg_AC1 = 0x33302714;
1310 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1311 param->reg_DQSIC = 0x000000E2;
1312 param->reg_MRS = 0x00000C02 | trap_MRS;
1313 param->reg_EMRS = 0x00000040;
1314 param->reg_DRV = 0x000000FA;
1315 param->reg_IOZ = 0x00000034;
1316 param->reg_DQIDLY = 0x00000089;
1317 param->reg_FREQ = 0x00005040;
1318 param->madj_max = 96;
1319 param->dll2_finetune_step = 4;
1320
1321 switch (param->dram_chipid) {
1322 case AST_DRAM_512Mx16:
1323 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1324 break;
1325 default:
1326 case AST_DRAM_1Gx16:
1327 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1328 break;
1329 case AST_DRAM_2Gx16:
1330 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1331 break;
1332 case AST_DRAM_4Gx16:
1333 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1334 break;
1335 }
1336
1337 break;
1338
1339 case 408:
1340 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1341 param->wodt = 1;
1342 param->rodt = 0;
1343 param->reg_AC1 = 0x33302714;
1344 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1345 param->reg_DQSIC = 0x000000E2;
1346 param->reg_MRS = 0x00000C02 | trap_MRS;
1347 param->reg_EMRS = 0x00000040;
1348 param->reg_DRV = 0x000000FA;
1349 param->reg_IOZ = 0x00000034;
1350 param->reg_DQIDLY = 0x00000089;
1351 param->reg_FREQ = 0x000050C0;
1352 param->madj_max = 96;
1353 param->dll2_finetune_step = 4;
1354
1355 switch (param->dram_chipid) {
1356 case AST_DRAM_512Mx16:
1357 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1358 break;
1359 default:
1360 case AST_DRAM_1Gx16:
1361 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1362 break;
1363 case AST_DRAM_2Gx16:
1364 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1365 break;
1366 case AST_DRAM_4Gx16:
1367 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1368 break;
1369 }
1370
1371 break;
1372 case 456:
1373 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1374 param->wodt = 0;
1375 param->reg_AC1 = 0x33302815;
1376 param->reg_AC2 = 0xCD44B01E;
1377 param->reg_DQSIC = 0x000000FC;
1378 param->reg_MRS = 0x00000E72;
1379 param->reg_EMRS = 0x00000000;
1380 param->reg_DRV = 0x00000000;
1381 param->reg_IOZ = 0x00000034;
1382 param->reg_DQIDLY = 0x00000097;
1383 param->reg_FREQ = 0x000052C0;
1384 param->madj_max = 88;
1385 param->dll2_finetune_step = 3;
1386 break;
1387 case 504:
1388 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1389 param->wodt = 1;
1390 param->rodt = 1;
1391 param->reg_AC1 = 0x33302815;
1392 param->reg_AC2 = 0xDE44C022;
1393 param->reg_DQSIC = 0x00000117;
1394 param->reg_MRS = 0x00000E72;
1395 param->reg_EMRS = 0x00000040;
1396 param->reg_DRV = 0x0000000A;
1397 param->reg_IOZ = 0x00000045;
1398 param->reg_DQIDLY = 0x000000A0;
1399 param->reg_FREQ = 0x000054C0;
1400 param->madj_max = 79;
1401 param->dll2_finetune_step = 3;
1402 break;
1403 case 528:
1404 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1405 param->wodt = 1;
1406 param->rodt = 1;
1407 param->reg_AC1 = 0x33302815;
1408 param->reg_AC2 = 0xEF44D024;
1409 param->reg_DQSIC = 0x00000125;
1410 param->reg_MRS = 0x00000E72;
1411 param->reg_EMRS = 0x00000004;
1412 param->reg_DRV = 0x000000F9;
1413 param->reg_IOZ = 0x00000045;
1414 param->reg_DQIDLY = 0x000000A7;
1415 param->reg_FREQ = 0x000055C0;
1416 param->madj_max = 76;
1417 param->dll2_finetune_step = 3;
1418 break;
1419 case 552:
1420 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1421 param->wodt = 1;
1422 param->rodt = 1;
1423 param->reg_AC1 = 0x43402915;
1424 param->reg_AC2 = 0xFF44E025;
1425 param->reg_DQSIC = 0x00000132;
1426 param->reg_MRS = 0x00000E72;
1427 param->reg_EMRS = 0x00000040;
1428 param->reg_DRV = 0x0000000A;
1429 param->reg_IOZ = 0x00000045;
1430 param->reg_DQIDLY = 0x000000AD;
1431 param->reg_FREQ = 0x000056C0;
1432 param->madj_max = 76;
1433 param->dll2_finetune_step = 3;
1434 break;
1435 case 576:
1436 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1437 param->wodt = 1;
1438 param->rodt = 1;
1439 param->reg_AC1 = 0x43402915;
1440 param->reg_AC2 = 0xFF44E027;
1441 param->reg_DQSIC = 0x0000013F;
1442 param->reg_MRS = 0x00000E72;
1443 param->reg_EMRS = 0x00000004;
1444 param->reg_DRV = 0x000000F5;
1445 param->reg_IOZ = 0x00000045;
1446 param->reg_DQIDLY = 0x000000B3;
1447 param->reg_FREQ = 0x000057C0;
1448 param->madj_max = 76;
1449 param->dll2_finetune_step = 3;
1450 break;
1451 }
1452
1453 switch (param->dram_chipid) {
1454 case AST_DRAM_512Mx16:
1455 param->dram_config = 0x100;
1456 break;
1457 default:
1458 case AST_DRAM_1Gx16:
1459 param->dram_config = 0x121;
1460 break;
1461 case AST_DRAM_2Gx16:
1462 param->dram_config = 0x122;
1463 break;
1464 case AST_DRAM_4Gx16:
1465 param->dram_config = 0x123;
1466 break;
1467 } /* switch size */
1468
1469 switch (param->vram_size) {
1470 default:
1471 case AST_VIDMEM_SIZE_8M:
1472 param->dram_config |= 0x00;
1473 break;
1474 case AST_VIDMEM_SIZE_16M:
1475 param->dram_config |= 0x04;
1476 break;
1477 case AST_VIDMEM_SIZE_32M:
1478 param->dram_config |= 0x08;
1479 break;
1480 case AST_VIDMEM_SIZE_64M:
1481 param->dram_config |= 0x0c;
1482 break;
1483 }
1484 }
1485
1486 static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1487 {
1488 u32 data, data2, retry = 0;
1489
1490 ddr2_init_start:
1491 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1492 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1493 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1494 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1495 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1496 udelay(10);
1497 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1498 udelay(10);
1499
1500 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1501 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1502 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1503 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1504 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1505 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1506 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1507 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1508 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1509 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1510 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1511 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1512 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1513 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1514 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1515 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1516 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1517 ast_moutdwm(ast, 0x1E6E0054, 0);
1518 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1519 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1520 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1521 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1522 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1523 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1524
1525 /* Wait MCLK2X lock to MCLK */
1526 do {
1527 data = ast_mindwm(ast, 0x1E6E001C);
1528 } while (!(data & 0x08000000));
1529 data = ast_mindwm(ast, 0x1E6E001C);
1530 data = (data >> 8) & 0xff;
1531 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1532 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1533 if ((data2 & 0xff) > param->madj_max) {
1534 break;
1535 }
1536 ast_moutdwm(ast, 0x1E6E0064, data2);
1537 if (data2 & 0x00100000) {
1538 data2 = ((data2 & 0xff) >> 3) + 3;
1539 } else {
1540 data2 = ((data2 & 0xff) >> 2) + 5;
1541 }
1542 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1543 data2 += data & 0xff;
1544 data = data | (data2 << 8);
1545 ast_moutdwm(ast, 0x1E6E0068, data);
1546 udelay(10);
1547 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1548 udelay(10);
1549 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1550 ast_moutdwm(ast, 0x1E6E0018, data);
1551 data = data | 0x200;
1552 ast_moutdwm(ast, 0x1E6E0018, data);
1553 do {
1554 data = ast_mindwm(ast, 0x1E6E001C);
1555 } while (!(data & 0x08000000));
1556
1557 data = ast_mindwm(ast, 0x1E6E001C);
1558 data = (data >> 8) & 0xff;
1559 }
1560 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1561 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1562 ast_moutdwm(ast, 0x1E6E0018, data);
1563
1564 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1565 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1566 udelay(50);
1567 /* Mode Register Setting */
1568 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1569 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1570 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1571 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1572 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1573 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1574
1575 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1576 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1577 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1578 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1579 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1580 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1581 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1582
1583 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1584 data = 0;
1585 if (param->wodt) {
1586 data = 0x500;
1587 }
1588 if (param->rodt) {
1589 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1590 }
1591 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1592 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1593
1594 /* Calibrate the DQSI delay */
1595 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1596 goto ddr2_init_start;
1597
1598 /* ECC Memory Initialization */
1599 #ifdef ECC
1600 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1601 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1602 do {
1603 data = ast_mindwm(ast, 0x1E6E0070);
1604 } while (!(data & 0x00001000));
1605 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1606 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1607 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1608 #endif
1609
1610 }
1611
1612 static void ast_init_dram_2300(struct drm_device *dev)
1613 {
1614 struct ast_private *ast = dev->dev_private;
1615 struct ast2300_dram_param param;
1616 u32 temp;
1617 u8 reg;
1618
1619 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1620 if ((reg & 0x80) == 0) {/* vga only */
1621 ast_write32(ast, 0xf004, 0x1e6e0000);
1622 ast_write32(ast, 0xf000, 0x1);
1623 ast_write32(ast, 0x12000, 0x1688a8a8);
1624 do {
1625 ;
1626 } while (ast_read32(ast, 0x12000) != 0x1);
1627
1628 ast_write32(ast, 0x10000, 0xfc600309);
1629 do {
1630 ;
1631 } while (ast_read32(ast, 0x10000) != 0x1);
1632
1633 /* Slow down CPU/AHB CLK in VGA only mode */
1634 temp = ast_read32(ast, 0x12008);
1635 temp |= 0x73;
1636 ast_write32(ast, 0x12008, temp);
1637
1638 param.dram_type = AST_DDR3;
1639 if (temp & 0x01000000)
1640 param.dram_type = AST_DDR2;
1641 param.dram_chipid = ast->dram_type;
1642 param.dram_freq = ast->mclk;
1643 param.vram_size = ast->vram_size;
1644
1645 if (param.dram_type == AST_DDR3) {
1646 get_ddr3_info(ast, &param);
1647 ddr3_init(ast, &param);
1648 } else {
1649 get_ddr2_info(ast, &param);
1650 ddr2_init(ast, &param);
1651 }
1652
1653 temp = ast_mindwm(ast, 0x1e6e2040);
1654 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1655 }
1656
1657 /* wait ready */
1658 do {
1659 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1660 } while ((reg & 0x40) == 0);
1661 }
1662
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