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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / ast / ast_post.c
1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29 #include <drm/drmP.h>
30 #include "ast_drv.h"
31
32 #include "ast_dram_tables.h"
33
34 static void ast_post_chip_2300(struct drm_device *dev);
35
36 void ast_enable_vga(struct drm_device *dev)
37 {
38 struct ast_private *ast = dev->dev_private;
39
40 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
41 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01);
42 }
43
44 void ast_enable_mmio(struct drm_device *dev)
45 {
46 struct ast_private *ast = dev->dev_private;
47
48 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
49 }
50
51
52 bool ast_is_vga_enabled(struct drm_device *dev)
53 {
54 struct ast_private *ast = dev->dev_private;
55 u8 ch;
56
57 if (ast->chip == AST1180) {
58 /* TODO 1180 */
59 } else {
60 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
61 if (ch) {
62 ast_open_key(ast);
63 ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff);
64 return ch & 0x04;
65 }
66 }
67 return 0;
68 }
69
70 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
71 static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
72 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
73
74 static void
75 ast_set_def_ext_reg(struct drm_device *dev)
76 {
77 struct ast_private *ast = dev->dev_private;
78 u8 i, index, reg;
79 const u8 *ext_reg_info;
80
81 /* reset scratch */
82 for (i = 0x81; i <= 0x9f; i++)
83 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
84
85 if (ast->chip == AST2300 || ast->chip == AST2400) {
86 if (dev->pdev->revision >= 0x20)
87 ext_reg_info = extreginfo_ast2300;
88 else
89 ext_reg_info = extreginfo_ast2300a0;
90 } else
91 ext_reg_info = extreginfo;
92
93 index = 0xa0;
94 while (*ext_reg_info != 0xff) {
95 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
96 index++;
97 ext_reg_info++;
98 }
99
100 /* disable standard IO/MEM decode if secondary */
101 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
102
103 /* Set Ext. Default */
104 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
105 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
106
107 /* Enable RAMDAC for A1 */
108 reg = 0x04;
109 if (ast->chip == AST2300 || ast->chip == AST2400)
110 reg |= 0x20;
111 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
112 }
113
114 u32 ast_mindwm(struct ast_private *ast, u32 r)
115 {
116 uint32_t data;
117
118 ast_write32(ast, 0xf004, r & 0xffff0000);
119 ast_write32(ast, 0xf000, 0x1);
120
121 do {
122 data = ast_read32(ast, 0xf004) & 0xffff0000;
123 } while (data != (r & 0xffff0000));
124 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
125 }
126
127 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
128 {
129 uint32_t data;
130 ast_write32(ast, 0xf004, r & 0xffff0000);
131 ast_write32(ast, 0xf000, 0x1);
132 do {
133 data = ast_read32(ast, 0xf004) & 0xffff0000;
134 } while (data != (r & 0xffff0000));
135 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
136 }
137
138 /*
139 * AST2100/2150 DLL CBR Setting
140 */
141 #define CBR_SIZE_AST2150 ((16 << 10) - 1)
142 #define CBR_PASSNUM_AST2150 5
143 #define CBR_THRESHOLD_AST2150 10
144 #define CBR_THRESHOLD2_AST2150 10
145 #define TIMEOUT_AST2150 5000000
146
147 #define CBR_PATNUM_AST2150 8
148
149 static const u32 pattern_AST2150[14] = {
150 0xFF00FF00,
151 0xCC33CC33,
152 0xAA55AA55,
153 0xFFFE0001,
154 0x683501FE,
155 0x0F1929B0,
156 0x2D0B4346,
157 0x60767F02,
158 0x6FBE36A6,
159 0x3A253035,
160 0x3019686D,
161 0x41C6167E,
162 0x620152BF,
163 0x20F050E0
164 };
165
166 static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
167 {
168 u32 data, timeout;
169
170 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
171 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
172 timeout = 0;
173 do {
174 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
175 if (++timeout > TIMEOUT_AST2150) {
176 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
177 return 0xffffffff;
178 }
179 } while (!data);
180 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
181 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
182 timeout = 0;
183 do {
184 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
185 if (++timeout > TIMEOUT_AST2150) {
186 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
187 return 0xffffffff;
188 }
189 } while (!data);
190 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
191 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
192 return data;
193 }
194
195 #if 0 /* unused in DDX driver - here for completeness */
196 static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
197 {
198 u32 data, timeout;
199
200 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
201 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
202 timeout = 0;
203 do {
204 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
205 if (++timeout > TIMEOUT_AST2150) {
206 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
207 return 0xffffffff;
208 }
209 } while (!data);
210 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
211 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
212 return data;
213 }
214 #endif
215
216 static int cbrtest_ast2150(struct ast_private *ast)
217 {
218 int i;
219
220 for (i = 0; i < 8; i++)
221 if (mmctestburst2_ast2150(ast, i))
222 return 0;
223 return 1;
224 }
225
226 static int cbrscan_ast2150(struct ast_private *ast, int busw)
227 {
228 u32 patcnt, loop;
229
230 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
231 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
232 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
233 if (cbrtest_ast2150(ast))
234 break;
235 }
236 if (loop == CBR_PASSNUM_AST2150)
237 return 0;
238 }
239 return 1;
240 }
241
242
243 static void cbrdlli_ast2150(struct ast_private *ast, int busw)
244 {
245 u32 dll_min[4], dll_max[4], dlli, data, passcnt;
246
247 cbr_start:
248 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
249 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
250 passcnt = 0;
251
252 for (dlli = 0; dlli < 100; dlli++) {
253 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
254 data = cbrscan_ast2150(ast, busw);
255 if (data != 0) {
256 if (data & 0x1) {
257 if (dll_min[0] > dlli)
258 dll_min[0] = dlli;
259 if (dll_max[0] < dlli)
260 dll_max[0] = dlli;
261 }
262 passcnt++;
263 } else if (passcnt >= CBR_THRESHOLD_AST2150)
264 goto cbr_start;
265 }
266 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
267 goto cbr_start;
268
269 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
270 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
271 }
272
273
274
275 static void ast_init_dram_reg(struct drm_device *dev)
276 {
277 struct ast_private *ast = dev->dev_private;
278 u8 j;
279 u32 data, temp, i;
280 const struct ast_dramstruct *dram_reg_info;
281
282 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
283
284 if ((j & 0x80) == 0) { /* VGA only */
285 if (ast->chip == AST2000) {
286 dram_reg_info = ast2000_dram_table_data;
287 ast_write32(ast, 0xf004, 0x1e6e0000);
288 ast_write32(ast, 0xf000, 0x1);
289 ast_write32(ast, 0x10100, 0xa8);
290
291 do {
292 ;
293 } while (ast_read32(ast, 0x10100) != 0xa8);
294 } else {/* AST2100/1100 */
295 if (ast->chip == AST2100 || ast->chip == 2200)
296 dram_reg_info = ast2100_dram_table_data;
297 else
298 dram_reg_info = ast1100_dram_table_data;
299
300 ast_write32(ast, 0xf004, 0x1e6e0000);
301 ast_write32(ast, 0xf000, 0x1);
302 ast_write32(ast, 0x12000, 0x1688A8A8);
303 do {
304 ;
305 } while (ast_read32(ast, 0x12000) != 0x01);
306
307 ast_write32(ast, 0x10000, 0xfc600309);
308 do {
309 ;
310 } while (ast_read32(ast, 0x10000) != 0x01);
311 }
312
313 while (dram_reg_info->index != 0xffff) {
314 if (dram_reg_info->index == 0xff00) {/* delay fn */
315 for (i = 0; i < 15; i++)
316 udelay(dram_reg_info->data);
317 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
318 data = dram_reg_info->data;
319 if (ast->dram_type == AST_DRAM_1Gx16)
320 data = 0x00000d89;
321 else if (ast->dram_type == AST_DRAM_1Gx32)
322 data = 0x00000c8d;
323
324 temp = ast_read32(ast, 0x12070);
325 temp &= 0xc;
326 temp <<= 2;
327 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
328 } else
329 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
330 dram_reg_info++;
331 }
332
333 /* AST 2100/2150 DRAM calibration */
334 data = ast_read32(ast, 0x10120);
335 if (data == 0x5061) { /* 266Mhz */
336 data = ast_read32(ast, 0x10004);
337 if (data & 0x40)
338 cbrdlli_ast2150(ast, 16); /* 16 bits */
339 else
340 cbrdlli_ast2150(ast, 32); /* 32 bits */
341 }
342
343 switch (ast->chip) {
344 case AST2000:
345 temp = ast_read32(ast, 0x10140);
346 ast_write32(ast, 0x10140, temp | 0x40);
347 break;
348 case AST1100:
349 case AST2100:
350 case AST2200:
351 case AST2150:
352 temp = ast_read32(ast, 0x1200c);
353 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
354 temp = ast_read32(ast, 0x12040);
355 ast_write32(ast, 0x12040, temp | 0x40);
356 break;
357 default:
358 break;
359 }
360 }
361
362 /* wait ready */
363 do {
364 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
365 } while ((j & 0x40) == 0);
366 }
367
368 void ast_post_gpu(struct drm_device *dev)
369 {
370 u32 reg;
371 struct ast_private *ast = dev->dev_private;
372
373 pci_read_config_dword(ast->dev->pdev, 0x04, &reg);
374 reg |= 0x3;
375 pci_write_config_dword(ast->dev->pdev, 0x04, reg);
376
377 ast_enable_vga(dev);
378 ast_enable_mmio(dev);
379 ast_open_key(ast);
380 ast_set_def_ext_reg(dev);
381
382 if (ast->config_mode == ast_use_p2a) {
383 if (ast->chip == AST2300 || ast->chip == AST2400)
384 ast_post_chip_2300(dev);
385 else
386 ast_init_dram_reg(dev);
387
388 ast_init_3rdtx(dev);
389 } else {
390 if (ast->tx_chip_type != AST_TX_NONE)
391 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */
392 }
393 }
394
395 /* AST 2300 DRAM settings */
396 #define AST_DDR3 0
397 #define AST_DDR2 1
398
399 struct ast2300_dram_param {
400 u32 dram_type;
401 u32 dram_chipid;
402 u32 dram_freq;
403 u32 vram_size;
404 u32 odt;
405 u32 wodt;
406 u32 rodt;
407 u32 dram_config;
408 u32 reg_PERIOD;
409 u32 reg_MADJ;
410 u32 reg_SADJ;
411 u32 reg_MRS;
412 u32 reg_EMRS;
413 u32 reg_AC1;
414 u32 reg_AC2;
415 u32 reg_DQSIC;
416 u32 reg_DRV;
417 u32 reg_IOZ;
418 u32 reg_DQIDLY;
419 u32 reg_FREQ;
420 u32 madj_max;
421 u32 dll2_finetune_step;
422 };
423
424 /*
425 * DQSI DLL CBR Setting
426 */
427 #define CBR_SIZE0 ((1 << 10) - 1)
428 #define CBR_SIZE1 ((4 << 10) - 1)
429 #define CBR_SIZE2 ((64 << 10) - 1)
430 #define CBR_PASSNUM 5
431 #define CBR_PASSNUM2 5
432 #define CBR_THRESHOLD 10
433 #define CBR_THRESHOLD2 10
434 #define TIMEOUT 5000000
435 #define CBR_PATNUM 8
436
437 static const u32 pattern[8] = {
438 0xFF00FF00,
439 0xCC33CC33,
440 0xAA55AA55,
441 0x88778877,
442 0x92CC4D6E,
443 0x543D3CDE,
444 0xF1E843C7,
445 0x7C61D253
446 };
447
448 static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl)
449 {
450 u32 data, timeout;
451
452 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
453 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
454 timeout = 0;
455 do {
456 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
457 if (data & 0x2000)
458 return false;
459 if (++timeout > TIMEOUT) {
460 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
461 return false;
462 }
463 } while (!data);
464 ast_moutdwm(ast, 0x1e6e0070, 0x0);
465 return true;
466 }
467
468 static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
469 {
470 u32 data, timeout;
471
472 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
473 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
474 timeout = 0;
475 do {
476 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
477 if (++timeout > TIMEOUT) {
478 ast_moutdwm(ast, 0x1e6e0070, 0x0);
479 return 0xffffffff;
480 }
481 } while (!data);
482 data = ast_mindwm(ast, 0x1e6e0078);
483 data = (data | (data >> 16)) & 0xffff;
484 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
485 return data;
486 }
487
488
489 static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
490 {
491 return mmc_test(ast, datagen, 0xc1);
492 }
493
494 static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen)
495 {
496 return mmc_test2(ast, datagen, 0x41);
497 }
498
499 static bool mmc_test_single(struct ast_private *ast, u32 datagen)
500 {
501 return mmc_test(ast, datagen, 0xc5);
502 }
503
504 static u32 mmc_test_single2(struct ast_private *ast, u32 datagen)
505 {
506 return mmc_test2(ast, datagen, 0x05);
507 }
508
509 static int cbr_test(struct ast_private *ast)
510 {
511 u32 data;
512 int i;
513 data = mmc_test_single2(ast, 0);
514 if ((data & 0xff) && (data & 0xff00))
515 return 0;
516 for (i = 0; i < 8; i++) {
517 data = mmc_test_burst2(ast, i);
518 if ((data & 0xff) && (data & 0xff00))
519 return 0;
520 }
521 if (!data)
522 return 3;
523 else if (data & 0xff)
524 return 2;
525 return 1;
526 }
527
528 static int cbr_scan(struct ast_private *ast)
529 {
530 u32 data, data2, patcnt, loop;
531
532 data2 = 3;
533 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
534 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
535 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
536 if ((data = cbr_test(ast)) != 0) {
537 data2 &= data;
538 if (!data2)
539 return 0;
540 break;
541 }
542 }
543 if (loop == CBR_PASSNUM2)
544 return 0;
545 }
546 return data2;
547 }
548
549 static u32 cbr_test2(struct ast_private *ast)
550 {
551 u32 data;
552
553 data = mmc_test_burst2(ast, 0);
554 if (data == 0xffff)
555 return 0;
556 data |= mmc_test_single2(ast, 0);
557 if (data == 0xffff)
558 return 0;
559
560 return ~data & 0xffff;
561 }
562
563 static u32 cbr_scan2(struct ast_private *ast)
564 {
565 u32 data, data2, patcnt, loop;
566
567 data2 = 0xffff;
568 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
569 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
570 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
571 if ((data = cbr_test2(ast)) != 0) {
572 data2 &= data;
573 if (!data2)
574 return 0;
575 break;
576 }
577 }
578 if (loop == CBR_PASSNUM2)
579 return 0;
580 }
581 return data2;
582 }
583
584 static bool cbr_test3(struct ast_private *ast)
585 {
586 if (!mmc_test_burst(ast, 0))
587 return false;
588 if (!mmc_test_single(ast, 0))
589 return false;
590 return true;
591 }
592
593 static bool cbr_scan3(struct ast_private *ast)
594 {
595 u32 patcnt, loop;
596
597 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
598 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
599 for (loop = 0; loop < 2; loop++) {
600 if (cbr_test3(ast))
601 break;
602 }
603 if (loop == 2)
604 return false;
605 }
606 return true;
607 }
608
609 static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
610 {
611 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
612 bool status = false;
613 FINETUNE_START:
614 for (cnt = 0; cnt < 16; cnt++) {
615 dllmin[cnt] = 0xff;
616 dllmax[cnt] = 0x0;
617 }
618 passcnt = 0;
619 for (dlli = 0; dlli < 76; dlli++) {
620 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
621 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
622 data = cbr_scan2(ast);
623 if (data != 0) {
624 mask = 0x00010001;
625 for (cnt = 0; cnt < 16; cnt++) {
626 if (data & mask) {
627 if (dllmin[cnt] > dlli) {
628 dllmin[cnt] = dlli;
629 }
630 if (dllmax[cnt] < dlli) {
631 dllmax[cnt] = dlli;
632 }
633 }
634 mask <<= 1;
635 }
636 passcnt++;
637 } else if (passcnt >= CBR_THRESHOLD2) {
638 break;
639 }
640 }
641 gold_sadj[0] = 0x0;
642 passcnt = 0;
643 for (cnt = 0; cnt < 16; cnt++) {
644 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
645 gold_sadj[0] += dllmin[cnt];
646 passcnt++;
647 }
648 }
649 if (retry++ > 10)
650 goto FINETUNE_DONE;
651 if (passcnt != 16) {
652 goto FINETUNE_START;
653 }
654 status = true;
655 FINETUNE_DONE:
656 gold_sadj[0] = gold_sadj[0] >> 4;
657 gold_sadj[1] = gold_sadj[0];
658
659 data = 0;
660 for (cnt = 0; cnt < 8; cnt++) {
661 data >>= 3;
662 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
663 dlli = dllmin[cnt];
664 if (gold_sadj[0] >= dlli) {
665 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
666 if (dlli > 3) {
667 dlli = 3;
668 }
669 } else {
670 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
671 if (dlli > 4) {
672 dlli = 4;
673 }
674 dlli = (8 - dlli) & 0x7;
675 }
676 data |= dlli << 21;
677 }
678 }
679 ast_moutdwm(ast, 0x1E6E0080, data);
680
681 data = 0;
682 for (cnt = 8; cnt < 16; cnt++) {
683 data >>= 3;
684 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
685 dlli = dllmin[cnt];
686 if (gold_sadj[1] >= dlli) {
687 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
688 if (dlli > 3) {
689 dlli = 3;
690 } else {
691 dlli = (dlli - 1) & 0x7;
692 }
693 } else {
694 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
695 dlli += 1;
696 if (dlli > 4) {
697 dlli = 4;
698 }
699 dlli = (8 - dlli) & 0x7;
700 }
701 data |= dlli << 21;
702 }
703 }
704 ast_moutdwm(ast, 0x1E6E0084, data);
705 return status;
706 } /* finetuneDQI_L */
707
708 static void finetuneDQSI(struct ast_private *ast)
709 {
710 u32 dlli, dqsip, dqidly;
711 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
712 u32 g_dqidly, g_dqsip, g_margin, g_side;
713 u16 pass[32][2][2];
714 char tag[2][76];
715
716 /* Disable DQI CBR */
717 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
718 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
719 reg_mcr18 &= 0x0000ffff;
720 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
721
722 for (dlli = 0; dlli < 76; dlli++) {
723 tag[0][dlli] = 0x0;
724 tag[1][dlli] = 0x0;
725 }
726 for (dqidly = 0; dqidly < 32; dqidly++) {
727 pass[dqidly][0][0] = 0xff;
728 pass[dqidly][0][1] = 0x0;
729 pass[dqidly][1][0] = 0xff;
730 pass[dqidly][1][1] = 0x0;
731 }
732 for (dqidly = 0; dqidly < 32; dqidly++) {
733 passcnt[0] = passcnt[1] = 0;
734 for (dqsip = 0; dqsip < 2; dqsip++) {
735 ast_moutdwm(ast, 0x1E6E000C, 0);
736 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
737 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
738 for (dlli = 0; dlli < 76; dlli++) {
739 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
740 ast_moutdwm(ast, 0x1E6E0070, 0);
741 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
742 if (cbr_scan3(ast)) {
743 if (dlli == 0)
744 break;
745 passcnt[dqsip]++;
746 tag[dqsip][dlli] = 'P';
747 if (dlli < pass[dqidly][dqsip][0])
748 pass[dqidly][dqsip][0] = (u16) dlli;
749 if (dlli > pass[dqidly][dqsip][1])
750 pass[dqidly][dqsip][1] = (u16) dlli;
751 } else if (passcnt[dqsip] >= 5)
752 break;
753 else {
754 pass[dqidly][dqsip][0] = 0xff;
755 pass[dqidly][dqsip][1] = 0x0;
756 }
757 }
758 }
759 if (passcnt[0] == 0 && passcnt[1] == 0)
760 dqidly++;
761 }
762 /* Search margin */
763 g_dqidly = g_dqsip = g_margin = g_side = 0;
764
765 for (dqidly = 0; dqidly < 32; dqidly++) {
766 for (dqsip = 0; dqsip < 2; dqsip++) {
767 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
768 continue;
769 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
770 if ((diff+2) < g_margin)
771 continue;
772 passcnt[0] = passcnt[1] = 0;
773 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
774 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
775 if (passcnt[0] > passcnt[1])
776 passcnt[0] = passcnt[1];
777 passcnt[1] = 0;
778 if (passcnt[0] > g_side)
779 passcnt[1] = passcnt[0] - g_side;
780 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
781 g_margin = diff;
782 g_dqidly = dqidly;
783 g_dqsip = dqsip;
784 g_side = passcnt[0];
785 } else if (passcnt[1] > 1 && g_side < 8) {
786 if (diff > g_margin)
787 g_margin = diff;
788 g_dqidly = dqidly;
789 g_dqsip = dqsip;
790 g_side = passcnt[0];
791 }
792 }
793 }
794 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
795 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
796
797 }
798 static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
799 {
800 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
801 bool status = false;
802
803 finetuneDQSI(ast);
804 if (finetuneDQI_L(ast, param) == false)
805 return status;
806
807 CBR_START2:
808 dllmin[0] = dllmin[1] = 0xff;
809 dllmax[0] = dllmax[1] = 0x0;
810 passcnt = 0;
811 for (dlli = 0; dlli < 76; dlli++) {
812 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
813 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
814 data = cbr_scan(ast);
815 if (data != 0) {
816 if (data & 0x1) {
817 if (dllmin[0] > dlli) {
818 dllmin[0] = dlli;
819 }
820 if (dllmax[0] < dlli) {
821 dllmax[0] = dlli;
822 }
823 }
824 if (data & 0x2) {
825 if (dllmin[1] > dlli) {
826 dllmin[1] = dlli;
827 }
828 if (dllmax[1] < dlli) {
829 dllmax[1] = dlli;
830 }
831 }
832 passcnt++;
833 } else if (passcnt >= CBR_THRESHOLD) {
834 break;
835 }
836 }
837 if (retry++ > 10)
838 goto CBR_DONE2;
839 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
840 goto CBR_START2;
841 }
842 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
843 goto CBR_START2;
844 }
845 status = true;
846 CBR_DONE2:
847 dlli = (dllmin[1] + dllmax[1]) >> 1;
848 dlli <<= 8;
849 dlli += (dllmin[0] + dllmax[0]) >> 1;
850 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
851 return status;
852 } /* CBRDLL2 */
853
854 static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
855 {
856 u32 trap, trap_AC2, trap_MRS;
857
858 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
859
860 /* Ger trap info */
861 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
862 trap_AC2 = 0x00020000 + (trap << 16);
863 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
864 trap_MRS = 0x00000010 + (trap << 4);
865 trap_MRS |= ((trap & 0x2) << 18);
866
867 param->reg_MADJ = 0x00034C4C;
868 param->reg_SADJ = 0x00001800;
869 param->reg_DRV = 0x000000F0;
870 param->reg_PERIOD = param->dram_freq;
871 param->rodt = 0;
872
873 switch (param->dram_freq) {
874 case 336:
875 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
876 param->wodt = 0;
877 param->reg_AC1 = 0x22202725;
878 param->reg_AC2 = 0xAA007613 | trap_AC2;
879 param->reg_DQSIC = 0x000000BA;
880 param->reg_MRS = 0x04001400 | trap_MRS;
881 param->reg_EMRS = 0x00000000;
882 param->reg_IOZ = 0x00000023;
883 param->reg_DQIDLY = 0x00000074;
884 param->reg_FREQ = 0x00004DC0;
885 param->madj_max = 96;
886 param->dll2_finetune_step = 3;
887 switch (param->dram_chipid) {
888 default:
889 case AST_DRAM_512Mx16:
890 case AST_DRAM_1Gx16:
891 param->reg_AC2 = 0xAA007613 | trap_AC2;
892 break;
893 case AST_DRAM_2Gx16:
894 param->reg_AC2 = 0xAA00761C | trap_AC2;
895 break;
896 case AST_DRAM_4Gx16:
897 param->reg_AC2 = 0xAA007636 | trap_AC2;
898 break;
899 }
900 break;
901 default:
902 case 396:
903 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
904 param->wodt = 1;
905 param->reg_AC1 = 0x33302825;
906 param->reg_AC2 = 0xCC009617 | trap_AC2;
907 param->reg_DQSIC = 0x000000E2;
908 param->reg_MRS = 0x04001600 | trap_MRS;
909 param->reg_EMRS = 0x00000000;
910 param->reg_IOZ = 0x00000034;
911 param->reg_DRV = 0x000000FA;
912 param->reg_DQIDLY = 0x00000089;
913 param->reg_FREQ = 0x00005040;
914 param->madj_max = 96;
915 param->dll2_finetune_step = 4;
916
917 switch (param->dram_chipid) {
918 default:
919 case AST_DRAM_512Mx16:
920 case AST_DRAM_1Gx16:
921 param->reg_AC2 = 0xCC009617 | trap_AC2;
922 break;
923 case AST_DRAM_2Gx16:
924 param->reg_AC2 = 0xCC009622 | trap_AC2;
925 break;
926 case AST_DRAM_4Gx16:
927 param->reg_AC2 = 0xCC00963F | trap_AC2;
928 break;
929 }
930 break;
931
932 case 408:
933 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
934 param->wodt = 1;
935 param->reg_AC1 = 0x33302825;
936 param->reg_AC2 = 0xCC009617 | trap_AC2;
937 param->reg_DQSIC = 0x000000E2;
938 param->reg_MRS = 0x04001600 | trap_MRS;
939 param->reg_EMRS = 0x00000000;
940 param->reg_IOZ = 0x00000023;
941 param->reg_DRV = 0x000000FA;
942 param->reg_DQIDLY = 0x00000089;
943 param->reg_FREQ = 0x000050C0;
944 param->madj_max = 96;
945 param->dll2_finetune_step = 4;
946
947 switch (param->dram_chipid) {
948 default:
949 case AST_DRAM_512Mx16:
950 case AST_DRAM_1Gx16:
951 param->reg_AC2 = 0xCC009617 | trap_AC2;
952 break;
953 case AST_DRAM_2Gx16:
954 param->reg_AC2 = 0xCC009622 | trap_AC2;
955 break;
956 case AST_DRAM_4Gx16:
957 param->reg_AC2 = 0xCC00963F | trap_AC2;
958 break;
959 }
960
961 break;
962 case 456:
963 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
964 param->wodt = 0;
965 param->reg_AC1 = 0x33302926;
966 param->reg_AC2 = 0xCD44961A;
967 param->reg_DQSIC = 0x000000FC;
968 param->reg_MRS = 0x00081830;
969 param->reg_EMRS = 0x00000000;
970 param->reg_IOZ = 0x00000045;
971 param->reg_DQIDLY = 0x00000097;
972 param->reg_FREQ = 0x000052C0;
973 param->madj_max = 88;
974 param->dll2_finetune_step = 4;
975 break;
976 case 504:
977 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
978 param->wodt = 1;
979 param->reg_AC1 = 0x33302926;
980 param->reg_AC2 = 0xDE44A61D;
981 param->reg_DQSIC = 0x00000117;
982 param->reg_MRS = 0x00081A30;
983 param->reg_EMRS = 0x00000000;
984 param->reg_IOZ = 0x070000BB;
985 param->reg_DQIDLY = 0x000000A0;
986 param->reg_FREQ = 0x000054C0;
987 param->madj_max = 79;
988 param->dll2_finetune_step = 4;
989 break;
990 case 528:
991 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
992 param->wodt = 1;
993 param->rodt = 1;
994 param->reg_AC1 = 0x33302926;
995 param->reg_AC2 = 0xEF44B61E;
996 param->reg_DQSIC = 0x00000125;
997 param->reg_MRS = 0x00081A30;
998 param->reg_EMRS = 0x00000040;
999 param->reg_DRV = 0x000000F5;
1000 param->reg_IOZ = 0x00000023;
1001 param->reg_DQIDLY = 0x00000088;
1002 param->reg_FREQ = 0x000055C0;
1003 param->madj_max = 76;
1004 param->dll2_finetune_step = 3;
1005 break;
1006 case 576:
1007 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1008 param->reg_MADJ = 0x00136868;
1009 param->reg_SADJ = 0x00004534;
1010 param->wodt = 1;
1011 param->rodt = 1;
1012 param->reg_AC1 = 0x33302A37;
1013 param->reg_AC2 = 0xEF56B61E;
1014 param->reg_DQSIC = 0x0000013F;
1015 param->reg_MRS = 0x00101A50;
1016 param->reg_EMRS = 0x00000040;
1017 param->reg_DRV = 0x000000FA;
1018 param->reg_IOZ = 0x00000023;
1019 param->reg_DQIDLY = 0x00000078;
1020 param->reg_FREQ = 0x000057C0;
1021 param->madj_max = 136;
1022 param->dll2_finetune_step = 3;
1023 break;
1024 case 600:
1025 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1026 param->reg_MADJ = 0x00136868;
1027 param->reg_SADJ = 0x00004534;
1028 param->wodt = 1;
1029 param->rodt = 1;
1030 param->reg_AC1 = 0x32302A37;
1031 param->reg_AC2 = 0xDF56B61F;
1032 param->reg_DQSIC = 0x0000014D;
1033 param->reg_MRS = 0x00101A50;
1034 param->reg_EMRS = 0x00000004;
1035 param->reg_DRV = 0x000000F5;
1036 param->reg_IOZ = 0x00000023;
1037 param->reg_DQIDLY = 0x00000078;
1038 param->reg_FREQ = 0x000058C0;
1039 param->madj_max = 132;
1040 param->dll2_finetune_step = 3;
1041 break;
1042 case 624:
1043 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1044 param->reg_MADJ = 0x00136868;
1045 param->reg_SADJ = 0x00004534;
1046 param->wodt = 1;
1047 param->rodt = 1;
1048 param->reg_AC1 = 0x32302A37;
1049 param->reg_AC2 = 0xEF56B621;
1050 param->reg_DQSIC = 0x0000015A;
1051 param->reg_MRS = 0x02101A50;
1052 param->reg_EMRS = 0x00000004;
1053 param->reg_DRV = 0x000000F5;
1054 param->reg_IOZ = 0x00000034;
1055 param->reg_DQIDLY = 0x00000078;
1056 param->reg_FREQ = 0x000059C0;
1057 param->madj_max = 128;
1058 param->dll2_finetune_step = 3;
1059 break;
1060 } /* switch freq */
1061
1062 switch (param->dram_chipid) {
1063 case AST_DRAM_512Mx16:
1064 param->dram_config = 0x130;
1065 break;
1066 default:
1067 case AST_DRAM_1Gx16:
1068 param->dram_config = 0x131;
1069 break;
1070 case AST_DRAM_2Gx16:
1071 param->dram_config = 0x132;
1072 break;
1073 case AST_DRAM_4Gx16:
1074 param->dram_config = 0x133;
1075 break;
1076 } /* switch size */
1077
1078 switch (param->vram_size) {
1079 default:
1080 case AST_VIDMEM_SIZE_8M:
1081 param->dram_config |= 0x00;
1082 break;
1083 case AST_VIDMEM_SIZE_16M:
1084 param->dram_config |= 0x04;
1085 break;
1086 case AST_VIDMEM_SIZE_32M:
1087 param->dram_config |= 0x08;
1088 break;
1089 case AST_VIDMEM_SIZE_64M:
1090 param->dram_config |= 0x0c;
1091 break;
1092 }
1093
1094 }
1095
1096 static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1097 {
1098 u32 data, data2, retry = 0;
1099
1100 ddr3_init_start:
1101 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1102 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1103 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1104 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1105 udelay(10);
1106 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1107 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1108 udelay(10);
1109 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1110 udelay(10);
1111
1112 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1113 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1114 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1115 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1116 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1117 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1118 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1119 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1120 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1121 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1122 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1123 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1124 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1125 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1126 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1127 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1128 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1129 ast_moutdwm(ast, 0x1E6E0054, 0);
1130 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1131 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1132 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1133 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1134 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1135 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1136 /* Wait MCLK2X lock to MCLK */
1137 do {
1138 data = ast_mindwm(ast, 0x1E6E001C);
1139 } while (!(data & 0x08000000));
1140 data = ast_mindwm(ast, 0x1E6E001C);
1141 data = (data >> 8) & 0xff;
1142 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1143 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1144 if ((data2 & 0xff) > param->madj_max) {
1145 break;
1146 }
1147 ast_moutdwm(ast, 0x1E6E0064, data2);
1148 if (data2 & 0x00100000) {
1149 data2 = ((data2 & 0xff) >> 3) + 3;
1150 } else {
1151 data2 = ((data2 & 0xff) >> 2) + 5;
1152 }
1153 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1154 data2 += data & 0xff;
1155 data = data | (data2 << 8);
1156 ast_moutdwm(ast, 0x1E6E0068, data);
1157 udelay(10);
1158 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1159 udelay(10);
1160 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1161 ast_moutdwm(ast, 0x1E6E0018, data);
1162 data = data | 0x200;
1163 ast_moutdwm(ast, 0x1E6E0018, data);
1164 do {
1165 data = ast_mindwm(ast, 0x1E6E001C);
1166 } while (!(data & 0x08000000));
1167
1168 data = ast_mindwm(ast, 0x1E6E001C);
1169 data = (data >> 8) & 0xff;
1170 }
1171 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1172 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1173 ast_moutdwm(ast, 0x1E6E0018, data);
1174
1175 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1176 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1177 udelay(50);
1178 /* Mode Register Setting */
1179 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1180 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1181 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1182 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1183 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1184 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1185 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1186 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1187 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1188
1189 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1190 data = 0;
1191 if (param->wodt) {
1192 data = 0x300;
1193 }
1194 if (param->rodt) {
1195 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1196 }
1197 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1198
1199 /* Calibrate the DQSI delay */
1200 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1201 goto ddr3_init_start;
1202
1203 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1204 /* ECC Memory Initialization */
1205 #ifdef ECC
1206 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1207 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1208 do {
1209 data = ast_mindwm(ast, 0x1E6E0070);
1210 } while (!(data & 0x00001000));
1211 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1212 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1213 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1214 #endif
1215
1216
1217 }
1218
1219 static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
1220 {
1221 u32 trap, trap_AC2, trap_MRS;
1222
1223 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1224
1225 /* Ger trap info */
1226 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1227 trap_AC2 = (trap << 20) | (trap << 16);
1228 trap_AC2 += 0x00110000;
1229 trap_MRS = 0x00000040 | (trap << 4);
1230
1231
1232 param->reg_MADJ = 0x00034C4C;
1233 param->reg_SADJ = 0x00001800;
1234 param->reg_DRV = 0x000000F0;
1235 param->reg_PERIOD = param->dram_freq;
1236 param->rodt = 0;
1237
1238 switch (param->dram_freq) {
1239 case 264:
1240 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1241 param->wodt = 0;
1242 param->reg_AC1 = 0x11101513;
1243 param->reg_AC2 = 0x78117011;
1244 param->reg_DQSIC = 0x00000092;
1245 param->reg_MRS = 0x00000842;
1246 param->reg_EMRS = 0x00000000;
1247 param->reg_DRV = 0x000000F0;
1248 param->reg_IOZ = 0x00000034;
1249 param->reg_DQIDLY = 0x0000005A;
1250 param->reg_FREQ = 0x00004AC0;
1251 param->madj_max = 138;
1252 param->dll2_finetune_step = 3;
1253 break;
1254 case 336:
1255 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1256 param->wodt = 1;
1257 param->reg_AC1 = 0x22202613;
1258 param->reg_AC2 = 0xAA009016 | trap_AC2;
1259 param->reg_DQSIC = 0x000000BA;
1260 param->reg_MRS = 0x00000A02 | trap_MRS;
1261 param->reg_EMRS = 0x00000040;
1262 param->reg_DRV = 0x000000FA;
1263 param->reg_IOZ = 0x00000034;
1264 param->reg_DQIDLY = 0x00000074;
1265 param->reg_FREQ = 0x00004DC0;
1266 param->madj_max = 96;
1267 param->dll2_finetune_step = 3;
1268 switch (param->dram_chipid) {
1269 default:
1270 case AST_DRAM_512Mx16:
1271 param->reg_AC2 = 0xAA009012 | trap_AC2;
1272 break;
1273 case AST_DRAM_1Gx16:
1274 param->reg_AC2 = 0xAA009016 | trap_AC2;
1275 break;
1276 case AST_DRAM_2Gx16:
1277 param->reg_AC2 = 0xAA009023 | trap_AC2;
1278 break;
1279 case AST_DRAM_4Gx16:
1280 param->reg_AC2 = 0xAA00903B | trap_AC2;
1281 break;
1282 }
1283 break;
1284 default:
1285 case 396:
1286 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1287 param->wodt = 1;
1288 param->rodt = 0;
1289 param->reg_AC1 = 0x33302714;
1290 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1291 param->reg_DQSIC = 0x000000E2;
1292 param->reg_MRS = 0x00000C02 | trap_MRS;
1293 param->reg_EMRS = 0x00000040;
1294 param->reg_DRV = 0x000000FA;
1295 param->reg_IOZ = 0x00000034;
1296 param->reg_DQIDLY = 0x00000089;
1297 param->reg_FREQ = 0x00005040;
1298 param->madj_max = 96;
1299 param->dll2_finetune_step = 4;
1300
1301 switch (param->dram_chipid) {
1302 case AST_DRAM_512Mx16:
1303 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1304 break;
1305 default:
1306 case AST_DRAM_1Gx16:
1307 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1308 break;
1309 case AST_DRAM_2Gx16:
1310 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1311 break;
1312 case AST_DRAM_4Gx16:
1313 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1314 break;
1315 }
1316
1317 break;
1318
1319 case 408:
1320 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1321 param->wodt = 1;
1322 param->rodt = 0;
1323 param->reg_AC1 = 0x33302714;
1324 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1325 param->reg_DQSIC = 0x000000E2;
1326 param->reg_MRS = 0x00000C02 | trap_MRS;
1327 param->reg_EMRS = 0x00000040;
1328 param->reg_DRV = 0x000000FA;
1329 param->reg_IOZ = 0x00000034;
1330 param->reg_DQIDLY = 0x00000089;
1331 param->reg_FREQ = 0x000050C0;
1332 param->madj_max = 96;
1333 param->dll2_finetune_step = 4;
1334
1335 switch (param->dram_chipid) {
1336 case AST_DRAM_512Mx16:
1337 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1338 break;
1339 default:
1340 case AST_DRAM_1Gx16:
1341 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1342 break;
1343 case AST_DRAM_2Gx16:
1344 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1345 break;
1346 case AST_DRAM_4Gx16:
1347 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1348 break;
1349 }
1350
1351 break;
1352 case 456:
1353 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1354 param->wodt = 0;
1355 param->reg_AC1 = 0x33302815;
1356 param->reg_AC2 = 0xCD44B01E;
1357 param->reg_DQSIC = 0x000000FC;
1358 param->reg_MRS = 0x00000E72;
1359 param->reg_EMRS = 0x00000000;
1360 param->reg_DRV = 0x00000000;
1361 param->reg_IOZ = 0x00000034;
1362 param->reg_DQIDLY = 0x00000097;
1363 param->reg_FREQ = 0x000052C0;
1364 param->madj_max = 88;
1365 param->dll2_finetune_step = 3;
1366 break;
1367 case 504:
1368 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1369 param->wodt = 1;
1370 param->rodt = 1;
1371 param->reg_AC1 = 0x33302815;
1372 param->reg_AC2 = 0xDE44C022;
1373 param->reg_DQSIC = 0x00000117;
1374 param->reg_MRS = 0x00000E72;
1375 param->reg_EMRS = 0x00000040;
1376 param->reg_DRV = 0x0000000A;
1377 param->reg_IOZ = 0x00000045;
1378 param->reg_DQIDLY = 0x000000A0;
1379 param->reg_FREQ = 0x000054C0;
1380 param->madj_max = 79;
1381 param->dll2_finetune_step = 3;
1382 break;
1383 case 528:
1384 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1385 param->wodt = 1;
1386 param->rodt = 1;
1387 param->reg_AC1 = 0x33302815;
1388 param->reg_AC2 = 0xEF44D024;
1389 param->reg_DQSIC = 0x00000125;
1390 param->reg_MRS = 0x00000E72;
1391 param->reg_EMRS = 0x00000004;
1392 param->reg_DRV = 0x000000F9;
1393 param->reg_IOZ = 0x00000045;
1394 param->reg_DQIDLY = 0x000000A7;
1395 param->reg_FREQ = 0x000055C0;
1396 param->madj_max = 76;
1397 param->dll2_finetune_step = 3;
1398 break;
1399 case 552:
1400 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1401 param->wodt = 1;
1402 param->rodt = 1;
1403 param->reg_AC1 = 0x43402915;
1404 param->reg_AC2 = 0xFF44E025;
1405 param->reg_DQSIC = 0x00000132;
1406 param->reg_MRS = 0x00000E72;
1407 param->reg_EMRS = 0x00000040;
1408 param->reg_DRV = 0x0000000A;
1409 param->reg_IOZ = 0x00000045;
1410 param->reg_DQIDLY = 0x000000AD;
1411 param->reg_FREQ = 0x000056C0;
1412 param->madj_max = 76;
1413 param->dll2_finetune_step = 3;
1414 break;
1415 case 576:
1416 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1417 param->wodt = 1;
1418 param->rodt = 1;
1419 param->reg_AC1 = 0x43402915;
1420 param->reg_AC2 = 0xFF44E027;
1421 param->reg_DQSIC = 0x0000013F;
1422 param->reg_MRS = 0x00000E72;
1423 param->reg_EMRS = 0x00000004;
1424 param->reg_DRV = 0x000000F5;
1425 param->reg_IOZ = 0x00000045;
1426 param->reg_DQIDLY = 0x000000B3;
1427 param->reg_FREQ = 0x000057C0;
1428 param->madj_max = 76;
1429 param->dll2_finetune_step = 3;
1430 break;
1431 }
1432
1433 switch (param->dram_chipid) {
1434 case AST_DRAM_512Mx16:
1435 param->dram_config = 0x100;
1436 break;
1437 default:
1438 case AST_DRAM_1Gx16:
1439 param->dram_config = 0x121;
1440 break;
1441 case AST_DRAM_2Gx16:
1442 param->dram_config = 0x122;
1443 break;
1444 case AST_DRAM_4Gx16:
1445 param->dram_config = 0x123;
1446 break;
1447 } /* switch size */
1448
1449 switch (param->vram_size) {
1450 default:
1451 case AST_VIDMEM_SIZE_8M:
1452 param->dram_config |= 0x00;
1453 break;
1454 case AST_VIDMEM_SIZE_16M:
1455 param->dram_config |= 0x04;
1456 break;
1457 case AST_VIDMEM_SIZE_32M:
1458 param->dram_config |= 0x08;
1459 break;
1460 case AST_VIDMEM_SIZE_64M:
1461 param->dram_config |= 0x0c;
1462 break;
1463 }
1464 }
1465
1466 static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1467 {
1468 u32 data, data2, retry = 0;
1469
1470 ddr2_init_start:
1471 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1472 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1473 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1474 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1475 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1476 udelay(10);
1477 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1478 udelay(10);
1479
1480 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1481 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1482 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1483 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1484 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1485 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1486 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1487 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1488 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1489 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1490 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1491 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1492 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1493 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1494 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1495 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1496 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1497 ast_moutdwm(ast, 0x1E6E0054, 0);
1498 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1499 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1500 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1501 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1502 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1503 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1504
1505 /* Wait MCLK2X lock to MCLK */
1506 do {
1507 data = ast_mindwm(ast, 0x1E6E001C);
1508 } while (!(data & 0x08000000));
1509 data = ast_mindwm(ast, 0x1E6E001C);
1510 data = (data >> 8) & 0xff;
1511 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1512 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1513 if ((data2 & 0xff) > param->madj_max) {
1514 break;
1515 }
1516 ast_moutdwm(ast, 0x1E6E0064, data2);
1517 if (data2 & 0x00100000) {
1518 data2 = ((data2 & 0xff) >> 3) + 3;
1519 } else {
1520 data2 = ((data2 & 0xff) >> 2) + 5;
1521 }
1522 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1523 data2 += data & 0xff;
1524 data = data | (data2 << 8);
1525 ast_moutdwm(ast, 0x1E6E0068, data);
1526 udelay(10);
1527 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1528 udelay(10);
1529 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1530 ast_moutdwm(ast, 0x1E6E0018, data);
1531 data = data | 0x200;
1532 ast_moutdwm(ast, 0x1E6E0018, data);
1533 do {
1534 data = ast_mindwm(ast, 0x1E6E001C);
1535 } while (!(data & 0x08000000));
1536
1537 data = ast_mindwm(ast, 0x1E6E001C);
1538 data = (data >> 8) & 0xff;
1539 }
1540 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1541 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1542 ast_moutdwm(ast, 0x1E6E0018, data);
1543
1544 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1545 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1546 udelay(50);
1547 /* Mode Register Setting */
1548 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1549 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1550 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1551 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1552 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1553 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1554
1555 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1556 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1557 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1558 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1559 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1560 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1561 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1562
1563 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1564 data = 0;
1565 if (param->wodt) {
1566 data = 0x500;
1567 }
1568 if (param->rodt) {
1569 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1570 }
1571 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1572 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1573
1574 /* Calibrate the DQSI delay */
1575 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1576 goto ddr2_init_start;
1577
1578 /* ECC Memory Initialization */
1579 #ifdef ECC
1580 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1581 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1582 do {
1583 data = ast_mindwm(ast, 0x1E6E0070);
1584 } while (!(data & 0x00001000));
1585 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1586 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1587 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1588 #endif
1589
1590 }
1591
1592 static void ast_post_chip_2300(struct drm_device *dev)
1593 {
1594 struct ast_private *ast = dev->dev_private;
1595 struct ast2300_dram_param param;
1596 u32 temp;
1597 u8 reg;
1598
1599 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1600 if ((reg & 0x80) == 0) {/* vga only */
1601 ast_write32(ast, 0xf004, 0x1e6e0000);
1602 ast_write32(ast, 0xf000, 0x1);
1603 ast_write32(ast, 0x12000, 0x1688a8a8);
1604 do {
1605 ;
1606 } while (ast_read32(ast, 0x12000) != 0x1);
1607
1608 ast_write32(ast, 0x10000, 0xfc600309);
1609 do {
1610 ;
1611 } while (ast_read32(ast, 0x10000) != 0x1);
1612
1613 /* Slow down CPU/AHB CLK in VGA only mode */
1614 temp = ast_read32(ast, 0x12008);
1615 temp |= 0x73;
1616 ast_write32(ast, 0x12008, temp);
1617
1618 param.dram_type = AST_DDR3;
1619 if (temp & 0x01000000)
1620 param.dram_type = AST_DDR2;
1621 param.dram_chipid = ast->dram_type;
1622 param.dram_freq = ast->mclk;
1623 param.vram_size = ast->vram_size;
1624
1625 if (param.dram_type == AST_DDR3) {
1626 get_ddr3_info(ast, &param);
1627 ddr3_init(ast, &param);
1628 } else {
1629 get_ddr2_info(ast, &param);
1630 ddr2_init(ast, &param);
1631 }
1632
1633 temp = ast_mindwm(ast, 0x1e6e2040);
1634 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1635 }
1636
1637 /* wait ready */
1638 do {
1639 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1640 } while ((reg & 0x40) == 0);
1641 }
1642
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