drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

   1 /*
   2  * Copyright (C) 2014 Traphandler
   3  * Copyright (C) 2014 Free Electrons
   4  *
   5  * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
   6  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/pm.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/pinctrl/consumer.h>
  25
  26 #include <drm/drm_crtc.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/drmP.h>
  29
  30 #include <video/videomode.h>
  31
  32 #include "atmel_hlcdc_dc.h"
  33
  34 /**
  35  * Atmel HLCDC CRTC state structure
  36  *
  37  * @base: base CRTC state
  38  * @output_mode: RGBXXX output mode
  39  */
  40 struct atmel_hlcdc_crtc_state {
  41         struct drm_crtc_state base;
  42         unsigned int output_mode;
  43 };
  44
  45 static inline struct atmel_hlcdc_crtc_state *
  46 drm_crtc_state_to_atmel_hlcdc_crtc_state(struct drm_crtc_state *state)
  47 {
  48         return container_of(state, struct atmel_hlcdc_crtc_state, base);
  49 }
  50
  51 /**
  52  * Atmel HLCDC CRTC structure
  53  *
  54  * @base: base DRM CRTC structure
  55  * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
  56  * @event: pointer to the current page flip event
  57  * @id: CRTC id (returned by drm_crtc_index)
  58  */
  59 struct atmel_hlcdc_crtc {
  60         struct drm_crtc base;
  61         struct atmel_hlcdc_dc *dc;
  62         struct drm_pending_vblank_event *event;
  63         int id;
  64 };
  65
  66 static inline struct atmel_hlcdc_crtc *
  67 drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc)
  68 {
  69         return container_of(crtc, struct atmel_hlcdc_crtc, base);
  70 }
  71
  72 static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
  73 {
  74         struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
  75         struct regmap *regmap = crtc->dc->hlcdc->regmap;
  76         struct drm_display_mode *adj = &c->state->adjusted_mode;
  77         struct atmel_hlcdc_crtc_state *state;
  78         unsigned long mode_rate;
  79         struct videomode vm;
  80         unsigned long prate;
  81         unsigned int cfg;
  82         int div;
  83
  84         vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
  85         vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
  86         vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start;
  87         vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay;
  88         vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end;
  89         vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start;
  90
  91         regmap_write(regmap, ATMEL_HLCDC_CFG(1),
  92                      (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16));
  93
  94         regmap_write(regmap, ATMEL_HLCDC_CFG(2),
  95                      (vm.vfront_porch - 1) | (vm.vback_porch << 16));
  96
  97         regmap_write(regmap, ATMEL_HLCDC_CFG(3),
  98                      (vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16));
  99
 100         regmap_write(regmap, ATMEL_HLCDC_CFG(4),
 101                      (adj->crtc_hdisplay - 1) |
 102                      ((adj->crtc_vdisplay - 1) << 16));
 103
 104         cfg = 0;
 105
 106         prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
 107         mode_rate = adj->crtc_clock * 1000;
 108         if ((prate / 2) < mode_rate) {
 109                 prate *= 2;
 110                 cfg |= ATMEL_HLCDC_CLKSEL;
 111         }
 112
 113         div = DIV_ROUND_UP(prate, mode_rate);
 114         if (div < 2)
 115                 div = 2;
 116
 117         cfg |= ATMEL_HLCDC_CLKDIV(div);
 118
 119         regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0),
 120                            ATMEL_HLCDC_CLKSEL | ATMEL_HLCDC_CLKDIV_MASK |
 121                            ATMEL_HLCDC_CLKPOL, cfg);
 122
 123         cfg = 0;
 124
 125         if (adj->flags & DRM_MODE_FLAG_NVSYNC)
 126                 cfg |= ATMEL_HLCDC_VSPOL;
 127
 128         if (adj->flags & DRM_MODE_FLAG_NHSYNC)
 129                 cfg |= ATMEL_HLCDC_HSPOL;
 130
 131         state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state);
 132         cfg |= state->output_mode << 8;
 133
 134         regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
 135                            ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL |
 136                            ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE |
 137                            ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY |
 138                            ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |
 139                            ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK,
 140                            cfg);
 141 }
 142
 143 static enum drm_mode_status
 144 atmel_hlcdc_crtc_mode_valid(struct drm_crtc *c,
 145                             const struct drm_display_mode *mode)
 146 {
 147         struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
 148
 149         return atmel_hlcdc_dc_mode_valid(crtc->dc, mode);
 150 }
 151
 152 static void atmel_hlcdc_crtc_disable(struct drm_crtc *c)
 153 {
 154         struct drm_device *dev = c->dev;
 155         struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
 156         struct regmap *regmap = crtc->dc->hlcdc->regmap;
 157         unsigned int status;
 158
 159         drm_crtc_vblank_off(c);
 160
 161         pm_runtime_get_sync(dev->dev);
 162
 163         regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
 164         while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
 165                (status & ATMEL_HLCDC_DISP))
 166                 cpu_relax();
 167
 168         regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
 169         while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
 170                (status & ATMEL_HLCDC_SYNC))
 171                 cpu_relax();
 172
 173         regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
 174         while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
 175                (status & ATMEL_HLCDC_PIXEL_CLK))
 176                 cpu_relax();
 177
 178         clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
 179         pinctrl_pm_select_sleep_state(dev->dev);
 180
 181         pm_runtime_allow(dev->dev);
 182
 183         pm_runtime_put_sync(dev->dev);
 184 }
 185
 186 static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c,
 187                                            struct drm_crtc_state *old_state)
 188 {
 189         struct drm_device *dev = c->dev;
 190         struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
 191         struct regmap *regmap = crtc->dc->hlcdc->regmap;
 192         unsigned int status;
 193
 194         pm_runtime_get_sync(dev->dev);
 195
 196         pm_runtime_forbid(dev->dev);
 197
 198         pinctrl_pm_select_default_state(dev->dev);
 199         clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
 200
 201         regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
 202         while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
 203                !(status & ATMEL_HLCDC_PIXEL_CLK))
 204                 cpu_relax();
 205
 206
 207         regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
 208         while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
 209                !(status & ATMEL_HLCDC_SYNC))
 210                 cpu_relax();
 211
 212         regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
 213         while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
 214                !(status & ATMEL_HLCDC_DISP))
 215                 cpu_relax();
 216
 217         pm_runtime_put_sync(dev->dev);
 218
 219         drm_crtc_vblank_on(c);
 220 }
 221
 222 #define ATMEL_HLCDC_RGB444_OUTPUT       BIT(0)
 223 #define ATMEL_HLCDC_RGB565_OUTPUT       BIT(1)
 224 #define ATMEL_HLCDC_RGB666_OUTPUT       BIT(2)
 225 #define ATMEL_HLCDC_RGB888_OUTPUT       BIT(3)
 226 #define ATMEL_HLCDC_OUTPUT_MODE_MASK    GENMASK(3, 0)
 227
 228 static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state)
 229 {
 230         unsigned int output_fmts = ATMEL_HLCDC_OUTPUT_MODE_MASK;
 231         struct atmel_hlcdc_crtc_state *hstate;
 232         struct drm_connector_state *cstate;
 233         struct drm_connector *connector;
 234         struct atmel_hlcdc_crtc *crtc;
 235         int i;
 236
 237         crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc);
 238
 239         for_each_connector_in_state(state->state, connector, cstate, i) {
 240                 struct drm_display_info *info = &connector->display_info;
 241                 unsigned int supported_fmts = 0;
 242                 int j;
 243
 244                 if (!cstate->crtc)
 245                         continue;
 246
 247                 for (j = 0; j < info->num_bus_formats; j++) {
 248                         switch (info->bus_formats[j]) {
 249                         case MEDIA_BUS_FMT_RGB444_1X12:
 250                                 supported_fmts |= ATMEL_HLCDC_RGB444_OUTPUT;
 251                                 break;
 252                         case MEDIA_BUS_FMT_RGB565_1X16:
 253                                 supported_fmts |= ATMEL_HLCDC_RGB565_OUTPUT;
 254                                 break;
 255                         case MEDIA_BUS_FMT_RGB666_1X18:
 256                                 supported_fmts |= ATMEL_HLCDC_RGB666_OUTPUT;
 257                                 break;
 258                         case MEDIA_BUS_FMT_RGB888_1X24:
 259                                 supported_fmts |= ATMEL_HLCDC_RGB888_OUTPUT;
 260                                 break;
 261                         default:
 262                                 break;
 263                         }
 264                 }
 265
 266                 if (crtc->dc->desc->conflicting_output_formats)
 267                         output_fmts &= supported_fmts;
 268                 else
 269                         output_fmts |= supported_fmts;
 270         }
 271
 272         if (!output_fmts)
 273                 return -EINVAL;
 274
 275         hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state);
 276         hstate->output_mode = fls(output_fmts) - 1;
 277
 278         return 0;
 279 }
 280
 281 static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c,
 282                                          struct drm_crtc_state *s)
 283 {
 284         int ret;
 285
 286         ret = atmel_hlcdc_crtc_select_output_mode(s);
 287         if (ret)
 288                 return ret;
 289
 290         ret = atmel_hlcdc_plane_prepare_disc_area(s);
 291         if (ret)
 292                 return ret;
 293
 294         return atmel_hlcdc_plane_prepare_ahb_routing(s);
 295 }
 296
 297 static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c,
 298                                           struct drm_crtc_state *old_s)
 299 {
 300         struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
 301
 302         if (c->state->event) {
 303                 c->state->event->pipe = drm_crtc_index(c);
 304
 305                 WARN_ON(drm_crtc_vblank_get(c) != 0);
 306
 307                 crtc->event = c->state->event;
 308                 c->state->event = NULL;
 309         }
 310 }
 311
 312 static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *crtc,
 313                                           struct drm_crtc_state *old_s)
 314 {
 315         /* TODO: write common plane control register if available */
 316 }
 317
 318 static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
 319         .mode_valid = atmel_hlcdc_crtc_mode_valid,
 320         .mode_set = drm_helper_crtc_mode_set,
 321         .mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
 322         .mode_set_base = drm_helper_crtc_mode_set_base,
 323         .disable = atmel_hlcdc_crtc_disable,
 324         .atomic_check = atmel_hlcdc_crtc_atomic_check,
 325         .atomic_begin = atmel_hlcdc_crtc_atomic_begin,
 326         .atomic_flush = atmel_hlcdc_crtc_atomic_flush,
 327         .atomic_enable = atmel_hlcdc_crtc_atomic_enable,
 328 };
 329
 330 static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c)
 331 {
 332         struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
 333
 334         drm_crtc_cleanup(c);
 335         kfree(crtc);
 336 }
 337
 338 static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc)
 339 {
 340         struct drm_device *dev = crtc->base.dev;
 341         unsigned long flags;
 342
 343         spin_lock_irqsave(&dev->event_lock, flags);
 344         if (crtc->event) {
 345                 drm_crtc_send_vblank_event(&crtc->base, crtc->event);
 346                 drm_crtc_vblank_put(&crtc->base);
 347                 crtc->event = NULL;
 348         }
 349         spin_unlock_irqrestore(&dev->event_lock, flags);
 350 }
 351
 352 void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
 353 {
 354         drm_crtc_handle_vblank(c);
 355         atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
 356 }
 357
 358 static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
 359 {
 360         struct atmel_hlcdc_crtc_state *state;
 361
 362         if (crtc->state) {
 363                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 364                 state = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
 365                 kfree(state);
 366                 crtc->state = NULL;
 367         }
 368
 369         state = kzalloc(sizeof(*state), GFP_KERNEL);
 370         if (state) {
 371                 crtc->state = &state->base;
 372                 crtc->state->crtc = crtc;
 373         }
 374 }
 375
 376 static struct drm_crtc_state *
 377 atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc)
 378 {
 379         struct atmel_hlcdc_crtc_state *state, *cur;
 380
 381         if (WARN_ON(!crtc->state))
 382                 return NULL;
 383
 384         state = kmalloc(sizeof(*state), GFP_KERNEL);
 385         if (!state)
 386                 return NULL;
 387         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 388
 389         cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
 390         state->output_mode = cur->output_mode;
 391
 392         return &state->base;
 393 }
 394
 395 static void atmel_hlcdc_crtc_destroy_state(struct drm_crtc *crtc,
 396                                            struct drm_crtc_state *s)
 397 {
 398         struct atmel_hlcdc_crtc_state *state;
 399
 400         state = drm_crtc_state_to_atmel_hlcdc_crtc_state(s);
 401         __drm_atomic_helper_crtc_destroy_state(s);
 402         kfree(state);
 403 }
 404
 405 static int atmel_hlcdc_crtc_enable_vblank(struct drm_crtc *c)
 406 {
 407         struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
 408         struct regmap *regmap = crtc->dc->hlcdc->regmap;
 409
 410         /* Enable SOF (Start Of Frame) interrupt for vblank counting */
 411         regmap_write(regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
 412
 413         return 0;
 414 }
 415
 416 static void atmel_hlcdc_crtc_disable_vblank(struct drm_crtc *c)
 417 {
 418         struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
 419         struct regmap *regmap = crtc->dc->hlcdc->regmap;
 420
 421         regmap_write(regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
 422 }
 423
 424 static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = {
 425         .page_flip = drm_atomic_helper_page_flip,
 426         .set_config = drm_atomic_helper_set_config,
 427         .destroy = atmel_hlcdc_crtc_destroy,
 428         .reset = atmel_hlcdc_crtc_reset,
 429         .atomic_duplicate_state =  atmel_hlcdc_crtc_duplicate_state,
 430         .atomic_destroy_state = atmel_hlcdc_crtc_destroy_state,
 431         .enable_vblank = atmel_hlcdc_crtc_enable_vblank,
 432         .disable_vblank = atmel_hlcdc_crtc_disable_vblank,
 433         .set_property = drm_atomic_helper_crtc_set_property,
 434         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 435 };
 436
 437 int atmel_hlcdc_crtc_create(struct drm_device *dev)
 438 {
 439         struct atmel_hlcdc_plane *primary = NULL, *cursor = NULL;
 440         struct atmel_hlcdc_dc *dc = dev->dev_private;
 441         struct atmel_hlcdc_crtc *crtc;
 442         int ret;
 443         int i;
 444
 445         crtc = kzalloc(sizeof(*crtc), GFP_KERNEL);
 446         if (!crtc)
 447                 return -ENOMEM;
 448
 449         crtc->dc = dc;
 450
 451         for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
 452                 if (!dc->layers[i])
 453                         continue;
 454
 455                 switch (dc->layers[i]->desc->type) {
 456                 case ATMEL_HLCDC_BASE_LAYER:
 457                         primary = atmel_hlcdc_layer_to_plane(dc->layers[i]);
 458                         break;
 459
 460                 case ATMEL_HLCDC_CURSOR_LAYER:
 461                         cursor = atmel_hlcdc_layer_to_plane(dc->layers[i]);
 462                         break;
 463
 464                 default:
 465                         break;
 466                 }
 467         }
 468
 469         ret = drm_crtc_init_with_planes(dev, &crtc->base, &primary->base,
 470                                         &cursor->base, &atmel_hlcdc_crtc_funcs,
 471                                         NULL);
 472         if (ret < 0)
 473                 goto fail;
 474
 475         crtc->id = drm_crtc_index(&crtc->base);
 476
 477         for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
 478                 struct atmel_hlcdc_plane *overlay;
 479
 480                 if (dc->layers[i] &&
 481                     dc->layers[i]->desc->type == ATMEL_HLCDC_OVERLAY_LAYER) {
 482                         overlay = atmel_hlcdc_layer_to_plane(dc->layers[i]);
 483                         overlay->base.possible_crtcs = 1 << crtc->id;
 484                 }
 485         }
 486
 487         drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);
 488         drm_crtc_vblank_reset(&crtc->base);
 489
 490         drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE);
 491         drm_crtc_enable_color_mgmt(&crtc->base, 0, false,
 492                                    ATMEL_HLCDC_CLUT_SIZE);
 493
 494         dc->crtc = &crtc->base;
 495
 496         return 0;
 497
 498 fail:
 499         atmel_hlcdc_crtc_destroy(&crtc->base);
 500         return ret;
 501 }