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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / bridge / dw-hdmi.c
1 /*
2 * DesignWare High-Definition Multimedia Interface (HDMI) driver
3 *
4 * Copyright (C) 2013-2015 Mentor Graphics Inc.
5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14 #include <linux/module.h>
15 #include <linux/irq.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/hdmi.h>
20 #include <linux/mutex.h>
21 #include <linux/of_device.h>
22 #include <linux/spinlock.h>
23
24 #include <drm/drm_of.h>
25 #include <drm/drmP.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_edid.h>
29 #include <drm/drm_encoder_slave.h>
30 #include <drm/bridge/dw_hdmi.h>
31
32 #include "dw-hdmi.h"
33 #include "dw-hdmi-audio.h"
34
35 #define HDMI_EDID_LEN 512
36
37 #define RGB 0
38 #define YCBCR444 1
39 #define YCBCR422_16BITS 2
40 #define YCBCR422_8BITS 3
41 #define XVYCC444 4
42
43 enum hdmi_datamap {
44 RGB444_8B = 0x01,
45 RGB444_10B = 0x03,
46 RGB444_12B = 0x05,
47 RGB444_16B = 0x07,
48 YCbCr444_8B = 0x09,
49 YCbCr444_10B = 0x0B,
50 YCbCr444_12B = 0x0D,
51 YCbCr444_16B = 0x0F,
52 YCbCr422_8B = 0x16,
53 YCbCr422_10B = 0x14,
54 YCbCr422_12B = 0x12,
55 };
56
57 static const u16 csc_coeff_default[3][4] = {
58 { 0x2000, 0x0000, 0x0000, 0x0000 },
59 { 0x0000, 0x2000, 0x0000, 0x0000 },
60 { 0x0000, 0x0000, 0x2000, 0x0000 }
61 };
62
63 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
64 { 0x2000, 0x6926, 0x74fd, 0x010e },
65 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
66 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
67 };
68
69 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
70 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
71 { 0x2000, 0x3264, 0x0000, 0x7e6d },
72 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
73 };
74
75 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
76 { 0x2591, 0x1322, 0x074b, 0x0000 },
77 { 0x6535, 0x2000, 0x7acc, 0x0200 },
78 { 0x6acd, 0x7534, 0x2000, 0x0200 }
79 };
80
81 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
82 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
83 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
84 { 0x6756, 0x78ab, 0x2000, 0x0200 }
85 };
86
87 struct hdmi_vmode {
88 bool mdataenablepolarity;
89
90 unsigned int mpixelclock;
91 unsigned int mpixelrepetitioninput;
92 unsigned int mpixelrepetitionoutput;
93 };
94
95 struct hdmi_data_info {
96 unsigned int enc_in_format;
97 unsigned int enc_out_format;
98 unsigned int enc_color_depth;
99 unsigned int colorimetry;
100 unsigned int pix_repet_factor;
101 unsigned int hdcp_enable;
102 struct hdmi_vmode video_mode;
103 };
104
105 struct dw_hdmi_i2c {
106 struct i2c_adapter adap;
107
108 struct mutex lock; /* used to serialize data transfers */
109 struct completion cmp;
110 u8 stat;
111
112 u8 slave_reg;
113 bool is_regaddr;
114 };
115
116 struct dw_hdmi {
117 struct drm_connector connector;
118 struct drm_bridge bridge;
119
120 struct platform_device *audio;
121 enum dw_hdmi_devtype dev_type;
122 struct device *dev;
123 struct clk *isfr_clk;
124 struct clk *iahb_clk;
125 struct dw_hdmi_i2c *i2c;
126
127 struct hdmi_data_info hdmi_data;
128 const struct dw_hdmi_plat_data *plat_data;
129
130 int vic;
131
132 u8 edid[HDMI_EDID_LEN];
133 bool cable_plugin;
134
135 bool phy_enabled;
136 struct drm_display_mode previous_mode;
137
138 struct i2c_adapter *ddc;
139 void __iomem *regs;
140 bool sink_is_hdmi;
141 bool sink_has_audio;
142
143 struct mutex mutex; /* for state below and previous_mode */
144 enum drm_connector_force force; /* mutex-protected force state */
145 bool disabled; /* DRM has disabled our bridge */
146 bool bridge_is_on; /* indicates the bridge is on */
147 bool rxsense; /* rxsense state */
148 u8 phy_mask; /* desired phy int mask settings */
149
150 spinlock_t audio_lock;
151 struct mutex audio_mutex;
152 unsigned int sample_rate;
153 unsigned int audio_cts;
154 unsigned int audio_n;
155 bool audio_enable;
156
157 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
158 u8 (*read)(struct dw_hdmi *hdmi, int offset);
159 };
160
161 #define HDMI_IH_PHY_STAT0_RX_SENSE \
162 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
163 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
164
165 #define HDMI_PHY_RX_SENSE \
166 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
167 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
168
169 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
170 {
171 writel(val, hdmi->regs + (offset << 2));
172 }
173
174 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
175 {
176 return readl(hdmi->regs + (offset << 2));
177 }
178
179 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
180 {
181 writeb(val, hdmi->regs + offset);
182 }
183
184 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
185 {
186 return readb(hdmi->regs + offset);
187 }
188
189 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
190 {
191 hdmi->write(hdmi, val, offset);
192 }
193
194 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
195 {
196 return hdmi->read(hdmi, offset);
197 }
198
199 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
200 {
201 u8 val = hdmi_readb(hdmi, reg) & ~mask;
202
203 val |= data & mask;
204 hdmi_writeb(hdmi, val, reg);
205 }
206
207 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
208 u8 shift, u8 mask)
209 {
210 hdmi_modb(hdmi, data << shift, mask, reg);
211 }
212
213 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
214 {
215 /* Software reset */
216 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
217
218 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
219 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
220
221 /* Set done, not acknowledged and arbitration interrupt polarities */
222 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
223 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
224 HDMI_I2CM_CTLINT);
225
226 /* Clear DONE and ERROR interrupts */
227 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
228 HDMI_IH_I2CM_STAT0);
229
230 /* Mute DONE and ERROR interrupts */
231 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
232 HDMI_IH_MUTE_I2CM_STAT0);
233 }
234
235 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
236 unsigned char *buf, unsigned int length)
237 {
238 struct dw_hdmi_i2c *i2c = hdmi->i2c;
239 int stat;
240
241 if (!i2c->is_regaddr) {
242 dev_dbg(hdmi->dev, "set read register address to 0\n");
243 i2c->slave_reg = 0x00;
244 i2c->is_regaddr = true;
245 }
246
247 while (length--) {
248 reinit_completion(&i2c->cmp);
249
250 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
251 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
252 HDMI_I2CM_OPERATION);
253
254 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
255 if (!stat)
256 return -EAGAIN;
257
258 /* Check for error condition on the bus */
259 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
260 return -EIO;
261
262 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
263 }
264
265 return 0;
266 }
267
268 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
269 unsigned char *buf, unsigned int length)
270 {
271 struct dw_hdmi_i2c *i2c = hdmi->i2c;
272 int stat;
273
274 if (!i2c->is_regaddr) {
275 /* Use the first write byte as register address */
276 i2c->slave_reg = buf[0];
277 length--;
278 buf++;
279 i2c->is_regaddr = true;
280 }
281
282 while (length--) {
283 reinit_completion(&i2c->cmp);
284
285 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
286 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
287 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
288 HDMI_I2CM_OPERATION);
289
290 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
291 if (!stat)
292 return -EAGAIN;
293
294 /* Check for error condition on the bus */
295 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
296 return -EIO;
297 }
298
299 return 0;
300 }
301
302 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
303 struct i2c_msg *msgs, int num)
304 {
305 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
306 struct dw_hdmi_i2c *i2c = hdmi->i2c;
307 u8 addr = msgs[0].addr;
308 int i, ret = 0;
309
310 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
311
312 for (i = 0; i < num; i++) {
313 if (msgs[i].addr != addr) {
314 dev_warn(hdmi->dev,
315 "unsupported transfer, changed slave address\n");
316 return -EOPNOTSUPP;
317 }
318
319 if (msgs[i].len == 0) {
320 dev_dbg(hdmi->dev,
321 "unsupported transfer %d/%d, no data\n",
322 i + 1, num);
323 return -EOPNOTSUPP;
324 }
325 }
326
327 mutex_lock(&i2c->lock);
328
329 /* Unmute DONE and ERROR interrupts */
330 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
331
332 /* Set slave device address taken from the first I2C message */
333 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
334
335 /* Set slave device register address on transfer */
336 i2c->is_regaddr = false;
337
338 for (i = 0; i < num; i++) {
339 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
340 i + 1, num, msgs[i].len, msgs[i].flags);
341
342 if (msgs[i].flags & I2C_M_RD)
343 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
344 else
345 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
346
347 if (ret < 0)
348 break;
349 }
350
351 if (!ret)
352 ret = num;
353
354 /* Mute DONE and ERROR interrupts */
355 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
356 HDMI_IH_MUTE_I2CM_STAT0);
357
358 mutex_unlock(&i2c->lock);
359
360 return ret;
361 }
362
363 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
364 {
365 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
366 }
367
368 static const struct i2c_algorithm dw_hdmi_algorithm = {
369 .master_xfer = dw_hdmi_i2c_xfer,
370 .functionality = dw_hdmi_i2c_func,
371 };
372
373 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
374 {
375 struct i2c_adapter *adap;
376 struct dw_hdmi_i2c *i2c;
377 int ret;
378
379 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
380 if (!i2c)
381 return ERR_PTR(-ENOMEM);
382
383 mutex_init(&i2c->lock);
384 init_completion(&i2c->cmp);
385
386 adap = &i2c->adap;
387 adap->class = I2C_CLASS_DDC;
388 adap->owner = THIS_MODULE;
389 adap->dev.parent = hdmi->dev;
390 adap->algo = &dw_hdmi_algorithm;
391 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
392 i2c_set_adapdata(adap, hdmi);
393
394 ret = i2c_add_adapter(adap);
395 if (ret) {
396 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
397 devm_kfree(hdmi->dev, i2c);
398 return ERR_PTR(ret);
399 }
400
401 hdmi->i2c = i2c;
402
403 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
404
405 return adap;
406 }
407
408 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
409 unsigned int n)
410 {
411 /* Must be set/cleared first */
412 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
413
414 /* nshift factor = 0 */
415 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
416
417 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
418 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
419 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
420 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
421
422 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
423 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
424 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
425 }
426
427 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
428 {
429 unsigned int n = (128 * freq) / 1000;
430 unsigned int mult = 1;
431
432 while (freq > 48000) {
433 mult *= 2;
434 freq /= 2;
435 }
436
437 switch (freq) {
438 case 32000:
439 if (pixel_clk == 25175000)
440 n = 4576;
441 else if (pixel_clk == 27027000)
442 n = 4096;
443 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
444 n = 11648;
445 else
446 n = 4096;
447 n *= mult;
448 break;
449
450 case 44100:
451 if (pixel_clk == 25175000)
452 n = 7007;
453 else if (pixel_clk == 74176000)
454 n = 17836;
455 else if (pixel_clk == 148352000)
456 n = 8918;
457 else
458 n = 6272;
459 n *= mult;
460 break;
461
462 case 48000:
463 if (pixel_clk == 25175000)
464 n = 6864;
465 else if (pixel_clk == 27027000)
466 n = 6144;
467 else if (pixel_clk == 74176000)
468 n = 11648;
469 else if (pixel_clk == 148352000)
470 n = 5824;
471 else
472 n = 6144;
473 n *= mult;
474 break;
475
476 default:
477 break;
478 }
479
480 return n;
481 }
482
483 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
484 unsigned long pixel_clk, unsigned int sample_rate)
485 {
486 unsigned long ftdms = pixel_clk;
487 unsigned int n, cts;
488 u64 tmp;
489
490 n = hdmi_compute_n(sample_rate, pixel_clk);
491
492 /*
493 * Compute the CTS value from the N value. Note that CTS and N
494 * can be up to 20 bits in total, so we need 64-bit math. Also
495 * note that our TDMS clock is not fully accurate; it is accurate
496 * to kHz. This can introduce an unnecessary remainder in the
497 * calculation below, so we don't try to warn about that.
498 */
499 tmp = (u64)ftdms * n;
500 do_div(tmp, 128 * sample_rate);
501 cts = tmp;
502
503 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
504 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
505 n, cts);
506
507 spin_lock_irq(&hdmi->audio_lock);
508 hdmi->audio_n = n;
509 hdmi->audio_cts = cts;
510 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
511 spin_unlock_irq(&hdmi->audio_lock);
512 }
513
514 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
515 {
516 mutex_lock(&hdmi->audio_mutex);
517 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
518 mutex_unlock(&hdmi->audio_mutex);
519 }
520
521 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
522 {
523 mutex_lock(&hdmi->audio_mutex);
524 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
525 hdmi->sample_rate);
526 mutex_unlock(&hdmi->audio_mutex);
527 }
528
529 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
530 {
531 mutex_lock(&hdmi->audio_mutex);
532 hdmi->sample_rate = rate;
533 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
534 hdmi->sample_rate);
535 mutex_unlock(&hdmi->audio_mutex);
536 }
537 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
538
539 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
540 {
541 unsigned long flags;
542
543 spin_lock_irqsave(&hdmi->audio_lock, flags);
544 hdmi->audio_enable = true;
545 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
546 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
547 }
548 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
549
550 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
551 {
552 unsigned long flags;
553
554 spin_lock_irqsave(&hdmi->audio_lock, flags);
555 hdmi->audio_enable = false;
556 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
557 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
558 }
559 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
560
561 /*
562 * this submodule is responsible for the video data synchronization.
563 * for example, for RGB 4:4:4 input, the data map is defined as
564 * pin{47~40} <==> R[7:0]
565 * pin{31~24} <==> G[7:0]
566 * pin{15~8} <==> B[7:0]
567 */
568 static void hdmi_video_sample(struct dw_hdmi *hdmi)
569 {
570 int color_format = 0;
571 u8 val;
572
573 if (hdmi->hdmi_data.enc_in_format == RGB) {
574 if (hdmi->hdmi_data.enc_color_depth == 8)
575 color_format = 0x01;
576 else if (hdmi->hdmi_data.enc_color_depth == 10)
577 color_format = 0x03;
578 else if (hdmi->hdmi_data.enc_color_depth == 12)
579 color_format = 0x05;
580 else if (hdmi->hdmi_data.enc_color_depth == 16)
581 color_format = 0x07;
582 else
583 return;
584 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
585 if (hdmi->hdmi_data.enc_color_depth == 8)
586 color_format = 0x09;
587 else if (hdmi->hdmi_data.enc_color_depth == 10)
588 color_format = 0x0B;
589 else if (hdmi->hdmi_data.enc_color_depth == 12)
590 color_format = 0x0D;
591 else if (hdmi->hdmi_data.enc_color_depth == 16)
592 color_format = 0x0F;
593 else
594 return;
595 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
596 if (hdmi->hdmi_data.enc_color_depth == 8)
597 color_format = 0x16;
598 else if (hdmi->hdmi_data.enc_color_depth == 10)
599 color_format = 0x14;
600 else if (hdmi->hdmi_data.enc_color_depth == 12)
601 color_format = 0x12;
602 else
603 return;
604 }
605
606 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
607 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
608 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
609 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
610
611 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
612 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
613 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
614 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
615 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
616 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
617 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
618 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
619 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
620 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
621 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
622 }
623
624 static int is_color_space_conversion(struct dw_hdmi *hdmi)
625 {
626 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
627 }
628
629 static int is_color_space_decimation(struct dw_hdmi *hdmi)
630 {
631 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
632 return 0;
633 if (hdmi->hdmi_data.enc_in_format == RGB ||
634 hdmi->hdmi_data.enc_in_format == YCBCR444)
635 return 1;
636 return 0;
637 }
638
639 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
640 {
641 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
642 return 0;
643 if (hdmi->hdmi_data.enc_out_format == RGB ||
644 hdmi->hdmi_data.enc_out_format == YCBCR444)
645 return 1;
646 return 0;
647 }
648
649 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
650 {
651 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
652 unsigned i;
653 u32 csc_scale = 1;
654
655 if (is_color_space_conversion(hdmi)) {
656 if (hdmi->hdmi_data.enc_out_format == RGB) {
657 if (hdmi->hdmi_data.colorimetry ==
658 HDMI_COLORIMETRY_ITU_601)
659 csc_coeff = &csc_coeff_rgb_out_eitu601;
660 else
661 csc_coeff = &csc_coeff_rgb_out_eitu709;
662 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
663 if (hdmi->hdmi_data.colorimetry ==
664 HDMI_COLORIMETRY_ITU_601)
665 csc_coeff = &csc_coeff_rgb_in_eitu601;
666 else
667 csc_coeff = &csc_coeff_rgb_in_eitu709;
668 csc_scale = 0;
669 }
670 }
671
672 /* The CSC registers are sequential, alternating MSB then LSB */
673 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
674 u16 coeff_a = (*csc_coeff)[0][i];
675 u16 coeff_b = (*csc_coeff)[1][i];
676 u16 coeff_c = (*csc_coeff)[2][i];
677
678 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
679 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
680 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
681 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
682 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
683 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
684 }
685
686 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
687 HDMI_CSC_SCALE);
688 }
689
690 static void hdmi_video_csc(struct dw_hdmi *hdmi)
691 {
692 int color_depth = 0;
693 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
694 int decimation = 0;
695
696 /* YCC422 interpolation to 444 mode */
697 if (is_color_space_interpolation(hdmi))
698 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
699 else if (is_color_space_decimation(hdmi))
700 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
701
702 if (hdmi->hdmi_data.enc_color_depth == 8)
703 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
704 else if (hdmi->hdmi_data.enc_color_depth == 10)
705 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
706 else if (hdmi->hdmi_data.enc_color_depth == 12)
707 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
708 else if (hdmi->hdmi_data.enc_color_depth == 16)
709 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
710 else
711 return;
712
713 /* Configure the CSC registers */
714 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
715 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
716 HDMI_CSC_SCALE);
717
718 dw_hdmi_update_csc_coeffs(hdmi);
719 }
720
721 /*
722 * HDMI video packetizer is used to packetize the data.
723 * for example, if input is YCC422 mode or repeater is used,
724 * data should be repacked this module can be bypassed.
725 */
726 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
727 {
728 unsigned int color_depth = 0;
729 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
730 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
731 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
732 u8 val, vp_conf;
733
734 if (hdmi_data->enc_out_format == RGB ||
735 hdmi_data->enc_out_format == YCBCR444) {
736 if (!hdmi_data->enc_color_depth) {
737 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
738 } else if (hdmi_data->enc_color_depth == 8) {
739 color_depth = 4;
740 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
741 } else if (hdmi_data->enc_color_depth == 10) {
742 color_depth = 5;
743 } else if (hdmi_data->enc_color_depth == 12) {
744 color_depth = 6;
745 } else if (hdmi_data->enc_color_depth == 16) {
746 color_depth = 7;
747 } else {
748 return;
749 }
750 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
751 if (!hdmi_data->enc_color_depth ||
752 hdmi_data->enc_color_depth == 8)
753 remap_size = HDMI_VP_REMAP_YCC422_16bit;
754 else if (hdmi_data->enc_color_depth == 10)
755 remap_size = HDMI_VP_REMAP_YCC422_20bit;
756 else if (hdmi_data->enc_color_depth == 12)
757 remap_size = HDMI_VP_REMAP_YCC422_24bit;
758 else
759 return;
760 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
761 } else {
762 return;
763 }
764
765 /* set the packetizer registers */
766 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
767 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
768 ((hdmi_data->pix_repet_factor <<
769 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
770 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
771 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
772
773 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
774 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
775
776 /* Data from pixel repeater block */
777 if (hdmi_data->pix_repet_factor > 1) {
778 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
779 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
780 } else { /* data from packetizer block */
781 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
782 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
783 }
784
785 hdmi_modb(hdmi, vp_conf,
786 HDMI_VP_CONF_PR_EN_MASK |
787 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
788
789 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
790 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
791
792 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
793
794 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
795 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
796 HDMI_VP_CONF_PP_EN_ENABLE |
797 HDMI_VP_CONF_YCC422_EN_DISABLE;
798 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
799 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
800 HDMI_VP_CONF_PP_EN_DISABLE |
801 HDMI_VP_CONF_YCC422_EN_ENABLE;
802 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
803 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
804 HDMI_VP_CONF_PP_EN_DISABLE |
805 HDMI_VP_CONF_YCC422_EN_DISABLE;
806 } else {
807 return;
808 }
809
810 hdmi_modb(hdmi, vp_conf,
811 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
812 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
813
814 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
815 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
816 HDMI_VP_STUFF_PP_STUFFING_MASK |
817 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
818
819 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
820 HDMI_VP_CONF);
821 }
822
823 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
824 unsigned char bit)
825 {
826 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
827 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
828 }
829
830 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
831 unsigned char bit)
832 {
833 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
834 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
835 }
836
837 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
838 unsigned char bit)
839 {
840 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
841 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
842 }
843
844 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
845 unsigned char bit)
846 {
847 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
848 }
849
850 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
851 unsigned char bit)
852 {
853 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
854 }
855
856 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
857 {
858 u32 val;
859
860 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
861 if (msec-- == 0)
862 return false;
863 udelay(1000);
864 }
865 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
866
867 return true;
868 }
869
870 static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
871 unsigned char addr)
872 {
873 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
874 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
875 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
876 HDMI_PHY_I2CM_DATAO_1_ADDR);
877 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
878 HDMI_PHY_I2CM_DATAO_0_ADDR);
879 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
880 HDMI_PHY_I2CM_OPERATION_ADDR);
881 hdmi_phy_wait_i2c_done(hdmi, 1000);
882 }
883
884 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
885 {
886 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
887 HDMI_PHY_CONF0_PDZ_OFFSET,
888 HDMI_PHY_CONF0_PDZ_MASK);
889 }
890
891 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
892 {
893 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
894 HDMI_PHY_CONF0_ENTMDS_OFFSET,
895 HDMI_PHY_CONF0_ENTMDS_MASK);
896 }
897
898 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
899 {
900 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
901 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
902 HDMI_PHY_CONF0_SPARECTRL_MASK);
903 }
904
905 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
906 {
907 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
908 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
909 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
910 }
911
912 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
913 {
914 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
915 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
916 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
917 }
918
919 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
920 {
921 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
922 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
923 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
924 }
925
926 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
927 {
928 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
929 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
930 HDMI_PHY_CONF0_SELDIPIF_MASK);
931 }
932
933 static int hdmi_phy_configure(struct dw_hdmi *hdmi,
934 unsigned char res, int cscon)
935 {
936 unsigned res_idx;
937 u8 val, msec;
938 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
939 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
940 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
941 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
942
943 switch (res) {
944 case 0: /* color resolution 0 is 8 bit colour depth */
945 case 8:
946 res_idx = DW_HDMI_RES_8;
947 break;
948 case 10:
949 res_idx = DW_HDMI_RES_10;
950 break;
951 case 12:
952 res_idx = DW_HDMI_RES_12;
953 break;
954 default:
955 return -EINVAL;
956 }
957
958 /* PLL/MPLL Cfg - always match on final entry */
959 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
960 if (hdmi->hdmi_data.video_mode.mpixelclock <=
961 mpll_config->mpixelclock)
962 break;
963
964 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
965 if (hdmi->hdmi_data.video_mode.mpixelclock <=
966 curr_ctrl->mpixelclock)
967 break;
968
969 for (; phy_config->mpixelclock != ~0UL; phy_config++)
970 if (hdmi->hdmi_data.video_mode.mpixelclock <=
971 phy_config->mpixelclock)
972 break;
973
974 if (mpll_config->mpixelclock == ~0UL ||
975 curr_ctrl->mpixelclock == ~0UL ||
976 phy_config->mpixelclock == ~0UL) {
977 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
978 hdmi->hdmi_data.video_mode.mpixelclock);
979 return -EINVAL;
980 }
981
982 /* Enable csc path */
983 if (cscon)
984 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
985 else
986 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
987
988 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
989
990 /* gen2 tx power off */
991 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
992
993 /* gen2 pddq */
994 dw_hdmi_phy_gen2_pddq(hdmi, 1);
995
996 /* PHY reset */
997 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
998 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
999
1000 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1001
1002 hdmi_phy_test_clear(hdmi, 1);
1003 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1004 HDMI_PHY_I2CM_SLAVE_ADDR);
1005 hdmi_phy_test_clear(hdmi, 0);
1006
1007 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1008 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1009
1010 /* CURRCTRL */
1011 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1012
1013 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
1014 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1015
1016 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
1017 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1018 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1019
1020 /* REMOVE CLK TERM */
1021 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
1022
1023 dw_hdmi_phy_enable_powerdown(hdmi, false);
1024
1025 /* toggle TMDS enable */
1026 dw_hdmi_phy_enable_tmds(hdmi, 0);
1027 dw_hdmi_phy_enable_tmds(hdmi, 1);
1028
1029 /* gen2 tx power on */
1030 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1031 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1032
1033 if (hdmi->dev_type == RK3288_HDMI)
1034 dw_hdmi_phy_enable_spare(hdmi, 1);
1035
1036 /*Wait for PHY PLL lock */
1037 msec = 5;
1038 do {
1039 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1040 if (!val)
1041 break;
1042
1043 if (msec == 0) {
1044 dev_err(hdmi->dev, "PHY PLL not locked\n");
1045 return -ETIMEDOUT;
1046 }
1047
1048 udelay(1000);
1049 msec--;
1050 } while (1);
1051
1052 return 0;
1053 }
1054
1055 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1056 {
1057 int i, ret;
1058 bool cscon;
1059
1060 /*check csc whether needed activated in HDMI mode */
1061 cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1062
1063 /* HDMI Phy spec says to do the phy initialization sequence twice */
1064 for (i = 0; i < 2; i++) {
1065 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1066 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1067 dw_hdmi_phy_enable_tmds(hdmi, 0);
1068 dw_hdmi_phy_enable_powerdown(hdmi, true);
1069
1070 /* Enable CSC */
1071 ret = hdmi_phy_configure(hdmi, 8, cscon);
1072 if (ret)
1073 return ret;
1074 }
1075
1076 hdmi->phy_enabled = true;
1077 return 0;
1078 }
1079
1080 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1081 {
1082 u8 de;
1083
1084 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1085 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1086 else
1087 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1088
1089 /* disable rx detect */
1090 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1091 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1092
1093 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1094
1095 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1096 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1097 }
1098
1099 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1100 {
1101 struct hdmi_avi_infoframe frame;
1102 u8 val;
1103
1104 /* Initialise info frame from DRM mode */
1105 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1106
1107 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1108 frame.colorspace = HDMI_COLORSPACE_YUV444;
1109 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1110 frame.colorspace = HDMI_COLORSPACE_YUV422;
1111 else
1112 frame.colorspace = HDMI_COLORSPACE_RGB;
1113
1114 /* Set up colorimetry */
1115 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1116 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1117 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1118 frame.extended_colorimetry =
1119 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1120 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1121 frame.extended_colorimetry =
1122 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1123 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1124 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1125 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1126 } else { /* Carries no data */
1127 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1128 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1129 }
1130
1131 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1132
1133 /*
1134 * The Designware IP uses a different byte format from standard
1135 * AVI info frames, though generally the bits are in the correct
1136 * bytes.
1137 */
1138
1139 /*
1140 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1141 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1142 * bit 6 rather than 4.
1143 */
1144 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1145 if (frame.active_aspect & 15)
1146 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1147 if (frame.top_bar || frame.bottom_bar)
1148 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1149 if (frame.left_bar || frame.right_bar)
1150 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1151 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1152
1153 /* AVI data byte 2 differences: none */
1154 val = ((frame.colorimetry & 0x3) << 6) |
1155 ((frame.picture_aspect & 0x3) << 4) |
1156 (frame.active_aspect & 0xf);
1157 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1158
1159 /* AVI data byte 3 differences: none */
1160 val = ((frame.extended_colorimetry & 0x7) << 4) |
1161 ((frame.quantization_range & 0x3) << 2) |
1162 (frame.nups & 0x3);
1163 if (frame.itc)
1164 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1165 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1166
1167 /* AVI data byte 4 differences: none */
1168 val = frame.video_code & 0x7f;
1169 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1170
1171 /* AVI Data Byte 5- set up input and output pixel repetition */
1172 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1173 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1174 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1175 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1176 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1177 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1178 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1179
1180 /*
1181 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1182 * ycc range in bits 2,3 rather than 6,7
1183 */
1184 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1185 (frame.content_type & 0x3);
1186 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1187
1188 /* AVI Data Bytes 6-13 */
1189 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1190 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1191 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1192 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1193 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1194 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1195 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1196 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1197 }
1198
1199 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1200 const struct drm_display_mode *mode)
1201 {
1202 u8 inv_val;
1203 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1204 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1205 unsigned int vdisplay;
1206
1207 vmode->mpixelclock = mode->clock * 1000;
1208
1209 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1210
1211 /* Set up HDMI_FC_INVIDCONF */
1212 inv_val = (hdmi->hdmi_data.hdcp_enable ?
1213 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1214 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1215
1216 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1217 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1218 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1219
1220 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1221 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1222 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1223
1224 inv_val |= (vmode->mdataenablepolarity ?
1225 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1226 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1227
1228 if (hdmi->vic == 39)
1229 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1230 else
1231 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1232 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1233 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1234
1235 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1236 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1237 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1238
1239 inv_val |= hdmi->sink_is_hdmi ?
1240 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1241 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1242
1243 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1244
1245 vdisplay = mode->vdisplay;
1246 vblank = mode->vtotal - mode->vdisplay;
1247 v_de_vs = mode->vsync_start - mode->vdisplay;
1248 vsync_len = mode->vsync_end - mode->vsync_start;
1249
1250 /*
1251 * When we're setting an interlaced mode, we need
1252 * to adjust the vertical timing to suit.
1253 */
1254 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1255 vdisplay /= 2;
1256 vblank /= 2;
1257 v_de_vs /= 2;
1258 vsync_len /= 2;
1259 }
1260
1261 /* Set up horizontal active pixel width */
1262 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1263 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1264
1265 /* Set up vertical active lines */
1266 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1267 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1268
1269 /* Set up horizontal blanking pixel region width */
1270 hblank = mode->htotal - mode->hdisplay;
1271 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1272 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1273
1274 /* Set up vertical blanking pixel region width */
1275 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1276
1277 /* Set up HSYNC active edge delay width (in pixel clks) */
1278 h_de_hs = mode->hsync_start - mode->hdisplay;
1279 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1280 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1281
1282 /* Set up VSYNC active edge delay (in lines) */
1283 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1284
1285 /* Set up HSYNC active pulse width (in pixel clks) */
1286 hsync_len = mode->hsync_end - mode->hsync_start;
1287 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1288 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1289
1290 /* Set up VSYNC active edge delay (in lines) */
1291 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1292 }
1293
1294 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1295 {
1296 if (!hdmi->phy_enabled)
1297 return;
1298
1299 dw_hdmi_phy_enable_tmds(hdmi, 0);
1300 dw_hdmi_phy_enable_powerdown(hdmi, true);
1301
1302 hdmi->phy_enabled = false;
1303 }
1304
1305 /* HDMI Initialization Step B.4 */
1306 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1307 {
1308 u8 clkdis;
1309
1310 /* control period minimum duration */
1311 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1312 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1313 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1314
1315 /* Set to fill TMDS data channels */
1316 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1317 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1318 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1319
1320 /* Enable pixel clock and tmds data path */
1321 clkdis = 0x7F;
1322 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1323 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1324
1325 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1326 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1327
1328 /* Enable csc path */
1329 if (is_color_space_conversion(hdmi)) {
1330 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1331 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1332 }
1333 }
1334
1335 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1336 {
1337 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1338 }
1339
1340 /* Workaround to clear the overflow condition */
1341 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1342 {
1343 int count;
1344 u8 val;
1345
1346 /* TMDS software reset */
1347 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1348
1349 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1350 if (hdmi->dev_type == IMX6DL_HDMI) {
1351 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1352 return;
1353 }
1354
1355 for (count = 0; count < 4; count++)
1356 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1357 }
1358
1359 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1360 {
1361 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1362 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1363 }
1364
1365 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1366 {
1367 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1368 HDMI_IH_MUTE_FC_STAT2);
1369 }
1370
1371 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1372 {
1373 int ret;
1374
1375 hdmi_disable_overflow_interrupts(hdmi);
1376
1377 hdmi->vic = drm_match_cea_mode(mode);
1378
1379 if (!hdmi->vic) {
1380 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1381 } else {
1382 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1383 }
1384
1385 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1386 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1387 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1388 (hdmi->vic == 17) || (hdmi->vic == 18))
1389 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1390 else
1391 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1392
1393 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1394 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1395
1396 /* TODO: Get input format from IPU (via FB driver interface) */
1397 hdmi->hdmi_data.enc_in_format = RGB;
1398
1399 hdmi->hdmi_data.enc_out_format = RGB;
1400
1401 hdmi->hdmi_data.enc_color_depth = 8;
1402 hdmi->hdmi_data.pix_repet_factor = 0;
1403 hdmi->hdmi_data.hdcp_enable = 0;
1404 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1405
1406 /* HDMI Initialization Step B.1 */
1407 hdmi_av_composer(hdmi, mode);
1408
1409 /* HDMI Initializateion Step B.2 */
1410 ret = dw_hdmi_phy_init(hdmi);
1411 if (ret)
1412 return ret;
1413
1414 /* HDMI Initialization Step B.3 */
1415 dw_hdmi_enable_video_path(hdmi);
1416
1417 if (hdmi->sink_has_audio) {
1418 dev_dbg(hdmi->dev, "sink has audio support\n");
1419
1420 /* HDMI Initialization Step E - Configure audio */
1421 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1422 hdmi_enable_audio_clk(hdmi);
1423 }
1424
1425 /* not for DVI mode */
1426 if (hdmi->sink_is_hdmi) {
1427 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1428
1429 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1430 hdmi_config_AVI(hdmi, mode);
1431 } else {
1432 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1433 }
1434
1435 hdmi_video_packetize(hdmi);
1436 hdmi_video_csc(hdmi);
1437 hdmi_video_sample(hdmi);
1438 hdmi_tx_hdcp_config(hdmi);
1439
1440 dw_hdmi_clear_overflow(hdmi);
1441 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1442 hdmi_enable_overflow_interrupts(hdmi);
1443
1444 return 0;
1445 }
1446
1447 /* Wait until we are registered to enable interrupts */
1448 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1449 {
1450 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1451 HDMI_PHY_I2CM_INT_ADDR);
1452
1453 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1454 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1455 HDMI_PHY_I2CM_CTLINT_ADDR);
1456
1457 /* enable cable hot plug irq */
1458 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1459
1460 /* Clear Hotplug interrupts */
1461 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1462 HDMI_IH_PHY_STAT0);
1463
1464 return 0;
1465 }
1466
1467 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1468 {
1469 u8 ih_mute;
1470
1471 /*
1472 * Boot up defaults are:
1473 * HDMI_IH_MUTE = 0x03 (disabled)
1474 * HDMI_IH_MUTE_* = 0x00 (enabled)
1475 *
1476 * Disable top level interrupt bits in HDMI block
1477 */
1478 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1479 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1480 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1481
1482 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1483
1484 /* by default mask all interrupts */
1485 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1486 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1487 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1488 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1489 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1490 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1491 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1492 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1493 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1494 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1495 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1496 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1497 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1498 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1499 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1500
1501 /* Disable interrupts in the IH_MUTE_* registers */
1502 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1503 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1504 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1505 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1506 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1507 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1508 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1509 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1510 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1511 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1512
1513 /* Enable top level interrupt bits in HDMI block */
1514 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1515 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1516 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1517 }
1518
1519 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1520 {
1521 hdmi->bridge_is_on = true;
1522 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1523 }
1524
1525 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1526 {
1527 dw_hdmi_phy_disable(hdmi);
1528 hdmi->bridge_is_on = false;
1529 }
1530
1531 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1532 {
1533 int force = hdmi->force;
1534
1535 if (hdmi->disabled) {
1536 force = DRM_FORCE_OFF;
1537 } else if (force == DRM_FORCE_UNSPECIFIED) {
1538 if (hdmi->rxsense)
1539 force = DRM_FORCE_ON;
1540 else
1541 force = DRM_FORCE_OFF;
1542 }
1543
1544 if (force == DRM_FORCE_OFF) {
1545 if (hdmi->bridge_is_on)
1546 dw_hdmi_poweroff(hdmi);
1547 } else {
1548 if (!hdmi->bridge_is_on)
1549 dw_hdmi_poweron(hdmi);
1550 }
1551 }
1552
1553 /*
1554 * Adjust the detection of RXSENSE according to whether we have a forced
1555 * connection mode enabled, or whether we have been disabled. There is
1556 * no point processing RXSENSE interrupts if we have a forced connection
1557 * state, or DRM has us disabled.
1558 *
1559 * We also disable rxsense interrupts when we think we're disconnected
1560 * to avoid floating TDMS signals giving false rxsense interrupts.
1561 *
1562 * Note: we still need to listen for HPD interrupts even when DRM has us
1563 * disabled so that we can detect a connect event.
1564 */
1565 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1566 {
1567 u8 old_mask = hdmi->phy_mask;
1568
1569 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1570 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1571 else
1572 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1573
1574 if (old_mask != hdmi->phy_mask)
1575 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1576 }
1577
1578 static enum drm_connector_status
1579 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1580 {
1581 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1582 connector);
1583
1584 mutex_lock(&hdmi->mutex);
1585 hdmi->force = DRM_FORCE_UNSPECIFIED;
1586 dw_hdmi_update_power(hdmi);
1587 dw_hdmi_update_phy_mask(hdmi);
1588 mutex_unlock(&hdmi->mutex);
1589
1590 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1591 connector_status_connected : connector_status_disconnected;
1592 }
1593
1594 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1595 {
1596 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1597 connector);
1598 struct edid *edid;
1599 int ret = 0;
1600
1601 if (!hdmi->ddc)
1602 return 0;
1603
1604 edid = drm_get_edid(connector, hdmi->ddc);
1605 if (edid) {
1606 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1607 edid->width_cm, edid->height_cm);
1608
1609 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1610 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1611 drm_mode_connector_update_edid_property(connector, edid);
1612 ret = drm_add_edid_modes(connector, edid);
1613 /* Store the ELD */
1614 drm_edid_to_eld(connector, edid);
1615 kfree(edid);
1616 } else {
1617 dev_dbg(hdmi->dev, "failed to get edid\n");
1618 }
1619
1620 return ret;
1621 }
1622
1623 static enum drm_mode_status
1624 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1625 struct drm_display_mode *mode)
1626 {
1627 struct dw_hdmi *hdmi = container_of(connector,
1628 struct dw_hdmi, connector);
1629 enum drm_mode_status mode_status = MODE_OK;
1630
1631 /* We don't support double-clocked modes */
1632 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1633 return MODE_BAD;
1634
1635 if (hdmi->plat_data->mode_valid)
1636 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1637
1638 return mode_status;
1639 }
1640
1641 static void dw_hdmi_connector_force(struct drm_connector *connector)
1642 {
1643 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1644 connector);
1645
1646 mutex_lock(&hdmi->mutex);
1647 hdmi->force = connector->force;
1648 dw_hdmi_update_power(hdmi);
1649 dw_hdmi_update_phy_mask(hdmi);
1650 mutex_unlock(&hdmi->mutex);
1651 }
1652
1653 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1654 .dpms = drm_atomic_helper_connector_dpms,
1655 .fill_modes = drm_helper_probe_single_connector_modes,
1656 .detect = dw_hdmi_connector_detect,
1657 .destroy = drm_connector_cleanup,
1658 .force = dw_hdmi_connector_force,
1659 .reset = drm_atomic_helper_connector_reset,
1660 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1661 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1662 };
1663
1664 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1665 .get_modes = dw_hdmi_connector_get_modes,
1666 .mode_valid = dw_hdmi_connector_mode_valid,
1667 .best_encoder = drm_atomic_helper_best_encoder,
1668 };
1669
1670 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1671 struct drm_display_mode *orig_mode,
1672 struct drm_display_mode *mode)
1673 {
1674 struct dw_hdmi *hdmi = bridge->driver_private;
1675
1676 mutex_lock(&hdmi->mutex);
1677
1678 /* Store the display mode for plugin/DKMS poweron events */
1679 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1680
1681 mutex_unlock(&hdmi->mutex);
1682 }
1683
1684 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1685 {
1686 struct dw_hdmi *hdmi = bridge->driver_private;
1687
1688 mutex_lock(&hdmi->mutex);
1689 hdmi->disabled = true;
1690 dw_hdmi_update_power(hdmi);
1691 dw_hdmi_update_phy_mask(hdmi);
1692 mutex_unlock(&hdmi->mutex);
1693 }
1694
1695 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1696 {
1697 struct dw_hdmi *hdmi = bridge->driver_private;
1698
1699 mutex_lock(&hdmi->mutex);
1700 hdmi->disabled = false;
1701 dw_hdmi_update_power(hdmi);
1702 dw_hdmi_update_phy_mask(hdmi);
1703 mutex_unlock(&hdmi->mutex);
1704 }
1705
1706 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1707 .enable = dw_hdmi_bridge_enable,
1708 .disable = dw_hdmi_bridge_disable,
1709 .mode_set = dw_hdmi_bridge_mode_set,
1710 };
1711
1712 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
1713 {
1714 struct dw_hdmi_i2c *i2c = hdmi->i2c;
1715 unsigned int stat;
1716
1717 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
1718 if (!stat)
1719 return IRQ_NONE;
1720
1721 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
1722
1723 i2c->stat = stat;
1724
1725 complete(&i2c->cmp);
1726
1727 return IRQ_HANDLED;
1728 }
1729
1730 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1731 {
1732 struct dw_hdmi *hdmi = dev_id;
1733 u8 intr_stat;
1734 irqreturn_t ret = IRQ_NONE;
1735
1736 if (hdmi->i2c)
1737 ret = dw_hdmi_i2c_irq(hdmi);
1738
1739 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1740 if (intr_stat) {
1741 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1742 return IRQ_WAKE_THREAD;
1743 }
1744
1745 return ret;
1746 }
1747
1748 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1749 {
1750 struct dw_hdmi *hdmi = dev_id;
1751 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1752
1753 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1754 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1755 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1756
1757 phy_pol_mask = 0;
1758 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1759 phy_pol_mask |= HDMI_PHY_HPD;
1760 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1761 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1762 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1763 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1764 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1765 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1766 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1767 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1768
1769 if (phy_pol_mask)
1770 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1771
1772 /*
1773 * RX sense tells us whether the TDMS transmitters are detecting
1774 * load - in other words, there's something listening on the
1775 * other end of the link. Use this to decide whether we should
1776 * power on the phy as HPD may be toggled by the sink to merely
1777 * ask the source to re-read the EDID.
1778 */
1779 if (intr_stat &
1780 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1781 mutex_lock(&hdmi->mutex);
1782 if (!hdmi->disabled && !hdmi->force) {
1783 /*
1784 * If the RX sense status indicates we're disconnected,
1785 * clear the software rxsense status.
1786 */
1787 if (!(phy_stat & HDMI_PHY_RX_SENSE))
1788 hdmi->rxsense = false;
1789
1790 /*
1791 * Only set the software rxsense status when both
1792 * rxsense and hpd indicates we're connected.
1793 * This avoids what seems to be bad behaviour in
1794 * at least iMX6S versions of the phy.
1795 */
1796 if (phy_stat & HDMI_PHY_HPD)
1797 hdmi->rxsense = true;
1798
1799 dw_hdmi_update_power(hdmi);
1800 dw_hdmi_update_phy_mask(hdmi);
1801 }
1802 mutex_unlock(&hdmi->mutex);
1803 }
1804
1805 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1806 dev_dbg(hdmi->dev, "EVENT=%s\n",
1807 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1808 if (hdmi->bridge.dev)
1809 drm_helper_hpd_irq_event(hdmi->bridge.dev);
1810 }
1811
1812 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1813 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1814 HDMI_IH_MUTE_PHY_STAT0);
1815
1816 return IRQ_HANDLED;
1817 }
1818
1819 static int dw_hdmi_register(struct drm_encoder *encoder, struct dw_hdmi *hdmi)
1820 {
1821 struct drm_bridge *bridge = &hdmi->bridge;
1822 int ret;
1823
1824 bridge->driver_private = hdmi;
1825 bridge->funcs = &dw_hdmi_bridge_funcs;
1826 ret = drm_bridge_attach(encoder, bridge, NULL);
1827 if (ret) {
1828 DRM_ERROR("Failed to initialize bridge with drm\n");
1829 return -EINVAL;
1830 }
1831
1832 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1833
1834 drm_connector_helper_add(&hdmi->connector,
1835 &dw_hdmi_connector_helper_funcs);
1836
1837 drm_connector_init(encoder->dev, &hdmi->connector,
1838 &dw_hdmi_connector_funcs,
1839 DRM_MODE_CONNECTOR_HDMIA);
1840
1841 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1842
1843 return 0;
1844 }
1845
1846 int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
1847 const struct dw_hdmi_plat_data *plat_data)
1848 {
1849 struct device *dev = &pdev->dev;
1850 struct device_node *np = dev->of_node;
1851 struct platform_device_info pdevinfo;
1852 struct device_node *ddc_node;
1853 struct dw_hdmi *hdmi;
1854 struct resource *iores;
1855 int irq;
1856 int ret;
1857 u32 val = 1;
1858 u8 config0;
1859 u8 config1;
1860
1861 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1862 if (!hdmi)
1863 return -ENOMEM;
1864
1865 hdmi->connector.interlace_allowed = 1;
1866
1867 hdmi->plat_data = plat_data;
1868 hdmi->dev = dev;
1869 hdmi->dev_type = plat_data->dev_type;
1870 hdmi->sample_rate = 48000;
1871 hdmi->disabled = true;
1872 hdmi->rxsense = true;
1873 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
1874
1875 mutex_init(&hdmi->mutex);
1876 mutex_init(&hdmi->audio_mutex);
1877 spin_lock_init(&hdmi->audio_lock);
1878
1879 of_property_read_u32(np, "reg-io-width", &val);
1880
1881 switch (val) {
1882 case 4:
1883 hdmi->write = dw_hdmi_writel;
1884 hdmi->read = dw_hdmi_readl;
1885 break;
1886 case 1:
1887 hdmi->write = dw_hdmi_writeb;
1888 hdmi->read = dw_hdmi_readb;
1889 break;
1890 default:
1891 dev_err(dev, "reg-io-width must be 1 or 4\n");
1892 return -EINVAL;
1893 }
1894
1895 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1896 if (ddc_node) {
1897 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
1898 of_node_put(ddc_node);
1899 if (!hdmi->ddc) {
1900 dev_dbg(hdmi->dev, "failed to read ddc node\n");
1901 return -EPROBE_DEFER;
1902 }
1903
1904 } else {
1905 dev_dbg(hdmi->dev, "no ddc property found\n");
1906 }
1907
1908 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1909 hdmi->regs = devm_ioremap_resource(dev, iores);
1910 if (IS_ERR(hdmi->regs)) {
1911 ret = PTR_ERR(hdmi->regs);
1912 goto err_res;
1913 }
1914
1915 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1916 if (IS_ERR(hdmi->isfr_clk)) {
1917 ret = PTR_ERR(hdmi->isfr_clk);
1918 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1919 goto err_res;
1920 }
1921
1922 ret = clk_prepare_enable(hdmi->isfr_clk);
1923 if (ret) {
1924 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1925 goto err_res;
1926 }
1927
1928 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1929 if (IS_ERR(hdmi->iahb_clk)) {
1930 ret = PTR_ERR(hdmi->iahb_clk);
1931 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1932 goto err_isfr;
1933 }
1934
1935 ret = clk_prepare_enable(hdmi->iahb_clk);
1936 if (ret) {
1937 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1938 goto err_isfr;
1939 }
1940
1941 /* Product and revision IDs */
1942 dev_info(dev,
1943 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1944 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1945 hdmi_readb(hdmi, HDMI_REVISION_ID),
1946 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1947 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1948
1949 initialize_hdmi_ih_mutes(hdmi);
1950
1951 irq = platform_get_irq(pdev, 0);
1952 if (irq < 0)
1953 goto err_iahb;
1954
1955 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1956 dw_hdmi_irq, IRQF_SHARED,
1957 dev_name(dev), hdmi);
1958 if (ret)
1959 goto err_iahb;
1960
1961 /*
1962 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1963 * N and cts values before enabling phy
1964 */
1965 hdmi_init_clk_regenerator(hdmi);
1966
1967 /* If DDC bus is not specified, try to register HDMI I2C bus */
1968 if (!hdmi->ddc) {
1969 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
1970 if (IS_ERR(hdmi->ddc))
1971 hdmi->ddc = NULL;
1972 }
1973
1974 /*
1975 * Configure registers related to HDMI interrupt
1976 * generation before registering IRQ.
1977 */
1978 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1979
1980 /* Clear Hotplug interrupts */
1981 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1982 HDMI_IH_PHY_STAT0);
1983
1984 ret = dw_hdmi_fb_registered(hdmi);
1985 if (ret)
1986 goto err_iahb;
1987
1988 ret = dw_hdmi_register(encoder, hdmi);
1989 if (ret)
1990 goto err_iahb;
1991
1992 /* Unmute interrupts */
1993 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1994 HDMI_IH_MUTE_PHY_STAT0);
1995
1996 memset(&pdevinfo, 0, sizeof(pdevinfo));
1997 pdevinfo.parent = dev;
1998 pdevinfo.id = PLATFORM_DEVID_AUTO;
1999
2000 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2001 config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2002
2003 if (config1 & HDMI_CONFIG1_AHB) {
2004 struct dw_hdmi_audio_data audio;
2005
2006 audio.phys = iores->start;
2007 audio.base = hdmi->regs;
2008 audio.irq = irq;
2009 audio.hdmi = hdmi;
2010 audio.eld = hdmi->connector.eld;
2011
2012 pdevinfo.name = "dw-hdmi-ahb-audio";
2013 pdevinfo.data = &audio;
2014 pdevinfo.size_data = sizeof(audio);
2015 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2016 hdmi->audio = platform_device_register_full(&pdevinfo);
2017 } else if (config0 & HDMI_CONFIG0_I2S) {
2018 struct dw_hdmi_i2s_audio_data audio;
2019
2020 audio.hdmi = hdmi;
2021 audio.write = hdmi_writeb;
2022 audio.read = hdmi_readb;
2023
2024 pdevinfo.name = "dw-hdmi-i2s-audio";
2025 pdevinfo.data = &audio;
2026 pdevinfo.size_data = sizeof(audio);
2027 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2028 hdmi->audio = platform_device_register_full(&pdevinfo);
2029 }
2030
2031 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2032 if (hdmi->i2c)
2033 dw_hdmi_i2c_init(hdmi);
2034
2035 platform_set_drvdata(pdev, hdmi);
2036
2037 return 0;
2038
2039 err_iahb:
2040 if (hdmi->i2c) {
2041 i2c_del_adapter(&hdmi->i2c->adap);
2042 hdmi->ddc = NULL;
2043 }
2044
2045 clk_disable_unprepare(hdmi->iahb_clk);
2046 err_isfr:
2047 clk_disable_unprepare(hdmi->isfr_clk);
2048 err_res:
2049 i2c_put_adapter(hdmi->ddc);
2050
2051 return ret;
2052 }
2053 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2054
2055 void dw_hdmi_unbind(struct device *dev)
2056 {
2057 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2058
2059 if (hdmi->audio && !IS_ERR(hdmi->audio))
2060 platform_device_unregister(hdmi->audio);
2061
2062 /* Disable all interrupts */
2063 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2064
2065 clk_disable_unprepare(hdmi->iahb_clk);
2066 clk_disable_unprepare(hdmi->isfr_clk);
2067
2068 if (hdmi->i2c)
2069 i2c_del_adapter(&hdmi->i2c->adap);
2070 else
2071 i2c_put_adapter(hdmi->ddc);
2072 }
2073 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2074
2075 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2076 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2077 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2078 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2079 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2080 MODULE_LICENSE("GPL");
2081 MODULE_ALIAS("platform:dw-hdmi");
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