1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
7 #include <linux/auxiliary_bus.h>
8 #include <linux/bits.h>
10 #include <linux/debugfs.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/i2c.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/of_graph.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
21 #include <asm/unaligned.h>
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_dp_aux_bus.h>
27 #include <drm/drm_dp_helper.h>
28 #include <drm/drm_mipi_dsi.h>
29 #include <drm/drm_of.h>
30 #include <drm/drm_panel.h>
31 #include <drm/drm_print.h>
32 #include <drm/drm_probe_helper.h>
34 #define SN_DEVICE_REV_REG 0x08
35 #define SN_DPPLL_SRC_REG 0x0A
36 #define DPPLL_CLK_SRC_DSICLK BIT(0)
37 #define REFCLK_FREQ_MASK GENMASK(3, 1)
38 #define REFCLK_FREQ(x) ((x) << 1)
39 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
40 #define SN_PLL_ENABLE_REG 0x0D
41 #define SN_DSI_LANES_REG 0x10
42 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
43 #define CHA_DSI_LANES(x) ((x) << 3)
44 #define SN_DSIA_CLK_FREQ_REG 0x12
45 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
46 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
47 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
48 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
49 #define CHA_HSYNC_POLARITY BIT(7)
50 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
51 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
52 #define CHA_VSYNC_POLARITY BIT(7)
53 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
54 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
55 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
56 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
57 #define SN_LN_ASSIGN_REG 0x59
58 #define LN_ASSIGN_WIDTH 2
59 #define SN_ENH_FRAME_REG 0x5A
60 #define VSTREAM_ENABLE BIT(3)
61 #define LN_POLRS_OFFSET 4
62 #define LN_POLRS_MASK 0xf0
63 #define SN_DATA_FORMAT_REG 0x5B
64 #define BPP_18_RGB BIT(0)
65 #define SN_HPD_DISABLE_REG 0x5C
66 #define HPD_DISABLE BIT(0)
67 #define SN_GPIO_IO_REG 0x5E
68 #define SN_GPIO_INPUT_SHIFT 4
69 #define SN_GPIO_OUTPUT_SHIFT 0
70 #define SN_GPIO_CTRL_REG 0x5F
71 #define SN_GPIO_MUX_INPUT 0
72 #define SN_GPIO_MUX_OUTPUT 1
73 #define SN_GPIO_MUX_SPECIAL 2
74 #define SN_GPIO_MUX_MASK 0x3
75 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
76 #define SN_AUX_ADDR_19_16_REG 0x74
77 #define SN_AUX_ADDR_15_8_REG 0x75
78 #define SN_AUX_ADDR_7_0_REG 0x76
79 #define SN_AUX_ADDR_MASK GENMASK(19, 0)
80 #define SN_AUX_LENGTH_REG 0x77
81 #define SN_AUX_CMD_REG 0x78
82 #define AUX_CMD_SEND BIT(0)
83 #define AUX_CMD_REQ(x) ((x) << 4)
84 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
85 #define SN_SSC_CONFIG_REG 0x93
86 #define DP_NUM_LANES_MASK GENMASK(5, 4)
87 #define DP_NUM_LANES(x) ((x) << 4)
88 #define SN_DATARATE_CONFIG_REG 0x94
89 #define DP_DATARATE_MASK GENMASK(7, 5)
90 #define DP_DATARATE(x) ((x) << 5)
91 #define SN_ML_TX_MODE_REG 0x96
92 #define ML_TX_MAIN_LINK_OFF 0
93 #define ML_TX_NORMAL_MODE BIT(0)
94 #define SN_AUX_CMD_STATUS_REG 0xF4
95 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
96 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
97 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
99 #define MIN_DSI_CLK_FREQ_MHZ 40
101 /* fudge factor required to account for 8b/10b encoding */
102 #define DP_CLK_FUDGE_NUM 10
103 #define DP_CLK_FUDGE_DEN 8
105 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
106 #define SN_AUX_MAX_PAYLOAD_BYTES 16
108 #define SN_REGULATOR_SUPPLY_NUM 4
110 #define SN_MAX_DP_LANES 4
111 #define SN_NUM_GPIOS 4
112 #define SN_GPIO_PHYSICAL_OFFSET 1
114 #define SN_LINK_TRAINING_TRIES 10
117 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
118 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
119 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
120 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
122 * @dev: Pointer to the top level (i2c) device.
123 * @regmap: Regmap for accessing i2c.
124 * @aux: Our aux channel.
125 * @bridge: Our bridge.
126 * @connector: Our connector.
127 * @host_node: Remote DSI node.
128 * @dsi: Our MIPI DSI source.
129 * @refclk: Our reference clock.
130 * @next_bridge: The bridge on the eDP side.
131 * @enable_gpio: The GPIO we toggle to enable the bridge.
132 * @supplies: Data for bulk enabling/disabling our regulators.
133 * @dp_lanes: Count of dp_lanes we're using.
134 * @ln_assign: Value to program to the LN_ASSIGN register.
135 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
136 * @comms_enabled: If true then communication over the aux channel is enabled.
137 * @comms_mutex: Protects modification of comms_enabled.
139 * @gchip: If we expose our GPIOs, this is used.
140 * @gchip_output: A cache of whether we've set GPIOs to output. This
141 * serves double-duty of keeping track of the direction and
142 * also keeping track of whether we've incremented the
143 * pm_runtime reference count for this pin, which we do
144 * whenever a pin is configured as an output. This is a
145 * bitmap so we can do atomic ops on it without an extra
146 * lock so concurrent users of our 4 GPIOs don't stomp on
147 * each other's read-modify-write.
149 struct ti_sn65dsi86
{
150 struct auxiliary_device bridge_aux
;
151 struct auxiliary_device gpio_aux
;
152 struct auxiliary_device aux_aux
;
155 struct regmap
*regmap
;
156 struct drm_dp_aux aux
;
157 struct drm_bridge bridge
;
158 struct drm_connector connector
;
159 struct device_node
*host_node
;
160 struct mipi_dsi_device
*dsi
;
162 struct drm_bridge
*next_bridge
;
163 struct gpio_desc
*enable_gpio
;
164 struct regulator_bulk_data supplies
[SN_REGULATOR_SUPPLY_NUM
];
169 struct mutex comms_mutex
;
171 #if defined(CONFIG_OF_GPIO)
172 struct gpio_chip gchip
;
173 DECLARE_BITMAP(gchip_output
, SN_NUM_GPIOS
);
177 static const struct regmap_range ti_sn65dsi86_volatile_ranges
[] = {
178 { .range_min
= 0, .range_max
= 0xFF },
181 static const struct regmap_access_table ti_sn_bridge_volatile_table
= {
182 .yes_ranges
= ti_sn65dsi86_volatile_ranges
,
183 .n_yes_ranges
= ARRAY_SIZE(ti_sn65dsi86_volatile_ranges
),
186 static const struct regmap_config ti_sn65dsi86_regmap_config
= {
189 .volatile_table
= &ti_sn_bridge_volatile_table
,
190 .cache_type
= REGCACHE_NONE
,
191 .max_register
= 0xFF,
194 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86
*pdata
,
195 unsigned int reg
, u16 val
)
197 regmap_write(pdata
->regmap
, reg
, val
& 0xFF);
198 regmap_write(pdata
->regmap
, reg
+ 1, val
>> 8);
201 static u32
ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86
*pdata
)
203 u32 bit_rate_khz
, clk_freq_khz
;
204 struct drm_display_mode
*mode
=
205 &pdata
->bridge
.encoder
->crtc
->state
->adjusted_mode
;
207 bit_rate_khz
= mode
->clock
*
208 mipi_dsi_pixel_format_to_bpp(pdata
->dsi
->format
);
209 clk_freq_khz
= bit_rate_khz
/ (pdata
->dsi
->lanes
* 2);
214 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
215 static const u32 ti_sn_bridge_refclk_lut
[] = {
223 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
224 static const u32 ti_sn_bridge_dsiclk_lut
[] = {
232 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86
*pdata
)
236 const u32
*refclk_lut
;
237 size_t refclk_lut_size
;
240 refclk_rate
= clk_get_rate(pdata
->refclk
);
241 refclk_lut
= ti_sn_bridge_refclk_lut
;
242 refclk_lut_size
= ARRAY_SIZE(ti_sn_bridge_refclk_lut
);
243 clk_prepare_enable(pdata
->refclk
);
245 refclk_rate
= ti_sn_bridge_get_dsi_freq(pdata
) * 1000;
246 refclk_lut
= ti_sn_bridge_dsiclk_lut
;
247 refclk_lut_size
= ARRAY_SIZE(ti_sn_bridge_dsiclk_lut
);
250 /* for i equals to refclk_lut_size means default frequency */
251 for (i
= 0; i
< refclk_lut_size
; i
++)
252 if (refclk_lut
[i
] == refclk_rate
)
255 regmap_update_bits(pdata
->regmap
, SN_DPPLL_SRC_REG
, REFCLK_FREQ_MASK
,
259 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86
*pdata
)
261 mutex_lock(&pdata
->comms_mutex
);
263 /* configure bridge ref_clk */
264 ti_sn_bridge_set_refclk_freq(pdata
);
267 * HPD on this bridge chip is a bit useless. This is an eDP bridge
268 * so the HPD is an internal signal that's only there to signal that
269 * the panel is done powering up. ...but the bridge chip debounces
270 * this signal by between 100 ms and 400 ms (depending on process,
271 * voltage, and temperate--I measured it at about 200 ms). One
272 * particular panel asserted HPD 84 ms after it was powered on meaning
273 * that we saw HPD 284 ms after power on. ...but the same panel said
274 * that instead of looking at HPD you could just hardcode a delay of
275 * 200 ms. We'll assume that the panel driver will have the hardcoded
276 * delay in its prepare and always disable HPD.
278 * If HPD somehow makes sense on some future panel we'll have to
279 * change this to be conditional on someone specifying that HPD should
282 regmap_update_bits(pdata
->regmap
, SN_HPD_DISABLE_REG
, HPD_DISABLE
,
285 pdata
->comms_enabled
= true;
287 mutex_unlock(&pdata
->comms_mutex
);
290 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86
*pdata
)
292 mutex_lock(&pdata
->comms_mutex
);
294 pdata
->comms_enabled
= false;
295 clk_disable_unprepare(pdata
->refclk
);
297 mutex_unlock(&pdata
->comms_mutex
);
300 static int __maybe_unused
ti_sn65dsi86_resume(struct device
*dev
)
302 struct ti_sn65dsi86
*pdata
= dev_get_drvdata(dev
);
305 ret
= regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM
, pdata
->supplies
);
307 DRM_ERROR("failed to enable supplies %d\n", ret
);
311 /* td2: min 100 us after regulators before enabling the GPIO */
312 usleep_range(100, 110);
314 gpiod_set_value(pdata
->enable_gpio
, 1);
317 * If we have a reference clock we can enable communication w/ the
318 * panel (including the aux channel) w/out any need for an input clock
319 * so we can do it in resume which lets us read the EDID before
320 * pre_enable(). Without a reference clock we need the MIPI reference
321 * clock so reading early doesn't work.
324 ti_sn65dsi86_enable_comms(pdata
);
329 static int __maybe_unused
ti_sn65dsi86_suspend(struct device
*dev
)
331 struct ti_sn65dsi86
*pdata
= dev_get_drvdata(dev
);
335 ti_sn65dsi86_disable_comms(pdata
);
337 gpiod_set_value(pdata
->enable_gpio
, 0);
339 ret
= regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM
, pdata
->supplies
);
341 DRM_ERROR("failed to disable supplies %d\n", ret
);
346 static const struct dev_pm_ops ti_sn65dsi86_pm_ops
= {
347 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend
, ti_sn65dsi86_resume
, NULL
)
348 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
349 pm_runtime_force_resume
)
352 static int status_show(struct seq_file
*s
, void *data
)
354 struct ti_sn65dsi86
*pdata
= s
->private;
355 unsigned int reg
, val
;
357 seq_puts(s
, "STATUS REGISTERS:\n");
359 pm_runtime_get_sync(pdata
->dev
);
361 /* IRQ Status Registers, see Table 31 in datasheet */
362 for (reg
= 0xf0; reg
<= 0xf8; reg
++) {
363 regmap_read(pdata
->regmap
, reg
, &val
);
364 seq_printf(s
, "[0x%02x] = 0x%08x\n", reg
, val
);
367 pm_runtime_put_autosuspend(pdata
->dev
);
372 DEFINE_SHOW_ATTRIBUTE(status
);
374 static void ti_sn65dsi86_debugfs_remove(void *data
)
376 debugfs_remove_recursive(data
);
379 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86
*pdata
)
381 struct device
*dev
= pdata
->dev
;
382 struct dentry
*debugfs
;
385 debugfs
= debugfs_create_dir(dev_name(dev
), NULL
);
388 * We might get an error back if debugfs wasn't enabled in the kernel
389 * so let's just silently return upon failure.
391 if (IS_ERR_OR_NULL(debugfs
))
394 ret
= devm_add_action_or_reset(dev
, ti_sn65dsi86_debugfs_remove
, debugfs
);
398 debugfs_create_file("status", 0600, debugfs
, pdata
, &status_fops
);
401 /* -----------------------------------------------------------------------------
402 * Auxiliary Devices (*not* AUX)
405 static void ti_sn65dsi86_uninit_aux(void *data
)
407 auxiliary_device_uninit(data
);
410 static void ti_sn65dsi86_delete_aux(void *data
)
412 auxiliary_device_delete(data
);
416 * AUX bus docs say that a non-NULL release is mandatory, but it makes no
417 * sense for the model used here where all of the aux devices are allocated
418 * in the single shared structure. We'll use this noop as a workaround.
420 static void ti_sn65dsi86_noop(struct device
*dev
) {}
422 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86
*pdata
,
423 struct auxiliary_device
*aux
,
426 struct device
*dev
= pdata
->dev
;
430 aux
->dev
.parent
= dev
;
431 aux
->dev
.release
= ti_sn65dsi86_noop
;
432 device_set_of_node_from_dev(&aux
->dev
, dev
);
433 ret
= auxiliary_device_init(aux
);
436 ret
= devm_add_action_or_reset(dev
, ti_sn65dsi86_uninit_aux
, aux
);
440 ret
= auxiliary_device_add(aux
);
443 ret
= devm_add_action_or_reset(dev
, ti_sn65dsi86_delete_aux
, aux
);
448 /* -----------------------------------------------------------------------------
452 static struct ti_sn65dsi86
*aux_to_ti_sn65dsi86(struct drm_dp_aux
*aux
)
454 return container_of(aux
, struct ti_sn65dsi86
, aux
);
457 static ssize_t
ti_sn_aux_transfer(struct drm_dp_aux
*aux
,
458 struct drm_dp_aux_msg
*msg
)
460 struct ti_sn65dsi86
*pdata
= aux_to_ti_sn65dsi86(aux
);
461 u32 request
= msg
->request
& ~(DP_AUX_I2C_MOT
| DP_AUX_I2C_WRITE_STATUS_UPDATE
);
462 u32 request_val
= AUX_CMD_REQ(msg
->request
);
463 u8
*buf
= msg
->buffer
;
464 unsigned int len
= msg
->size
;
467 u8 addr_len
[SN_AUX_LENGTH_REG
+ 1 - SN_AUX_ADDR_19_16_REG
];
469 if (len
> SN_AUX_MAX_PAYLOAD_BYTES
)
472 pm_runtime_get_sync(pdata
->dev
);
473 mutex_lock(&pdata
->comms_mutex
);
476 * If someone tries to do a DDC over AUX transaction before pre_enable()
477 * on a device without a dedicated reference clock then we just can't
478 * do it. Fail right away. This prevents non-refclk users from reading
479 * the EDID before enabling the panel but such is life.
481 if (!pdata
->comms_enabled
) {
487 case DP_AUX_NATIVE_WRITE
:
488 case DP_AUX_I2C_WRITE
:
489 case DP_AUX_NATIVE_READ
:
490 case DP_AUX_I2C_READ
:
491 regmap_write(pdata
->regmap
, SN_AUX_CMD_REG
, request_val
);
492 /* Assume it's good */
500 BUILD_BUG_ON(sizeof(addr_len
) != sizeof(__be32
));
501 put_unaligned_be32((msg
->address
& SN_AUX_ADDR_MASK
) << 8 | len
,
503 regmap_bulk_write(pdata
->regmap
, SN_AUX_ADDR_19_16_REG
, addr_len
,
504 ARRAY_SIZE(addr_len
));
506 if (request
== DP_AUX_NATIVE_WRITE
|| request
== DP_AUX_I2C_WRITE
)
507 regmap_bulk_write(pdata
->regmap
, SN_AUX_WDATA_REG(0), buf
, len
);
509 /* Clear old status bits before start so we don't get confused */
510 regmap_write(pdata
->regmap
, SN_AUX_CMD_STATUS_REG
,
511 AUX_IRQ_STATUS_NAT_I2C_FAIL
|
512 AUX_IRQ_STATUS_AUX_RPLY_TOUT
|
513 AUX_IRQ_STATUS_AUX_SHORT
);
515 regmap_write(pdata
->regmap
, SN_AUX_CMD_REG
, request_val
| AUX_CMD_SEND
);
517 /* Zero delay loop because i2c transactions are slow already */
518 ret
= regmap_read_poll_timeout(pdata
->regmap
, SN_AUX_CMD_REG
, val
,
519 !(val
& AUX_CMD_SEND
), 0, 50 * 1000);
523 ret
= regmap_read(pdata
->regmap
, SN_AUX_CMD_STATUS_REG
, &val
);
527 if (val
& AUX_IRQ_STATUS_AUX_RPLY_TOUT
) {
529 * The hardware tried the message seven times per the DP spec
530 * but it hit a timeout. We ignore defers here because they're
531 * handled in hardware.
537 if (val
& AUX_IRQ_STATUS_AUX_SHORT
) {
538 ret
= regmap_read(pdata
->regmap
, SN_AUX_LENGTH_REG
, &len
);
541 } else if (val
& AUX_IRQ_STATUS_NAT_I2C_FAIL
) {
543 case DP_AUX_I2C_WRITE
:
544 case DP_AUX_I2C_READ
:
545 msg
->reply
|= DP_AUX_I2C_REPLY_NACK
;
547 case DP_AUX_NATIVE_READ
:
548 case DP_AUX_NATIVE_WRITE
:
549 msg
->reply
|= DP_AUX_NATIVE_REPLY_NACK
;
556 if (request
!= DP_AUX_NATIVE_WRITE
&& request
!= DP_AUX_I2C_WRITE
&& len
!= 0)
557 ret
= regmap_bulk_read(pdata
->regmap
, SN_AUX_RDATA_REG(0), buf
, len
);
560 mutex_unlock(&pdata
->comms_mutex
);
561 pm_runtime_mark_last_busy(pdata
->dev
);
562 pm_runtime_put_autosuspend(pdata
->dev
);
569 static int ti_sn_aux_probe(struct auxiliary_device
*adev
,
570 const struct auxiliary_device_id
*id
)
572 struct ti_sn65dsi86
*pdata
= dev_get_drvdata(adev
->dev
.parent
);
575 pdata
->aux
.name
= "ti-sn65dsi86-aux";
576 pdata
->aux
.dev
= &adev
->dev
;
577 pdata
->aux
.transfer
= ti_sn_aux_transfer
;
578 drm_dp_aux_init(&pdata
->aux
);
580 ret
= devm_of_dp_aux_populate_ep_devices(&pdata
->aux
);
585 * The eDP to MIPI bridge parts don't work until the AUX channel is
586 * setup so we don't add it in the main driver probe, we add it now.
588 return ti_sn65dsi86_add_aux_device(pdata
, &pdata
->bridge_aux
, "bridge");
591 static const struct auxiliary_device_id ti_sn_aux_id_table
[] = {
592 { .name
= "ti_sn65dsi86.aux", },
596 static struct auxiliary_driver ti_sn_aux_driver
= {
598 .probe
= ti_sn_aux_probe
,
599 .id_table
= ti_sn_aux_id_table
,
602 /* -----------------------------------------------------------------------------
603 * DRM Connector Operations
606 static struct ti_sn65dsi86
*
607 connector_to_ti_sn65dsi86(struct drm_connector
*connector
)
609 return container_of(connector
, struct ti_sn65dsi86
, connector
);
612 static int ti_sn_bridge_connector_get_modes(struct drm_connector
*connector
)
614 struct ti_sn65dsi86
*pdata
= connector_to_ti_sn65dsi86(connector
);
616 return drm_bridge_get_modes(pdata
->next_bridge
, connector
);
619 static enum drm_mode_status
620 ti_sn_bridge_connector_mode_valid(struct drm_connector
*connector
,
621 struct drm_display_mode
*mode
)
623 /* maximum supported resolution is 4K at 60 fps */
624 if (mode
->clock
> 594000)
625 return MODE_CLOCK_HIGH
;
630 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs
= {
631 .get_modes
= ti_sn_bridge_connector_get_modes
,
632 .mode_valid
= ti_sn_bridge_connector_mode_valid
,
635 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs
= {
636 .fill_modes
= drm_helper_probe_single_connector_modes
,
637 .destroy
= drm_connector_cleanup
,
638 .reset
= drm_atomic_helper_connector_reset
,
639 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
640 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
643 static int ti_sn_bridge_connector_init(struct ti_sn65dsi86
*pdata
)
647 ret
= drm_connector_init(pdata
->bridge
.dev
, &pdata
->connector
,
648 &ti_sn_bridge_connector_funcs
,
649 DRM_MODE_CONNECTOR_eDP
);
651 DRM_ERROR("Failed to initialize connector with drm\n");
655 drm_connector_helper_add(&pdata
->connector
,
656 &ti_sn_bridge_connector_helper_funcs
);
657 drm_connector_attach_encoder(&pdata
->connector
, pdata
->bridge
.encoder
);
662 /*------------------------------------------------------------------------------
666 static struct ti_sn65dsi86
*bridge_to_ti_sn65dsi86(struct drm_bridge
*bridge
)
668 return container_of(bridge
, struct ti_sn65dsi86
, bridge
);
671 static int ti_sn_bridge_attach(struct drm_bridge
*bridge
,
672 enum drm_bridge_attach_flags flags
)
675 struct ti_sn65dsi86
*pdata
= bridge_to_ti_sn65dsi86(bridge
);
676 struct mipi_dsi_host
*host
;
677 struct mipi_dsi_device
*dsi
;
678 const struct mipi_dsi_device_info info
= { .type
= "ti_sn_bridge",
683 if (flags
& DRM_BRIDGE_ATTACH_NO_CONNECTOR
) {
684 DRM_ERROR("Fix bridge driver to make connector optional!");
688 pdata
->aux
.drm_dev
= bridge
->dev
;
689 ret
= drm_dp_aux_register(&pdata
->aux
);
691 drm_err(bridge
->dev
, "Failed to register DP AUX channel: %d\n", ret
);
695 ret
= ti_sn_bridge_connector_init(pdata
);
700 * TODO: ideally finding host resource and dsi dev registration needs
701 * to be done in bridge probe. But some existing DSI host drivers will
702 * wait for any of the drm_bridge/drm_panel to get added to the global
703 * bridge/panel list, before completing their probe. So if we do the
704 * dsi dev registration part in bridge probe, before populating in
705 * the global bridge list, then it will cause deadlock as dsi host probe
706 * will never complete, neither our bridge probe. So keeping it here
707 * will satisfy most of the existing host drivers. Once the host driver
708 * is fixed we can move the below code to bridge probe safely.
710 host
= of_find_mipi_dsi_host_by_node(pdata
->host_node
);
712 DRM_ERROR("failed to find dsi host\n");
717 dsi
= mipi_dsi_device_register_full(host
, &info
);
719 DRM_ERROR("failed to create dsi device\n");
724 /* TODO: setting to 4 MIPI lanes always for now */
726 dsi
->format
= MIPI_DSI_FMT_RGB888
;
727 dsi
->mode_flags
= MIPI_DSI_MODE_VIDEO
;
729 /* check if continuous dsi clock is required or not */
730 pm_runtime_get_sync(pdata
->dev
);
731 regmap_read(pdata
->regmap
, SN_DPPLL_SRC_REG
, &val
);
732 pm_runtime_put_autosuspend(pdata
->dev
);
733 if (!(val
& DPPLL_CLK_SRC_DSICLK
))
734 dsi
->mode_flags
|= MIPI_DSI_CLOCK_NON_CONTINUOUS
;
736 ret
= mipi_dsi_attach(dsi
);
738 DRM_ERROR("failed to attach dsi to host\n");
743 /* We never want the next bridge to *also* create a connector: */
744 flags
|= DRM_BRIDGE_ATTACH_NO_CONNECTOR
;
746 /* Attach the next bridge */
747 ret
= drm_bridge_attach(bridge
->encoder
, pdata
->next_bridge
,
748 &pdata
->bridge
, flags
);
755 mipi_dsi_detach(dsi
);
757 mipi_dsi_device_unregister(dsi
);
759 drm_connector_cleanup(&pdata
->connector
);
761 drm_dp_aux_unregister(&pdata
->aux
);
765 static void ti_sn_bridge_detach(struct drm_bridge
*bridge
)
767 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge
)->aux
);
770 static void ti_sn_bridge_disable(struct drm_bridge
*bridge
)
772 struct ti_sn65dsi86
*pdata
= bridge_to_ti_sn65dsi86(bridge
);
774 /* disable video stream */
775 regmap_update_bits(pdata
->regmap
, SN_ENH_FRAME_REG
, VSTREAM_ENABLE
, 0);
778 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86
*pdata
)
780 unsigned int bit_rate_mhz
, clk_freq_mhz
;
782 struct drm_display_mode
*mode
=
783 &pdata
->bridge
.encoder
->crtc
->state
->adjusted_mode
;
785 /* set DSIA clk frequency */
786 bit_rate_mhz
= (mode
->clock
/ 1000) *
787 mipi_dsi_pixel_format_to_bpp(pdata
->dsi
->format
);
788 clk_freq_mhz
= bit_rate_mhz
/ (pdata
->dsi
->lanes
* 2);
790 /* for each increment in val, frequency increases by 5MHz */
791 val
= (MIN_DSI_CLK_FREQ_MHZ
/ 5) +
792 (((clk_freq_mhz
- MIN_DSI_CLK_FREQ_MHZ
) / 5) & 0xFF);
793 regmap_write(pdata
->regmap
, SN_DSIA_CLK_FREQ_REG
, val
);
796 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86
*pdata
)
798 if (pdata
->connector
.display_info
.bpc
<= 6)
805 * LUT index corresponds to register value and
806 * LUT values corresponds to dp data rate supported
807 * by the bridge in Mbps unit.
809 static const unsigned int ti_sn_bridge_dp_rate_lut
[] = {
810 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
813 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86
*pdata
)
815 unsigned int bit_rate_khz
, dp_rate_mhz
;
817 struct drm_display_mode
*mode
=
818 &pdata
->bridge
.encoder
->crtc
->state
->adjusted_mode
;
820 /* Calculate minimum bit rate based on our pixel clock. */
821 bit_rate_khz
= mode
->clock
* ti_sn_bridge_get_bpp(pdata
);
823 /* Calculate minimum DP data rate, taking 80% as per DP spec */
824 dp_rate_mhz
= DIV_ROUND_UP(bit_rate_khz
* DP_CLK_FUDGE_NUM
,
825 1000 * pdata
->dp_lanes
* DP_CLK_FUDGE_DEN
);
827 for (i
= 1; i
< ARRAY_SIZE(ti_sn_bridge_dp_rate_lut
) - 1; i
++)
828 if (ti_sn_bridge_dp_rate_lut
[i
] >= dp_rate_mhz
)
834 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86
*pdata
)
836 unsigned int valid_rates
= 0;
837 unsigned int rate_per_200khz
;
838 unsigned int rate_mhz
;
843 ret
= drm_dp_dpcd_readb(&pdata
->aux
, DP_EDP_DPCD_REV
, &dpcd_val
);
845 DRM_DEV_ERROR(pdata
->dev
,
846 "Can't read eDP rev (%d), assuming 1.1\n", ret
);
847 dpcd_val
= DP_EDP_11
;
850 if (dpcd_val
>= DP_EDP_14
) {
851 /* eDP 1.4 devices must provide a custom table */
852 __le16 sink_rates
[DP_MAX_SUPPORTED_RATES
];
854 ret
= drm_dp_dpcd_read(&pdata
->aux
, DP_SUPPORTED_LINK_RATES
,
855 sink_rates
, sizeof(sink_rates
));
857 if (ret
!= sizeof(sink_rates
)) {
858 DRM_DEV_ERROR(pdata
->dev
,
859 "Can't read supported rate table (%d)\n", ret
);
861 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
862 memset(sink_rates
, 0, sizeof(sink_rates
));
865 for (i
= 0; i
< ARRAY_SIZE(sink_rates
); i
++) {
866 rate_per_200khz
= le16_to_cpu(sink_rates
[i
]);
868 if (!rate_per_200khz
)
871 rate_mhz
= rate_per_200khz
* 200 / 1000;
873 j
< ARRAY_SIZE(ti_sn_bridge_dp_rate_lut
);
875 if (ti_sn_bridge_dp_rate_lut
[j
] == rate_mhz
)
876 valid_rates
|= BIT(j
);
880 for (i
= 0; i
< ARRAY_SIZE(ti_sn_bridge_dp_rate_lut
); i
++) {
881 if (valid_rates
& BIT(i
))
884 DRM_DEV_ERROR(pdata
->dev
,
885 "No matching eDP rates in table; falling back\n");
888 /* On older versions best we can do is use DP_MAX_LINK_RATE */
889 ret
= drm_dp_dpcd_readb(&pdata
->aux
, DP_MAX_LINK_RATE
, &dpcd_val
);
891 DRM_DEV_ERROR(pdata
->dev
,
892 "Can't read max rate (%d); assuming 5.4 GHz\n",
894 dpcd_val
= DP_LINK_BW_5_4
;
899 DRM_DEV_ERROR(pdata
->dev
,
900 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
904 valid_rates
|= BIT(7);
907 valid_rates
|= BIT(4);
909 case DP_LINK_BW_1_62
:
910 valid_rates
|= BIT(1);
917 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86
*pdata
)
919 struct drm_display_mode
*mode
=
920 &pdata
->bridge
.encoder
->crtc
->state
->adjusted_mode
;
921 u8 hsync_polarity
= 0, vsync_polarity
= 0;
923 if (mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
924 hsync_polarity
= CHA_HSYNC_POLARITY
;
925 if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
926 vsync_polarity
= CHA_VSYNC_POLARITY
;
928 ti_sn65dsi86_write_u16(pdata
, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG
,
930 ti_sn65dsi86_write_u16(pdata
, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG
,
932 regmap_write(pdata
->regmap
, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG
,
933 (mode
->hsync_end
- mode
->hsync_start
) & 0xFF);
934 regmap_write(pdata
->regmap
, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG
,
935 (((mode
->hsync_end
- mode
->hsync_start
) >> 8) & 0x7F) |
937 regmap_write(pdata
->regmap
, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG
,
938 (mode
->vsync_end
- mode
->vsync_start
) & 0xFF);
939 regmap_write(pdata
->regmap
, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG
,
940 (((mode
->vsync_end
- mode
->vsync_start
) >> 8) & 0x7F) |
943 regmap_write(pdata
->regmap
, SN_CHA_HORIZONTAL_BACK_PORCH_REG
,
944 (mode
->htotal
- mode
->hsync_end
) & 0xFF);
945 regmap_write(pdata
->regmap
, SN_CHA_VERTICAL_BACK_PORCH_REG
,
946 (mode
->vtotal
- mode
->vsync_end
) & 0xFF);
948 regmap_write(pdata
->regmap
, SN_CHA_HORIZONTAL_FRONT_PORCH_REG
,
949 (mode
->hsync_start
- mode
->hdisplay
) & 0xFF);
950 regmap_write(pdata
->regmap
, SN_CHA_VERTICAL_FRONT_PORCH_REG
,
951 (mode
->vsync_start
- mode
->vdisplay
) & 0xFF);
953 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
956 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86
*pdata
)
961 ret
= drm_dp_dpcd_readb(&pdata
->aux
, DP_MAX_LANE_COUNT
, &data
);
963 DRM_DEV_ERROR(pdata
->dev
,
964 "Can't read lane count (%d); assuming 4\n", ret
);
968 return data
& DP_LANE_COUNT_MASK
;
971 static int ti_sn_link_training(struct ti_sn65dsi86
*pdata
, int dp_rate_idx
,
972 const char **last_err_str
)
978 /* set dp clk frequency value */
979 regmap_update_bits(pdata
->regmap
, SN_DATARATE_CONFIG_REG
,
980 DP_DATARATE_MASK
, DP_DATARATE(dp_rate_idx
));
983 regmap_write(pdata
->regmap
, SN_PLL_ENABLE_REG
, 1);
985 ret
= regmap_read_poll_timeout(pdata
->regmap
, SN_DPPLL_SRC_REG
, val
,
986 val
& DPPLL_SRC_DP_PLL_LOCK
, 1000,
989 *last_err_str
= "DP_PLL_LOCK polling failed";
994 * We'll try to link train several times. As part of link training
995 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
996 * the panel isn't ready quite it might respond NAK here which means
997 * we need to try again.
999 for (i
= 0; i
< SN_LINK_TRAINING_TRIES
; i
++) {
1000 /* Semi auto link training mode */
1001 regmap_write(pdata
->regmap
, SN_ML_TX_MODE_REG
, 0x0A);
1002 ret
= regmap_read_poll_timeout(pdata
->regmap
, SN_ML_TX_MODE_REG
, val
,
1003 val
== ML_TX_MAIN_LINK_OFF
||
1004 val
== ML_TX_NORMAL_MODE
, 1000,
1007 *last_err_str
= "Training complete polling failed";
1008 } else if (val
== ML_TX_MAIN_LINK_OFF
) {
1009 *last_err_str
= "Link training failed, link is off";
1017 /* If we saw quite a few retries, add a note about it */
1018 if (!ret
&& i
> SN_LINK_TRAINING_TRIES
/ 2)
1019 DRM_DEV_INFO(pdata
->dev
, "Link training needed %d retries\n", i
);
1022 /* Disable the PLL if we failed */
1024 regmap_write(pdata
->regmap
, SN_PLL_ENABLE_REG
, 0);
1029 static void ti_sn_bridge_enable(struct drm_bridge
*bridge
)
1031 struct ti_sn65dsi86
*pdata
= bridge_to_ti_sn65dsi86(bridge
);
1032 const char *last_err_str
= "No supported DP rate";
1033 unsigned int valid_rates
;
1039 max_dp_lanes
= ti_sn_get_max_lanes(pdata
);
1040 pdata
->dp_lanes
= min(pdata
->dp_lanes
, max_dp_lanes
);
1042 /* DSI_A lane config */
1043 val
= CHA_DSI_LANES(SN_MAX_DP_LANES
- pdata
->dsi
->lanes
);
1044 regmap_update_bits(pdata
->regmap
, SN_DSI_LANES_REG
,
1045 CHA_DSI_LANES_MASK
, val
);
1047 regmap_write(pdata
->regmap
, SN_LN_ASSIGN_REG
, pdata
->ln_assign
);
1048 regmap_update_bits(pdata
->regmap
, SN_ENH_FRAME_REG
, LN_POLRS_MASK
,
1049 pdata
->ln_polrs
<< LN_POLRS_OFFSET
);
1051 /* set dsi clk frequency value */
1052 ti_sn_bridge_set_dsi_rate(pdata
);
1055 * The SN65DSI86 only supports ASSR Display Authentication method and
1056 * this method is enabled by default. An eDP panel must support this
1057 * authentication method. We need to enable this method in the eDP panel
1058 * at DisplayPort address 0x0010A prior to link training.
1060 drm_dp_dpcd_writeb(&pdata
->aux
, DP_EDP_CONFIGURATION_SET
,
1061 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE
);
1063 /* Set the DP output format (18 bpp or 24 bpp) */
1064 val
= (ti_sn_bridge_get_bpp(pdata
) == 18) ? BPP_18_RGB
: 0;
1065 regmap_update_bits(pdata
->regmap
, SN_DATA_FORMAT_REG
, BPP_18_RGB
, val
);
1067 /* DP lane config */
1068 val
= DP_NUM_LANES(min(pdata
->dp_lanes
, 3));
1069 regmap_update_bits(pdata
->regmap
, SN_SSC_CONFIG_REG
, DP_NUM_LANES_MASK
,
1072 valid_rates
= ti_sn_bridge_read_valid_rates(pdata
);
1074 /* Train until we run out of rates */
1075 for (dp_rate_idx
= ti_sn_bridge_calc_min_dp_rate_idx(pdata
);
1076 dp_rate_idx
< ARRAY_SIZE(ti_sn_bridge_dp_rate_lut
);
1078 if (!(valid_rates
& BIT(dp_rate_idx
)))
1081 ret
= ti_sn_link_training(pdata
, dp_rate_idx
, &last_err_str
);
1086 DRM_DEV_ERROR(pdata
->dev
, "%s (%d)\n", last_err_str
, ret
);
1090 /* config video parameters */
1091 ti_sn_bridge_set_video_timings(pdata
);
1093 /* enable video stream */
1094 regmap_update_bits(pdata
->regmap
, SN_ENH_FRAME_REG
, VSTREAM_ENABLE
,
1098 static void ti_sn_bridge_pre_enable(struct drm_bridge
*bridge
)
1100 struct ti_sn65dsi86
*pdata
= bridge_to_ti_sn65dsi86(bridge
);
1102 pm_runtime_get_sync(pdata
->dev
);
1105 ti_sn65dsi86_enable_comms(pdata
);
1107 /* td7: min 100 us after enable before DSI data */
1108 usleep_range(100, 110);
1111 static void ti_sn_bridge_post_disable(struct drm_bridge
*bridge
)
1113 struct ti_sn65dsi86
*pdata
= bridge_to_ti_sn65dsi86(bridge
);
1115 /* semi auto link training mode OFF */
1116 regmap_write(pdata
->regmap
, SN_ML_TX_MODE_REG
, 0);
1117 /* Num lanes to 0 as per power sequencing in data sheet */
1118 regmap_update_bits(pdata
->regmap
, SN_SSC_CONFIG_REG
, DP_NUM_LANES_MASK
, 0);
1119 /* disable DP PLL */
1120 regmap_write(pdata
->regmap
, SN_PLL_ENABLE_REG
, 0);
1123 ti_sn65dsi86_disable_comms(pdata
);
1125 pm_runtime_put_sync(pdata
->dev
);
1128 static const struct drm_bridge_funcs ti_sn_bridge_funcs
= {
1129 .attach
= ti_sn_bridge_attach
,
1130 .detach
= ti_sn_bridge_detach
,
1131 .pre_enable
= ti_sn_bridge_pre_enable
,
1132 .enable
= ti_sn_bridge_enable
,
1133 .disable
= ti_sn_bridge_disable
,
1134 .post_disable
= ti_sn_bridge_post_disable
,
1137 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86
*pdata
,
1138 struct device_node
*np
)
1140 u32 lane_assignments
[SN_MAX_DP_LANES
] = { 0, 1, 2, 3 };
1141 u32 lane_polarities
[SN_MAX_DP_LANES
] = { };
1142 struct device_node
*endpoint
;
1149 * Read config from the device tree about lane remapping and lane
1150 * polarities. These are optional and we assume identity map and
1151 * normal polarity if nothing is specified. It's OK to specify just
1152 * data-lanes but not lane-polarities but not vice versa.
1154 * Error checking is light (we just make sure we don't crash or
1155 * buffer overrun) and we assume dts is well formed and specifying
1156 * mappings that the hardware supports.
1158 endpoint
= of_graph_get_endpoint_by_regs(np
, 1, -1);
1159 dp_lanes
= of_property_count_u32_elems(endpoint
, "data-lanes");
1160 if (dp_lanes
> 0 && dp_lanes
<= SN_MAX_DP_LANES
) {
1161 of_property_read_u32_array(endpoint
, "data-lanes",
1162 lane_assignments
, dp_lanes
);
1163 of_property_read_u32_array(endpoint
, "lane-polarities",
1164 lane_polarities
, dp_lanes
);
1166 dp_lanes
= SN_MAX_DP_LANES
;
1168 of_node_put(endpoint
);
1171 * Convert into register format. Loop over all lanes even if
1172 * data-lanes had fewer elements so that we nicely initialize
1173 * the LN_ASSIGN register.
1175 for (i
= SN_MAX_DP_LANES
- 1; i
>= 0; i
--) {
1176 ln_assign
= ln_assign
<< LN_ASSIGN_WIDTH
| lane_assignments
[i
];
1177 ln_polrs
= ln_polrs
<< 1 | lane_polarities
[i
];
1180 /* Stash in our struct for when we power on */
1181 pdata
->dp_lanes
= dp_lanes
;
1182 pdata
->ln_assign
= ln_assign
;
1183 pdata
->ln_polrs
= ln_polrs
;
1186 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86
*pdata
)
1188 struct device_node
*np
= pdata
->dev
->of_node
;
1190 pdata
->host_node
= of_graph_get_remote_node(np
, 0, 0);
1192 if (!pdata
->host_node
) {
1193 DRM_ERROR("remote dsi host node not found\n");
1200 static int ti_sn_bridge_probe(struct auxiliary_device
*adev
,
1201 const struct auxiliary_device_id
*id
)
1203 struct ti_sn65dsi86
*pdata
= dev_get_drvdata(adev
->dev
.parent
);
1204 struct device_node
*np
= pdata
->dev
->of_node
;
1205 struct drm_panel
*panel
;
1208 ret
= drm_of_find_panel_or_bridge(np
, 1, 0, &panel
, NULL
);
1210 return dev_err_probe(&adev
->dev
, ret
,
1211 "could not find any panel node\n");
1213 pdata
->next_bridge
= devm_drm_panel_bridge_add(pdata
->dev
, panel
);
1214 if (IS_ERR(pdata
->next_bridge
)) {
1215 DRM_ERROR("failed to create panel bridge\n");
1216 return PTR_ERR(pdata
->next_bridge
);
1219 ti_sn_bridge_parse_lanes(pdata
, np
);
1221 ret
= ti_sn_bridge_parse_dsi_host(pdata
);
1225 pdata
->bridge
.funcs
= &ti_sn_bridge_funcs
;
1226 pdata
->bridge
.of_node
= np
;
1228 drm_bridge_add(&pdata
->bridge
);
1233 static void ti_sn_bridge_remove(struct auxiliary_device
*adev
)
1235 struct ti_sn65dsi86
*pdata
= dev_get_drvdata(adev
->dev
.parent
);
1241 mipi_dsi_detach(pdata
->dsi
);
1242 mipi_dsi_device_unregister(pdata
->dsi
);
1245 drm_bridge_remove(&pdata
->bridge
);
1247 of_node_put(pdata
->host_node
);
1250 static const struct auxiliary_device_id ti_sn_bridge_id_table
[] = {
1251 { .name
= "ti_sn65dsi86.bridge", },
1255 static struct auxiliary_driver ti_sn_bridge_driver
= {
1257 .probe
= ti_sn_bridge_probe
,
1258 .remove
= ti_sn_bridge_remove
,
1259 .id_table
= ti_sn_bridge_id_table
,
1262 /* -----------------------------------------------------------------------------
1266 #if defined(CONFIG_OF_GPIO)
1268 static int tn_sn_bridge_of_xlate(struct gpio_chip
*chip
,
1269 const struct of_phandle_args
*gpiospec
,
1272 if (WARN_ON(gpiospec
->args_count
< chip
->of_gpio_n_cells
))
1275 if (gpiospec
->args
[0] > chip
->ngpio
|| gpiospec
->args
[0] < 1)
1279 *flags
= gpiospec
->args
[1];
1281 return gpiospec
->args
[0] - SN_GPIO_PHYSICAL_OFFSET
;
1284 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip
*chip
,
1285 unsigned int offset
)
1287 struct ti_sn65dsi86
*pdata
= gpiochip_get_data(chip
);
1290 * We already have to keep track of the direction because we use
1291 * that to figure out whether we've powered the device. We can
1292 * just return that rather than (maybe) powering up the device
1293 * to ask its direction.
1295 return test_bit(offset
, pdata
->gchip_output
) ?
1296 GPIO_LINE_DIRECTION_OUT
: GPIO_LINE_DIRECTION_IN
;
1299 static int ti_sn_bridge_gpio_get(struct gpio_chip
*chip
, unsigned int offset
)
1301 struct ti_sn65dsi86
*pdata
= gpiochip_get_data(chip
);
1306 * When the pin is an input we don't forcibly keep the bridge
1307 * powered--we just power it on to read the pin. NOTE: part of
1308 * the reason this works is that the bridge defaults (when
1309 * powered back on) to all 4 GPIOs being configured as GPIO input.
1310 * Also note that if something else is keeping the chip powered the
1311 * pm_runtime functions are lightweight increments of a refcount.
1313 pm_runtime_get_sync(pdata
->dev
);
1314 ret
= regmap_read(pdata
->regmap
, SN_GPIO_IO_REG
, &val
);
1315 pm_runtime_put_autosuspend(pdata
->dev
);
1320 return !!(val
& BIT(SN_GPIO_INPUT_SHIFT
+ offset
));
1323 static void ti_sn_bridge_gpio_set(struct gpio_chip
*chip
, unsigned int offset
,
1326 struct ti_sn65dsi86
*pdata
= gpiochip_get_data(chip
);
1329 if (!test_bit(offset
, pdata
->gchip_output
)) {
1330 dev_err(pdata
->dev
, "Ignoring GPIO set while input\n");
1335 ret
= regmap_update_bits(pdata
->regmap
, SN_GPIO_IO_REG
,
1336 BIT(SN_GPIO_OUTPUT_SHIFT
+ offset
),
1337 val
<< (SN_GPIO_OUTPUT_SHIFT
+ offset
));
1339 dev_warn(pdata
->dev
,
1340 "Failed to set bridge GPIO %u: %d\n", offset
, ret
);
1343 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip
*chip
,
1344 unsigned int offset
)
1346 struct ti_sn65dsi86
*pdata
= gpiochip_get_data(chip
);
1347 int shift
= offset
* 2;
1350 if (!test_and_clear_bit(offset
, pdata
->gchip_output
))
1353 ret
= regmap_update_bits(pdata
->regmap
, SN_GPIO_CTRL_REG
,
1354 SN_GPIO_MUX_MASK
<< shift
,
1355 SN_GPIO_MUX_INPUT
<< shift
);
1357 set_bit(offset
, pdata
->gchip_output
);
1362 * NOTE: if nobody else is powering the device this may fully power
1363 * it off and when it comes back it will have lost all state, but
1364 * that's OK because the default is input and we're now an input.
1366 pm_runtime_put_autosuspend(pdata
->dev
);
1371 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip
*chip
,
1372 unsigned int offset
, int val
)
1374 struct ti_sn65dsi86
*pdata
= gpiochip_get_data(chip
);
1375 int shift
= offset
* 2;
1378 if (test_and_set_bit(offset
, pdata
->gchip_output
))
1381 pm_runtime_get_sync(pdata
->dev
);
1383 /* Set value first to avoid glitching */
1384 ti_sn_bridge_gpio_set(chip
, offset
, val
);
1387 ret
= regmap_update_bits(pdata
->regmap
, SN_GPIO_CTRL_REG
,
1388 SN_GPIO_MUX_MASK
<< shift
,
1389 SN_GPIO_MUX_OUTPUT
<< shift
);
1391 clear_bit(offset
, pdata
->gchip_output
);
1392 pm_runtime_put_autosuspend(pdata
->dev
);
1398 static void ti_sn_bridge_gpio_free(struct gpio_chip
*chip
, unsigned int offset
)
1400 /* We won't keep pm_runtime if we're input, so switch there on free */
1401 ti_sn_bridge_gpio_direction_input(chip
, offset
);
1404 static const char * const ti_sn_bridge_gpio_names
[SN_NUM_GPIOS
] = {
1405 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1408 static int ti_sn_gpio_probe(struct auxiliary_device
*adev
,
1409 const struct auxiliary_device_id
*id
)
1411 struct ti_sn65dsi86
*pdata
= dev_get_drvdata(adev
->dev
.parent
);
1414 /* Only init if someone is going to use us as a GPIO controller */
1415 if (!of_property_read_bool(pdata
->dev
->of_node
, "gpio-controller"))
1418 pdata
->gchip
.label
= dev_name(pdata
->dev
);
1419 pdata
->gchip
.parent
= pdata
->dev
;
1420 pdata
->gchip
.owner
= THIS_MODULE
;
1421 pdata
->gchip
.of_xlate
= tn_sn_bridge_of_xlate
;
1422 pdata
->gchip
.of_gpio_n_cells
= 2;
1423 pdata
->gchip
.free
= ti_sn_bridge_gpio_free
;
1424 pdata
->gchip
.get_direction
= ti_sn_bridge_gpio_get_direction
;
1425 pdata
->gchip
.direction_input
= ti_sn_bridge_gpio_direction_input
;
1426 pdata
->gchip
.direction_output
= ti_sn_bridge_gpio_direction_output
;
1427 pdata
->gchip
.get
= ti_sn_bridge_gpio_get
;
1428 pdata
->gchip
.set
= ti_sn_bridge_gpio_set
;
1429 pdata
->gchip
.can_sleep
= true;
1430 pdata
->gchip
.names
= ti_sn_bridge_gpio_names
;
1431 pdata
->gchip
.ngpio
= SN_NUM_GPIOS
;
1432 pdata
->gchip
.base
= -1;
1433 ret
= devm_gpiochip_add_data(&adev
->dev
, &pdata
->gchip
, pdata
);
1435 dev_err(pdata
->dev
, "can't add gpio chip\n");
1440 static const struct auxiliary_device_id ti_sn_gpio_id_table
[] = {
1441 { .name
= "ti_sn65dsi86.gpio", },
1445 MODULE_DEVICE_TABLE(auxiliary
, ti_sn_gpio_id_table
);
1447 static struct auxiliary_driver ti_sn_gpio_driver
= {
1449 .probe
= ti_sn_gpio_probe
,
1450 .id_table
= ti_sn_gpio_id_table
,
1453 static int __init
ti_sn_gpio_register(void)
1455 return auxiliary_driver_register(&ti_sn_gpio_driver
);
1458 static void ti_sn_gpio_unregister(void)
1460 auxiliary_driver_unregister(&ti_sn_gpio_driver
);
1465 static inline int ti_sn_gpio_register(void) { return 0; }
1466 static inline void ti_sn_gpio_unregister(void) {}
1470 /* -----------------------------------------------------------------------------
1474 static void ti_sn65dsi86_runtime_disable(void *data
)
1476 pm_runtime_dont_use_autosuspend(data
);
1477 pm_runtime_disable(data
);
1480 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86
*pdata
)
1483 const char * const ti_sn_bridge_supply_names
[] = {
1484 "vcca", "vcc", "vccio", "vpll",
1487 for (i
= 0; i
< SN_REGULATOR_SUPPLY_NUM
; i
++)
1488 pdata
->supplies
[i
].supply
= ti_sn_bridge_supply_names
[i
];
1490 return devm_regulator_bulk_get(pdata
->dev
, SN_REGULATOR_SUPPLY_NUM
,
1494 static int ti_sn65dsi86_probe(struct i2c_client
*client
,
1495 const struct i2c_device_id
*id
)
1497 struct device
*dev
= &client
->dev
;
1498 struct ti_sn65dsi86
*pdata
;
1501 if (!i2c_check_functionality(client
->adapter
, I2C_FUNC_I2C
)) {
1502 DRM_ERROR("device doesn't support I2C\n");
1506 pdata
= devm_kzalloc(dev
, sizeof(struct ti_sn65dsi86
), GFP_KERNEL
);
1509 dev_set_drvdata(dev
, pdata
);
1512 mutex_init(&pdata
->comms_mutex
);
1514 pdata
->regmap
= devm_regmap_init_i2c(client
,
1515 &ti_sn65dsi86_regmap_config
);
1516 if (IS_ERR(pdata
->regmap
))
1517 return dev_err_probe(dev
, PTR_ERR(pdata
->regmap
),
1518 "regmap i2c init failed\n");
1520 pdata
->enable_gpio
= devm_gpiod_get_optional(dev
, "enable",
1522 if (IS_ERR(pdata
->enable_gpio
))
1523 return dev_err_probe(dev
, PTR_ERR(pdata
->enable_gpio
),
1524 "failed to get enable gpio from DT\n");
1526 ret
= ti_sn65dsi86_parse_regulators(pdata
);
1528 return dev_err_probe(dev
, ret
, "failed to parse regulators\n");
1530 pdata
->refclk
= devm_clk_get_optional(dev
, "refclk");
1531 if (IS_ERR(pdata
->refclk
))
1532 return dev_err_probe(dev
, PTR_ERR(pdata
->refclk
),
1533 "failed to get reference clock\n");
1535 pm_runtime_enable(dev
);
1536 pm_runtime_set_autosuspend_delay(pdata
->dev
, 500);
1537 pm_runtime_use_autosuspend(pdata
->dev
);
1538 ret
= devm_add_action_or_reset(dev
, ti_sn65dsi86_runtime_disable
, dev
);
1542 ti_sn65dsi86_debugfs_init(pdata
);
1545 * Break ourselves up into a collection of aux devices. The only real
1546 * motiviation here is to solve the chicken-and-egg problem of probe
1547 * ordering. The bridge wants the panel to be there when it probes.
1548 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1549 * when it probes. The panel and maybe backlight might want the DDC
1550 * bus. Soon the PWM provided by the bridge chip will have the same
1551 * problem. Having sub-devices allows the some sub devices to finish
1552 * probing even if others return -EPROBE_DEFER and gets us around the
1556 if (IS_ENABLED(CONFIG_OF_GPIO
)) {
1557 ret
= ti_sn65dsi86_add_aux_device(pdata
, &pdata
->gpio_aux
, "gpio");
1563 * NOTE: At the end of the AUX channel probe we'll add the aux device
1564 * for the bridge. This is because the bridge can't be used until the
1565 * AUX channel is there and this is a very simple solution to the
1566 * dependency problem.
1568 return ti_sn65dsi86_add_aux_device(pdata
, &pdata
->aux_aux
, "aux");
1571 static struct i2c_device_id ti_sn65dsi86_id
[] = {
1572 { "ti,sn65dsi86", 0},
1575 MODULE_DEVICE_TABLE(i2c
, ti_sn65dsi86_id
);
1577 static const struct of_device_id ti_sn65dsi86_match_table
[] = {
1578 {.compatible
= "ti,sn65dsi86"},
1581 MODULE_DEVICE_TABLE(of
, ti_sn65dsi86_match_table
);
1583 static struct i2c_driver ti_sn65dsi86_driver
= {
1585 .name
= "ti_sn65dsi86",
1586 .of_match_table
= ti_sn65dsi86_match_table
,
1587 .pm
= &ti_sn65dsi86_pm_ops
,
1589 .probe
= ti_sn65dsi86_probe
,
1590 .id_table
= ti_sn65dsi86_id
,
1593 static int __init
ti_sn65dsi86_init(void)
1597 ret
= i2c_add_driver(&ti_sn65dsi86_driver
);
1601 ret
= ti_sn_gpio_register();
1603 goto err_main_was_registered
;
1605 ret
= auxiliary_driver_register(&ti_sn_aux_driver
);
1607 goto err_gpio_was_registered
;
1609 ret
= auxiliary_driver_register(&ti_sn_bridge_driver
);
1611 goto err_aux_was_registered
;
1615 err_aux_was_registered
:
1616 auxiliary_driver_unregister(&ti_sn_aux_driver
);
1617 err_gpio_was_registered
:
1618 ti_sn_gpio_unregister();
1619 err_main_was_registered
:
1620 i2c_del_driver(&ti_sn65dsi86_driver
);
1624 module_init(ti_sn65dsi86_init
);
1626 static void __exit
ti_sn65dsi86_exit(void)
1628 auxiliary_driver_unregister(&ti_sn_bridge_driver
);
1629 auxiliary_driver_unregister(&ti_sn_aux_driver
);
1630 ti_sn_gpio_unregister();
1631 i2c_del_driver(&ti_sn65dsi86_driver
);
1633 module_exit(ti_sn65dsi86_exit
);
1635 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
1636 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1637 MODULE_LICENSE("GPL v2");