2 * Copyright © 2009 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/i2c.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/sched.h>
30 #include <linux/seq_file.h>
32 #include <drm/drm_dp_helper.h>
33 #include <drm/drm_print.h>
34 #include <drm/drm_vblank.h>
35 #include <drm/drm_dp_mst_helper.h>
37 #include "drm_crtc_helper_internal.h"
42 * These functions contain some common logic and helpers at various abstraction
43 * levels to deal with Display Port sink devices and related things like DP aux
44 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
48 /* Helpers for DP link training */
49 static u8
dp_link_status(const u8 link_status
[DP_LINK_STATUS_SIZE
], int r
)
51 return link_status
[r
- DP_LANE0_1_STATUS
];
54 static u8
dp_get_lane_status(const u8 link_status
[DP_LINK_STATUS_SIZE
],
57 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
58 int s
= (lane
& 1) * 4;
59 u8 l
= dp_link_status(link_status
, i
);
60 return (l
>> s
) & 0xf;
63 bool drm_dp_channel_eq_ok(const u8 link_status
[DP_LINK_STATUS_SIZE
],
70 lane_align
= dp_link_status(link_status
,
71 DP_LANE_ALIGN_STATUS_UPDATED
);
72 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
74 for (lane
= 0; lane
< lane_count
; lane
++) {
75 lane_status
= dp_get_lane_status(link_status
, lane
);
76 if ((lane_status
& DP_CHANNEL_EQ_BITS
) != DP_CHANNEL_EQ_BITS
)
81 EXPORT_SYMBOL(drm_dp_channel_eq_ok
);
83 bool drm_dp_clock_recovery_ok(const u8 link_status
[DP_LINK_STATUS_SIZE
],
89 for (lane
= 0; lane
< lane_count
; lane
++) {
90 lane_status
= dp_get_lane_status(link_status
, lane
);
91 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
96 EXPORT_SYMBOL(drm_dp_clock_recovery_ok
);
98 u8
drm_dp_get_adjust_request_voltage(const u8 link_status
[DP_LINK_STATUS_SIZE
],
101 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
102 int s
= ((lane
& 1) ?
103 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
104 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
105 u8 l
= dp_link_status(link_status
, i
);
107 return ((l
>> s
) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
109 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage
);
111 u8
drm_dp_get_adjust_request_pre_emphasis(const u8 link_status
[DP_LINK_STATUS_SIZE
],
114 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
115 int s
= ((lane
& 1) ?
116 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
117 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
118 u8 l
= dp_link_status(link_status
, i
);
120 return ((l
>> s
) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
122 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis
);
124 u8
drm_dp_get_adjust_request_post_cursor(const u8 link_status
[DP_LINK_STATUS_SIZE
],
127 unsigned int offset
= DP_ADJUST_REQUEST_POST_CURSOR2
;
128 u8 value
= dp_link_status(link_status
, offset
);
130 return (value
>> (lane
<< 1)) & 0x3;
132 EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor
);
134 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
136 unsigned long rd_interval
= dpcd
[DP_TRAINING_AUX_RD_INTERVAL
] &
137 DP_TRAINING_AUX_RD_MASK
;
140 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
143 if (rd_interval
== 0 || dpcd
[DP_DPCD_REV
] >= DP_DPCD_REV_14
)
146 rd_interval
*= 4 * USEC_PER_MSEC
;
148 usleep_range(rd_interval
, rd_interval
* 2);
150 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay
);
152 void drm_dp_link_train_channel_eq_delay(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
])
154 unsigned long rd_interval
= dpcd
[DP_TRAINING_AUX_RD_INTERVAL
] &
155 DP_TRAINING_AUX_RD_MASK
;
158 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
161 if (rd_interval
== 0)
164 rd_interval
*= 4 * USEC_PER_MSEC
;
166 usleep_range(rd_interval
, rd_interval
* 2);
168 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay
);
170 u8
drm_dp_link_rate_to_bw_code(int link_rate
)
172 /* Spec says link_bw = link_rate / 0.27Gbps */
173 return link_rate
/ 27000;
175 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code
);
177 int drm_dp_bw_code_to_link_rate(u8 link_bw
)
179 /* Spec says link_rate = link_bw * 0.27Gbps */
180 return link_bw
* 27000;
182 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate
);
184 #define AUX_RETRY_INTERVAL 500 /* us */
187 drm_dp_dump_access(const struct drm_dp_aux
*aux
,
188 u8 request
, uint offset
, void *buffer
, int ret
)
190 const char *arrow
= request
== DP_AUX_NATIVE_READ
? "->" : "<-";
193 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
194 aux
->name
, offset
, arrow
, ret
, min(ret
, 20), buffer
);
196 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
197 aux
->name
, offset
, arrow
, ret
);
203 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
204 * independent access to AUX functionality. Drivers can take advantage of
205 * this by filling in the fields of the drm_dp_aux structure.
207 * Transactions are described using a hardware-independent drm_dp_aux_msg
208 * structure, which is passed into a driver's .transfer() implementation.
209 * Both native and I2C-over-AUX transactions are supported.
212 static int drm_dp_dpcd_access(struct drm_dp_aux
*aux
, u8 request
,
213 unsigned int offset
, void *buffer
, size_t size
)
215 struct drm_dp_aux_msg msg
;
216 unsigned int retry
, native_reply
;
217 int err
= 0, ret
= 0;
219 memset(&msg
, 0, sizeof(msg
));
220 msg
.address
= offset
;
221 msg
.request
= request
;
225 mutex_lock(&aux
->hw_mutex
);
228 * The specification doesn't give any recommendation on how often to
229 * retry native transactions. We used to retry 7 times like for
230 * aux i2c transactions but real world devices this wasn't
231 * sufficient, bump to 32 which makes Dell 4k monitors happier.
233 for (retry
= 0; retry
< 32; retry
++) {
234 if (ret
!= 0 && ret
!= -ETIMEDOUT
) {
235 usleep_range(AUX_RETRY_INTERVAL
,
236 AUX_RETRY_INTERVAL
+ 100);
239 ret
= aux
->transfer(aux
, &msg
);
241 native_reply
= msg
.reply
& DP_AUX_NATIVE_REPLY_MASK
;
242 if (native_reply
== DP_AUX_NATIVE_REPLY_ACK
) {
252 * We want the error we return to be the error we received on
253 * the first transaction, since we may get a different error the
260 DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err
);
264 mutex_unlock(&aux
->hw_mutex
);
269 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
270 * @aux: DisplayPort AUX channel (SST or MST)
271 * @offset: address of the (first) register to read
272 * @buffer: buffer to store the register values
273 * @size: number of bytes in @buffer
275 * Returns the number of bytes transferred on success, or a negative error
276 * code on failure. -EIO is returned if the request was NAKed by the sink or
277 * if the retry count was exceeded. If not all bytes were transferred, this
278 * function returns -EPROTO. Errors from the underlying AUX channel transfer
279 * function, with the exception of -EBUSY (which causes the transaction to
280 * be retried), are propagated to the caller.
282 ssize_t
drm_dp_dpcd_read(struct drm_dp_aux
*aux
, unsigned int offset
,
283 void *buffer
, size_t size
)
288 * HP ZR24w corrupts the first DPCD access after entering power save
289 * mode. Eg. on a read, the entire buffer will be filled with the same
290 * byte. Do a throw away read to avoid corrupting anything we care
291 * about. Afterwards things will work correctly until the monitor
292 * gets woken up and subsequently re-enters power save mode.
294 * The user pressing any button on the monitor is enough to wake it
295 * up, so there is no particularly good place to do the workaround.
296 * We just have to do it before any DPCD access and hope that the
297 * monitor doesn't power down exactly after the throw away read.
299 if (!aux
->is_remote
) {
300 ret
= drm_dp_dpcd_access(aux
, DP_AUX_NATIVE_READ
, DP_DPCD_REV
,
307 ret
= drm_dp_mst_dpcd_read(aux
, offset
, buffer
, size
);
309 ret
= drm_dp_dpcd_access(aux
, DP_AUX_NATIVE_READ
, offset
,
313 drm_dp_dump_access(aux
, DP_AUX_NATIVE_READ
, offset
, buffer
, ret
);
316 EXPORT_SYMBOL(drm_dp_dpcd_read
);
319 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
320 * @aux: DisplayPort AUX channel (SST or MST)
321 * @offset: address of the (first) register to write
322 * @buffer: buffer containing the values to write
323 * @size: number of bytes in @buffer
325 * Returns the number of bytes transferred on success, or a negative error
326 * code on failure. -EIO is returned if the request was NAKed by the sink or
327 * if the retry count was exceeded. If not all bytes were transferred, this
328 * function returns -EPROTO. Errors from the underlying AUX channel transfer
329 * function, with the exception of -EBUSY (which causes the transaction to
330 * be retried), are propagated to the caller.
332 ssize_t
drm_dp_dpcd_write(struct drm_dp_aux
*aux
, unsigned int offset
,
333 void *buffer
, size_t size
)
338 ret
= drm_dp_mst_dpcd_write(aux
, offset
, buffer
, size
);
340 ret
= drm_dp_dpcd_access(aux
, DP_AUX_NATIVE_WRITE
, offset
,
343 drm_dp_dump_access(aux
, DP_AUX_NATIVE_WRITE
, offset
, buffer
, ret
);
346 EXPORT_SYMBOL(drm_dp_dpcd_write
);
349 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
350 * @aux: DisplayPort AUX channel
351 * @status: buffer to store the link status in (must be at least 6 bytes)
353 * Returns the number of bytes transferred on success or a negative error
356 int drm_dp_dpcd_read_link_status(struct drm_dp_aux
*aux
,
357 u8 status
[DP_LINK_STATUS_SIZE
])
359 return drm_dp_dpcd_read(aux
, DP_LANE0_1_STATUS
, status
,
360 DP_LINK_STATUS_SIZE
);
362 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status
);
365 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
366 * @aux: DisplayPort AUX channel
367 * @real_edid_checksum: real edid checksum for the last block
372 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux
*aux
,
373 u8 real_edid_checksum
)
375 u8 link_edid_read
= 0, auto_test_req
= 0, test_resp
= 0;
377 if (drm_dp_dpcd_read(aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
,
378 &auto_test_req
, 1) < 1) {
379 DRM_ERROR("DPCD failed read at register 0x%x\n",
380 DP_DEVICE_SERVICE_IRQ_VECTOR
);
383 auto_test_req
&= DP_AUTOMATED_TEST_REQUEST
;
385 if (drm_dp_dpcd_read(aux
, DP_TEST_REQUEST
, &link_edid_read
, 1) < 1) {
386 DRM_ERROR("DPCD failed read at register 0x%x\n",
390 link_edid_read
&= DP_TEST_LINK_EDID_READ
;
392 if (!auto_test_req
|| !link_edid_read
) {
393 DRM_DEBUG_KMS("Source DUT does not support TEST_EDID_READ\n");
397 if (drm_dp_dpcd_write(aux
, DP_DEVICE_SERVICE_IRQ_VECTOR
,
398 &auto_test_req
, 1) < 1) {
399 DRM_ERROR("DPCD failed write at register 0x%x\n",
400 DP_DEVICE_SERVICE_IRQ_VECTOR
);
404 /* send back checksum for the last edid extension block data */
405 if (drm_dp_dpcd_write(aux
, DP_TEST_EDID_CHECKSUM
,
406 &real_edid_checksum
, 1) < 1) {
407 DRM_ERROR("DPCD failed write at register 0x%x\n",
408 DP_TEST_EDID_CHECKSUM
);
412 test_resp
|= DP_TEST_EDID_CHECKSUM_WRITE
;
413 if (drm_dp_dpcd_write(aux
, DP_TEST_RESPONSE
, &test_resp
, 1) < 1) {
414 DRM_ERROR("DPCD failed write at register 0x%x\n",
421 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum
);
424 * drm_dp_downstream_max_clock() - extract branch device max
425 * pixel rate for legacy VGA
426 * converter or max TMDS clock
428 * @dpcd: DisplayPort configuration data
429 * @port_cap: port capabilities
431 * Returns max clock in kHz on success or 0 if max clock not defined
433 int drm_dp_downstream_max_clock(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
434 const u8 port_cap
[4])
436 int type
= port_cap
[0] & DP_DS_PORT_TYPE_MASK
;
437 bool detailed_cap_info
= dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
438 DP_DETAILED_CAP_INFO_AVAILABLE
;
440 if (!detailed_cap_info
)
444 case DP_DS_PORT_TYPE_VGA
:
445 return port_cap
[1] * 8 * 1000;
446 case DP_DS_PORT_TYPE_DVI
:
447 case DP_DS_PORT_TYPE_HDMI
:
448 case DP_DS_PORT_TYPE_DP_DUALMODE
:
449 return port_cap
[1] * 2500;
454 EXPORT_SYMBOL(drm_dp_downstream_max_clock
);
457 * drm_dp_downstream_max_bpc() - extract branch device max
459 * @dpcd: DisplayPort configuration data
460 * @port_cap: port capabilities
462 * Returns max bpc on success or 0 if max bpc not defined
464 int drm_dp_downstream_max_bpc(const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
465 const u8 port_cap
[4])
467 int type
= port_cap
[0] & DP_DS_PORT_TYPE_MASK
;
468 bool detailed_cap_info
= dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
469 DP_DETAILED_CAP_INFO_AVAILABLE
;
472 if (!detailed_cap_info
)
476 case DP_DS_PORT_TYPE_VGA
:
477 case DP_DS_PORT_TYPE_DVI
:
478 case DP_DS_PORT_TYPE_HDMI
:
479 case DP_DS_PORT_TYPE_DP_DUALMODE
:
480 bpc
= port_cap
[2] & DP_DS_MAX_BPC_MASK
;
497 EXPORT_SYMBOL(drm_dp_downstream_max_bpc
);
500 * drm_dp_downstream_id() - identify branch device
501 * @aux: DisplayPort AUX channel
502 * @id: DisplayPort branch device id
504 * Returns branch device id on success or NULL on failure
506 int drm_dp_downstream_id(struct drm_dp_aux
*aux
, char id
[6])
508 return drm_dp_dpcd_read(aux
, DP_BRANCH_ID
, id
, 6);
510 EXPORT_SYMBOL(drm_dp_downstream_id
);
513 * drm_dp_downstream_debug() - debug DP branch devices
514 * @m: pointer for debugfs file
515 * @dpcd: DisplayPort configuration data
516 * @port_cap: port capabilities
517 * @aux: DisplayPort AUX channel
520 void drm_dp_downstream_debug(struct seq_file
*m
,
521 const u8 dpcd
[DP_RECEIVER_CAP_SIZE
],
522 const u8 port_cap
[4], struct drm_dp_aux
*aux
)
524 bool detailed_cap_info
= dpcd
[DP_DOWNSTREAMPORT_PRESENT
] &
525 DP_DETAILED_CAP_INFO_AVAILABLE
;
531 int type
= port_cap
[0] & DP_DS_PORT_TYPE_MASK
;
532 bool branch_device
= drm_dp_is_branch(dpcd
);
534 seq_printf(m
, "\tDP branch device present: %s\n",
535 branch_device
? "yes" : "no");
541 case DP_DS_PORT_TYPE_DP
:
542 seq_puts(m
, "\t\tType: DisplayPort\n");
544 case DP_DS_PORT_TYPE_VGA
:
545 seq_puts(m
, "\t\tType: VGA\n");
547 case DP_DS_PORT_TYPE_DVI
:
548 seq_puts(m
, "\t\tType: DVI\n");
550 case DP_DS_PORT_TYPE_HDMI
:
551 seq_puts(m
, "\t\tType: HDMI\n");
553 case DP_DS_PORT_TYPE_NON_EDID
:
554 seq_puts(m
, "\t\tType: others without EDID support\n");
556 case DP_DS_PORT_TYPE_DP_DUALMODE
:
557 seq_puts(m
, "\t\tType: DP++\n");
559 case DP_DS_PORT_TYPE_WIRELESS
:
560 seq_puts(m
, "\t\tType: Wireless\n");
563 seq_puts(m
, "\t\tType: N/A\n");
566 memset(id
, 0, sizeof(id
));
567 drm_dp_downstream_id(aux
, id
);
568 seq_printf(m
, "\t\tID: %s\n", id
);
570 len
= drm_dp_dpcd_read(aux
, DP_BRANCH_HW_REV
, &rev
[0], 1);
572 seq_printf(m
, "\t\tHW: %d.%d\n",
573 (rev
[0] & 0xf0) >> 4, rev
[0] & 0xf);
575 len
= drm_dp_dpcd_read(aux
, DP_BRANCH_SW_REV
, rev
, 2);
577 seq_printf(m
, "\t\tSW: %d.%d\n", rev
[0], rev
[1]);
579 if (detailed_cap_info
) {
580 clk
= drm_dp_downstream_max_clock(dpcd
, port_cap
);
583 if (type
== DP_DS_PORT_TYPE_VGA
)
584 seq_printf(m
, "\t\tMax dot clock: %d kHz\n", clk
);
586 seq_printf(m
, "\t\tMax TMDS clock: %d kHz\n", clk
);
589 bpc
= drm_dp_downstream_max_bpc(dpcd
, port_cap
);
592 seq_printf(m
, "\t\tMax bpc: %d\n", bpc
);
595 EXPORT_SYMBOL(drm_dp_downstream_debug
);
598 * I2C-over-AUX implementation
601 static u32
drm_dp_i2c_functionality(struct i2c_adapter
*adapter
)
603 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
|
604 I2C_FUNC_SMBUS_READ_BLOCK_DATA
|
605 I2C_FUNC_SMBUS_BLOCK_PROC_CALL
|
609 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg
*msg
)
612 * In case of i2c defer or short i2c ack reply to a write,
613 * we need to switch to WRITE_STATUS_UPDATE to drain the
614 * rest of the message
616 if ((msg
->request
& ~DP_AUX_I2C_MOT
) == DP_AUX_I2C_WRITE
) {
617 msg
->request
&= DP_AUX_I2C_MOT
;
618 msg
->request
|= DP_AUX_I2C_WRITE_STATUS_UPDATE
;
622 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
623 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
624 #define AUX_STOP_LEN 4
625 #define AUX_CMD_LEN 4
626 #define AUX_ADDRESS_LEN 20
627 #define AUX_REPLY_PAD_LEN 4
628 #define AUX_LENGTH_LEN 8
631 * Calculate the duration of the AUX request/reply in usec. Gives the
632 * "best" case estimate, ie. successful while as short as possible.
634 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg
*msg
)
636 int len
= AUX_PRECHARGE_LEN
+ AUX_SYNC_LEN
+ AUX_STOP_LEN
+
637 AUX_CMD_LEN
+ AUX_ADDRESS_LEN
+ AUX_LENGTH_LEN
;
639 if ((msg
->request
& DP_AUX_I2C_READ
) == 0)
640 len
+= msg
->size
* 8;
645 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg
*msg
)
647 int len
= AUX_PRECHARGE_LEN
+ AUX_SYNC_LEN
+ AUX_STOP_LEN
+
648 AUX_CMD_LEN
+ AUX_REPLY_PAD_LEN
;
651 * For read we expect what was asked. For writes there will
652 * be 0 or 1 data bytes. Assume 0 for the "best" case.
654 if (msg
->request
& DP_AUX_I2C_READ
)
655 len
+= msg
->size
* 8;
660 #define I2C_START_LEN 1
661 #define I2C_STOP_LEN 1
662 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
663 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
666 * Calculate the length of the i2c transfer in usec, assuming
667 * the i2c bus speed is as specified. Gives the the "worst"
668 * case estimate, ie. successful while as long as possible.
669 * Doesn't account the the "MOT" bit, and instead assumes each
670 * message includes a START, ADDRESS and STOP. Neither does it
671 * account for additional random variables such as clock stretching.
673 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg
*msg
,
676 /* AUX bitrate is 1MHz, i2c bitrate as specified */
677 return DIV_ROUND_UP((I2C_START_LEN
+ I2C_ADDR_LEN
+
678 msg
->size
* I2C_DATA_LEN
+
679 I2C_STOP_LEN
) * 1000, i2c_speed_khz
);
683 * Deterine how many retries should be attempted to successfully transfer
684 * the specified message, based on the estimated durations of the
685 * i2c and AUX transfers.
687 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg
*msg
,
690 int aux_time_us
= drm_dp_aux_req_duration(msg
) +
691 drm_dp_aux_reply_duration(msg
);
692 int i2c_time_us
= drm_dp_i2c_msg_duration(msg
, i2c_speed_khz
);
694 return DIV_ROUND_UP(i2c_time_us
, aux_time_us
+ AUX_RETRY_INTERVAL
);
698 * FIXME currently assumes 10 kHz as some real world devices seem
699 * to require it. We should query/set the speed via DPCD if supported.
701 static int dp_aux_i2c_speed_khz __read_mostly
= 10;
702 module_param_unsafe(dp_aux_i2c_speed_khz
, int, 0644);
703 MODULE_PARM_DESC(dp_aux_i2c_speed_khz
,
704 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
707 * Transfer a single I2C-over-AUX message and handle various error conditions,
708 * retrying the transaction as appropriate. It is assumed that the
709 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
712 * Returns bytes transferred on success, or a negative error code on failure.
714 static int drm_dp_i2c_do_msg(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*msg
)
716 unsigned int retry
, defer_i2c
;
719 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
720 * is required to retry at least seven times upon receiving AUX_DEFER
721 * before giving up the AUX transaction.
723 * We also try to account for the i2c bus speed.
725 int max_retries
= max(7, drm_dp_i2c_retry_count(msg
, dp_aux_i2c_speed_khz
));
727 for (retry
= 0, defer_i2c
= 0; retry
< (max_retries
+ defer_i2c
); retry
++) {
728 ret
= aux
->transfer(aux
, msg
);
734 * While timeouts can be errors, they're usually normal
735 * behavior (for instance, when a driver tries to
736 * communicate with a non-existant DisplayPort device).
737 * Avoid spamming the kernel log with timeout errors.
739 if (ret
== -ETIMEDOUT
)
740 DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n");
742 DRM_DEBUG_KMS("transaction failed: %d\n", ret
);
748 switch (msg
->reply
& DP_AUX_NATIVE_REPLY_MASK
) {
749 case DP_AUX_NATIVE_REPLY_ACK
:
751 * For I2C-over-AUX transactions this isn't enough, we
752 * need to check for the I2C ACK reply.
756 case DP_AUX_NATIVE_REPLY_NACK
:
757 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret
, msg
->size
);
760 case DP_AUX_NATIVE_REPLY_DEFER
:
761 DRM_DEBUG_KMS("native defer\n");
763 * We could check for I2C bit rate capabilities and if
764 * available adjust this interval. We could also be
765 * more careful with DP-to-legacy adapters where a
766 * long legacy cable may force very low I2C bit rates.
768 * For now just defer for long enough to hopefully be
769 * safe for all use-cases.
771 usleep_range(AUX_RETRY_INTERVAL
, AUX_RETRY_INTERVAL
+ 100);
775 DRM_ERROR("invalid native reply %#04x\n", msg
->reply
);
779 switch (msg
->reply
& DP_AUX_I2C_REPLY_MASK
) {
780 case DP_AUX_I2C_REPLY_ACK
:
782 * Both native ACK and I2C ACK replies received. We
783 * can assume the transfer was successful.
785 if (ret
!= msg
->size
)
786 drm_dp_i2c_msg_write_status_update(msg
);
789 case DP_AUX_I2C_REPLY_NACK
:
790 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu)\n",
792 aux
->i2c_nack_count
++;
795 case DP_AUX_I2C_REPLY_DEFER
:
796 DRM_DEBUG_KMS("I2C defer\n");
797 /* DP Compliance Test 4.2.2.5 Requirement:
798 * Must have at least 7 retries for I2C defers on the
799 * transaction to pass this test
801 aux
->i2c_defer_count
++;
804 usleep_range(AUX_RETRY_INTERVAL
, AUX_RETRY_INTERVAL
+ 100);
805 drm_dp_i2c_msg_write_status_update(msg
);
810 DRM_ERROR("invalid I2C reply %#04x\n", msg
->reply
);
815 DRM_DEBUG_KMS("too many retries, giving up\n");
819 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg
*msg
,
820 const struct i2c_msg
*i2c_msg
)
822 msg
->request
= (i2c_msg
->flags
& I2C_M_RD
) ?
823 DP_AUX_I2C_READ
: DP_AUX_I2C_WRITE
;
824 if (!(i2c_msg
->flags
& I2C_M_STOP
))
825 msg
->request
|= DP_AUX_I2C_MOT
;
829 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
831 * Returns an error code on failure, or a recommended transfer size on success.
833 static int drm_dp_i2c_drain_msg(struct drm_dp_aux
*aux
, struct drm_dp_aux_msg
*orig_msg
)
835 int err
, ret
= orig_msg
->size
;
836 struct drm_dp_aux_msg msg
= *orig_msg
;
838 while (msg
.size
> 0) {
839 err
= drm_dp_i2c_do_msg(aux
, &msg
);
841 return err
== 0 ? -EPROTO
: err
;
843 if (err
< msg
.size
&& err
< ret
) {
844 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n",
857 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
858 * packets to be as large as possible. If not, the I2C transactions never
859 * succeed. Hence the default is maximum.
861 static int dp_aux_i2c_transfer_size __read_mostly
= DP_AUX_MAX_PAYLOAD_BYTES
;
862 module_param_unsafe(dp_aux_i2c_transfer_size
, int, 0644);
863 MODULE_PARM_DESC(dp_aux_i2c_transfer_size
,
864 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
866 static int drm_dp_i2c_xfer(struct i2c_adapter
*adapter
, struct i2c_msg
*msgs
,
869 struct drm_dp_aux
*aux
= adapter
->algo_data
;
871 unsigned transfer_size
;
872 struct drm_dp_aux_msg msg
;
875 dp_aux_i2c_transfer_size
= clamp(dp_aux_i2c_transfer_size
, 1, DP_AUX_MAX_PAYLOAD_BYTES
);
877 memset(&msg
, 0, sizeof(msg
));
879 for (i
= 0; i
< num
; i
++) {
880 msg
.address
= msgs
[i
].addr
;
881 drm_dp_i2c_msg_set_request(&msg
, &msgs
[i
]);
882 /* Send a bare address packet to start the transaction.
883 * Zero sized messages specify an address only (bare
884 * address) transaction.
888 err
= drm_dp_i2c_do_msg(aux
, &msg
);
891 * Reset msg.request in case in case it got
892 * changed into a WRITE_STATUS_UPDATE.
894 drm_dp_i2c_msg_set_request(&msg
, &msgs
[i
]);
898 /* We want each transaction to be as large as possible, but
899 * we'll go to smaller sizes if the hardware gives us a
902 transfer_size
= dp_aux_i2c_transfer_size
;
903 for (j
= 0; j
< msgs
[i
].len
; j
+= msg
.size
) {
904 msg
.buffer
= msgs
[i
].buf
+ j
;
905 msg
.size
= min(transfer_size
, msgs
[i
].len
- j
);
907 err
= drm_dp_i2c_drain_msg(aux
, &msg
);
910 * Reset msg.request in case in case it got
911 * changed into a WRITE_STATUS_UPDATE.
913 drm_dp_i2c_msg_set_request(&msg
, &msgs
[i
]);
924 /* Send a bare address packet to close out the transaction.
925 * Zero sized messages specify an address only (bare
926 * address) transaction.
928 msg
.request
&= ~DP_AUX_I2C_MOT
;
931 (void)drm_dp_i2c_do_msg(aux
, &msg
);
936 static const struct i2c_algorithm drm_dp_i2c_algo
= {
937 .functionality
= drm_dp_i2c_functionality
,
938 .master_xfer
= drm_dp_i2c_xfer
,
941 static struct drm_dp_aux
*i2c_to_aux(struct i2c_adapter
*i2c
)
943 return container_of(i2c
, struct drm_dp_aux
, ddc
);
946 static void lock_bus(struct i2c_adapter
*i2c
, unsigned int flags
)
948 mutex_lock(&i2c_to_aux(i2c
)->hw_mutex
);
951 static int trylock_bus(struct i2c_adapter
*i2c
, unsigned int flags
)
953 return mutex_trylock(&i2c_to_aux(i2c
)->hw_mutex
);
956 static void unlock_bus(struct i2c_adapter
*i2c
, unsigned int flags
)
958 mutex_unlock(&i2c_to_aux(i2c
)->hw_mutex
);
961 static const struct i2c_lock_operations drm_dp_i2c_lock_ops
= {
962 .lock_bus
= lock_bus
,
963 .trylock_bus
= trylock_bus
,
964 .unlock_bus
= unlock_bus
,
967 static int drm_dp_aux_get_crc(struct drm_dp_aux
*aux
, u8
*crc
)
972 ret
= drm_dp_dpcd_readb(aux
, DP_TEST_SINK
, &buf
);
976 WARN_ON(!(buf
& DP_TEST_SINK_START
));
978 ret
= drm_dp_dpcd_readb(aux
, DP_TEST_SINK_MISC
, &buf
);
982 count
= buf
& DP_TEST_COUNT_MASK
;
983 if (count
== aux
->crc_count
)
984 return -EAGAIN
; /* No CRC yet */
986 aux
->crc_count
= count
;
989 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
990 * per component (RGB or CrYCb).
992 ret
= drm_dp_dpcd_read(aux
, DP_TEST_CRC_R_CR
, crc
, 6);
999 static void drm_dp_aux_crc_work(struct work_struct
*work
)
1001 struct drm_dp_aux
*aux
= container_of(work
, struct drm_dp_aux
,
1003 struct drm_crtc
*crtc
;
1008 if (WARN_ON(!aux
->crtc
))
1012 while (crtc
->crc
.opened
) {
1013 drm_crtc_wait_one_vblank(crtc
);
1014 if (!crtc
->crc
.opened
)
1017 ret
= drm_dp_aux_get_crc(aux
, crc_bytes
);
1018 if (ret
== -EAGAIN
) {
1019 usleep_range(1000, 2000);
1020 ret
= drm_dp_aux_get_crc(aux
, crc_bytes
);
1023 if (ret
== -EAGAIN
) {
1024 DRM_DEBUG_KMS("Get CRC failed after retrying: %d\n",
1028 DRM_DEBUG_KMS("Failed to get a CRC: %d\n", ret
);
1032 crcs
[0] = crc_bytes
[0] | crc_bytes
[1] << 8;
1033 crcs
[1] = crc_bytes
[2] | crc_bytes
[3] << 8;
1034 crcs
[2] = crc_bytes
[4] | crc_bytes
[5] << 8;
1035 drm_crtc_add_crc_entry(crtc
, false, 0, crcs
);
1040 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
1041 * @aux: DisplayPort AUX channel
1043 * Used for remote aux channel in general. Merely initialize the crc work
1046 void drm_dp_remote_aux_init(struct drm_dp_aux
*aux
)
1048 INIT_WORK(&aux
->crc_work
, drm_dp_aux_crc_work
);
1050 EXPORT_SYMBOL(drm_dp_remote_aux_init
);
1053 * drm_dp_aux_init() - minimally initialise an aux channel
1054 * @aux: DisplayPort AUX channel
1056 * If you need to use the drm_dp_aux's i2c adapter prior to registering it
1057 * with the outside world, call drm_dp_aux_init() first. You must still
1058 * call drm_dp_aux_register() once the connector has been registered to
1059 * allow userspace access to the auxiliary DP channel.
1061 void drm_dp_aux_init(struct drm_dp_aux
*aux
)
1063 mutex_init(&aux
->hw_mutex
);
1064 mutex_init(&aux
->cec
.lock
);
1065 INIT_WORK(&aux
->crc_work
, drm_dp_aux_crc_work
);
1067 aux
->ddc
.algo
= &drm_dp_i2c_algo
;
1068 aux
->ddc
.algo_data
= aux
;
1069 aux
->ddc
.retries
= 3;
1071 aux
->ddc
.lock_ops
= &drm_dp_i2c_lock_ops
;
1073 EXPORT_SYMBOL(drm_dp_aux_init
);
1076 * drm_dp_aux_register() - initialise and register aux channel
1077 * @aux: DisplayPort AUX channel
1079 * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
1080 * This should only be called when the underlying &struct drm_connector is
1081 * initialiazed already. Therefore the best place to call this is from
1082 * &drm_connector_funcs.late_register. Not that drivers which don't follow this
1083 * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled.
1085 * Drivers which need to use the aux channel before that point (e.g. at driver
1086 * load time, before drm_dev_register() has been called) need to call
1087 * drm_dp_aux_init().
1089 * Returns 0 on success or a negative error code on failure.
1091 int drm_dp_aux_register(struct drm_dp_aux
*aux
)
1096 drm_dp_aux_init(aux
);
1098 aux
->ddc
.class = I2C_CLASS_DDC
;
1099 aux
->ddc
.owner
= THIS_MODULE
;
1100 aux
->ddc
.dev
.parent
= aux
->dev
;
1102 strlcpy(aux
->ddc
.name
, aux
->name
? aux
->name
: dev_name(aux
->dev
),
1103 sizeof(aux
->ddc
.name
));
1105 ret
= drm_dp_aux_register_devnode(aux
);
1109 ret
= i2c_add_adapter(&aux
->ddc
);
1111 drm_dp_aux_unregister_devnode(aux
);
1117 EXPORT_SYMBOL(drm_dp_aux_register
);
1120 * drm_dp_aux_unregister() - unregister an AUX adapter
1121 * @aux: DisplayPort AUX channel
1123 void drm_dp_aux_unregister(struct drm_dp_aux
*aux
)
1125 drm_dp_aux_unregister_devnode(aux
);
1126 i2c_del_adapter(&aux
->ddc
);
1128 EXPORT_SYMBOL(drm_dp_aux_unregister
);
1130 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1133 * drm_dp_psr_setup_time() - PSR setup in time usec
1134 * @psr_cap: PSR capabilities from DPCD
1137 * PSR setup time for the panel in microseconds, negative
1138 * error code on failure.
1140 int drm_dp_psr_setup_time(const u8 psr_cap
[EDP_PSR_RECEIVER_CAP_SIZE
])
1142 static const u16 psr_setup_time_us
[] = {
1143 PSR_SETUP_TIME(330),
1144 PSR_SETUP_TIME(275),
1145 PSR_SETUP_TIME(220),
1146 PSR_SETUP_TIME(165),
1147 PSR_SETUP_TIME(110),
1153 i
= (psr_cap
[1] & DP_PSR_SETUP_TIME_MASK
) >> DP_PSR_SETUP_TIME_SHIFT
;
1154 if (i
>= ARRAY_SIZE(psr_setup_time_us
))
1157 return psr_setup_time_us
[i
];
1159 EXPORT_SYMBOL(drm_dp_psr_setup_time
);
1161 #undef PSR_SETUP_TIME
1164 * drm_dp_start_crc() - start capture of frame CRCs
1165 * @aux: DisplayPort AUX channel
1166 * @crtc: CRTC displaying the frames whose CRCs are to be captured
1168 * Returns 0 on success or a negative error code on failure.
1170 int drm_dp_start_crc(struct drm_dp_aux
*aux
, struct drm_crtc
*crtc
)
1175 ret
= drm_dp_dpcd_readb(aux
, DP_TEST_SINK
, &buf
);
1179 ret
= drm_dp_dpcd_writeb(aux
, DP_TEST_SINK
, buf
| DP_TEST_SINK_START
);
1185 schedule_work(&aux
->crc_work
);
1189 EXPORT_SYMBOL(drm_dp_start_crc
);
1192 * drm_dp_stop_crc() - stop capture of frame CRCs
1193 * @aux: DisplayPort AUX channel
1195 * Returns 0 on success or a negative error code on failure.
1197 int drm_dp_stop_crc(struct drm_dp_aux
*aux
)
1202 ret
= drm_dp_dpcd_readb(aux
, DP_TEST_SINK
, &buf
);
1206 ret
= drm_dp_dpcd_writeb(aux
, DP_TEST_SINK
, buf
& ~DP_TEST_SINK_START
);
1210 flush_work(&aux
->crc_work
);
1215 EXPORT_SYMBOL(drm_dp_stop_crc
);
1224 #define OUI(first, second, third) { (first), (second), (third) }
1225 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1226 { (first), (second), (third), (fourth), (fifth), (sixth) }
1228 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
1230 static const struct dpcd_quirk dpcd_quirk_list
[] = {
1231 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
1232 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY
, true, BIT(DP_DPCD_QUIRK_CONSTANT_N
) },
1233 /* LG LP140WF6-SPM1 eDP panel */
1234 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N
) },
1235 /* Apple panels need some additional handling to support PSR */
1236 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY
, false, BIT(DP_DPCD_QUIRK_NO_PSR
) },
1237 /* CH7511 seems to leave SINK_COUNT zeroed */
1238 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT
) },
1239 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
1240 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY
, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD
) },
1241 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
1242 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS
) },
1248 * Get a bit mask of DPCD quirks for the sink/branch device identified by
1249 * ident. The quirk data is shared but it's up to the drivers to act on the
1252 * For now, only the OUI (first three bytes) is used, but this may be extended
1253 * to device identification string and hardware/firmware revisions later.
1256 drm_dp_get_quirks(const struct drm_dp_dpcd_ident
*ident
, bool is_branch
)
1258 const struct dpcd_quirk
*quirk
;
1261 u8 any_device
[] = DEVICE_ID_ANY
;
1263 for (i
= 0; i
< ARRAY_SIZE(dpcd_quirk_list
); i
++) {
1264 quirk
= &dpcd_quirk_list
[i
];
1266 if (quirk
->is_branch
!= is_branch
)
1269 if (memcmp(quirk
->oui
, ident
->oui
, sizeof(ident
->oui
)) != 0)
1272 if (memcmp(quirk
->device_id
, any_device
, sizeof(any_device
)) != 0 &&
1273 memcmp(quirk
->device_id
, ident
->device_id
, sizeof(ident
->device_id
)) != 0)
1276 quirks
|= quirk
->quirks
;
1282 #undef DEVICE_ID_ANY
1291 #define MFG(first, second) { (first), (second) }
1292 #define PROD_ID(first, second) { (first), (second) }
1295 * Some devices have unreliable OUIDs where they don't set the device ID
1296 * correctly, and as a result we need to use the EDID for finding additional
1297 * DP quirks in such cases.
1299 static const struct edid_quirk edid_quirk_list
[] = {
1300 /* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
1301 * only supports DPCD backlight controls
1303 { MFG(0x4c, 0x83), PROD_ID(0x41, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT
) },
1305 * Some Dell CML 2020 systems have panels support both AUX and PWM
1306 * backlight control, and some only support AUX backlight control. All
1307 * said panels start up in AUX mode by default, and we don't have any
1308 * support for disabling HDR mode on these panels which would be
1309 * required to switch to PWM backlight control mode (plus, I'm not
1310 * even sure we want PWM backlight controls over DPCD backlight
1311 * controls anyway...). Until we have a better way of detecting these,
1312 * force DPCD backlight mode on all of them.
1314 { MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT
) },
1315 { MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT
) },
1316 { MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT
) },
1317 { MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT
) },
1318 { MFG(0x4c, 0x83), PROD_ID(0x47, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT
) },
1325 * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional
1326 * DP-specific quirks
1327 * @edid: The EDID to check
1329 * While OUIDs are meant to be used to recognize a DisplayPort device, a lot
1330 * of manufacturers don't seem to like following standards and neglect to fill
1331 * the dev-ID in, making it impossible to only use OUIDs for determining
1332 * quirks in some cases. This function can be used to check the EDID and look
1333 * up any additional DP quirks. The bits returned by this function correspond
1334 * to the quirk bits in &drm_dp_quirk.
1336 * Returns: a bitmask of quirks, if any. The driver can check this using
1337 * drm_dp_has_quirk().
1339 u32
drm_dp_get_edid_quirks(const struct edid
*edid
)
1341 const struct edid_quirk
*quirk
;
1348 for (i
= 0; i
< ARRAY_SIZE(edid_quirk_list
); i
++) {
1349 quirk
= &edid_quirk_list
[i
];
1350 if (memcmp(quirk
->mfg_id
, edid
->mfg_id
,
1351 sizeof(edid
->mfg_id
)) == 0 &&
1352 memcmp(quirk
->prod_id
, edid
->prod_code
,
1353 sizeof(edid
->prod_code
)) == 0)
1354 quirks
|= quirk
->quirks
;
1357 DRM_DEBUG_KMS("DP sink: EDID mfg %*phD prod-ID %*phD quirks: 0x%04x\n",
1358 (int)sizeof(edid
->mfg_id
), edid
->mfg_id
,
1359 (int)sizeof(edid
->prod_code
), edid
->prod_code
, quirks
);
1363 EXPORT_SYMBOL(drm_dp_get_edid_quirks
);
1366 * drm_dp_read_desc - read sink/branch descriptor from DPCD
1367 * @aux: DisplayPort AUX channel
1368 * @desc: Device decriptor to fill from DPCD
1369 * @is_branch: true for branch devices, false for sink devices
1371 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1374 * Returns 0 on success or a negative error code on failure.
1376 int drm_dp_read_desc(struct drm_dp_aux
*aux
, struct drm_dp_desc
*desc
,
1379 struct drm_dp_dpcd_ident
*ident
= &desc
->ident
;
1380 unsigned int offset
= is_branch
? DP_BRANCH_OUI
: DP_SINK_OUI
;
1381 int ret
, dev_id_len
;
1383 ret
= drm_dp_dpcd_read(aux
, offset
, ident
, sizeof(*ident
));
1387 desc
->quirks
= drm_dp_get_quirks(ident
, is_branch
);
1389 dev_id_len
= strnlen(ident
->device_id
, sizeof(ident
->device_id
));
1391 DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
1392 is_branch
? "branch" : "sink",
1393 (int)sizeof(ident
->oui
), ident
->oui
,
1394 dev_id_len
, ident
->device_id
,
1395 ident
->hw_rev
>> 4, ident
->hw_rev
& 0xf,
1396 ident
->sw_major_rev
, ident
->sw_minor_rev
,
1401 EXPORT_SYMBOL(drm_dp_read_desc
);
1404 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
1405 * supported by the DSC sink.
1406 * @dsc_dpcd: DSC capabilities from DPCD
1407 * @is_edp: true if its eDP, false for DP
1409 * Read the slice capabilities DPCD register from DSC sink to get
1410 * the maximum slice count supported. This is used to populate
1411 * the DSC parameters in the &struct drm_dsc_config by the driver.
1412 * Driver creates an infoframe using these parameters to populate
1413 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1414 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1417 * Maximum slice count supported by DSC sink or 0 its invalid
1419 u8
drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
],
1422 u8 slice_cap1
= dsc_dpcd
[DP_DSC_SLICE_CAP_1
- DP_DSC_SUPPORT
];
1425 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
1426 if (slice_cap1
& DP_DSC_4_PER_DP_DSC_SINK
)
1428 if (slice_cap1
& DP_DSC_2_PER_DP_DSC_SINK
)
1430 if (slice_cap1
& DP_DSC_1_PER_DP_DSC_SINK
)
1433 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
1434 u8 slice_cap2
= dsc_dpcd
[DP_DSC_SLICE_CAP_2
- DP_DSC_SUPPORT
];
1436 if (slice_cap2
& DP_DSC_24_PER_DP_DSC_SINK
)
1438 if (slice_cap2
& DP_DSC_20_PER_DP_DSC_SINK
)
1440 if (slice_cap2
& DP_DSC_16_PER_DP_DSC_SINK
)
1442 if (slice_cap1
& DP_DSC_12_PER_DP_DSC_SINK
)
1444 if (slice_cap1
& DP_DSC_10_PER_DP_DSC_SINK
)
1446 if (slice_cap1
& DP_DSC_8_PER_DP_DSC_SINK
)
1448 if (slice_cap1
& DP_DSC_6_PER_DP_DSC_SINK
)
1450 if (slice_cap1
& DP_DSC_4_PER_DP_DSC_SINK
)
1452 if (slice_cap1
& DP_DSC_2_PER_DP_DSC_SINK
)
1454 if (slice_cap1
& DP_DSC_1_PER_DP_DSC_SINK
)
1460 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count
);
1463 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
1464 * @dsc_dpcd: DSC capabilities from DPCD
1466 * Read the DSC DPCD register to parse the line buffer depth in bits which is
1467 * number of bits of precision within the decoder line buffer supported by
1468 * the DSC sink. This is used to populate the DSC parameters in the
1469 * &struct drm_dsc_config by the driver.
1470 * Driver creates an infoframe using these parameters to populate
1471 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1472 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1475 * Line buffer depth supported by DSC panel or 0 its invalid
1477 u8
drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
])
1479 u8 line_buf_depth
= dsc_dpcd
[DP_DSC_LINE_BUF_BIT_DEPTH
- DP_DSC_SUPPORT
];
1481 switch (line_buf_depth
& DP_DSC_LINE_BUF_BIT_DEPTH_MASK
) {
1482 case DP_DSC_LINE_BUF_BIT_DEPTH_9
:
1484 case DP_DSC_LINE_BUF_BIT_DEPTH_10
:
1486 case DP_DSC_LINE_BUF_BIT_DEPTH_11
:
1488 case DP_DSC_LINE_BUF_BIT_DEPTH_12
:
1490 case DP_DSC_LINE_BUF_BIT_DEPTH_13
:
1492 case DP_DSC_LINE_BUF_BIT_DEPTH_14
:
1494 case DP_DSC_LINE_BUF_BIT_DEPTH_15
:
1496 case DP_DSC_LINE_BUF_BIT_DEPTH_16
:
1498 case DP_DSC_LINE_BUF_BIT_DEPTH_8
:
1504 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth
);
1507 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
1508 * values supported by the DSC sink.
1509 * @dsc_dpcd: DSC capabilities from DPCD
1510 * @dsc_bpc: An array to be filled by this helper with supported
1513 * Read the DSC DPCD from the sink device to parse the supported bits per
1514 * component values. This is used to populate the DSC parameters
1515 * in the &struct drm_dsc_config by the driver.
1516 * Driver creates an infoframe using these parameters to populate
1517 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1518 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1521 * Number of input BPC values parsed from the DPCD
1523 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
],
1527 u8 color_depth
= dsc_dpcd
[DP_DSC_DEC_COLOR_DEPTH_CAP
- DP_DSC_SUPPORT
];
1529 if (color_depth
& DP_DSC_12_BPC
)
1530 dsc_bpc
[num_bpc
++] = 12;
1531 if (color_depth
& DP_DSC_10_BPC
)
1532 dsc_bpc
[num_bpc
++] = 10;
1533 if (color_depth
& DP_DSC_8_BPC
)
1534 dsc_bpc
[num_bpc
++] = 8;
1538 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs
);
1541 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
1542 * @aux: DisplayPort AUX channel
1543 * @data: DP phy compliance test parameters.
1545 * Returns 0 on success or a negative error code on failure.
1547 int drm_dp_get_phy_test_pattern(struct drm_dp_aux
*aux
,
1548 struct drm_dp_phy_test_params
*data
)
1553 err
= drm_dp_dpcd_readb(aux
, DP_TEST_LINK_RATE
, &rate
);
1556 data
->link_rate
= drm_dp_bw_code_to_link_rate(rate
);
1558 err
= drm_dp_dpcd_readb(aux
, DP_TEST_LANE_COUNT
, &lanes
);
1561 data
->num_lanes
= lanes
& DP_MAX_LANE_COUNT_MASK
;
1563 if (lanes
& DP_ENHANCED_FRAME_CAP
)
1564 data
->enhanced_frame_cap
= true;
1566 err
= drm_dp_dpcd_readb(aux
, DP_PHY_TEST_PATTERN
, &data
->phy_pattern
);
1570 switch (data
->phy_pattern
) {
1571 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM
:
1572 err
= drm_dp_dpcd_read(aux
, DP_TEST_80BIT_CUSTOM_PATTERN_7_0
,
1573 &data
->custom80
, sizeof(data
->custom80
));
1578 case DP_PHY_TEST_PATTERN_CP2520
:
1579 err
= drm_dp_dpcd_read(aux
, DP_TEST_HBR2_SCRAMBLER_RESET
,
1581 sizeof(data
->hbr2_reset
));
1588 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern
);
1591 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
1592 * @aux: DisplayPort AUX channel
1593 * @data: DP phy compliance test parameters.
1595 * Returns 0 on success or a negative error code on failure.
1597 int drm_dp_set_phy_test_pattern(struct drm_dp_aux
*aux
,
1598 struct drm_dp_phy_test_params
*data
, u8 dp_rev
)
1604 link_config
[0] = drm_dp_link_rate_to_bw_code(data
->link_rate
);
1605 link_config
[1] = data
->num_lanes
;
1606 if (data
->enhanced_frame_cap
)
1607 link_config
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
1608 err
= drm_dp_dpcd_write(aux
, DP_LINK_BW_SET
, link_config
, 2);
1612 test_pattern
= data
->phy_pattern
;
1613 if (dp_rev
< 0x12) {
1614 test_pattern
= (test_pattern
<< 2) &
1615 DP_LINK_QUAL_PATTERN_11_MASK
;
1616 err
= drm_dp_dpcd_writeb(aux
, DP_TRAINING_PATTERN_SET
,
1621 for (i
= 0; i
< data
->num_lanes
; i
++) {
1622 err
= drm_dp_dpcd_writeb(aux
,
1623 DP_LINK_QUAL_LANE0_SET
+ i
,
1632 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern
);
1634 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat
)
1636 if (pixelformat
< 0 || pixelformat
> DP_PIXELFORMAT_RESERVED
)
1639 switch (pixelformat
) {
1640 case DP_PIXELFORMAT_RGB
:
1642 case DP_PIXELFORMAT_YUV444
:
1644 case DP_PIXELFORMAT_YUV422
:
1646 case DP_PIXELFORMAT_YUV420
:
1648 case DP_PIXELFORMAT_Y_ONLY
:
1650 case DP_PIXELFORMAT_RAW
:
1657 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat
,
1658 enum dp_colorimetry colorimetry
)
1660 if (pixelformat
< 0 || pixelformat
> DP_PIXELFORMAT_RESERVED
)
1663 switch (colorimetry
) {
1664 case DP_COLORIMETRY_DEFAULT
:
1665 switch (pixelformat
) {
1666 case DP_PIXELFORMAT_RGB
:
1668 case DP_PIXELFORMAT_YUV444
:
1669 case DP_PIXELFORMAT_YUV422
:
1670 case DP_PIXELFORMAT_YUV420
:
1672 case DP_PIXELFORMAT_Y_ONLY
:
1673 return "DICOM PS3.14";
1674 case DP_PIXELFORMAT_RAW
:
1675 return "Custom Color Profile";
1679 case DP_COLORIMETRY_RGB_WIDE_FIXED
: /* and DP_COLORIMETRY_BT709_YCC */
1680 switch (pixelformat
) {
1681 case DP_PIXELFORMAT_RGB
:
1682 return "Wide Fixed";
1683 case DP_PIXELFORMAT_YUV444
:
1684 case DP_PIXELFORMAT_YUV422
:
1685 case DP_PIXELFORMAT_YUV420
:
1690 case DP_COLORIMETRY_RGB_WIDE_FLOAT
: /* and DP_COLORIMETRY_XVYCC_601 */
1691 switch (pixelformat
) {
1692 case DP_PIXELFORMAT_RGB
:
1693 return "Wide Float";
1694 case DP_PIXELFORMAT_YUV444
:
1695 case DP_PIXELFORMAT_YUV422
:
1696 case DP_PIXELFORMAT_YUV420
:
1701 case DP_COLORIMETRY_OPRGB
: /* and DP_COLORIMETRY_XVYCC_709 */
1702 switch (pixelformat
) {
1703 case DP_PIXELFORMAT_RGB
:
1705 case DP_PIXELFORMAT_YUV444
:
1706 case DP_PIXELFORMAT_YUV422
:
1707 case DP_PIXELFORMAT_YUV420
:
1712 case DP_COLORIMETRY_DCI_P3_RGB
: /* and DP_COLORIMETRY_SYCC_601 */
1713 switch (pixelformat
) {
1714 case DP_PIXELFORMAT_RGB
:
1716 case DP_PIXELFORMAT_YUV444
:
1717 case DP_PIXELFORMAT_YUV422
:
1718 case DP_PIXELFORMAT_YUV420
:
1723 case DP_COLORIMETRY_RGB_CUSTOM
: /* and DP_COLORIMETRY_OPYCC_601 */
1724 switch (pixelformat
) {
1725 case DP_PIXELFORMAT_RGB
:
1726 return "Custom Profile";
1727 case DP_PIXELFORMAT_YUV444
:
1728 case DP_PIXELFORMAT_YUV422
:
1729 case DP_PIXELFORMAT_YUV420
:
1734 case DP_COLORIMETRY_BT2020_RGB
: /* and DP_COLORIMETRY_BT2020_CYCC */
1735 switch (pixelformat
) {
1736 case DP_PIXELFORMAT_RGB
:
1737 return "BT.2020 RGB";
1738 case DP_PIXELFORMAT_YUV444
:
1739 case DP_PIXELFORMAT_YUV422
:
1740 case DP_PIXELFORMAT_YUV420
:
1741 return "BT.2020 CYCC";
1745 case DP_COLORIMETRY_BT2020_YCC
:
1746 switch (pixelformat
) {
1747 case DP_PIXELFORMAT_YUV444
:
1748 case DP_PIXELFORMAT_YUV422
:
1749 case DP_PIXELFORMAT_YUV420
:
1750 return "BT.2020 YCC";
1759 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range
)
1761 switch (dynamic_range
) {
1762 case DP_DYNAMIC_RANGE_VESA
:
1763 return "VESA range";
1764 case DP_DYNAMIC_RANGE_CTA
:
1771 static const char *dp_content_type_get_name(enum dp_content_type content_type
)
1773 switch (content_type
) {
1774 case DP_CONTENT_TYPE_NOT_DEFINED
:
1775 return "Not defined";
1776 case DP_CONTENT_TYPE_GRAPHICS
:
1778 case DP_CONTENT_TYPE_PHOTO
:
1780 case DP_CONTENT_TYPE_VIDEO
:
1782 case DP_CONTENT_TYPE_GAME
:
1789 void drm_dp_vsc_sdp_log(const char *level
, struct device
*dev
,
1790 const struct drm_dp_vsc_sdp
*vsc
)
1792 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
1793 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
1794 vsc
->revision
, vsc
->length
);
1795 DP_SDP_LOG(" pixelformat: %s\n",
1796 dp_pixelformat_get_name(vsc
->pixelformat
));
1797 DP_SDP_LOG(" colorimetry: %s\n",
1798 dp_colorimetry_get_name(vsc
->pixelformat
, vsc
->colorimetry
));
1799 DP_SDP_LOG(" bpc: %u\n", vsc
->bpc
);
1800 DP_SDP_LOG(" dynamic range: %s\n",
1801 dp_dynamic_range_get_name(vsc
->dynamic_range
));
1802 DP_SDP_LOG(" content type: %s\n",
1803 dp_content_type_get_name(vsc
->content_type
));
1806 EXPORT_SYMBOL(drm_dp_vsc_sdp_log
);