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Merge tag 'drm-misc-fixes-2017-11-20' of git://anongit.freedesktop.org/drm/drm-misc...
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / drm_edid.c
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
36 #include <drm/drmP.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
41
42 #include "drm_crtc_internal.h"
43
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
47
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
51
52 /*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
77 /* Force 8bpc */
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
79 /* Force 12bpc */
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
81 /* Force 6bpc */
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
83 /* Force 10bpc */
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
87
88 struct detailed_mode_closure {
89 struct drm_connector *connector;
90 struct edid *edid;
91 bool preferred;
92 u32 quirks;
93 int modes;
94 };
95
96 #define LEVEL_DMT 0
97 #define LEVEL_GTF 1
98 #define LEVEL_GTF2 2
99 #define LEVEL_CVT 3
100
101 static const struct edid_quirk {
102 char vendor[4];
103 int product_id;
104 u32 quirks;
105 } edid_quirk_list[] = {
106 /* Acer AL1706 */
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
108 /* Acer F51 */
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
110 /* Unknown Acer */
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
112
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115
116 /* Belinea 10 15 55 */
117 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
118 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
119
120 /* Envision Peripherals, Inc. EN-7100e */
121 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
122 /* Envision EN2028 */
123 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
124
125 /* Funai Electronics PM36B */
126 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
127 EDID_QUIRK_DETAILED_IN_CM },
128
129 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
130 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
131
132 /* LG Philips LCD LP154W01-A5 */
133 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
134 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
135
136 /* Philips 107p5 CRT */
137 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
138
139 /* Proview AY765C */
140 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
141
142 /* Samsung SyncMaster 205BW. Note: irony */
143 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
144 /* Samsung SyncMaster 22[5-6]BW */
145 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
146 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
147
148 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
149 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
150
151 /* ViewSonic VA2026w */
152 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
153
154 /* Medion MD 30217 PG */
155 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
156
157 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
158 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
159
160 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
161 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
162
163 /* HTC Vive VR Headset */
164 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
165 };
166
167 /*
168 * Autogenerated from the DMT spec.
169 * This table is copied from xfree86/modes/xf86EdidModes.c.
170 */
171 static const struct drm_display_mode drm_dmt_modes[] = {
172 /* 0x01 - 640x350@85Hz */
173 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
174 736, 832, 0, 350, 382, 385, 445, 0,
175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
176 /* 0x02 - 640x400@85Hz */
177 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
178 736, 832, 0, 400, 401, 404, 445, 0,
179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
180 /* 0x03 - 720x400@85Hz */
181 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
182 828, 936, 0, 400, 401, 404, 446, 0,
183 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
184 /* 0x04 - 640x480@60Hz */
185 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
186 752, 800, 0, 480, 490, 492, 525, 0,
187 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
188 /* 0x05 - 640x480@72Hz */
189 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
190 704, 832, 0, 480, 489, 492, 520, 0,
191 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
192 /* 0x06 - 640x480@75Hz */
193 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
194 720, 840, 0, 480, 481, 484, 500, 0,
195 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
196 /* 0x07 - 640x480@85Hz */
197 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
198 752, 832, 0, 480, 481, 484, 509, 0,
199 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
200 /* 0x08 - 800x600@56Hz */
201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
202 896, 1024, 0, 600, 601, 603, 625, 0,
203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
204 /* 0x09 - 800x600@60Hz */
205 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
206 968, 1056, 0, 600, 601, 605, 628, 0,
207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
208 /* 0x0a - 800x600@72Hz */
209 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
210 976, 1040, 0, 600, 637, 643, 666, 0,
211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
212 /* 0x0b - 800x600@75Hz */
213 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
214 896, 1056, 0, 600, 601, 604, 625, 0,
215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
216 /* 0x0c - 800x600@85Hz */
217 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
218 896, 1048, 0, 600, 601, 604, 631, 0,
219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
220 /* 0x0d - 800x600@120Hz RB */
221 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
222 880, 960, 0, 600, 603, 607, 636, 0,
223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
224 /* 0x0e - 848x480@60Hz */
225 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
226 976, 1088, 0, 480, 486, 494, 517, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
228 /* 0x0f - 1024x768@43Hz, interlace */
229 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
230 1208, 1264, 0, 768, 768, 776, 817, 0,
231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
232 DRM_MODE_FLAG_INTERLACE) },
233 /* 0x10 - 1024x768@60Hz */
234 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
235 1184, 1344, 0, 768, 771, 777, 806, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 0x11 - 1024x768@70Hz */
238 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
239 1184, 1328, 0, 768, 771, 777, 806, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
241 /* 0x12 - 1024x768@75Hz */
242 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
243 1136, 1312, 0, 768, 769, 772, 800, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 0x13 - 1024x768@85Hz */
246 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
247 1168, 1376, 0, 768, 769, 772, 808, 0,
248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 0x14 - 1024x768@120Hz RB */
250 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
251 1104, 1184, 0, 768, 771, 775, 813, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x15 - 1152x864@75Hz */
254 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
255 1344, 1600, 0, 864, 865, 868, 900, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x55 - 1280x720@60Hz */
258 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
259 1430, 1650, 0, 720, 725, 730, 750, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 0x16 - 1280x768@60Hz RB */
262 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
263 1360, 1440, 0, 768, 771, 778, 790, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
265 /* 0x17 - 1280x768@60Hz */
266 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
267 1472, 1664, 0, 768, 771, 778, 798, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x18 - 1280x768@75Hz */
270 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
271 1488, 1696, 0, 768, 771, 778, 805, 0,
272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x19 - 1280x768@85Hz */
274 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
275 1496, 1712, 0, 768, 771, 778, 809, 0,
276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x1a - 1280x768@120Hz RB */
278 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
279 1360, 1440, 0, 768, 771, 778, 813, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
281 /* 0x1b - 1280x800@60Hz RB */
282 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
283 1360, 1440, 0, 800, 803, 809, 823, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
285 /* 0x1c - 1280x800@60Hz */
286 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
287 1480, 1680, 0, 800, 803, 809, 831, 0,
288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x1d - 1280x800@75Hz */
290 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
291 1488, 1696, 0, 800, 803, 809, 838, 0,
292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
293 /* 0x1e - 1280x800@85Hz */
294 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
295 1496, 1712, 0, 800, 803, 809, 843, 0,
296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 0x1f - 1280x800@120Hz RB */
298 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
299 1360, 1440, 0, 800, 803, 809, 847, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
301 /* 0x20 - 1280x960@60Hz */
302 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
303 1488, 1800, 0, 960, 961, 964, 1000, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
305 /* 0x21 - 1280x960@85Hz */
306 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
307 1504, 1728, 0, 960, 961, 964, 1011, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
309 /* 0x22 - 1280x960@120Hz RB */
310 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
311 1360, 1440, 0, 960, 963, 967, 1017, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
313 /* 0x23 - 1280x1024@60Hz */
314 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
315 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
317 /* 0x24 - 1280x1024@75Hz */
318 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
319 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 0x25 - 1280x1024@85Hz */
322 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
323 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 0x26 - 1280x1024@120Hz RB */
326 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
327 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
329 /* 0x27 - 1360x768@60Hz */
330 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
331 1536, 1792, 0, 768, 771, 777, 795, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x28 - 1360x768@120Hz RB */
334 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
335 1440, 1520, 0, 768, 771, 776, 813, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x51 - 1366x768@60Hz */
338 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
339 1579, 1792, 0, 768, 771, 774, 798, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x56 - 1366x768@60Hz */
342 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
343 1436, 1500, 0, 768, 769, 772, 800, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x29 - 1400x1050@60Hz RB */
346 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
347 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
349 /* 0x2a - 1400x1050@60Hz */
350 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
351 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 0x2b - 1400x1050@75Hz */
354 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
355 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x2c - 1400x1050@85Hz */
358 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
359 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x2d - 1400x1050@120Hz RB */
362 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
363 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x2e - 1440x900@60Hz RB */
366 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
367 1520, 1600, 0, 900, 903, 909, 926, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
369 /* 0x2f - 1440x900@60Hz */
370 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
371 1672, 1904, 0, 900, 903, 909, 934, 0,
372 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x30 - 1440x900@75Hz */
374 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
375 1688, 1936, 0, 900, 903, 909, 942, 0,
376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x31 - 1440x900@85Hz */
378 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
379 1696, 1952, 0, 900, 903, 909, 948, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x32 - 1440x900@120Hz RB */
382 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
383 1520, 1600, 0, 900, 903, 909, 953, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
385 /* 0x53 - 1600x900@60Hz */
386 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
387 1704, 1800, 0, 900, 901, 904, 1000, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x33 - 1600x1200@60Hz */
390 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
391 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x34 - 1600x1200@65Hz */
394 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
395 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
397 /* 0x35 - 1600x1200@70Hz */
398 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
399 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 0x36 - 1600x1200@75Hz */
402 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
403 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x37 - 1600x1200@85Hz */
406 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
407 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x38 - 1600x1200@120Hz RB */
410 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
411 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
413 /* 0x39 - 1680x1050@60Hz RB */
414 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
415 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
417 /* 0x3a - 1680x1050@60Hz */
418 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
419 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
421 /* 0x3b - 1680x1050@75Hz */
422 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
423 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x3c - 1680x1050@85Hz */
426 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
427 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x3d - 1680x1050@120Hz RB */
430 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
431 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
433 /* 0x3e - 1792x1344@60Hz */
434 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
435 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 0x3f - 1792x1344@75Hz */
438 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
439 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 0x40 - 1792x1344@120Hz RB */
442 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
443 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
445 /* 0x41 - 1856x1392@60Hz */
446 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
447 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x42 - 1856x1392@75Hz */
450 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
451 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 0x43 - 1856x1392@120Hz RB */
454 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
455 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
457 /* 0x52 - 1920x1080@60Hz */
458 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
459 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
461 /* 0x44 - 1920x1200@60Hz RB */
462 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
463 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
465 /* 0x45 - 1920x1200@60Hz */
466 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
467 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
469 /* 0x46 - 1920x1200@75Hz */
470 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
471 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x47 - 1920x1200@85Hz */
474 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
475 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x48 - 1920x1200@120Hz RB */
478 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
479 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
481 /* 0x49 - 1920x1440@60Hz */
482 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
483 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
485 /* 0x4a - 1920x1440@75Hz */
486 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
487 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x4b - 1920x1440@120Hz RB */
490 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
491 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
493 /* 0x54 - 2048x1152@60Hz */
494 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
495 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
497 /* 0x4c - 2560x1600@60Hz RB */
498 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
499 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
501 /* 0x4d - 2560x1600@60Hz */
502 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
503 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x4e - 2560x1600@75Hz */
506 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
507 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
509 /* 0x4f - 2560x1600@85Hz */
510 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
511 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 0x50 - 2560x1600@120Hz RB */
514 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
515 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x57 - 4096x2160@60Hz RB */
518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
519 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
521 /* 0x58 - 4096x2160@59.94Hz RB */
522 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
523 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
525 };
526
527 /*
528 * These more or less come from the DMT spec. The 720x400 modes are
529 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
530 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
531 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
532 * mode.
533 *
534 * The DMT modes have been fact-checked; the rest are mild guesses.
535 */
536 static const struct drm_display_mode edid_est_modes[] = {
537 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
538 968, 1056, 0, 600, 601, 605, 628, 0,
539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
540 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
541 896, 1024, 0, 600, 601, 603, 625, 0,
542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
543 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
544 720, 840, 0, 480, 481, 484, 500, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
546 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
547 704, 832, 0, 480, 489, 492, 520, 0,
548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
549 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
550 768, 864, 0, 480, 483, 486, 525, 0,
551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
552 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
553 752, 800, 0, 480, 490, 492, 525, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
555 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
556 846, 900, 0, 400, 421, 423, 449, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
558 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
559 846, 900, 0, 400, 412, 414, 449, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
561 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
562 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
564 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
565 1136, 1312, 0, 768, 769, 772, 800, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
567 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
568 1184, 1328, 0, 768, 771, 777, 806, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
570 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
571 1184, 1344, 0, 768, 771, 777, 806, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
573 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
574 1208, 1264, 0, 768, 768, 776, 817, 0,
575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
576 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
577 928, 1152, 0, 624, 625, 628, 667, 0,
578 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
579 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
580 896, 1056, 0, 600, 601, 604, 625, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
582 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
583 976, 1040, 0, 600, 637, 643, 666, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
585 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
586 1344, 1600, 0, 864, 865, 868, 900, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
588 };
589
590 struct minimode {
591 short w;
592 short h;
593 short r;
594 short rb;
595 };
596
597 static const struct minimode est3_modes[] = {
598 /* byte 6 */
599 { 640, 350, 85, 0 },
600 { 640, 400, 85, 0 },
601 { 720, 400, 85, 0 },
602 { 640, 480, 85, 0 },
603 { 848, 480, 60, 0 },
604 { 800, 600, 85, 0 },
605 { 1024, 768, 85, 0 },
606 { 1152, 864, 75, 0 },
607 /* byte 7 */
608 { 1280, 768, 60, 1 },
609 { 1280, 768, 60, 0 },
610 { 1280, 768, 75, 0 },
611 { 1280, 768, 85, 0 },
612 { 1280, 960, 60, 0 },
613 { 1280, 960, 85, 0 },
614 { 1280, 1024, 60, 0 },
615 { 1280, 1024, 85, 0 },
616 /* byte 8 */
617 { 1360, 768, 60, 0 },
618 { 1440, 900, 60, 1 },
619 { 1440, 900, 60, 0 },
620 { 1440, 900, 75, 0 },
621 { 1440, 900, 85, 0 },
622 { 1400, 1050, 60, 1 },
623 { 1400, 1050, 60, 0 },
624 { 1400, 1050, 75, 0 },
625 /* byte 9 */
626 { 1400, 1050, 85, 0 },
627 { 1680, 1050, 60, 1 },
628 { 1680, 1050, 60, 0 },
629 { 1680, 1050, 75, 0 },
630 { 1680, 1050, 85, 0 },
631 { 1600, 1200, 60, 0 },
632 { 1600, 1200, 65, 0 },
633 { 1600, 1200, 70, 0 },
634 /* byte 10 */
635 { 1600, 1200, 75, 0 },
636 { 1600, 1200, 85, 0 },
637 { 1792, 1344, 60, 0 },
638 { 1792, 1344, 75, 0 },
639 { 1856, 1392, 60, 0 },
640 { 1856, 1392, 75, 0 },
641 { 1920, 1200, 60, 1 },
642 { 1920, 1200, 60, 0 },
643 /* byte 11 */
644 { 1920, 1200, 75, 0 },
645 { 1920, 1200, 85, 0 },
646 { 1920, 1440, 60, 0 },
647 { 1920, 1440, 75, 0 },
648 };
649
650 static const struct minimode extra_modes[] = {
651 { 1024, 576, 60, 0 },
652 { 1366, 768, 60, 0 },
653 { 1600, 900, 60, 0 },
654 { 1680, 945, 60, 0 },
655 { 1920, 1080, 60, 0 },
656 { 2048, 1152, 60, 0 },
657 { 2048, 1536, 60, 0 },
658 };
659
660 /*
661 * Probably taken from CEA-861 spec.
662 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
663 *
664 * Index using the VIC.
665 */
666 static const struct drm_display_mode edid_cea_modes[] = {
667 /* 0 - dummy, VICs start at 1 */
668 { },
669 /* 1 - 640x480@60Hz */
670 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
671 752, 800, 0, 480, 490, 492, 525, 0,
672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
674 /* 2 - 720x480@60Hz */
675 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
676 798, 858, 0, 480, 489, 495, 525, 0,
677 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
678 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
679 /* 3 - 720x480@60Hz */
680 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
681 798, 858, 0, 480, 489, 495, 525, 0,
682 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
684 /* 4 - 1280x720@60Hz */
685 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
686 1430, 1650, 0, 720, 725, 730, 750, 0,
687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
688 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
689 /* 5 - 1920x1080i@60Hz */
690 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
691 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
693 DRM_MODE_FLAG_INTERLACE),
694 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
695 /* 6 - 720(1440)x480i@60Hz */
696 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
697 801, 858, 0, 480, 488, 494, 525, 0,
698 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
699 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
700 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
701 /* 7 - 720(1440)x480i@60Hz */
702 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
703 801, 858, 0, 480, 488, 494, 525, 0,
704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
705 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
706 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
707 /* 8 - 720(1440)x240@60Hz */
708 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
709 801, 858, 0, 240, 244, 247, 262, 0,
710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
711 DRM_MODE_FLAG_DBLCLK),
712 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
713 /* 9 - 720(1440)x240@60Hz */
714 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
715 801, 858, 0, 240, 244, 247, 262, 0,
716 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
717 DRM_MODE_FLAG_DBLCLK),
718 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
719 /* 10 - 2880x480i@60Hz */
720 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
721 3204, 3432, 0, 480, 488, 494, 525, 0,
722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
723 DRM_MODE_FLAG_INTERLACE),
724 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
725 /* 11 - 2880x480i@60Hz */
726 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
727 3204, 3432, 0, 480, 488, 494, 525, 0,
728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
729 DRM_MODE_FLAG_INTERLACE),
730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
731 /* 12 - 2880x240@60Hz */
732 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
733 3204, 3432, 0, 240, 244, 247, 262, 0,
734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
736 /* 13 - 2880x240@60Hz */
737 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
738 3204, 3432, 0, 240, 244, 247, 262, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741 /* 14 - 1440x480@60Hz */
742 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
743 1596, 1716, 0, 480, 489, 495, 525, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 15 - 1440x480@60Hz */
747 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
748 1596, 1716, 0, 480, 489, 495, 525, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
751 /* 16 - 1920x1080@60Hz */
752 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
753 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 17 - 720x576@50Hz */
757 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
758 796, 864, 0, 576, 581, 586, 625, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
760 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
761 /* 18 - 720x576@50Hz */
762 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
763 796, 864, 0, 576, 581, 586, 625, 0,
764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
765 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
766 /* 19 - 1280x720@50Hz */
767 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
768 1760, 1980, 0, 720, 725, 730, 750, 0,
769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
770 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
771 /* 20 - 1920x1080i@50Hz */
772 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
773 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
774 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
775 DRM_MODE_FLAG_INTERLACE),
776 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
777 /* 21 - 720(1440)x576i@50Hz */
778 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
779 795, 864, 0, 576, 580, 586, 625, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
781 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
782 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
783 /* 22 - 720(1440)x576i@50Hz */
784 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
785 795, 864, 0, 576, 580, 586, 625, 0,
786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
787 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
788 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
789 /* 23 - 720(1440)x288@50Hz */
790 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
791 795, 864, 0, 288, 290, 293, 312, 0,
792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
793 DRM_MODE_FLAG_DBLCLK),
794 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
795 /* 24 - 720(1440)x288@50Hz */
796 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
797 795, 864, 0, 288, 290, 293, 312, 0,
798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
799 DRM_MODE_FLAG_DBLCLK),
800 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
801 /* 25 - 2880x576i@50Hz */
802 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
803 3180, 3456, 0, 576, 580, 586, 625, 0,
804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
805 DRM_MODE_FLAG_INTERLACE),
806 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
807 /* 26 - 2880x576i@50Hz */
808 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
809 3180, 3456, 0, 576, 580, 586, 625, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
811 DRM_MODE_FLAG_INTERLACE),
812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
813 /* 27 - 2880x288@50Hz */
814 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
815 3180, 3456, 0, 288, 290, 293, 312, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
818 /* 28 - 2880x288@50Hz */
819 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
820 3180, 3456, 0, 288, 290, 293, 312, 0,
821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 29 - 1440x576@50Hz */
824 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
825 1592, 1728, 0, 576, 581, 586, 625, 0,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
828 /* 30 - 1440x576@50Hz */
829 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
830 1592, 1728, 0, 576, 581, 586, 625, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 31 - 1920x1080@50Hz */
834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
835 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 32 - 1920x1080@24Hz */
839 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
840 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
842 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 33 - 1920x1080@25Hz */
844 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
845 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
847 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
848 /* 34 - 1920x1080@30Hz */
849 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
850 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
852 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
853 /* 35 - 2880x480@60Hz */
854 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
855 3192, 3432, 0, 480, 489, 495, 525, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
857 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
858 /* 36 - 2880x480@60Hz */
859 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
860 3192, 3432, 0, 480, 489, 495, 525, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
862 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 37 - 2880x576@50Hz */
864 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
865 3184, 3456, 0, 576, 581, 586, 625, 0,
866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
868 /* 38 - 2880x576@50Hz */
869 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
870 3184, 3456, 0, 576, 581, 586, 625, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
872 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 39 - 1920x1080i@50Hz */
874 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
875 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
876 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
877 DRM_MODE_FLAG_INTERLACE),
878 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
879 /* 40 - 1920x1080i@100Hz */
880 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
881 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
883 DRM_MODE_FLAG_INTERLACE),
884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
885 /* 41 - 1280x720@100Hz */
886 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
887 1760, 1980, 0, 720, 725, 730, 750, 0,
888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
889 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890 /* 42 - 720x576@100Hz */
891 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
892 796, 864, 0, 576, 581, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
895 /* 43 - 720x576@100Hz */
896 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
897 796, 864, 0, 576, 581, 586, 625, 0,
898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
899 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 44 - 720(1440)x576i@100Hz */
901 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
902 795, 864, 0, 576, 580, 586, 625, 0,
903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
904 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
905 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
906 /* 45 - 720(1440)x576i@100Hz */
907 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
908 795, 864, 0, 576, 580, 586, 625, 0,
909 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
910 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
911 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912 /* 46 - 1920x1080i@120Hz */
913 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
914 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
916 DRM_MODE_FLAG_INTERLACE),
917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
918 /* 47 - 1280x720@120Hz */
919 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
920 1430, 1650, 0, 720, 725, 730, 750, 0,
921 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
922 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 48 - 720x480@120Hz */
924 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
925 798, 858, 0, 480, 489, 495, 525, 0,
926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
928 /* 49 - 720x480@120Hz */
929 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
930 798, 858, 0, 480, 489, 495, 525, 0,
931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
932 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
933 /* 50 - 720(1440)x480i@120Hz */
934 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
935 801, 858, 0, 480, 488, 494, 525, 0,
936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
937 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
938 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
939 /* 51 - 720(1440)x480i@120Hz */
940 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
941 801, 858, 0, 480, 488, 494, 525, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
943 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
944 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 52 - 720x576@200Hz */
946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
947 796, 864, 0, 576, 581, 586, 625, 0,
948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
949 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
950 /* 53 - 720x576@200Hz */
951 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
952 796, 864, 0, 576, 581, 586, 625, 0,
953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
954 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955 /* 54 - 720(1440)x576i@200Hz */
956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
957 795, 864, 0, 576, 580, 586, 625, 0,
958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
960 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
961 /* 55 - 720(1440)x576i@200Hz */
962 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
963 795, 864, 0, 576, 580, 586, 625, 0,
964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
965 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
966 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967 /* 56 - 720x480@240Hz */
968 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
969 798, 858, 0, 480, 489, 495, 525, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
971 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
972 /* 57 - 720x480@240Hz */
973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
974 798, 858, 0, 480, 489, 495, 525, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
976 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
977 /* 58 - 720(1440)x480i@240Hz */
978 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
979 801, 858, 0, 480, 488, 494, 525, 0,
980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
981 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
982 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
983 /* 59 - 720(1440)x480i@240Hz */
984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
985 801, 858, 0, 480, 488, 494, 525, 0,
986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
988 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
989 /* 60 - 1280x720@24Hz */
990 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
991 3080, 3300, 0, 720, 725, 730, 750, 0,
992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
993 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
994 /* 61 - 1280x720@25Hz */
995 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
996 3740, 3960, 0, 720, 725, 730, 750, 0,
997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
998 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 62 - 1280x720@30Hz */
1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1001 3080, 3300, 0, 720, 725, 730, 750, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 63 - 1920x1080@120Hz */
1005 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1006 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1008 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1009 /* 64 - 1920x1080@100Hz */
1010 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1011 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1013 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 65 - 1280x720@24Hz */
1015 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1016 3080, 3300, 0, 720, 725, 730, 750, 0,
1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1019 /* 66 - 1280x720@25Hz */
1020 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1021 3740, 3960, 0, 720, 725, 730, 750, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1024 /* 67 - 1280x720@30Hz */
1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1026 3080, 3300, 0, 720, 725, 730, 750, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1029 /* 68 - 1280x720@50Hz */
1030 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1031 1760, 1980, 0, 720, 725, 730, 750, 0,
1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1033 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1034 /* 69 - 1280x720@60Hz */
1035 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1036 1430, 1650, 0, 720, 725, 730, 750, 0,
1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1038 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1039 /* 70 - 1280x720@100Hz */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1041 1760, 1980, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1044 /* 71 - 1280x720@120Hz */
1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1046 1430, 1650, 0, 720, 725, 730, 750, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1049 /* 72 - 1920x1080@24Hz */
1050 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1051 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1054 /* 73 - 1920x1080@25Hz */
1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1056 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1059 /* 74 - 1920x1080@30Hz */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1061 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1064 /* 75 - 1920x1080@50Hz */
1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1066 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 76 - 1920x1080@60Hz */
1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1071 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 77 - 1920x1080@100Hz */
1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1076 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 78 - 1920x1080@120Hz */
1080 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1081 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 79 - 1680x720@24Hz */
1085 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1086 3080, 3300, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 80 - 1680x720@25Hz */
1090 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1091 2948, 3168, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 81 - 1680x720@30Hz */
1095 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1096 2420, 2640, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 82 - 1680x720@50Hz */
1100 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1101 1980, 2200, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 83 - 1680x720@60Hz */
1105 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1106 1980, 2200, 0, 720, 725, 730, 750, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 84 - 1680x720@100Hz */
1110 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1111 1780, 2000, 0, 720, 725, 730, 825, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 85 - 1680x720@120Hz */
1115 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1116 1780, 2000, 0, 720, 725, 730, 825, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 86 - 2560x1080@24Hz */
1120 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1121 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 87 - 2560x1080@25Hz */
1125 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1126 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 88 - 2560x1080@30Hz */
1130 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1131 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 89 - 2560x1080@50Hz */
1135 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1136 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 90 - 2560x1080@60Hz */
1140 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1141 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 91 - 2560x1080@100Hz */
1145 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1146 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 92 - 2560x1080@120Hz */
1150 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1151 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 93 - 3840x2160p@24Hz 16:9 */
1155 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1156 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1159 /* 94 - 3840x2160p@25Hz 16:9 */
1160 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1161 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1164 /* 95 - 3840x2160p@30Hz 16:9 */
1165 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1166 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1169 /* 96 - 3840x2160p@50Hz 16:9 */
1170 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1171 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1174 /* 97 - 3840x2160p@60Hz 16:9 */
1175 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1176 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1179 /* 98 - 4096x2160p@24Hz 256:135 */
1180 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1181 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1184 /* 99 - 4096x2160p@25Hz 256:135 */
1185 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1186 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1189 /* 100 - 4096x2160p@30Hz 256:135 */
1190 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1191 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1194 /* 101 - 4096x2160p@50Hz 256:135 */
1195 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1196 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1199 /* 102 - 4096x2160p@60Hz 256:135 */
1200 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1201 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1204 /* 103 - 3840x2160p@24Hz 64:27 */
1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1209 /* 104 - 3840x2160p@25Hz 64:27 */
1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1214 /* 105 - 3840x2160p@30Hz 64:27 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1219 /* 106 - 3840x2160p@50Hz 64:27 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1224 /* 107 - 3840x2160p@60Hz 64:27 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1229 };
1230
1231 /*
1232 * HDMI 1.4 4k modes. Index using the VIC.
1233 */
1234 static const struct drm_display_mode edid_4k_modes[] = {
1235 /* 0 - dummy, VICs start at 1 */
1236 { },
1237 /* 1 - 3840x2160@30Hz */
1238 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1239 3840, 4016, 4104, 4400, 0,
1240 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .vrefresh = 30, },
1243 /* 2 - 3840x2160@25Hz */
1244 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1245 3840, 4896, 4984, 5280, 0,
1246 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .vrefresh = 25, },
1249 /* 3 - 3840x2160@24Hz */
1250 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1251 3840, 5116, 5204, 5500, 0,
1252 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .vrefresh = 24, },
1255 /* 4 - 4096x2160@24Hz (SMPTE) */
1256 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1257 4096, 5116, 5204, 5500, 0,
1258 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .vrefresh = 24, },
1261 };
1262
1263 /*** DDC fetch and block validation ***/
1264
1265 static const u8 edid_header[] = {
1266 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1267 };
1268
1269 /**
1270 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1271 * @raw_edid: pointer to raw base EDID block
1272 *
1273 * Sanity check the header of the base EDID block.
1274 *
1275 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1276 */
1277 int drm_edid_header_is_valid(const u8 *raw_edid)
1278 {
1279 int i, score = 0;
1280
1281 for (i = 0; i < sizeof(edid_header); i++)
1282 if (raw_edid[i] == edid_header[i])
1283 score++;
1284
1285 return score;
1286 }
1287 EXPORT_SYMBOL(drm_edid_header_is_valid);
1288
1289 static int edid_fixup __read_mostly = 6;
1290 module_param_named(edid_fixup, edid_fixup, int, 0400);
1291 MODULE_PARM_DESC(edid_fixup,
1292 "Minimum number of valid EDID header bytes (0-8, default 6)");
1293
1294 static void drm_get_displayid(struct drm_connector *connector,
1295 struct edid *edid);
1296
1297 static int drm_edid_block_checksum(const u8 *raw_edid)
1298 {
1299 int i;
1300 u8 csum = 0;
1301 for (i = 0; i < EDID_LENGTH; i++)
1302 csum += raw_edid[i];
1303
1304 return csum;
1305 }
1306
1307 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1308 {
1309 if (memchr_inv(in_edid, 0, length))
1310 return false;
1311
1312 return true;
1313 }
1314
1315 /**
1316 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1317 * @raw_edid: pointer to raw EDID block
1318 * @block: type of block to validate (0 for base, extension otherwise)
1319 * @print_bad_edid: if true, dump bad EDID blocks to the console
1320 * @edid_corrupt: if true, the header or checksum is invalid
1321 *
1322 * Validate a base or extension EDID block and optionally dump bad blocks to
1323 * the console.
1324 *
1325 * Return: True if the block is valid, false otherwise.
1326 */
1327 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1328 bool *edid_corrupt)
1329 {
1330 u8 csum;
1331 struct edid *edid = (struct edid *)raw_edid;
1332
1333 if (WARN_ON(!raw_edid))
1334 return false;
1335
1336 if (edid_fixup > 8 || edid_fixup < 0)
1337 edid_fixup = 6;
1338
1339 if (block == 0) {
1340 int score = drm_edid_header_is_valid(raw_edid);
1341 if (score == 8) {
1342 if (edid_corrupt)
1343 *edid_corrupt = false;
1344 } else if (score >= edid_fixup) {
1345 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1346 * The corrupt flag needs to be set here otherwise, the
1347 * fix-up code here will correct the problem, the
1348 * checksum is correct and the test fails
1349 */
1350 if (edid_corrupt)
1351 *edid_corrupt = true;
1352 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1353 memcpy(raw_edid, edid_header, sizeof(edid_header));
1354 } else {
1355 if (edid_corrupt)
1356 *edid_corrupt = true;
1357 goto bad;
1358 }
1359 }
1360
1361 csum = drm_edid_block_checksum(raw_edid);
1362 if (csum) {
1363 if (edid_corrupt)
1364 *edid_corrupt = true;
1365
1366 /* allow CEA to slide through, switches mangle this */
1367 if (raw_edid[0] == CEA_EXT) {
1368 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1369 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1370 } else {
1371 if (print_bad_edid)
1372 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1373
1374 goto bad;
1375 }
1376 }
1377
1378 /* per-block-type checks */
1379 switch (raw_edid[0]) {
1380 case 0: /* base */
1381 if (edid->version != 1) {
1382 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1383 goto bad;
1384 }
1385
1386 if (edid->revision > 4)
1387 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1388 break;
1389
1390 default:
1391 break;
1392 }
1393
1394 return true;
1395
1396 bad:
1397 if (print_bad_edid) {
1398 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1399 pr_notice("EDID block is all zeroes\n");
1400 } else {
1401 pr_notice("Raw EDID:\n");
1402 print_hex_dump(KERN_NOTICE,
1403 " \t", DUMP_PREFIX_NONE, 16, 1,
1404 raw_edid, EDID_LENGTH, false);
1405 }
1406 }
1407 return false;
1408 }
1409 EXPORT_SYMBOL(drm_edid_block_valid);
1410
1411 /**
1412 * drm_edid_is_valid - sanity check EDID data
1413 * @edid: EDID data
1414 *
1415 * Sanity-check an entire EDID record (including extensions)
1416 *
1417 * Return: True if the EDID data is valid, false otherwise.
1418 */
1419 bool drm_edid_is_valid(struct edid *edid)
1420 {
1421 int i;
1422 u8 *raw = (u8 *)edid;
1423
1424 if (!edid)
1425 return false;
1426
1427 for (i = 0; i <= edid->extensions; i++)
1428 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1429 return false;
1430
1431 return true;
1432 }
1433 EXPORT_SYMBOL(drm_edid_is_valid);
1434
1435 #define DDC_SEGMENT_ADDR 0x30
1436 /**
1437 * drm_do_probe_ddc_edid() - get EDID information via I2C
1438 * @data: I2C device adapter
1439 * @buf: EDID data buffer to be filled
1440 * @block: 128 byte EDID block to start fetching from
1441 * @len: EDID data buffer length to fetch
1442 *
1443 * Try to fetch EDID information by calling I2C driver functions.
1444 *
1445 * Return: 0 on success or -1 on failure.
1446 */
1447 static int
1448 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1449 {
1450 struct i2c_adapter *adapter = data;
1451 unsigned char start = block * EDID_LENGTH;
1452 unsigned char segment = block >> 1;
1453 unsigned char xfers = segment ? 3 : 2;
1454 int ret, retries = 5;
1455
1456 /*
1457 * The core I2C driver will automatically retry the transfer if the
1458 * adapter reports EAGAIN. However, we find that bit-banging transfers
1459 * are susceptible to errors under a heavily loaded machine and
1460 * generate spurious NAKs and timeouts. Retrying the transfer
1461 * of the individual block a few times seems to overcome this.
1462 */
1463 do {
1464 struct i2c_msg msgs[] = {
1465 {
1466 .addr = DDC_SEGMENT_ADDR,
1467 .flags = 0,
1468 .len = 1,
1469 .buf = &segment,
1470 }, {
1471 .addr = DDC_ADDR,
1472 .flags = 0,
1473 .len = 1,
1474 .buf = &start,
1475 }, {
1476 .addr = DDC_ADDR,
1477 .flags = I2C_M_RD,
1478 .len = len,
1479 .buf = buf,
1480 }
1481 };
1482
1483 /*
1484 * Avoid sending the segment addr to not upset non-compliant
1485 * DDC monitors.
1486 */
1487 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1488
1489 if (ret == -ENXIO) {
1490 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1491 adapter->name);
1492 break;
1493 }
1494 } while (ret != xfers && --retries);
1495
1496 return ret == xfers ? 0 : -1;
1497 }
1498
1499 static void connector_bad_edid(struct drm_connector *connector,
1500 u8 *edid, int num_blocks)
1501 {
1502 int i;
1503
1504 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1505 return;
1506
1507 dev_warn(connector->dev->dev,
1508 "%s: EDID is invalid:\n",
1509 connector->name);
1510 for (i = 0; i < num_blocks; i++) {
1511 u8 *block = edid + i * EDID_LENGTH;
1512 char prefix[20];
1513
1514 if (drm_edid_is_zero(block, EDID_LENGTH))
1515 sprintf(prefix, "\t[%02x] ZERO ", i);
1516 else if (!drm_edid_block_valid(block, i, false, NULL))
1517 sprintf(prefix, "\t[%02x] BAD ", i);
1518 else
1519 sprintf(prefix, "\t[%02x] GOOD ", i);
1520
1521 print_hex_dump(KERN_WARNING,
1522 prefix, DUMP_PREFIX_NONE, 16, 1,
1523 block, EDID_LENGTH, false);
1524 }
1525 }
1526
1527 /**
1528 * drm_do_get_edid - get EDID data using a custom EDID block read function
1529 * @connector: connector we're probing
1530 * @get_edid_block: EDID block read function
1531 * @data: private data passed to the block read function
1532 *
1533 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1534 * exposes a different interface to read EDID blocks this function can be used
1535 * to get EDID data using a custom block read function.
1536 *
1537 * As in the general case the DDC bus is accessible by the kernel at the I2C
1538 * level, drivers must make all reasonable efforts to expose it as an I2C
1539 * adapter and use drm_get_edid() instead of abusing this function.
1540 *
1541 * The EDID may be overridden using debugfs override_edid or firmare EDID
1542 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1543 * order. Having either of them bypasses actual EDID reads.
1544 *
1545 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1546 */
1547 struct edid *drm_do_get_edid(struct drm_connector *connector,
1548 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1549 size_t len),
1550 void *data)
1551 {
1552 int i, j = 0, valid_extensions = 0;
1553 u8 *edid, *new;
1554 struct edid *override = NULL;
1555
1556 if (connector->override_edid)
1557 override = drm_edid_duplicate((const struct edid *)
1558 connector->edid_blob_ptr->data);
1559
1560 if (!override)
1561 override = drm_load_edid_firmware(connector);
1562
1563 if (!IS_ERR_OR_NULL(override))
1564 return override;
1565
1566 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1567 return NULL;
1568
1569 /* base block fetch */
1570 for (i = 0; i < 4; i++) {
1571 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1572 goto out;
1573 if (drm_edid_block_valid(edid, 0, false,
1574 &connector->edid_corrupt))
1575 break;
1576 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1577 connector->null_edid_counter++;
1578 goto carp;
1579 }
1580 }
1581 if (i == 4)
1582 goto carp;
1583
1584 /* if there's no extensions, we're done */
1585 valid_extensions = edid[0x7e];
1586 if (valid_extensions == 0)
1587 return (struct edid *)edid;
1588
1589 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1590 if (!new)
1591 goto out;
1592 edid = new;
1593
1594 for (j = 1; j <= edid[0x7e]; j++) {
1595 u8 *block = edid + j * EDID_LENGTH;
1596
1597 for (i = 0; i < 4; i++) {
1598 if (get_edid_block(data, block, j, EDID_LENGTH))
1599 goto out;
1600 if (drm_edid_block_valid(block, j, false, NULL))
1601 break;
1602 }
1603
1604 if (i == 4)
1605 valid_extensions--;
1606 }
1607
1608 if (valid_extensions != edid[0x7e]) {
1609 u8 *base;
1610
1611 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1612
1613 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1614 edid[0x7e] = valid_extensions;
1615
1616 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1617 if (!new)
1618 goto out;
1619
1620 base = new;
1621 for (i = 0; i <= edid[0x7e]; i++) {
1622 u8 *block = edid + i * EDID_LENGTH;
1623
1624 if (!drm_edid_block_valid(block, i, false, NULL))
1625 continue;
1626
1627 memcpy(base, block, EDID_LENGTH);
1628 base += EDID_LENGTH;
1629 }
1630
1631 kfree(edid);
1632 edid = new;
1633 }
1634
1635 return (struct edid *)edid;
1636
1637 carp:
1638 connector_bad_edid(connector, edid, 1);
1639 out:
1640 kfree(edid);
1641 return NULL;
1642 }
1643 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1644
1645 /**
1646 * drm_probe_ddc() - probe DDC presence
1647 * @adapter: I2C adapter to probe
1648 *
1649 * Return: True on success, false on failure.
1650 */
1651 bool
1652 drm_probe_ddc(struct i2c_adapter *adapter)
1653 {
1654 unsigned char out;
1655
1656 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1657 }
1658 EXPORT_SYMBOL(drm_probe_ddc);
1659
1660 /**
1661 * drm_get_edid - get EDID data, if available
1662 * @connector: connector we're probing
1663 * @adapter: I2C adapter to use for DDC
1664 *
1665 * Poke the given I2C channel to grab EDID data if possible. If found,
1666 * attach it to the connector.
1667 *
1668 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1669 */
1670 struct edid *drm_get_edid(struct drm_connector *connector,
1671 struct i2c_adapter *adapter)
1672 {
1673 struct edid *edid;
1674
1675 if (connector->force == DRM_FORCE_OFF)
1676 return NULL;
1677
1678 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1679 return NULL;
1680
1681 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1682 if (edid)
1683 drm_get_displayid(connector, edid);
1684 return edid;
1685 }
1686 EXPORT_SYMBOL(drm_get_edid);
1687
1688 /**
1689 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1690 * @connector: connector we're probing
1691 * @adapter: I2C adapter to use for DDC
1692 *
1693 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1694 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1695 * switch DDC to the GPU which is retrieving EDID.
1696 *
1697 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1698 */
1699 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1700 struct i2c_adapter *adapter)
1701 {
1702 struct pci_dev *pdev = connector->dev->pdev;
1703 struct edid *edid;
1704
1705 vga_switcheroo_lock_ddc(pdev);
1706 edid = drm_get_edid(connector, adapter);
1707 vga_switcheroo_unlock_ddc(pdev);
1708
1709 return edid;
1710 }
1711 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1712
1713 /**
1714 * drm_edid_duplicate - duplicate an EDID and the extensions
1715 * @edid: EDID to duplicate
1716 *
1717 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1718 */
1719 struct edid *drm_edid_duplicate(const struct edid *edid)
1720 {
1721 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1722 }
1723 EXPORT_SYMBOL(drm_edid_duplicate);
1724
1725 /*** EDID parsing ***/
1726
1727 /**
1728 * edid_vendor - match a string against EDID's obfuscated vendor field
1729 * @edid: EDID to match
1730 * @vendor: vendor string
1731 *
1732 * Returns true if @vendor is in @edid, false otherwise
1733 */
1734 static bool edid_vendor(struct edid *edid, const char *vendor)
1735 {
1736 char edid_vendor[3];
1737
1738 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1739 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1740 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1741 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1742
1743 return !strncmp(edid_vendor, vendor, 3);
1744 }
1745
1746 /**
1747 * edid_get_quirks - return quirk flags for a given EDID
1748 * @edid: EDID to process
1749 *
1750 * This tells subsequent routines what fixes they need to apply.
1751 */
1752 static u32 edid_get_quirks(struct edid *edid)
1753 {
1754 const struct edid_quirk *quirk;
1755 int i;
1756
1757 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1758 quirk = &edid_quirk_list[i];
1759
1760 if (edid_vendor(edid, quirk->vendor) &&
1761 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1762 return quirk->quirks;
1763 }
1764
1765 return 0;
1766 }
1767
1768 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1769 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1770
1771 /**
1772 * edid_fixup_preferred - set preferred modes based on quirk list
1773 * @connector: has mode list to fix up
1774 * @quirks: quirks list
1775 *
1776 * Walk the mode list for @connector, clearing the preferred status
1777 * on existing modes and setting it anew for the right mode ala @quirks.
1778 */
1779 static void edid_fixup_preferred(struct drm_connector *connector,
1780 u32 quirks)
1781 {
1782 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1783 int target_refresh = 0;
1784 int cur_vrefresh, preferred_vrefresh;
1785
1786 if (list_empty(&connector->probed_modes))
1787 return;
1788
1789 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1790 target_refresh = 60;
1791 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1792 target_refresh = 75;
1793
1794 preferred_mode = list_first_entry(&connector->probed_modes,
1795 struct drm_display_mode, head);
1796
1797 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1798 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1799
1800 if (cur_mode == preferred_mode)
1801 continue;
1802
1803 /* Largest mode is preferred */
1804 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1805 preferred_mode = cur_mode;
1806
1807 cur_vrefresh = cur_mode->vrefresh ?
1808 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1809 preferred_vrefresh = preferred_mode->vrefresh ?
1810 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1811 /* At a given size, try to get closest to target refresh */
1812 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1813 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1814 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1815 preferred_mode = cur_mode;
1816 }
1817 }
1818
1819 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1820 }
1821
1822 static bool
1823 mode_is_rb(const struct drm_display_mode *mode)
1824 {
1825 return (mode->htotal - mode->hdisplay == 160) &&
1826 (mode->hsync_end - mode->hdisplay == 80) &&
1827 (mode->hsync_end - mode->hsync_start == 32) &&
1828 (mode->vsync_start - mode->vdisplay == 3);
1829 }
1830
1831 /*
1832 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1833 * @dev: Device to duplicate against
1834 * @hsize: Mode width
1835 * @vsize: Mode height
1836 * @fresh: Mode refresh rate
1837 * @rb: Mode reduced-blanking-ness
1838 *
1839 * Walk the DMT mode list looking for a match for the given parameters.
1840 *
1841 * Return: A newly allocated copy of the mode, or NULL if not found.
1842 */
1843 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1844 int hsize, int vsize, int fresh,
1845 bool rb)
1846 {
1847 int i;
1848
1849 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1850 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1851 if (hsize != ptr->hdisplay)
1852 continue;
1853 if (vsize != ptr->vdisplay)
1854 continue;
1855 if (fresh != drm_mode_vrefresh(ptr))
1856 continue;
1857 if (rb != mode_is_rb(ptr))
1858 continue;
1859
1860 return drm_mode_duplicate(dev, ptr);
1861 }
1862
1863 return NULL;
1864 }
1865 EXPORT_SYMBOL(drm_mode_find_dmt);
1866
1867 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1868
1869 static void
1870 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1871 {
1872 int i, n = 0;
1873 u8 d = ext[0x02];
1874 u8 *det_base = ext + d;
1875
1876 n = (127 - d) / 18;
1877 for (i = 0; i < n; i++)
1878 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1879 }
1880
1881 static void
1882 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1883 {
1884 unsigned int i, n = min((int)ext[0x02], 6);
1885 u8 *det_base = ext + 5;
1886
1887 if (ext[0x01] != 1)
1888 return; /* unknown version */
1889
1890 for (i = 0; i < n; i++)
1891 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1892 }
1893
1894 static void
1895 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1896 {
1897 int i;
1898 struct edid *edid = (struct edid *)raw_edid;
1899
1900 if (edid == NULL)
1901 return;
1902
1903 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1904 cb(&(edid->detailed_timings[i]), closure);
1905
1906 for (i = 1; i <= raw_edid[0x7e]; i++) {
1907 u8 *ext = raw_edid + (i * EDID_LENGTH);
1908 switch (*ext) {
1909 case CEA_EXT:
1910 cea_for_each_detailed_block(ext, cb, closure);
1911 break;
1912 case VTB_EXT:
1913 vtb_for_each_detailed_block(ext, cb, closure);
1914 break;
1915 default:
1916 break;
1917 }
1918 }
1919 }
1920
1921 static void
1922 is_rb(struct detailed_timing *t, void *data)
1923 {
1924 u8 *r = (u8 *)t;
1925 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1926 if (r[15] & 0x10)
1927 *(bool *)data = true;
1928 }
1929
1930 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1931 static bool
1932 drm_monitor_supports_rb(struct edid *edid)
1933 {
1934 if (edid->revision >= 4) {
1935 bool ret = false;
1936 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1937 return ret;
1938 }
1939
1940 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1941 }
1942
1943 static void
1944 find_gtf2(struct detailed_timing *t, void *data)
1945 {
1946 u8 *r = (u8 *)t;
1947 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1948 *(u8 **)data = r;
1949 }
1950
1951 /* Secondary GTF curve kicks in above some break frequency */
1952 static int
1953 drm_gtf2_hbreak(struct edid *edid)
1954 {
1955 u8 *r = NULL;
1956 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1957 return r ? (r[12] * 2) : 0;
1958 }
1959
1960 static int
1961 drm_gtf2_2c(struct edid *edid)
1962 {
1963 u8 *r = NULL;
1964 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1965 return r ? r[13] : 0;
1966 }
1967
1968 static int
1969 drm_gtf2_m(struct edid *edid)
1970 {
1971 u8 *r = NULL;
1972 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1973 return r ? (r[15] << 8) + r[14] : 0;
1974 }
1975
1976 static int
1977 drm_gtf2_k(struct edid *edid)
1978 {
1979 u8 *r = NULL;
1980 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1981 return r ? r[16] : 0;
1982 }
1983
1984 static int
1985 drm_gtf2_2j(struct edid *edid)
1986 {
1987 u8 *r = NULL;
1988 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1989 return r ? r[17] : 0;
1990 }
1991
1992 /**
1993 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1994 * @edid: EDID block to scan
1995 */
1996 static int standard_timing_level(struct edid *edid)
1997 {
1998 if (edid->revision >= 2) {
1999 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2000 return LEVEL_CVT;
2001 if (drm_gtf2_hbreak(edid))
2002 return LEVEL_GTF2;
2003 return LEVEL_GTF;
2004 }
2005 return LEVEL_DMT;
2006 }
2007
2008 /*
2009 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2010 * monitors fill with ascii space (0x20) instead.
2011 */
2012 static int
2013 bad_std_timing(u8 a, u8 b)
2014 {
2015 return (a == 0x00 && b == 0x00) ||
2016 (a == 0x01 && b == 0x01) ||
2017 (a == 0x20 && b == 0x20);
2018 }
2019
2020 /**
2021 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2022 * @connector: connector of for the EDID block
2023 * @edid: EDID block to scan
2024 * @t: standard timing params
2025 *
2026 * Take the standard timing params (in this case width, aspect, and refresh)
2027 * and convert them into a real mode using CVT/GTF/DMT.
2028 */
2029 static struct drm_display_mode *
2030 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2031 struct std_timing *t)
2032 {
2033 struct drm_device *dev = connector->dev;
2034 struct drm_display_mode *m, *mode = NULL;
2035 int hsize, vsize;
2036 int vrefresh_rate;
2037 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2038 >> EDID_TIMING_ASPECT_SHIFT;
2039 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2040 >> EDID_TIMING_VFREQ_SHIFT;
2041 int timing_level = standard_timing_level(edid);
2042
2043 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2044 return NULL;
2045
2046 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2047 hsize = t->hsize * 8 + 248;
2048 /* vrefresh_rate = vfreq + 60 */
2049 vrefresh_rate = vfreq + 60;
2050 /* the vdisplay is calculated based on the aspect ratio */
2051 if (aspect_ratio == 0) {
2052 if (edid->revision < 3)
2053 vsize = hsize;
2054 else
2055 vsize = (hsize * 10) / 16;
2056 } else if (aspect_ratio == 1)
2057 vsize = (hsize * 3) / 4;
2058 else if (aspect_ratio == 2)
2059 vsize = (hsize * 4) / 5;
2060 else
2061 vsize = (hsize * 9) / 16;
2062
2063 /* HDTV hack, part 1 */
2064 if (vrefresh_rate == 60 &&
2065 ((hsize == 1360 && vsize == 765) ||
2066 (hsize == 1368 && vsize == 769))) {
2067 hsize = 1366;
2068 vsize = 768;
2069 }
2070
2071 /*
2072 * If this connector already has a mode for this size and refresh
2073 * rate (because it came from detailed or CVT info), use that
2074 * instead. This way we don't have to guess at interlace or
2075 * reduced blanking.
2076 */
2077 list_for_each_entry(m, &connector->probed_modes, head)
2078 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2079 drm_mode_vrefresh(m) == vrefresh_rate)
2080 return NULL;
2081
2082 /* HDTV hack, part 2 */
2083 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2084 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2085 false);
2086 mode->hdisplay = 1366;
2087 mode->hsync_start = mode->hsync_start - 1;
2088 mode->hsync_end = mode->hsync_end - 1;
2089 return mode;
2090 }
2091
2092 /* check whether it can be found in default mode table */
2093 if (drm_monitor_supports_rb(edid)) {
2094 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2095 true);
2096 if (mode)
2097 return mode;
2098 }
2099 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2100 if (mode)
2101 return mode;
2102
2103 /* okay, generate it */
2104 switch (timing_level) {
2105 case LEVEL_DMT:
2106 break;
2107 case LEVEL_GTF:
2108 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2109 break;
2110 case LEVEL_GTF2:
2111 /*
2112 * This is potentially wrong if there's ever a monitor with
2113 * more than one ranges section, each claiming a different
2114 * secondary GTF curve. Please don't do that.
2115 */
2116 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2117 if (!mode)
2118 return NULL;
2119 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2120 drm_mode_destroy(dev, mode);
2121 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2122 vrefresh_rate, 0, 0,
2123 drm_gtf2_m(edid),
2124 drm_gtf2_2c(edid),
2125 drm_gtf2_k(edid),
2126 drm_gtf2_2j(edid));
2127 }
2128 break;
2129 case LEVEL_CVT:
2130 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2131 false);
2132 break;
2133 }
2134 return mode;
2135 }
2136
2137 /*
2138 * EDID is delightfully ambiguous about how interlaced modes are to be
2139 * encoded. Our internal representation is of frame height, but some
2140 * HDTV detailed timings are encoded as field height.
2141 *
2142 * The format list here is from CEA, in frame size. Technically we
2143 * should be checking refresh rate too. Whatever.
2144 */
2145 static void
2146 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2147 struct detailed_pixel_timing *pt)
2148 {
2149 int i;
2150 static const struct {
2151 int w, h;
2152 } cea_interlaced[] = {
2153 { 1920, 1080 },
2154 { 720, 480 },
2155 { 1440, 480 },
2156 { 2880, 480 },
2157 { 720, 576 },
2158 { 1440, 576 },
2159 { 2880, 576 },
2160 };
2161
2162 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2163 return;
2164
2165 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2166 if ((mode->hdisplay == cea_interlaced[i].w) &&
2167 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2168 mode->vdisplay *= 2;
2169 mode->vsync_start *= 2;
2170 mode->vsync_end *= 2;
2171 mode->vtotal *= 2;
2172 mode->vtotal |= 1;
2173 }
2174 }
2175
2176 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2177 }
2178
2179 /**
2180 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2181 * @dev: DRM device (needed to create new mode)
2182 * @edid: EDID block
2183 * @timing: EDID detailed timing info
2184 * @quirks: quirks to apply
2185 *
2186 * An EDID detailed timing block contains enough info for us to create and
2187 * return a new struct drm_display_mode.
2188 */
2189 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2190 struct edid *edid,
2191 struct detailed_timing *timing,
2192 u32 quirks)
2193 {
2194 struct drm_display_mode *mode;
2195 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2196 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2197 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2198 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2199 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2200 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2201 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2202 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2203 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2204
2205 /* ignore tiny modes */
2206 if (hactive < 64 || vactive < 64)
2207 return NULL;
2208
2209 if (pt->misc & DRM_EDID_PT_STEREO) {
2210 DRM_DEBUG_KMS("stereo mode not supported\n");
2211 return NULL;
2212 }
2213 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2214 DRM_DEBUG_KMS("composite sync not supported\n");
2215 }
2216
2217 /* it is incorrect if hsync/vsync width is zero */
2218 if (!hsync_pulse_width || !vsync_pulse_width) {
2219 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2220 "Wrong Hsync/Vsync pulse width\n");
2221 return NULL;
2222 }
2223
2224 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2225 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2226 if (!mode)
2227 return NULL;
2228
2229 goto set_size;
2230 }
2231
2232 mode = drm_mode_create(dev);
2233 if (!mode)
2234 return NULL;
2235
2236 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2237 timing->pixel_clock = cpu_to_le16(1088);
2238
2239 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2240
2241 mode->hdisplay = hactive;
2242 mode->hsync_start = mode->hdisplay + hsync_offset;
2243 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2244 mode->htotal = mode->hdisplay + hblank;
2245
2246 mode->vdisplay = vactive;
2247 mode->vsync_start = mode->vdisplay + vsync_offset;
2248 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2249 mode->vtotal = mode->vdisplay + vblank;
2250
2251 /* Some EDIDs have bogus h/vtotal values */
2252 if (mode->hsync_end > mode->htotal)
2253 mode->htotal = mode->hsync_end + 1;
2254 if (mode->vsync_end > mode->vtotal)
2255 mode->vtotal = mode->vsync_end + 1;
2256
2257 drm_mode_do_interlace_quirk(mode, pt);
2258
2259 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2260 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2261 }
2262
2263 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2264 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2265 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2266 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2267
2268 set_size:
2269 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2270 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2271
2272 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2273 mode->width_mm *= 10;
2274 mode->height_mm *= 10;
2275 }
2276
2277 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2278 mode->width_mm = edid->width_cm * 10;
2279 mode->height_mm = edid->height_cm * 10;
2280 }
2281
2282 mode->type = DRM_MODE_TYPE_DRIVER;
2283 mode->vrefresh = drm_mode_vrefresh(mode);
2284 drm_mode_set_name(mode);
2285
2286 return mode;
2287 }
2288
2289 static bool
2290 mode_in_hsync_range(const struct drm_display_mode *mode,
2291 struct edid *edid, u8 *t)
2292 {
2293 int hsync, hmin, hmax;
2294
2295 hmin = t[7];
2296 if (edid->revision >= 4)
2297 hmin += ((t[4] & 0x04) ? 255 : 0);
2298 hmax = t[8];
2299 if (edid->revision >= 4)
2300 hmax += ((t[4] & 0x08) ? 255 : 0);
2301 hsync = drm_mode_hsync(mode);
2302
2303 return (hsync <= hmax && hsync >= hmin);
2304 }
2305
2306 static bool
2307 mode_in_vsync_range(const struct drm_display_mode *mode,
2308 struct edid *edid, u8 *t)
2309 {
2310 int vsync, vmin, vmax;
2311
2312 vmin = t[5];
2313 if (edid->revision >= 4)
2314 vmin += ((t[4] & 0x01) ? 255 : 0);
2315 vmax = t[6];
2316 if (edid->revision >= 4)
2317 vmax += ((t[4] & 0x02) ? 255 : 0);
2318 vsync = drm_mode_vrefresh(mode);
2319
2320 return (vsync <= vmax && vsync >= vmin);
2321 }
2322
2323 static u32
2324 range_pixel_clock(struct edid *edid, u8 *t)
2325 {
2326 /* unspecified */
2327 if (t[9] == 0 || t[9] == 255)
2328 return 0;
2329
2330 /* 1.4 with CVT support gives us real precision, yay */
2331 if (edid->revision >= 4 && t[10] == 0x04)
2332 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2333
2334 /* 1.3 is pathetic, so fuzz up a bit */
2335 return t[9] * 10000 + 5001;
2336 }
2337
2338 static bool
2339 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2340 struct detailed_timing *timing)
2341 {
2342 u32 max_clock;
2343 u8 *t = (u8 *)timing;
2344
2345 if (!mode_in_hsync_range(mode, edid, t))
2346 return false;
2347
2348 if (!mode_in_vsync_range(mode, edid, t))
2349 return false;
2350
2351 if ((max_clock = range_pixel_clock(edid, t)))
2352 if (mode->clock > max_clock)
2353 return false;
2354
2355 /* 1.4 max horizontal check */
2356 if (edid->revision >= 4 && t[10] == 0x04)
2357 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2358 return false;
2359
2360 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2361 return false;
2362
2363 return true;
2364 }
2365
2366 static bool valid_inferred_mode(const struct drm_connector *connector,
2367 const struct drm_display_mode *mode)
2368 {
2369 const struct drm_display_mode *m;
2370 bool ok = false;
2371
2372 list_for_each_entry(m, &connector->probed_modes, head) {
2373 if (mode->hdisplay == m->hdisplay &&
2374 mode->vdisplay == m->vdisplay &&
2375 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2376 return false; /* duplicated */
2377 if (mode->hdisplay <= m->hdisplay &&
2378 mode->vdisplay <= m->vdisplay)
2379 ok = true;
2380 }
2381 return ok;
2382 }
2383
2384 static int
2385 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2386 struct detailed_timing *timing)
2387 {
2388 int i, modes = 0;
2389 struct drm_display_mode *newmode;
2390 struct drm_device *dev = connector->dev;
2391
2392 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2393 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2394 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2395 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2396 if (newmode) {
2397 drm_mode_probed_add(connector, newmode);
2398 modes++;
2399 }
2400 }
2401 }
2402
2403 return modes;
2404 }
2405
2406 /* fix up 1366x768 mode from 1368x768;
2407 * GFT/CVT can't express 1366 width which isn't dividable by 8
2408 */
2409 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2410 {
2411 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2412 mode->hdisplay = 1366;
2413 mode->hsync_start--;
2414 mode->hsync_end--;
2415 drm_mode_set_name(mode);
2416 }
2417 }
2418
2419 static int
2420 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2421 struct detailed_timing *timing)
2422 {
2423 int i, modes = 0;
2424 struct drm_display_mode *newmode;
2425 struct drm_device *dev = connector->dev;
2426
2427 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2428 const struct minimode *m = &extra_modes[i];
2429 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2430 if (!newmode)
2431 return modes;
2432
2433 drm_mode_fixup_1366x768(newmode);
2434 if (!mode_in_range(newmode, edid, timing) ||
2435 !valid_inferred_mode(connector, newmode)) {
2436 drm_mode_destroy(dev, newmode);
2437 continue;
2438 }
2439
2440 drm_mode_probed_add(connector, newmode);
2441 modes++;
2442 }
2443
2444 return modes;
2445 }
2446
2447 static int
2448 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2449 struct detailed_timing *timing)
2450 {
2451 int i, modes = 0;
2452 struct drm_display_mode *newmode;
2453 struct drm_device *dev = connector->dev;
2454 bool rb = drm_monitor_supports_rb(edid);
2455
2456 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2457 const struct minimode *m = &extra_modes[i];
2458 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2459 if (!newmode)
2460 return modes;
2461
2462 drm_mode_fixup_1366x768(newmode);
2463 if (!mode_in_range(newmode, edid, timing) ||
2464 !valid_inferred_mode(connector, newmode)) {
2465 drm_mode_destroy(dev, newmode);
2466 continue;
2467 }
2468
2469 drm_mode_probed_add(connector, newmode);
2470 modes++;
2471 }
2472
2473 return modes;
2474 }
2475
2476 static void
2477 do_inferred_modes(struct detailed_timing *timing, void *c)
2478 {
2479 struct detailed_mode_closure *closure = c;
2480 struct detailed_non_pixel *data = &timing->data.other_data;
2481 struct detailed_data_monitor_range *range = &data->data.range;
2482
2483 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2484 return;
2485
2486 closure->modes += drm_dmt_modes_for_range(closure->connector,
2487 closure->edid,
2488 timing);
2489
2490 if (!version_greater(closure->edid, 1, 1))
2491 return; /* GTF not defined yet */
2492
2493 switch (range->flags) {
2494 case 0x02: /* secondary gtf, XXX could do more */
2495 case 0x00: /* default gtf */
2496 closure->modes += drm_gtf_modes_for_range(closure->connector,
2497 closure->edid,
2498 timing);
2499 break;
2500 case 0x04: /* cvt, only in 1.4+ */
2501 if (!version_greater(closure->edid, 1, 3))
2502 break;
2503
2504 closure->modes += drm_cvt_modes_for_range(closure->connector,
2505 closure->edid,
2506 timing);
2507 break;
2508 case 0x01: /* just the ranges, no formula */
2509 default:
2510 break;
2511 }
2512 }
2513
2514 static int
2515 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2516 {
2517 struct detailed_mode_closure closure = {
2518 .connector = connector,
2519 .edid = edid,
2520 };
2521
2522 if (version_greater(edid, 1, 0))
2523 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2524 &closure);
2525
2526 return closure.modes;
2527 }
2528
2529 static int
2530 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2531 {
2532 int i, j, m, modes = 0;
2533 struct drm_display_mode *mode;
2534 u8 *est = ((u8 *)timing) + 6;
2535
2536 for (i = 0; i < 6; i++) {
2537 for (j = 7; j >= 0; j--) {
2538 m = (i * 8) + (7 - j);
2539 if (m >= ARRAY_SIZE(est3_modes))
2540 break;
2541 if (est[i] & (1 << j)) {
2542 mode = drm_mode_find_dmt(connector->dev,
2543 est3_modes[m].w,
2544 est3_modes[m].h,
2545 est3_modes[m].r,
2546 est3_modes[m].rb);
2547 if (mode) {
2548 drm_mode_probed_add(connector, mode);
2549 modes++;
2550 }
2551 }
2552 }
2553 }
2554
2555 return modes;
2556 }
2557
2558 static void
2559 do_established_modes(struct detailed_timing *timing, void *c)
2560 {
2561 struct detailed_mode_closure *closure = c;
2562 struct detailed_non_pixel *data = &timing->data.other_data;
2563
2564 if (data->type == EDID_DETAIL_EST_TIMINGS)
2565 closure->modes += drm_est3_modes(closure->connector, timing);
2566 }
2567
2568 /**
2569 * add_established_modes - get est. modes from EDID and add them
2570 * @connector: connector to add mode(s) to
2571 * @edid: EDID block to scan
2572 *
2573 * Each EDID block contains a bitmap of the supported "established modes" list
2574 * (defined above). Tease them out and add them to the global modes list.
2575 */
2576 static int
2577 add_established_modes(struct drm_connector *connector, struct edid *edid)
2578 {
2579 struct drm_device *dev = connector->dev;
2580 unsigned long est_bits = edid->established_timings.t1 |
2581 (edid->established_timings.t2 << 8) |
2582 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2583 int i, modes = 0;
2584 struct detailed_mode_closure closure = {
2585 .connector = connector,
2586 .edid = edid,
2587 };
2588
2589 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2590 if (est_bits & (1<<i)) {
2591 struct drm_display_mode *newmode;
2592 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2593 if (newmode) {
2594 drm_mode_probed_add(connector, newmode);
2595 modes++;
2596 }
2597 }
2598 }
2599
2600 if (version_greater(edid, 1, 0))
2601 drm_for_each_detailed_block((u8 *)edid,
2602 do_established_modes, &closure);
2603
2604 return modes + closure.modes;
2605 }
2606
2607 static void
2608 do_standard_modes(struct detailed_timing *timing, void *c)
2609 {
2610 struct detailed_mode_closure *closure = c;
2611 struct detailed_non_pixel *data = &timing->data.other_data;
2612 struct drm_connector *connector = closure->connector;
2613 struct edid *edid = closure->edid;
2614
2615 if (data->type == EDID_DETAIL_STD_MODES) {
2616 int i;
2617 for (i = 0; i < 6; i++) {
2618 struct std_timing *std;
2619 struct drm_display_mode *newmode;
2620
2621 std = &data->data.timings[i];
2622 newmode = drm_mode_std(connector, edid, std);
2623 if (newmode) {
2624 drm_mode_probed_add(connector, newmode);
2625 closure->modes++;
2626 }
2627 }
2628 }
2629 }
2630
2631 /**
2632 * add_standard_modes - get std. modes from EDID and add them
2633 * @connector: connector to add mode(s) to
2634 * @edid: EDID block to scan
2635 *
2636 * Standard modes can be calculated using the appropriate standard (DMT,
2637 * GTF or CVT. Grab them from @edid and add them to the list.
2638 */
2639 static int
2640 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2641 {
2642 int i, modes = 0;
2643 struct detailed_mode_closure closure = {
2644 .connector = connector,
2645 .edid = edid,
2646 };
2647
2648 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2649 struct drm_display_mode *newmode;
2650
2651 newmode = drm_mode_std(connector, edid,
2652 &edid->standard_timings[i]);
2653 if (newmode) {
2654 drm_mode_probed_add(connector, newmode);
2655 modes++;
2656 }
2657 }
2658
2659 if (version_greater(edid, 1, 0))
2660 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2661 &closure);
2662
2663 /* XXX should also look for standard codes in VTB blocks */
2664
2665 return modes + closure.modes;
2666 }
2667
2668 static int drm_cvt_modes(struct drm_connector *connector,
2669 struct detailed_timing *timing)
2670 {
2671 int i, j, modes = 0;
2672 struct drm_display_mode *newmode;
2673 struct drm_device *dev = connector->dev;
2674 struct cvt_timing *cvt;
2675 const int rates[] = { 60, 85, 75, 60, 50 };
2676 const u8 empty[3] = { 0, 0, 0 };
2677
2678 for (i = 0; i < 4; i++) {
2679 int uninitialized_var(width), height;
2680 cvt = &(timing->data.other_data.data.cvt[i]);
2681
2682 if (!memcmp(cvt->code, empty, 3))
2683 continue;
2684
2685 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2686 switch (cvt->code[1] & 0x0c) {
2687 case 0x00:
2688 width = height * 4 / 3;
2689 break;
2690 case 0x04:
2691 width = height * 16 / 9;
2692 break;
2693 case 0x08:
2694 width = height * 16 / 10;
2695 break;
2696 case 0x0c:
2697 width = height * 15 / 9;
2698 break;
2699 }
2700
2701 for (j = 1; j < 5; j++) {
2702 if (cvt->code[2] & (1 << j)) {
2703 newmode = drm_cvt_mode(dev, width, height,
2704 rates[j], j == 0,
2705 false, false);
2706 if (newmode) {
2707 drm_mode_probed_add(connector, newmode);
2708 modes++;
2709 }
2710 }
2711 }
2712 }
2713
2714 return modes;
2715 }
2716
2717 static void
2718 do_cvt_mode(struct detailed_timing *timing, void *c)
2719 {
2720 struct detailed_mode_closure *closure = c;
2721 struct detailed_non_pixel *data = &timing->data.other_data;
2722
2723 if (data->type == EDID_DETAIL_CVT_3BYTE)
2724 closure->modes += drm_cvt_modes(closure->connector, timing);
2725 }
2726
2727 static int
2728 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2729 {
2730 struct detailed_mode_closure closure = {
2731 .connector = connector,
2732 .edid = edid,
2733 };
2734
2735 if (version_greater(edid, 1, 2))
2736 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2737
2738 /* XXX should also look for CVT codes in VTB blocks */
2739
2740 return closure.modes;
2741 }
2742
2743 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2744
2745 static void
2746 do_detailed_mode(struct detailed_timing *timing, void *c)
2747 {
2748 struct detailed_mode_closure *closure = c;
2749 struct drm_display_mode *newmode;
2750
2751 if (timing->pixel_clock) {
2752 newmode = drm_mode_detailed(closure->connector->dev,
2753 closure->edid, timing,
2754 closure->quirks);
2755 if (!newmode)
2756 return;
2757
2758 if (closure->preferred)
2759 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2760
2761 /*
2762 * Detailed modes are limited to 10kHz pixel clock resolution,
2763 * so fix up anything that looks like CEA/HDMI mode, but the clock
2764 * is just slightly off.
2765 */
2766 fixup_detailed_cea_mode_clock(newmode);
2767
2768 drm_mode_probed_add(closure->connector, newmode);
2769 closure->modes++;
2770 closure->preferred = 0;
2771 }
2772 }
2773
2774 /*
2775 * add_detailed_modes - Add modes from detailed timings
2776 * @connector: attached connector
2777 * @edid: EDID block to scan
2778 * @quirks: quirks to apply
2779 */
2780 static int
2781 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2782 u32 quirks)
2783 {
2784 struct detailed_mode_closure closure = {
2785 .connector = connector,
2786 .edid = edid,
2787 .preferred = 1,
2788 .quirks = quirks,
2789 };
2790
2791 if (closure.preferred && !version_greater(edid, 1, 3))
2792 closure.preferred =
2793 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2794
2795 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2796
2797 return closure.modes;
2798 }
2799
2800 #define AUDIO_BLOCK 0x01
2801 #define VIDEO_BLOCK 0x02
2802 #define VENDOR_BLOCK 0x03
2803 #define SPEAKER_BLOCK 0x04
2804 #define USE_EXTENDED_TAG 0x07
2805 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2806 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2807 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2808 #define EDID_BASIC_AUDIO (1 << 6)
2809 #define EDID_CEA_YCRCB444 (1 << 5)
2810 #define EDID_CEA_YCRCB422 (1 << 4)
2811 #define EDID_CEA_VCDB_QS (1 << 6)
2812
2813 /*
2814 * Search EDID for CEA extension block.
2815 */
2816 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2817 {
2818 u8 *edid_ext = NULL;
2819 int i;
2820
2821 /* No EDID or EDID extensions */
2822 if (edid == NULL || edid->extensions == 0)
2823 return NULL;
2824
2825 /* Find CEA extension */
2826 for (i = 0; i < edid->extensions; i++) {
2827 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2828 if (edid_ext[0] == ext_id)
2829 break;
2830 }
2831
2832 if (i == edid->extensions)
2833 return NULL;
2834
2835 return edid_ext;
2836 }
2837
2838 static u8 *drm_find_cea_extension(struct edid *edid)
2839 {
2840 return drm_find_edid_extension(edid, CEA_EXT);
2841 }
2842
2843 static u8 *drm_find_displayid_extension(struct edid *edid)
2844 {
2845 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2846 }
2847
2848 /*
2849 * Calculate the alternate clock for the CEA mode
2850 * (60Hz vs. 59.94Hz etc.)
2851 */
2852 static unsigned int
2853 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2854 {
2855 unsigned int clock = cea_mode->clock;
2856
2857 if (cea_mode->vrefresh % 6 != 0)
2858 return clock;
2859
2860 /*
2861 * edid_cea_modes contains the 59.94Hz
2862 * variant for 240 and 480 line modes,
2863 * and the 60Hz variant otherwise.
2864 */
2865 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2866 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2867 else
2868 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2869
2870 return clock;
2871 }
2872
2873 static bool
2874 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2875 {
2876 /*
2877 * For certain VICs the spec allows the vertical
2878 * front porch to vary by one or two lines.
2879 *
2880 * cea_modes[] stores the variant with the shortest
2881 * vertical front porch. We can adjust the mode to
2882 * get the other variants by simply increasing the
2883 * vertical front porch length.
2884 */
2885 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2886 edid_cea_modes[9].vtotal != 262 ||
2887 edid_cea_modes[12].vtotal != 262 ||
2888 edid_cea_modes[13].vtotal != 262 ||
2889 edid_cea_modes[23].vtotal != 312 ||
2890 edid_cea_modes[24].vtotal != 312 ||
2891 edid_cea_modes[27].vtotal != 312 ||
2892 edid_cea_modes[28].vtotal != 312);
2893
2894 if (((vic == 8 || vic == 9 ||
2895 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2896 ((vic == 23 || vic == 24 ||
2897 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2898 mode->vsync_start++;
2899 mode->vsync_end++;
2900 mode->vtotal++;
2901
2902 return true;
2903 }
2904
2905 return false;
2906 }
2907
2908 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2909 unsigned int clock_tolerance)
2910 {
2911 u8 vic;
2912
2913 if (!to_match->clock)
2914 return 0;
2915
2916 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2917 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2918 unsigned int clock1, clock2;
2919
2920 /* Check both 60Hz and 59.94Hz */
2921 clock1 = cea_mode.clock;
2922 clock2 = cea_mode_alternate_clock(&cea_mode);
2923
2924 if (abs(to_match->clock - clock1) > clock_tolerance &&
2925 abs(to_match->clock - clock2) > clock_tolerance)
2926 continue;
2927
2928 do {
2929 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2930 return vic;
2931 } while (cea_mode_alternate_timings(vic, &cea_mode));
2932 }
2933
2934 return 0;
2935 }
2936
2937 /**
2938 * drm_match_cea_mode - look for a CEA mode matching given mode
2939 * @to_match: display mode
2940 *
2941 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2942 * mode.
2943 */
2944 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2945 {
2946 u8 vic;
2947
2948 if (!to_match->clock)
2949 return 0;
2950
2951 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2952 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2953 unsigned int clock1, clock2;
2954
2955 /* Check both 60Hz and 59.94Hz */
2956 clock1 = cea_mode.clock;
2957 clock2 = cea_mode_alternate_clock(&cea_mode);
2958
2959 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2960 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2961 continue;
2962
2963 do {
2964 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2965 return vic;
2966 } while (cea_mode_alternate_timings(vic, &cea_mode));
2967 }
2968
2969 return 0;
2970 }
2971 EXPORT_SYMBOL(drm_match_cea_mode);
2972
2973 static bool drm_valid_cea_vic(u8 vic)
2974 {
2975 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2976 }
2977
2978 /**
2979 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2980 * the input VIC from the CEA mode list
2981 * @video_code: ID given to each of the CEA modes
2982 *
2983 * Returns picture aspect ratio
2984 */
2985 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2986 {
2987 return edid_cea_modes[video_code].picture_aspect_ratio;
2988 }
2989 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2990
2991 /*
2992 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2993 * specific block).
2994 *
2995 * It's almost like cea_mode_alternate_clock(), we just need to add an
2996 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2997 * one.
2998 */
2999 static unsigned int
3000 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3001 {
3002 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3003 return hdmi_mode->clock;
3004
3005 return cea_mode_alternate_clock(hdmi_mode);
3006 }
3007
3008 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3009 unsigned int clock_tolerance)
3010 {
3011 u8 vic;
3012
3013 if (!to_match->clock)
3014 return 0;
3015
3016 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3017 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3018 unsigned int clock1, clock2;
3019
3020 /* Make sure to also match alternate clocks */
3021 clock1 = hdmi_mode->clock;
3022 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3023
3024 if (abs(to_match->clock - clock1) > clock_tolerance &&
3025 abs(to_match->clock - clock2) > clock_tolerance)
3026 continue;
3027
3028 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
3029 return vic;
3030 }
3031
3032 return 0;
3033 }
3034
3035 /*
3036 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3037 * @to_match: display mode
3038 *
3039 * An HDMI mode is one defined in the HDMI vendor specific block.
3040 *
3041 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3042 */
3043 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3044 {
3045 u8 vic;
3046
3047 if (!to_match->clock)
3048 return 0;
3049
3050 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3051 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3052 unsigned int clock1, clock2;
3053
3054 /* Make sure to also match alternate clocks */
3055 clock1 = hdmi_mode->clock;
3056 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3057
3058 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3059 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3060 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3061 return vic;
3062 }
3063 return 0;
3064 }
3065
3066 static bool drm_valid_hdmi_vic(u8 vic)
3067 {
3068 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3069 }
3070
3071 static int
3072 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3073 {
3074 struct drm_device *dev = connector->dev;
3075 struct drm_display_mode *mode, *tmp;
3076 LIST_HEAD(list);
3077 int modes = 0;
3078
3079 /* Don't add CEA modes if the CEA extension block is missing */
3080 if (!drm_find_cea_extension(edid))
3081 return 0;
3082
3083 /*
3084 * Go through all probed modes and create a new mode
3085 * with the alternate clock for certain CEA modes.
3086 */
3087 list_for_each_entry(mode, &connector->probed_modes, head) {
3088 const struct drm_display_mode *cea_mode = NULL;
3089 struct drm_display_mode *newmode;
3090 u8 vic = drm_match_cea_mode(mode);
3091 unsigned int clock1, clock2;
3092
3093 if (drm_valid_cea_vic(vic)) {
3094 cea_mode = &edid_cea_modes[vic];
3095 clock2 = cea_mode_alternate_clock(cea_mode);
3096 } else {
3097 vic = drm_match_hdmi_mode(mode);
3098 if (drm_valid_hdmi_vic(vic)) {
3099 cea_mode = &edid_4k_modes[vic];
3100 clock2 = hdmi_mode_alternate_clock(cea_mode);
3101 }
3102 }
3103
3104 if (!cea_mode)
3105 continue;
3106
3107 clock1 = cea_mode->clock;
3108
3109 if (clock1 == clock2)
3110 continue;
3111
3112 if (mode->clock != clock1 && mode->clock != clock2)
3113 continue;
3114
3115 newmode = drm_mode_duplicate(dev, cea_mode);
3116 if (!newmode)
3117 continue;
3118
3119 /* Carry over the stereo flags */
3120 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3121
3122 /*
3123 * The current mode could be either variant. Make
3124 * sure to pick the "other" clock for the new mode.
3125 */
3126 if (mode->clock != clock1)
3127 newmode->clock = clock1;
3128 else
3129 newmode->clock = clock2;
3130
3131 list_add_tail(&newmode->head, &list);
3132 }
3133
3134 list_for_each_entry_safe(mode, tmp, &list, head) {
3135 list_del(&mode->head);
3136 drm_mode_probed_add(connector, mode);
3137 modes++;
3138 }
3139
3140 return modes;
3141 }
3142
3143 static u8 svd_to_vic(u8 svd)
3144 {
3145 /* 0-6 bit vic, 7th bit native mode indicator */
3146 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3147 return svd & 127;
3148
3149 return svd;
3150 }
3151
3152 static struct drm_display_mode *
3153 drm_display_mode_from_vic_index(struct drm_connector *connector,
3154 const u8 *video_db, u8 video_len,
3155 u8 video_index)
3156 {
3157 struct drm_device *dev = connector->dev;
3158 struct drm_display_mode *newmode;
3159 u8 vic;
3160
3161 if (video_db == NULL || video_index >= video_len)
3162 return NULL;
3163
3164 /* CEA modes are numbered 1..127 */
3165 vic = svd_to_vic(video_db[video_index]);
3166 if (!drm_valid_cea_vic(vic))
3167 return NULL;
3168
3169 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3170 if (!newmode)
3171 return NULL;
3172
3173 newmode->vrefresh = 0;
3174
3175 return newmode;
3176 }
3177
3178 /*
3179 * do_y420vdb_modes - Parse YCBCR 420 only modes
3180 * @connector: connector corresponding to the HDMI sink
3181 * @svds: start of the data block of CEA YCBCR 420 VDB
3182 * @len: length of the CEA YCBCR 420 VDB
3183 *
3184 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3185 * which contains modes which can be supported in YCBCR 420
3186 * output format only.
3187 */
3188 static int do_y420vdb_modes(struct drm_connector *connector,
3189 const u8 *svds, u8 svds_len)
3190 {
3191 int modes = 0, i;
3192 struct drm_device *dev = connector->dev;
3193 struct drm_display_info *info = &connector->display_info;
3194 struct drm_hdmi_info *hdmi = &info->hdmi;
3195
3196 for (i = 0; i < svds_len; i++) {
3197 u8 vic = svd_to_vic(svds[i]);
3198 struct drm_display_mode *newmode;
3199
3200 if (!drm_valid_cea_vic(vic))
3201 continue;
3202
3203 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3204 if (!newmode)
3205 break;
3206 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3207 drm_mode_probed_add(connector, newmode);
3208 modes++;
3209 }
3210
3211 if (modes > 0)
3212 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3213 return modes;
3214 }
3215
3216 /*
3217 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3218 * @connector: connector corresponding to the HDMI sink
3219 * @vic: CEA vic for the video mode to be added in the map
3220 *
3221 * Makes an entry for a videomode in the YCBCR 420 bitmap
3222 */
3223 static void
3224 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3225 {
3226 u8 vic = svd_to_vic(svd);
3227 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3228
3229 if (!drm_valid_cea_vic(vic))
3230 return;
3231
3232 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3233 }
3234
3235 static int
3236 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3237 {
3238 int i, modes = 0;
3239 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3240
3241 for (i = 0; i < len; i++) {
3242 struct drm_display_mode *mode;
3243 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3244 if (mode) {
3245 /*
3246 * YCBCR420 capability block contains a bitmap which
3247 * gives the index of CEA modes from CEA VDB, which
3248 * can support YCBCR 420 sampling output also (apart
3249 * from RGB/YCBCR444 etc).
3250 * For example, if the bit 0 in bitmap is set,
3251 * first mode in VDB can support YCBCR420 output too.
3252 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3253 */
3254 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3255 drm_add_cmdb_modes(connector, db[i]);
3256
3257 drm_mode_probed_add(connector, mode);
3258 modes++;
3259 }
3260 }
3261
3262 return modes;
3263 }
3264
3265 struct stereo_mandatory_mode {
3266 int width, height, vrefresh;
3267 unsigned int flags;
3268 };
3269
3270 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3271 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3272 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3273 { 1920, 1080, 50,
3274 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3275 { 1920, 1080, 60,
3276 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3277 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3278 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3279 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3280 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3281 };
3282
3283 static bool
3284 stereo_match_mandatory(const struct drm_display_mode *mode,
3285 const struct stereo_mandatory_mode *stereo_mode)
3286 {
3287 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3288
3289 return mode->hdisplay == stereo_mode->width &&
3290 mode->vdisplay == stereo_mode->height &&
3291 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3292 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3293 }
3294
3295 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3296 {
3297 struct drm_device *dev = connector->dev;
3298 const struct drm_display_mode *mode;
3299 struct list_head stereo_modes;
3300 int modes = 0, i;
3301
3302 INIT_LIST_HEAD(&stereo_modes);
3303
3304 list_for_each_entry(mode, &connector->probed_modes, head) {
3305 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3306 const struct stereo_mandatory_mode *mandatory;
3307 struct drm_display_mode *new_mode;
3308
3309 if (!stereo_match_mandatory(mode,
3310 &stereo_mandatory_modes[i]))
3311 continue;
3312
3313 mandatory = &stereo_mandatory_modes[i];
3314 new_mode = drm_mode_duplicate(dev, mode);
3315 if (!new_mode)
3316 continue;
3317
3318 new_mode->flags |= mandatory->flags;
3319 list_add_tail(&new_mode->head, &stereo_modes);
3320 modes++;
3321 }
3322 }
3323
3324 list_splice_tail(&stereo_modes, &connector->probed_modes);
3325
3326 return modes;
3327 }
3328
3329 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3330 {
3331 struct drm_device *dev = connector->dev;
3332 struct drm_display_mode *newmode;
3333
3334 if (!drm_valid_hdmi_vic(vic)) {
3335 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3336 return 0;
3337 }
3338
3339 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3340 if (!newmode)
3341 return 0;
3342
3343 drm_mode_probed_add(connector, newmode);
3344
3345 return 1;
3346 }
3347
3348 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3349 const u8 *video_db, u8 video_len, u8 video_index)
3350 {
3351 struct drm_display_mode *newmode;
3352 int modes = 0;
3353
3354 if (structure & (1 << 0)) {
3355 newmode = drm_display_mode_from_vic_index(connector, video_db,
3356 video_len,
3357 video_index);
3358 if (newmode) {
3359 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3360 drm_mode_probed_add(connector, newmode);
3361 modes++;
3362 }
3363 }
3364 if (structure & (1 << 6)) {
3365 newmode = drm_display_mode_from_vic_index(connector, video_db,
3366 video_len,
3367 video_index);
3368 if (newmode) {
3369 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3370 drm_mode_probed_add(connector, newmode);
3371 modes++;
3372 }
3373 }
3374 if (structure & (1 << 8)) {
3375 newmode = drm_display_mode_from_vic_index(connector, video_db,
3376 video_len,
3377 video_index);
3378 if (newmode) {
3379 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3380 drm_mode_probed_add(connector, newmode);
3381 modes++;
3382 }
3383 }
3384
3385 return modes;
3386 }
3387
3388 /*
3389 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3390 * @connector: connector corresponding to the HDMI sink
3391 * @db: start of the CEA vendor specific block
3392 * @len: length of the CEA block payload, ie. one can access up to db[len]
3393 *
3394 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3395 * also adds the stereo 3d modes when applicable.
3396 */
3397 static int
3398 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3399 const u8 *video_db, u8 video_len)
3400 {
3401 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3402 u8 vic_len, hdmi_3d_len = 0;
3403 u16 mask;
3404 u16 structure_all;
3405
3406 if (len < 8)
3407 goto out;
3408
3409 /* no HDMI_Video_Present */
3410 if (!(db[8] & (1 << 5)))
3411 goto out;
3412
3413 /* Latency_Fields_Present */
3414 if (db[8] & (1 << 7))
3415 offset += 2;
3416
3417 /* I_Latency_Fields_Present */
3418 if (db[8] & (1 << 6))
3419 offset += 2;
3420
3421 /* the declared length is not long enough for the 2 first bytes
3422 * of additional video format capabilities */
3423 if (len < (8 + offset + 2))
3424 goto out;
3425
3426 /* 3D_Present */
3427 offset++;
3428 if (db[8 + offset] & (1 << 7)) {
3429 modes += add_hdmi_mandatory_stereo_modes(connector);
3430
3431 /* 3D_Multi_present */
3432 multi_present = (db[8 + offset] & 0x60) >> 5;
3433 }
3434
3435 offset++;
3436 vic_len = db[8 + offset] >> 5;
3437 hdmi_3d_len = db[8 + offset] & 0x1f;
3438
3439 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3440 u8 vic;
3441
3442 vic = db[9 + offset + i];
3443 modes += add_hdmi_mode(connector, vic);
3444 }
3445 offset += 1 + vic_len;
3446
3447 if (multi_present == 1)
3448 multi_len = 2;
3449 else if (multi_present == 2)
3450 multi_len = 4;
3451 else
3452 multi_len = 0;
3453
3454 if (len < (8 + offset + hdmi_3d_len - 1))
3455 goto out;
3456
3457 if (hdmi_3d_len < multi_len)
3458 goto out;
3459
3460 if (multi_present == 1 || multi_present == 2) {
3461 /* 3D_Structure_ALL */
3462 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3463
3464 /* check if 3D_MASK is present */
3465 if (multi_present == 2)
3466 mask = (db[10 + offset] << 8) | db[11 + offset];
3467 else
3468 mask = 0xffff;
3469
3470 for (i = 0; i < 16; i++) {
3471 if (mask & (1 << i))
3472 modes += add_3d_struct_modes(connector,
3473 structure_all,
3474 video_db,
3475 video_len, i);
3476 }
3477 }
3478
3479 offset += multi_len;
3480
3481 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3482 int vic_index;
3483 struct drm_display_mode *newmode = NULL;
3484 unsigned int newflag = 0;
3485 bool detail_present;
3486
3487 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3488
3489 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3490 break;
3491
3492 /* 2D_VIC_order_X */
3493 vic_index = db[8 + offset + i] >> 4;
3494
3495 /* 3D_Structure_X */
3496 switch (db[8 + offset + i] & 0x0f) {
3497 case 0:
3498 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3499 break;
3500 case 6:
3501 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3502 break;
3503 case 8:
3504 /* 3D_Detail_X */
3505 if ((db[9 + offset + i] >> 4) == 1)
3506 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3507 break;
3508 }
3509
3510 if (newflag != 0) {
3511 newmode = drm_display_mode_from_vic_index(connector,
3512 video_db,
3513 video_len,
3514 vic_index);
3515
3516 if (newmode) {
3517 newmode->flags |= newflag;
3518 drm_mode_probed_add(connector, newmode);
3519 modes++;
3520 }
3521 }
3522
3523 if (detail_present)
3524 i++;
3525 }
3526
3527 out:
3528 return modes;
3529 }
3530
3531 static int
3532 cea_db_payload_len(const u8 *db)
3533 {
3534 return db[0] & 0x1f;
3535 }
3536
3537 static int
3538 cea_db_extended_tag(const u8 *db)
3539 {
3540 return db[1];
3541 }
3542
3543 static int
3544 cea_db_tag(const u8 *db)
3545 {
3546 return db[0] >> 5;
3547 }
3548
3549 static int
3550 cea_revision(const u8 *cea)
3551 {
3552 return cea[1];
3553 }
3554
3555 static int
3556 cea_db_offsets(const u8 *cea, int *start, int *end)
3557 {
3558 /* Data block offset in CEA extension block */
3559 *start = 4;
3560 *end = cea[2];
3561 if (*end == 0)
3562 *end = 127;
3563 if (*end < 4 || *end > 127)
3564 return -ERANGE;
3565 return 0;
3566 }
3567
3568 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3569 {
3570 int hdmi_id;
3571
3572 if (cea_db_tag(db) != VENDOR_BLOCK)
3573 return false;
3574
3575 if (cea_db_payload_len(db) < 5)
3576 return false;
3577
3578 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3579
3580 return hdmi_id == HDMI_IEEE_OUI;
3581 }
3582
3583 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3584 {
3585 unsigned int oui;
3586
3587 if (cea_db_tag(db) != VENDOR_BLOCK)
3588 return false;
3589
3590 if (cea_db_payload_len(db) < 7)
3591 return false;
3592
3593 oui = db[3] << 16 | db[2] << 8 | db[1];
3594
3595 return oui == HDMI_FORUM_IEEE_OUI;
3596 }
3597
3598 static bool cea_db_is_y420cmdb(const u8 *db)
3599 {
3600 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3601 return false;
3602
3603 if (!cea_db_payload_len(db))
3604 return false;
3605
3606 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3607 return false;
3608
3609 return true;
3610 }
3611
3612 static bool cea_db_is_y420vdb(const u8 *db)
3613 {
3614 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3615 return false;
3616
3617 if (!cea_db_payload_len(db))
3618 return false;
3619
3620 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3621 return false;
3622
3623 return true;
3624 }
3625
3626 #define for_each_cea_db(cea, i, start, end) \
3627 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3628
3629 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3630 const u8 *db)
3631 {
3632 struct drm_display_info *info = &connector->display_info;
3633 struct drm_hdmi_info *hdmi = &info->hdmi;
3634 u8 map_len = cea_db_payload_len(db) - 1;
3635 u8 count;
3636 u64 map = 0;
3637
3638 if (map_len == 0) {
3639 /* All CEA modes support ycbcr420 sampling also.*/
3640 hdmi->y420_cmdb_map = U64_MAX;
3641 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3642 return;
3643 }
3644
3645 /*
3646 * This map indicates which of the existing CEA block modes
3647 * from VDB can support YCBCR420 output too. So if bit=0 is
3648 * set, first mode from VDB can support YCBCR420 output too.
3649 * We will parse and keep this map, before parsing VDB itself
3650 * to avoid going through the same block again and again.
3651 *
3652 * Spec is not clear about max possible size of this block.
3653 * Clamping max bitmap block size at 8 bytes. Every byte can
3654 * address 8 CEA modes, in this way this map can address
3655 * 8*8 = first 64 SVDs.
3656 */
3657 if (WARN_ON_ONCE(map_len > 8))
3658 map_len = 8;
3659
3660 for (count = 0; count < map_len; count++)
3661 map |= (u64)db[2 + count] << (8 * count);
3662
3663 if (map)
3664 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3665
3666 hdmi->y420_cmdb_map = map;
3667 }
3668
3669 static int
3670 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3671 {
3672 const u8 *cea = drm_find_cea_extension(edid);
3673 const u8 *db, *hdmi = NULL, *video = NULL;
3674 u8 dbl, hdmi_len, video_len = 0;
3675 int modes = 0;
3676
3677 if (cea && cea_revision(cea) >= 3) {
3678 int i, start, end;
3679
3680 if (cea_db_offsets(cea, &start, &end))
3681 return 0;
3682
3683 for_each_cea_db(cea, i, start, end) {
3684 db = &cea[i];
3685 dbl = cea_db_payload_len(db);
3686
3687 if (cea_db_tag(db) == VIDEO_BLOCK) {
3688 video = db + 1;
3689 video_len = dbl;
3690 modes += do_cea_modes(connector, video, dbl);
3691 } else if (cea_db_is_hdmi_vsdb(db)) {
3692 hdmi = db;
3693 hdmi_len = dbl;
3694 } else if (cea_db_is_y420vdb(db)) {
3695 const u8 *vdb420 = &db[2];
3696
3697 /* Add 4:2:0(only) modes present in EDID */
3698 modes += do_y420vdb_modes(connector,
3699 vdb420,
3700 dbl - 1);
3701 }
3702 }
3703 }
3704
3705 /*
3706 * We parse the HDMI VSDB after having added the cea modes as we will
3707 * be patching their flags when the sink supports stereo 3D.
3708 */
3709 if (hdmi)
3710 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3711 video_len);
3712
3713 return modes;
3714 }
3715
3716 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3717 {
3718 const struct drm_display_mode *cea_mode;
3719 int clock1, clock2, clock;
3720 u8 vic;
3721 const char *type;
3722
3723 /*
3724 * allow 5kHz clock difference either way to account for
3725 * the 10kHz clock resolution limit of detailed timings.
3726 */
3727 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3728 if (drm_valid_cea_vic(vic)) {
3729 type = "CEA";
3730 cea_mode = &edid_cea_modes[vic];
3731 clock1 = cea_mode->clock;
3732 clock2 = cea_mode_alternate_clock(cea_mode);
3733 } else {
3734 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3735 if (drm_valid_hdmi_vic(vic)) {
3736 type = "HDMI";
3737 cea_mode = &edid_4k_modes[vic];
3738 clock1 = cea_mode->clock;
3739 clock2 = hdmi_mode_alternate_clock(cea_mode);
3740 } else {
3741 return;
3742 }
3743 }
3744
3745 /* pick whichever is closest */
3746 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3747 clock = clock1;
3748 else
3749 clock = clock2;
3750
3751 if (mode->clock == clock)
3752 return;
3753
3754 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3755 type, vic, mode->clock, clock);
3756 mode->clock = clock;
3757 }
3758
3759 static void
3760 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3761 {
3762 u8 len = cea_db_payload_len(db);
3763
3764 if (len >= 6)
3765 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3766 if (len >= 8) {
3767 connector->latency_present[0] = db[8] >> 7;
3768 connector->latency_present[1] = (db[8] >> 6) & 1;
3769 }
3770 if (len >= 9)
3771 connector->video_latency[0] = db[9];
3772 if (len >= 10)
3773 connector->audio_latency[0] = db[10];
3774 if (len >= 11)
3775 connector->video_latency[1] = db[11];
3776 if (len >= 12)
3777 connector->audio_latency[1] = db[12];
3778
3779 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3780 "video latency %d %d, "
3781 "audio latency %d %d\n",
3782 connector->latency_present[0],
3783 connector->latency_present[1],
3784 connector->video_latency[0],
3785 connector->video_latency[1],
3786 connector->audio_latency[0],
3787 connector->audio_latency[1]);
3788 }
3789
3790 static void
3791 monitor_name(struct detailed_timing *t, void *data)
3792 {
3793 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3794 *(u8 **)data = t->data.other_data.data.str.str;
3795 }
3796
3797 static int get_monitor_name(struct edid *edid, char name[13])
3798 {
3799 char *edid_name = NULL;
3800 int mnl;
3801
3802 if (!edid || !name)
3803 return 0;
3804
3805 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3806 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3807 if (edid_name[mnl] == 0x0a)
3808 break;
3809
3810 name[mnl] = edid_name[mnl];
3811 }
3812
3813 return mnl;
3814 }
3815
3816 /**
3817 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3818 * @edid: monitor EDID information
3819 * @name: pointer to a character array to hold the name of the monitor
3820 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3821 *
3822 */
3823 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3824 {
3825 int name_length;
3826 char buf[13];
3827
3828 if (bufsize <= 0)
3829 return;
3830
3831 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3832 memcpy(name, buf, name_length);
3833 name[name_length] = '\0';
3834 }
3835 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3836
3837 /**
3838 * drm_edid_to_eld - build ELD from EDID
3839 * @connector: connector corresponding to the HDMI/DP sink
3840 * @edid: EDID to parse
3841 *
3842 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3843 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3844 * fill in.
3845 */
3846 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3847 {
3848 uint8_t *eld = connector->eld;
3849 u8 *cea;
3850 u8 *db;
3851 int total_sad_count = 0;
3852 int mnl;
3853 int dbl;
3854
3855 memset(eld, 0, sizeof(connector->eld));
3856
3857 connector->latency_present[0] = false;
3858 connector->latency_present[1] = false;
3859 connector->video_latency[0] = 0;
3860 connector->audio_latency[0] = 0;
3861 connector->video_latency[1] = 0;
3862 connector->audio_latency[1] = 0;
3863
3864 if (!edid)
3865 return;
3866
3867 cea = drm_find_cea_extension(edid);
3868 if (!cea) {
3869 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3870 return;
3871 }
3872
3873 mnl = get_monitor_name(edid, eld + 20);
3874
3875 eld[4] = (cea[1] << 5) | mnl;
3876 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3877
3878 eld[0] = 2 << 3; /* ELD version: 2 */
3879
3880 eld[16] = edid->mfg_id[0];
3881 eld[17] = edid->mfg_id[1];
3882 eld[18] = edid->prod_code[0];
3883 eld[19] = edid->prod_code[1];
3884
3885 if (cea_revision(cea) >= 3) {
3886 int i, start, end;
3887
3888 if (cea_db_offsets(cea, &start, &end)) {
3889 start = 0;
3890 end = 0;
3891 }
3892
3893 for_each_cea_db(cea, i, start, end) {
3894 db = &cea[i];
3895 dbl = cea_db_payload_len(db);
3896
3897 switch (cea_db_tag(db)) {
3898 int sad_count;
3899
3900 case AUDIO_BLOCK:
3901 /* Audio Data Block, contains SADs */
3902 sad_count = min(dbl / 3, 15 - total_sad_count);
3903 if (sad_count >= 1)
3904 memcpy(eld + 20 + mnl + total_sad_count * 3,
3905 &db[1], sad_count * 3);
3906 total_sad_count += sad_count;
3907 break;
3908 case SPEAKER_BLOCK:
3909 /* Speaker Allocation Data Block */
3910 if (dbl >= 1)
3911 eld[7] = db[1];
3912 break;
3913 case VENDOR_BLOCK:
3914 /* HDMI Vendor-Specific Data Block */
3915 if (cea_db_is_hdmi_vsdb(db))
3916 drm_parse_hdmi_vsdb_audio(connector, db);
3917 break;
3918 default:
3919 break;
3920 }
3921 }
3922 }
3923 eld[5] |= total_sad_count << 4;
3924
3925 eld[DRM_ELD_BASELINE_ELD_LEN] =
3926 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3927
3928 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3929 drm_eld_size(eld), total_sad_count);
3930 }
3931 EXPORT_SYMBOL(drm_edid_to_eld);
3932
3933 /**
3934 * drm_edid_to_sad - extracts SADs from EDID
3935 * @edid: EDID to parse
3936 * @sads: pointer that will be set to the extracted SADs
3937 *
3938 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3939 *
3940 * Note: The returned pointer needs to be freed using kfree().
3941 *
3942 * Return: The number of found SADs or negative number on error.
3943 */
3944 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3945 {
3946 int count = 0;
3947 int i, start, end, dbl;
3948 u8 *cea;
3949
3950 cea = drm_find_cea_extension(edid);
3951 if (!cea) {
3952 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3953 return -ENOENT;
3954 }
3955
3956 if (cea_revision(cea) < 3) {
3957 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3958 return -ENOTSUPP;
3959 }
3960
3961 if (cea_db_offsets(cea, &start, &end)) {
3962 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3963 return -EPROTO;
3964 }
3965
3966 for_each_cea_db(cea, i, start, end) {
3967 u8 *db = &cea[i];
3968
3969 if (cea_db_tag(db) == AUDIO_BLOCK) {
3970 int j;
3971 dbl = cea_db_payload_len(db);
3972
3973 count = dbl / 3; /* SAD is 3B */
3974 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3975 if (!*sads)
3976 return -ENOMEM;
3977 for (j = 0; j < count; j++) {
3978 u8 *sad = &db[1 + j * 3];
3979
3980 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3981 (*sads)[j].channels = sad[0] & 0x7;
3982 (*sads)[j].freq = sad[1] & 0x7F;
3983 (*sads)[j].byte2 = sad[2];
3984 }
3985 break;
3986 }
3987 }
3988
3989 return count;
3990 }
3991 EXPORT_SYMBOL(drm_edid_to_sad);
3992
3993 /**
3994 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3995 * @edid: EDID to parse
3996 * @sadb: pointer to the speaker block
3997 *
3998 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3999 *
4000 * Note: The returned pointer needs to be freed using kfree().
4001 *
4002 * Return: The number of found Speaker Allocation Blocks or negative number on
4003 * error.
4004 */
4005 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4006 {
4007 int count = 0;
4008 int i, start, end, dbl;
4009 const u8 *cea;
4010
4011 cea = drm_find_cea_extension(edid);
4012 if (!cea) {
4013 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4014 return -ENOENT;
4015 }
4016
4017 if (cea_revision(cea) < 3) {
4018 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4019 return -ENOTSUPP;
4020 }
4021
4022 if (cea_db_offsets(cea, &start, &end)) {
4023 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4024 return -EPROTO;
4025 }
4026
4027 for_each_cea_db(cea, i, start, end) {
4028 const u8 *db = &cea[i];
4029
4030 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4031 dbl = cea_db_payload_len(db);
4032
4033 /* Speaker Allocation Data Block */
4034 if (dbl == 3) {
4035 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4036 if (!*sadb)
4037 return -ENOMEM;
4038 count = dbl;
4039 break;
4040 }
4041 }
4042 }
4043
4044 return count;
4045 }
4046 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4047
4048 /**
4049 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4050 * @connector: connector associated with the HDMI/DP sink
4051 * @mode: the display mode
4052 *
4053 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4054 * the sink doesn't support audio or video.
4055 */
4056 int drm_av_sync_delay(struct drm_connector *connector,
4057 const struct drm_display_mode *mode)
4058 {
4059 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4060 int a, v;
4061
4062 if (!connector->latency_present[0])
4063 return 0;
4064 if (!connector->latency_present[1])
4065 i = 0;
4066
4067 a = connector->audio_latency[i];
4068 v = connector->video_latency[i];
4069
4070 /*
4071 * HDMI/DP sink doesn't support audio or video?
4072 */
4073 if (a == 255 || v == 255)
4074 return 0;
4075
4076 /*
4077 * Convert raw EDID values to millisecond.
4078 * Treat unknown latency as 0ms.
4079 */
4080 if (a)
4081 a = min(2 * (a - 1), 500);
4082 if (v)
4083 v = min(2 * (v - 1), 500);
4084
4085 return max(v - a, 0);
4086 }
4087 EXPORT_SYMBOL(drm_av_sync_delay);
4088
4089 /**
4090 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4091 * @edid: monitor EDID information
4092 *
4093 * Parse the CEA extension according to CEA-861-B.
4094 *
4095 * Return: True if the monitor is HDMI, false if not or unknown.
4096 */
4097 bool drm_detect_hdmi_monitor(struct edid *edid)
4098 {
4099 u8 *edid_ext;
4100 int i;
4101 int start_offset, end_offset;
4102
4103 edid_ext = drm_find_cea_extension(edid);
4104 if (!edid_ext)
4105 return false;
4106
4107 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4108 return false;
4109
4110 /*
4111 * Because HDMI identifier is in Vendor Specific Block,
4112 * search it from all data blocks of CEA extension.
4113 */
4114 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4115 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4116 return true;
4117 }
4118
4119 return false;
4120 }
4121 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4122
4123 /**
4124 * drm_detect_monitor_audio - check monitor audio capability
4125 * @edid: EDID block to scan
4126 *
4127 * Monitor should have CEA extension block.
4128 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4129 * audio' only. If there is any audio extension block and supported
4130 * audio format, assume at least 'basic audio' support, even if 'basic
4131 * audio' is not defined in EDID.
4132 *
4133 * Return: True if the monitor supports audio, false otherwise.
4134 */
4135 bool drm_detect_monitor_audio(struct edid *edid)
4136 {
4137 u8 *edid_ext;
4138 int i, j;
4139 bool has_audio = false;
4140 int start_offset, end_offset;
4141
4142 edid_ext = drm_find_cea_extension(edid);
4143 if (!edid_ext)
4144 goto end;
4145
4146 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4147
4148 if (has_audio) {
4149 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4150 goto end;
4151 }
4152
4153 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4154 goto end;
4155
4156 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4157 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4158 has_audio = true;
4159 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4160 DRM_DEBUG_KMS("CEA audio format %d\n",
4161 (edid_ext[i + j] >> 3) & 0xf);
4162 goto end;
4163 }
4164 }
4165 end:
4166 return has_audio;
4167 }
4168 EXPORT_SYMBOL(drm_detect_monitor_audio);
4169
4170 /**
4171 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4172 * @edid: EDID block to scan
4173 *
4174 * Check whether the monitor reports the RGB quantization range selection
4175 * as supported. The AVI infoframe can then be used to inform the monitor
4176 * which quantization range (full or limited) is used.
4177 *
4178 * Return: True if the RGB quantization range is selectable, false otherwise.
4179 */
4180 bool drm_rgb_quant_range_selectable(struct edid *edid)
4181 {
4182 u8 *edid_ext;
4183 int i, start, end;
4184
4185 edid_ext = drm_find_cea_extension(edid);
4186 if (!edid_ext)
4187 return false;
4188
4189 if (cea_db_offsets(edid_ext, &start, &end))
4190 return false;
4191
4192 for_each_cea_db(edid_ext, i, start, end) {
4193 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4194 cea_db_payload_len(&edid_ext[i]) == 2 &&
4195 cea_db_extended_tag(&edid_ext[i]) ==
4196 EXT_VIDEO_CAPABILITY_BLOCK) {
4197 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4198 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4199 }
4200 }
4201
4202 return false;
4203 }
4204 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4205
4206 /**
4207 * drm_default_rgb_quant_range - default RGB quantization range
4208 * @mode: display mode
4209 *
4210 * Determine the default RGB quantization range for the mode,
4211 * as specified in CEA-861.
4212 *
4213 * Return: The default RGB quantization range for the mode
4214 */
4215 enum hdmi_quantization_range
4216 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4217 {
4218 /* All CEA modes other than VIC 1 use limited quantization range. */
4219 return drm_match_cea_mode(mode) > 1 ?
4220 HDMI_QUANTIZATION_RANGE_LIMITED :
4221 HDMI_QUANTIZATION_RANGE_FULL;
4222 }
4223 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4224
4225 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4226 const u8 *db)
4227 {
4228 u8 dc_mask;
4229 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4230
4231 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4232 hdmi->y420_dc_modes |= dc_mask;
4233 }
4234
4235 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4236 const u8 *hf_vsdb)
4237 {
4238 struct drm_display_info *display = &connector->display_info;
4239 struct drm_hdmi_info *hdmi = &display->hdmi;
4240
4241 if (hf_vsdb[6] & 0x80) {
4242 hdmi->scdc.supported = true;
4243 if (hf_vsdb[6] & 0x40)
4244 hdmi->scdc.read_request = true;
4245 }
4246
4247 /*
4248 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4249 * And as per the spec, three factors confirm this:
4250 * * Availability of a HF-VSDB block in EDID (check)
4251 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4252 * * SCDC support available (let's check)
4253 * Lets check it out.
4254 */
4255
4256 if (hf_vsdb[5]) {
4257 /* max clock is 5000 KHz times block value */
4258 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4259 struct drm_scdc *scdc = &hdmi->scdc;
4260
4261 if (max_tmds_clock > 340000) {
4262 display->max_tmds_clock = max_tmds_clock;
4263 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4264 display->max_tmds_clock);
4265 }
4266
4267 if (scdc->supported) {
4268 scdc->scrambling.supported = true;
4269
4270 /* Few sinks support scrambling for cloks < 340M */
4271 if ((hf_vsdb[6] & 0x8))
4272 scdc->scrambling.low_rates = true;
4273 }
4274 }
4275
4276 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4277 }
4278
4279 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4280 const u8 *hdmi)
4281 {
4282 struct drm_display_info *info = &connector->display_info;
4283 unsigned int dc_bpc = 0;
4284
4285 /* HDMI supports at least 8 bpc */
4286 info->bpc = 8;
4287
4288 if (cea_db_payload_len(hdmi) < 6)
4289 return;
4290
4291 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4292 dc_bpc = 10;
4293 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4294 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4295 connector->name);
4296 }
4297
4298 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4299 dc_bpc = 12;
4300 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4301 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4302 connector->name);
4303 }
4304
4305 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4306 dc_bpc = 16;
4307 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4308 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4309 connector->name);
4310 }
4311
4312 if (dc_bpc == 0) {
4313 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4314 connector->name);
4315 return;
4316 }
4317
4318 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4319 connector->name, dc_bpc);
4320 info->bpc = dc_bpc;
4321
4322 /*
4323 * Deep color support mandates RGB444 support for all video
4324 * modes and forbids YCRCB422 support for all video modes per
4325 * HDMI 1.3 spec.
4326 */
4327 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4328
4329 /* YCRCB444 is optional according to spec. */
4330 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4331 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4332 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4333 connector->name);
4334 }
4335
4336 /*
4337 * Spec says that if any deep color mode is supported at all,
4338 * then deep color 36 bit must be supported.
4339 */
4340 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4341 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4342 connector->name);
4343 }
4344 }
4345
4346 static void
4347 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4348 {
4349 struct drm_display_info *info = &connector->display_info;
4350 u8 len = cea_db_payload_len(db);
4351
4352 if (len >= 6)
4353 info->dvi_dual = db[6] & 1;
4354 if (len >= 7)
4355 info->max_tmds_clock = db[7] * 5000;
4356
4357 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4358 "max TMDS clock %d kHz\n",
4359 info->dvi_dual,
4360 info->max_tmds_clock);
4361
4362 drm_parse_hdmi_deep_color_info(connector, db);
4363 }
4364
4365 static void drm_parse_cea_ext(struct drm_connector *connector,
4366 struct edid *edid)
4367 {
4368 struct drm_display_info *info = &connector->display_info;
4369 const u8 *edid_ext;
4370 int i, start, end;
4371
4372 edid_ext = drm_find_cea_extension(edid);
4373 if (!edid_ext)
4374 return;
4375
4376 info->cea_rev = edid_ext[1];
4377
4378 /* The existence of a CEA block should imply RGB support */
4379 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4380 if (edid_ext[3] & EDID_CEA_YCRCB444)
4381 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4382 if (edid_ext[3] & EDID_CEA_YCRCB422)
4383 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4384
4385 if (cea_db_offsets(edid_ext, &start, &end))
4386 return;
4387
4388 for_each_cea_db(edid_ext, i, start, end) {
4389 const u8 *db = &edid_ext[i];
4390
4391 if (cea_db_is_hdmi_vsdb(db))
4392 drm_parse_hdmi_vsdb_video(connector, db);
4393 if (cea_db_is_hdmi_forum_vsdb(db))
4394 drm_parse_hdmi_forum_vsdb(connector, db);
4395 if (cea_db_is_y420cmdb(db))
4396 drm_parse_y420cmdb_bitmap(connector, db);
4397 }
4398 }
4399
4400 static void drm_add_display_info(struct drm_connector *connector,
4401 struct edid *edid, u32 quirks)
4402 {
4403 struct drm_display_info *info = &connector->display_info;
4404
4405 info->width_mm = edid->width_cm * 10;
4406 info->height_mm = edid->height_cm * 10;
4407
4408 /* driver figures it out in this case */
4409 info->bpc = 0;
4410 info->color_formats = 0;
4411 info->cea_rev = 0;
4412 info->max_tmds_clock = 0;
4413 info->dvi_dual = false;
4414
4415 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4416
4417 if (edid->revision < 3)
4418 return;
4419
4420 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4421 return;
4422
4423 drm_parse_cea_ext(connector, edid);
4424
4425 /*
4426 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4427 *
4428 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4429 * tells us to assume 8 bpc color depth if the EDID doesn't have
4430 * extensions which tell otherwise.
4431 */
4432 if ((info->bpc == 0) && (edid->revision < 4) &&
4433 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4434 info->bpc = 8;
4435 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4436 connector->name, info->bpc);
4437 }
4438
4439 /* Only defined for 1.4 with digital displays */
4440 if (edid->revision < 4)
4441 return;
4442
4443 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4444 case DRM_EDID_DIGITAL_DEPTH_6:
4445 info->bpc = 6;
4446 break;
4447 case DRM_EDID_DIGITAL_DEPTH_8:
4448 info->bpc = 8;
4449 break;
4450 case DRM_EDID_DIGITAL_DEPTH_10:
4451 info->bpc = 10;
4452 break;
4453 case DRM_EDID_DIGITAL_DEPTH_12:
4454 info->bpc = 12;
4455 break;
4456 case DRM_EDID_DIGITAL_DEPTH_14:
4457 info->bpc = 14;
4458 break;
4459 case DRM_EDID_DIGITAL_DEPTH_16:
4460 info->bpc = 16;
4461 break;
4462 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4463 default:
4464 info->bpc = 0;
4465 break;
4466 }
4467
4468 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4469 connector->name, info->bpc);
4470
4471 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4472 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4473 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4474 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4475 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4476 }
4477
4478 static int validate_displayid(u8 *displayid, int length, int idx)
4479 {
4480 int i;
4481 u8 csum = 0;
4482 struct displayid_hdr *base;
4483
4484 base = (struct displayid_hdr *)&displayid[idx];
4485
4486 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4487 base->rev, base->bytes, base->prod_id, base->ext_count);
4488
4489 if (base->bytes + 5 > length - idx)
4490 return -EINVAL;
4491 for (i = idx; i <= base->bytes + 5; i++) {
4492 csum += displayid[i];
4493 }
4494 if (csum) {
4495 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4496 return -EINVAL;
4497 }
4498 return 0;
4499 }
4500
4501 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4502 struct displayid_detailed_timings_1 *timings)
4503 {
4504 struct drm_display_mode *mode;
4505 unsigned pixel_clock = (timings->pixel_clock[0] |
4506 (timings->pixel_clock[1] << 8) |
4507 (timings->pixel_clock[2] << 16));
4508 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4509 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4510 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4511 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4512 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4513 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4514 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4515 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4516 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4517 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4518 mode = drm_mode_create(dev);
4519 if (!mode)
4520 return NULL;
4521
4522 mode->clock = pixel_clock * 10;
4523 mode->hdisplay = hactive;
4524 mode->hsync_start = mode->hdisplay + hsync;
4525 mode->hsync_end = mode->hsync_start + hsync_width;
4526 mode->htotal = mode->hdisplay + hblank;
4527
4528 mode->vdisplay = vactive;
4529 mode->vsync_start = mode->vdisplay + vsync;
4530 mode->vsync_end = mode->vsync_start + vsync_width;
4531 mode->vtotal = mode->vdisplay + vblank;
4532
4533 mode->flags = 0;
4534 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4535 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4536 mode->type = DRM_MODE_TYPE_DRIVER;
4537
4538 if (timings->flags & 0x80)
4539 mode->type |= DRM_MODE_TYPE_PREFERRED;
4540 mode->vrefresh = drm_mode_vrefresh(mode);
4541 drm_mode_set_name(mode);
4542
4543 return mode;
4544 }
4545
4546 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4547 struct displayid_block *block)
4548 {
4549 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4550 int i;
4551 int num_timings;
4552 struct drm_display_mode *newmode;
4553 int num_modes = 0;
4554 /* blocks must be multiple of 20 bytes length */
4555 if (block->num_bytes % 20)
4556 return 0;
4557
4558 num_timings = block->num_bytes / 20;
4559 for (i = 0; i < num_timings; i++) {
4560 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4561
4562 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4563 if (!newmode)
4564 continue;
4565
4566 drm_mode_probed_add(connector, newmode);
4567 num_modes++;
4568 }
4569 return num_modes;
4570 }
4571
4572 static int add_displayid_detailed_modes(struct drm_connector *connector,
4573 struct edid *edid)
4574 {
4575 u8 *displayid;
4576 int ret;
4577 int idx = 1;
4578 int length = EDID_LENGTH;
4579 struct displayid_block *block;
4580 int num_modes = 0;
4581
4582 displayid = drm_find_displayid_extension(edid);
4583 if (!displayid)
4584 return 0;
4585
4586 ret = validate_displayid(displayid, length, idx);
4587 if (ret)
4588 return 0;
4589
4590 idx += sizeof(struct displayid_hdr);
4591 while (block = (struct displayid_block *)&displayid[idx],
4592 idx + sizeof(struct displayid_block) <= length &&
4593 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4594 block->num_bytes > 0) {
4595 idx += block->num_bytes + sizeof(struct displayid_block);
4596 switch (block->tag) {
4597 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4598 num_modes += add_displayid_detailed_1_modes(connector, block);
4599 break;
4600 }
4601 }
4602 return num_modes;
4603 }
4604
4605 /**
4606 * drm_add_edid_modes - add modes from EDID data, if available
4607 * @connector: connector we're probing
4608 * @edid: EDID data
4609 *
4610 * Add the specified modes to the connector's mode list. Also fills out the
4611 * &drm_display_info structure in @connector with any information which can be
4612 * derived from the edid.
4613 *
4614 * Return: The number of modes added or 0 if we couldn't find any.
4615 */
4616 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4617 {
4618 int num_modes = 0;
4619 u32 quirks;
4620
4621 if (edid == NULL) {
4622 return 0;
4623 }
4624 if (!drm_edid_is_valid(edid)) {
4625 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4626 connector->name);
4627 return 0;
4628 }
4629
4630 quirks = edid_get_quirks(edid);
4631
4632 /*
4633 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4634 * To avoid multiple parsing of same block, lets parse that map
4635 * from sink info, before parsing CEA modes.
4636 */
4637 drm_add_display_info(connector, edid, quirks);
4638
4639 /*
4640 * EDID spec says modes should be preferred in this order:
4641 * - preferred detailed mode
4642 * - other detailed modes from base block
4643 * - detailed modes from extension blocks
4644 * - CVT 3-byte code modes
4645 * - standard timing codes
4646 * - established timing codes
4647 * - modes inferred from GTF or CVT range information
4648 *
4649 * We get this pretty much right.
4650 *
4651 * XXX order for additional mode types in extension blocks?
4652 */
4653 num_modes += add_detailed_modes(connector, edid, quirks);
4654 num_modes += add_cvt_modes(connector, edid);
4655 num_modes += add_standard_modes(connector, edid);
4656 num_modes += add_established_modes(connector, edid);
4657 num_modes += add_cea_modes(connector, edid);
4658 num_modes += add_alternate_cea_modes(connector, edid);
4659 num_modes += add_displayid_detailed_modes(connector, edid);
4660 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4661 num_modes += add_inferred_modes(connector, edid);
4662
4663 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4664 edid_fixup_preferred(connector, quirks);
4665
4666 if (quirks & EDID_QUIRK_FORCE_6BPC)
4667 connector->display_info.bpc = 6;
4668
4669 if (quirks & EDID_QUIRK_FORCE_8BPC)
4670 connector->display_info.bpc = 8;
4671
4672 if (quirks & EDID_QUIRK_FORCE_10BPC)
4673 connector->display_info.bpc = 10;
4674
4675 if (quirks & EDID_QUIRK_FORCE_12BPC)
4676 connector->display_info.bpc = 12;
4677
4678 return num_modes;
4679 }
4680 EXPORT_SYMBOL(drm_add_edid_modes);
4681
4682 /**
4683 * drm_add_modes_noedid - add modes for the connectors without EDID
4684 * @connector: connector we're probing
4685 * @hdisplay: the horizontal display limit
4686 * @vdisplay: the vertical display limit
4687 *
4688 * Add the specified modes to the connector's mode list. Only when the
4689 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4690 *
4691 * Return: The number of modes added or 0 if we couldn't find any.
4692 */
4693 int drm_add_modes_noedid(struct drm_connector *connector,
4694 int hdisplay, int vdisplay)
4695 {
4696 int i, count, num_modes = 0;
4697 struct drm_display_mode *mode;
4698 struct drm_device *dev = connector->dev;
4699
4700 count = ARRAY_SIZE(drm_dmt_modes);
4701 if (hdisplay < 0)
4702 hdisplay = 0;
4703 if (vdisplay < 0)
4704 vdisplay = 0;
4705
4706 for (i = 0; i < count; i++) {
4707 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4708 if (hdisplay && vdisplay) {
4709 /*
4710 * Only when two are valid, they will be used to check
4711 * whether the mode should be added to the mode list of
4712 * the connector.
4713 */
4714 if (ptr->hdisplay > hdisplay ||
4715 ptr->vdisplay > vdisplay)
4716 continue;
4717 }
4718 if (drm_mode_vrefresh(ptr) > 61)
4719 continue;
4720 mode = drm_mode_duplicate(dev, ptr);
4721 if (mode) {
4722 drm_mode_probed_add(connector, mode);
4723 num_modes++;
4724 }
4725 }
4726 return num_modes;
4727 }
4728 EXPORT_SYMBOL(drm_add_modes_noedid);
4729
4730 /**
4731 * drm_set_preferred_mode - Sets the preferred mode of a connector
4732 * @connector: connector whose mode list should be processed
4733 * @hpref: horizontal resolution of preferred mode
4734 * @vpref: vertical resolution of preferred mode
4735 *
4736 * Marks a mode as preferred if it matches the resolution specified by @hpref
4737 * and @vpref.
4738 */
4739 void drm_set_preferred_mode(struct drm_connector *connector,
4740 int hpref, int vpref)
4741 {
4742 struct drm_display_mode *mode;
4743
4744 list_for_each_entry(mode, &connector->probed_modes, head) {
4745 if (mode->hdisplay == hpref &&
4746 mode->vdisplay == vpref)
4747 mode->type |= DRM_MODE_TYPE_PREFERRED;
4748 }
4749 }
4750 EXPORT_SYMBOL(drm_set_preferred_mode);
4751
4752 /**
4753 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4754 * data from a DRM display mode
4755 * @frame: HDMI AVI infoframe
4756 * @mode: DRM display mode
4757 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4758 *
4759 * Return: 0 on success or a negative error code on failure.
4760 */
4761 int
4762 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4763 const struct drm_display_mode *mode,
4764 bool is_hdmi2_sink)
4765 {
4766 int err;
4767
4768 if (!frame || !mode)
4769 return -EINVAL;
4770
4771 err = hdmi_avi_infoframe_init(frame);
4772 if (err < 0)
4773 return err;
4774
4775 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4776 frame->pixel_repeat = 1;
4777
4778 frame->video_code = drm_match_cea_mode(mode);
4779
4780 /*
4781 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4782 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4783 * have to make sure we dont break HDMI 1.4 sinks.
4784 */
4785 if (!is_hdmi2_sink && frame->video_code > 64)
4786 frame->video_code = 0;
4787
4788 /*
4789 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4790 * we should send its VIC in vendor infoframes, else send the
4791 * VIC in AVI infoframes. Lets check if this mode is present in
4792 * HDMI 1.4b 4K modes
4793 */
4794 if (frame->video_code) {
4795 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4796 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4797
4798 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4799 frame->video_code = 0;
4800 }
4801
4802 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4803
4804 /*
4805 * Populate picture aspect ratio from either
4806 * user input (if specified) or from the CEA mode list.
4807 */
4808 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4809 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4810 frame->picture_aspect = mode->picture_aspect_ratio;
4811 else if (frame->video_code > 0)
4812 frame->picture_aspect = drm_get_cea_aspect_ratio(
4813 frame->video_code);
4814
4815 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4816 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4817
4818 return 0;
4819 }
4820 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4821
4822 /**
4823 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4824 * quantization range information
4825 * @frame: HDMI AVI infoframe
4826 * @mode: DRM display mode
4827 * @rgb_quant_range: RGB quantization range (Q)
4828 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4829 */
4830 void
4831 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4832 const struct drm_display_mode *mode,
4833 enum hdmi_quantization_range rgb_quant_range,
4834 bool rgb_quant_range_selectable,
4835 bool is_hdmi2_sink)
4836 {
4837 /*
4838 * CEA-861:
4839 * "A Source shall not send a non-zero Q value that does not correspond
4840 * to the default RGB Quantization Range for the transmitted Picture
4841 * unless the Sink indicates support for the Q bit in a Video
4842 * Capabilities Data Block."
4843 *
4844 * HDMI 2.0 recommends sending non-zero Q when it does match the
4845 * default RGB quantization range for the mode, even when QS=0.
4846 */
4847 if (rgb_quant_range_selectable ||
4848 rgb_quant_range == drm_default_rgb_quant_range(mode))
4849 frame->quantization_range = rgb_quant_range;
4850 else
4851 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4852
4853 /*
4854 * CEA-861-F:
4855 * "When transmitting any RGB colorimetry, the Source should set the
4856 * YQ-field to match the RGB Quantization Range being transmitted
4857 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4858 * set YQ=1) and the Sink shall ignore the YQ-field."
4859 *
4860 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4861 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4862 * good way to tell which version of CEA-861 the sink supports, so
4863 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4864 * on on CEA-861-F.
4865 */
4866 if (!is_hdmi2_sink ||
4867 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4868 frame->ycc_quantization_range =
4869 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4870 else
4871 frame->ycc_quantization_range =
4872 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4873 }
4874 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4875
4876 static enum hdmi_3d_structure
4877 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4878 {
4879 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4880
4881 switch (layout) {
4882 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4883 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4884 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4885 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4886 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4887 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4888 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4889 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4890 case DRM_MODE_FLAG_3D_L_DEPTH:
4891 return HDMI_3D_STRUCTURE_L_DEPTH;
4892 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4893 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4894 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4895 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4896 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4897 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4898 default:
4899 return HDMI_3D_STRUCTURE_INVALID;
4900 }
4901 }
4902
4903 /**
4904 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4905 * data from a DRM display mode
4906 * @frame: HDMI vendor infoframe
4907 * @mode: DRM display mode
4908 *
4909 * Note that there's is a need to send HDMI vendor infoframes only when using a
4910 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4911 * function will return -EINVAL, error that can be safely ignored.
4912 *
4913 * Return: 0 on success or a negative error code on failure.
4914 */
4915 int
4916 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4917 const struct drm_display_mode *mode)
4918 {
4919 int err;
4920 u32 s3d_flags;
4921 u8 vic;
4922
4923 if (!frame || !mode)
4924 return -EINVAL;
4925
4926 vic = drm_match_hdmi_mode(mode);
4927 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4928
4929 if (!vic && !s3d_flags)
4930 return -EINVAL;
4931
4932 if (vic && s3d_flags)
4933 return -EINVAL;
4934
4935 err = hdmi_vendor_infoframe_init(frame);
4936 if (err < 0)
4937 return err;
4938
4939 if (vic)
4940 frame->vic = vic;
4941 else
4942 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4943
4944 return 0;
4945 }
4946 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4947
4948 static int drm_parse_tiled_block(struct drm_connector *connector,
4949 struct displayid_block *block)
4950 {
4951 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4952 u16 w, h;
4953 u8 tile_v_loc, tile_h_loc;
4954 u8 num_v_tile, num_h_tile;
4955 struct drm_tile_group *tg;
4956
4957 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4958 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4959
4960 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4961 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4962 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4963 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4964
4965 connector->has_tile = true;
4966 if (tile->tile_cap & 0x80)
4967 connector->tile_is_single_monitor = true;
4968
4969 connector->num_h_tile = num_h_tile + 1;
4970 connector->num_v_tile = num_v_tile + 1;
4971 connector->tile_h_loc = tile_h_loc;
4972 connector->tile_v_loc = tile_v_loc;
4973 connector->tile_h_size = w + 1;
4974 connector->tile_v_size = h + 1;
4975
4976 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4977 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4978 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4979 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4980 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4981
4982 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4983 if (!tg) {
4984 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4985 }
4986 if (!tg)
4987 return -ENOMEM;
4988
4989 if (connector->tile_group != tg) {
4990 /* if we haven't got a pointer,
4991 take the reference, drop ref to old tile group */
4992 if (connector->tile_group) {
4993 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4994 }
4995 connector->tile_group = tg;
4996 } else
4997 /* if same tile group, then release the ref we just took. */
4998 drm_mode_put_tile_group(connector->dev, tg);
4999 return 0;
5000 }
5001
5002 static int drm_parse_display_id(struct drm_connector *connector,
5003 u8 *displayid, int length,
5004 bool is_edid_extension)
5005 {
5006 /* if this is an EDID extension the first byte will be 0x70 */
5007 int idx = 0;
5008 struct displayid_block *block;
5009 int ret;
5010
5011 if (is_edid_extension)
5012 idx = 1;
5013
5014 ret = validate_displayid(displayid, length, idx);
5015 if (ret)
5016 return ret;
5017
5018 idx += sizeof(struct displayid_hdr);
5019 while (block = (struct displayid_block *)&displayid[idx],
5020 idx + sizeof(struct displayid_block) <= length &&
5021 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5022 block->num_bytes > 0) {
5023 idx += block->num_bytes + sizeof(struct displayid_block);
5024 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5025 block->tag, block->rev, block->num_bytes);
5026
5027 switch (block->tag) {
5028 case DATA_BLOCK_TILED_DISPLAY:
5029 ret = drm_parse_tiled_block(connector, block);
5030 if (ret)
5031 return ret;
5032 break;
5033 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5034 /* handled in mode gathering code. */
5035 break;
5036 default:
5037 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5038 break;
5039 }
5040 }
5041 return 0;
5042 }
5043
5044 static void drm_get_displayid(struct drm_connector *connector,
5045 struct edid *edid)
5046 {
5047 void *displayid = NULL;
5048 int ret;
5049 connector->has_tile = false;
5050 displayid = drm_find_displayid_extension(edid);
5051 if (!displayid) {
5052 /* drop reference to any tile group we had */
5053 goto out_drop_ref;
5054 }
5055
5056 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5057 if (ret < 0)
5058 goto out_drop_ref;
5059 if (!connector->has_tile)
5060 goto out_drop_ref;
5061 return;
5062 out_drop_ref:
5063 if (connector->tile_group) {
5064 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5065 connector->tile_group = NULL;
5066 }
5067 return;
5068 }
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