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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / drm_edid.c
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
36 #include <drm/drmP.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40
41 #include "drm_crtc_internal.h"
42
43 #define version_greater(edid, maj, min) \
44 (((edid)->version > (maj)) || \
45 ((edid)->version == (maj) && (edid)->revision > (min)))
46
47 #define EDID_EST_TIMINGS 16
48 #define EDID_STD_TIMINGS 8
49 #define EDID_DETAILED_TIMINGS 4
50
51 /*
52 * EDID blocks out in the wild have a variety of bugs, try to collect
53 * them here (note that userspace may work around broken monitors first,
54 * but fixes should make their way here so that the kernel "just works"
55 * on as many displays as possible).
56 */
57
58 /* First detailed mode wrong, use largest 60Hz mode */
59 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
60 /* Reported 135MHz pixel clock is too high, needs adjustment */
61 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
62 /* Prefer the largest mode at 75 Hz */
63 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
64 /* Detail timing is in cm not mm */
65 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
66 /* Detailed timing descriptors have bogus size values, so just take the
67 * maximum size and use that.
68 */
69 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
70 /* Monitor forgot to set the first detailed is preferred bit. */
71 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
72 /* use +hsync +vsync for detailed mode */
73 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
74 /* Force reduced-blanking timings for detailed modes */
75 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
76 /* Force 8bpc */
77 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
78 /* Force 12bpc */
79 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
80 /* Force 6bpc */
81 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
82
83 struct detailed_mode_closure {
84 struct drm_connector *connector;
85 struct edid *edid;
86 bool preferred;
87 u32 quirks;
88 int modes;
89 };
90
91 #define LEVEL_DMT 0
92 #define LEVEL_GTF 1
93 #define LEVEL_GTF2 2
94 #define LEVEL_CVT 3
95
96 static const struct edid_quirk {
97 char vendor[4];
98 int product_id;
99 u32 quirks;
100 } edid_quirk_list[] = {
101 /* Acer AL1706 */
102 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
103 /* Acer F51 */
104 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
105 /* Unknown Acer */
106 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
107
108 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
109 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
110
111 /* Belinea 10 15 55 */
112 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
113 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
114
115 /* Envision Peripherals, Inc. EN-7100e */
116 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
117 /* Envision EN2028 */
118 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
119
120 /* Funai Electronics PM36B */
121 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
122 EDID_QUIRK_DETAILED_IN_CM },
123
124 /* LG Philips LCD LP154W01-A5 */
125 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
126 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
127
128 /* Philips 107p5 CRT */
129 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
130
131 /* Proview AY765C */
132 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
133
134 /* Samsung SyncMaster 205BW. Note: irony */
135 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
136 /* Samsung SyncMaster 22[5-6]BW */
137 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
138 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
139
140 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
141 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
142
143 /* ViewSonic VA2026w */
144 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
145
146 /* Medion MD 30217 PG */
147 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
148
149 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
150 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
151
152 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
153 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
154 };
155
156 /*
157 * Autogenerated from the DMT spec.
158 * This table is copied from xfree86/modes/xf86EdidModes.c.
159 */
160 static const struct drm_display_mode drm_dmt_modes[] = {
161 /* 0x01 - 640x350@85Hz */
162 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
163 736, 832, 0, 350, 382, 385, 445, 0,
164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
165 /* 0x02 - 640x400@85Hz */
166 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
167 736, 832, 0, 400, 401, 404, 445, 0,
168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
169 /* 0x03 - 720x400@85Hz */
170 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
171 828, 936, 0, 400, 401, 404, 446, 0,
172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
173 /* 0x04 - 640x480@60Hz */
174 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
175 752, 800, 0, 480, 490, 492, 525, 0,
176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
177 /* 0x05 - 640x480@72Hz */
178 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
179 704, 832, 0, 480, 489, 492, 520, 0,
180 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
181 /* 0x06 - 640x480@75Hz */
182 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
183 720, 840, 0, 480, 481, 484, 500, 0,
184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
185 /* 0x07 - 640x480@85Hz */
186 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
187 752, 832, 0, 480, 481, 484, 509, 0,
188 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
189 /* 0x08 - 800x600@56Hz */
190 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
191 896, 1024, 0, 600, 601, 603, 625, 0,
192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
193 /* 0x09 - 800x600@60Hz */
194 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
195 968, 1056, 0, 600, 601, 605, 628, 0,
196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
197 /* 0x0a - 800x600@72Hz */
198 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
199 976, 1040, 0, 600, 637, 643, 666, 0,
200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
201 /* 0x0b - 800x600@75Hz */
202 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
203 896, 1056, 0, 600, 601, 604, 625, 0,
204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 0x0c - 800x600@85Hz */
206 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
207 896, 1048, 0, 600, 601, 604, 631, 0,
208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
209 /* 0x0d - 800x600@120Hz RB */
210 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
211 880, 960, 0, 600, 603, 607, 636, 0,
212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
213 /* 0x0e - 848x480@60Hz */
214 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
215 976, 1088, 0, 480, 486, 494, 517, 0,
216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
217 /* 0x0f - 1024x768@43Hz, interlace */
218 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
219 1208, 1264, 0, 768, 768, 776, 817, 0,
220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
221 DRM_MODE_FLAG_INTERLACE) },
222 /* 0x10 - 1024x768@60Hz */
223 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
224 1184, 1344, 0, 768, 771, 777, 806, 0,
225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
226 /* 0x11 - 1024x768@70Hz */
227 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
228 1184, 1328, 0, 768, 771, 777, 806, 0,
229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
230 /* 0x12 - 1024x768@75Hz */
231 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
232 1136, 1312, 0, 768, 769, 772, 800, 0,
233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
234 /* 0x13 - 1024x768@85Hz */
235 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
236 1168, 1376, 0, 768, 769, 772, 808, 0,
237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
238 /* 0x14 - 1024x768@120Hz RB */
239 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
240 1104, 1184, 0, 768, 771, 775, 813, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
242 /* 0x15 - 1152x864@75Hz */
243 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
244 1344, 1600, 0, 864, 865, 868, 900, 0,
245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
246 /* 0x55 - 1280x720@60Hz */
247 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
248 1430, 1650, 0, 720, 725, 730, 750, 0,
249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 0x16 - 1280x768@60Hz RB */
251 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
252 1360, 1440, 0, 768, 771, 778, 790, 0,
253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
254 /* 0x17 - 1280x768@60Hz */
255 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
256 1472, 1664, 0, 768, 771, 778, 798, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
258 /* 0x18 - 1280x768@75Hz */
259 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
260 1488, 1696, 0, 768, 771, 778, 805, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
262 /* 0x19 - 1280x768@85Hz */
263 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
264 1496, 1712, 0, 768, 771, 778, 809, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
266 /* 0x1a - 1280x768@120Hz RB */
267 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
268 1360, 1440, 0, 768, 771, 778, 813, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
270 /* 0x1b - 1280x800@60Hz RB */
271 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
272 1360, 1440, 0, 800, 803, 809, 823, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
274 /* 0x1c - 1280x800@60Hz */
275 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
276 1480, 1680, 0, 800, 803, 809, 831, 0,
277 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 0x1d - 1280x800@75Hz */
279 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
280 1488, 1696, 0, 800, 803, 809, 838, 0,
281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x1e - 1280x800@85Hz */
283 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
284 1496, 1712, 0, 800, 803, 809, 843, 0,
285 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
286 /* 0x1f - 1280x800@120Hz RB */
287 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
288 1360, 1440, 0, 800, 803, 809, 847, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x20 - 1280x960@60Hz */
291 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
292 1488, 1800, 0, 960, 961, 964, 1000, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x21 - 1280x960@85Hz */
295 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
296 1504, 1728, 0, 960, 961, 964, 1011, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x22 - 1280x960@120Hz RB */
299 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
300 1360, 1440, 0, 960, 963, 967, 1017, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x23 - 1280x1024@60Hz */
303 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
304 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x24 - 1280x1024@75Hz */
307 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
308 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x25 - 1280x1024@85Hz */
311 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
312 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x26 - 1280x1024@120Hz RB */
315 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
316 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
318 /* 0x27 - 1360x768@60Hz */
319 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
320 1536, 1792, 0, 768, 771, 777, 795, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x28 - 1360x768@120Hz RB */
323 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
324 1440, 1520, 0, 768, 771, 776, 813, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x51 - 1366x768@60Hz */
327 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
328 1579, 1792, 0, 768, 771, 774, 798, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x56 - 1366x768@60Hz */
331 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
332 1436, 1500, 0, 768, 769, 772, 800, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x29 - 1400x1050@60Hz RB */
335 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
336 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x2a - 1400x1050@60Hz */
339 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
340 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x2b - 1400x1050@75Hz */
343 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
344 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x2c - 1400x1050@85Hz */
347 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
348 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x2d - 1400x1050@120Hz RB */
351 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
352 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x2e - 1440x900@60Hz RB */
355 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
356 1520, 1600, 0, 900, 903, 909, 926, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
358 /* 0x2f - 1440x900@60Hz */
359 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
360 1672, 1904, 0, 900, 903, 909, 934, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x30 - 1440x900@75Hz */
363 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
364 1688, 1936, 0, 900, 903, 909, 942, 0,
365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x31 - 1440x900@85Hz */
367 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
368 1696, 1952, 0, 900, 903, 909, 948, 0,
369 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x32 - 1440x900@120Hz RB */
371 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
372 1520, 1600, 0, 900, 903, 909, 953, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x53 - 1600x900@60Hz */
375 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
376 1704, 1800, 0, 900, 901, 904, 1000, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x33 - 1600x1200@60Hz */
379 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
380 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x34 - 1600x1200@65Hz */
383 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
384 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x35 - 1600x1200@70Hz */
387 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
388 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x36 - 1600x1200@75Hz */
391 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
392 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x37 - 1600x1200@85Hz */
395 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
396 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x38 - 1600x1200@120Hz RB */
399 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
400 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x39 - 1680x1050@60Hz RB */
403 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
404 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
406 /* 0x3a - 1680x1050@60Hz */
407 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
408 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x3b - 1680x1050@75Hz */
411 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
412 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x3c - 1680x1050@85Hz */
415 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
416 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x3d - 1680x1050@120Hz RB */
419 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
420 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 0x3e - 1792x1344@60Hz */
423 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
424 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x3f - 1792x1344@75Hz */
427 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
428 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x40 - 1792x1344@120Hz RB */
431 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
432 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
434 /* 0x41 - 1856x1392@60Hz */
435 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
436 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x42 - 1856x1392@75Hz */
439 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
440 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x43 - 1856x1392@120Hz RB */
443 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
444 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
446 /* 0x52 - 1920x1080@60Hz */
447 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
448 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
450 /* 0x44 - 1920x1200@60Hz RB */
451 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
452 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
454 /* 0x45 - 1920x1200@60Hz */
455 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
456 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x46 - 1920x1200@75Hz */
459 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
460 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x47 - 1920x1200@85Hz */
463 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
464 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x48 - 1920x1200@120Hz RB */
467 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
468 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 /* 0x49 - 1920x1440@60Hz */
471 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
472 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x4a - 1920x1440@75Hz */
475 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
476 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x4b - 1920x1440@120Hz RB */
479 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
480 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x54 - 2048x1152@60Hz */
483 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
484 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x4c - 2560x1600@60Hz RB */
487 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
488 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
490 /* 0x4d - 2560x1600@60Hz */
491 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
492 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x4e - 2560x1600@75Hz */
495 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
496 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x4f - 2560x1600@85Hz */
499 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
500 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x50 - 2560x1600@120Hz RB */
503 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
504 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x57 - 4096x2160@60Hz RB */
507 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
508 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 0x58 - 4096x2160@59.94Hz RB */
511 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
512 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 };
515
516 /*
517 * These more or less come from the DMT spec. The 720x400 modes are
518 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
519 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
520 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
521 * mode.
522 *
523 * The DMT modes have been fact-checked; the rest are mild guesses.
524 */
525 static const struct drm_display_mode edid_est_modes[] = {
526 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
527 968, 1056, 0, 600, 601, 605, 628, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
529 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
530 896, 1024, 0, 600, 601, 603, 625, 0,
531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
533 720, 840, 0, 480, 481, 484, 500, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
535 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
536 704, 832, 0, 480, 489, 492, 520, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
538 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
539 768, 864, 0, 480, 483, 486, 525, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
541 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
542 752, 800, 0, 480, 490, 492, 525, 0,
543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
544 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
545 846, 900, 0, 400, 421, 423, 449, 0,
546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
547 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
548 846, 900, 0, 400, 412, 414, 449, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
550 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
551 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
553 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
554 1136, 1312, 0, 768, 769, 772, 800, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
556 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
557 1184, 1328, 0, 768, 771, 777, 806, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
559 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
560 1184, 1344, 0, 768, 771, 777, 806, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
562 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
563 1208, 1264, 0, 768, 768, 776, 817, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
565 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
566 928, 1152, 0, 624, 625, 628, 667, 0,
567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
568 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
569 896, 1056, 0, 600, 601, 604, 625, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
571 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
572 976, 1040, 0, 600, 637, 643, 666, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
574 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
575 1344, 1600, 0, 864, 865, 868, 900, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
577 };
578
579 struct minimode {
580 short w;
581 short h;
582 short r;
583 short rb;
584 };
585
586 static const struct minimode est3_modes[] = {
587 /* byte 6 */
588 { 640, 350, 85, 0 },
589 { 640, 400, 85, 0 },
590 { 720, 400, 85, 0 },
591 { 640, 480, 85, 0 },
592 { 848, 480, 60, 0 },
593 { 800, 600, 85, 0 },
594 { 1024, 768, 85, 0 },
595 { 1152, 864, 75, 0 },
596 /* byte 7 */
597 { 1280, 768, 60, 1 },
598 { 1280, 768, 60, 0 },
599 { 1280, 768, 75, 0 },
600 { 1280, 768, 85, 0 },
601 { 1280, 960, 60, 0 },
602 { 1280, 960, 85, 0 },
603 { 1280, 1024, 60, 0 },
604 { 1280, 1024, 85, 0 },
605 /* byte 8 */
606 { 1360, 768, 60, 0 },
607 { 1440, 900, 60, 1 },
608 { 1440, 900, 60, 0 },
609 { 1440, 900, 75, 0 },
610 { 1440, 900, 85, 0 },
611 { 1400, 1050, 60, 1 },
612 { 1400, 1050, 60, 0 },
613 { 1400, 1050, 75, 0 },
614 /* byte 9 */
615 { 1400, 1050, 85, 0 },
616 { 1680, 1050, 60, 1 },
617 { 1680, 1050, 60, 0 },
618 { 1680, 1050, 75, 0 },
619 { 1680, 1050, 85, 0 },
620 { 1600, 1200, 60, 0 },
621 { 1600, 1200, 65, 0 },
622 { 1600, 1200, 70, 0 },
623 /* byte 10 */
624 { 1600, 1200, 75, 0 },
625 { 1600, 1200, 85, 0 },
626 { 1792, 1344, 60, 0 },
627 { 1792, 1344, 75, 0 },
628 { 1856, 1392, 60, 0 },
629 { 1856, 1392, 75, 0 },
630 { 1920, 1200, 60, 1 },
631 { 1920, 1200, 60, 0 },
632 /* byte 11 */
633 { 1920, 1200, 75, 0 },
634 { 1920, 1200, 85, 0 },
635 { 1920, 1440, 60, 0 },
636 { 1920, 1440, 75, 0 },
637 };
638
639 static const struct minimode extra_modes[] = {
640 { 1024, 576, 60, 0 },
641 { 1366, 768, 60, 0 },
642 { 1600, 900, 60, 0 },
643 { 1680, 945, 60, 0 },
644 { 1920, 1080, 60, 0 },
645 { 2048, 1152, 60, 0 },
646 { 2048, 1536, 60, 0 },
647 };
648
649 /*
650 * Probably taken from CEA-861 spec.
651 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
652 *
653 * Index using the VIC.
654 */
655 static const struct drm_display_mode edid_cea_modes[] = {
656 /* 0 - dummy, VICs start at 1 */
657 { },
658 /* 1 - 640x480@60Hz */
659 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
660 752, 800, 0, 480, 490, 492, 525, 0,
661 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
662 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
663 /* 2 - 720x480@60Hz */
664 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
665 798, 858, 0, 480, 489, 495, 525, 0,
666 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
667 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
668 /* 3 - 720x480@60Hz */
669 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
670 798, 858, 0, 480, 489, 495, 525, 0,
671 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
672 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
673 /* 4 - 1280x720@60Hz */
674 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
675 1430, 1650, 0, 720, 725, 730, 750, 0,
676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
677 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
678 /* 5 - 1920x1080i@60Hz */
679 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
680 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
681 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
682 DRM_MODE_FLAG_INTERLACE),
683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
684 /* 6 - 720(1440)x480i@60Hz */
685 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
686 801, 858, 0, 480, 488, 494, 525, 0,
687 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
688 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
689 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
690 /* 7 - 720(1440)x480i@60Hz */
691 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
692 801, 858, 0, 480, 488, 494, 525, 0,
693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
694 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
696 /* 8 - 720(1440)x240@60Hz */
697 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
698 801, 858, 0, 240, 244, 247, 262, 0,
699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
700 DRM_MODE_FLAG_DBLCLK),
701 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
702 /* 9 - 720(1440)x240@60Hz */
703 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
704 801, 858, 0, 240, 244, 247, 262, 0,
705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
706 DRM_MODE_FLAG_DBLCLK),
707 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
708 /* 10 - 2880x480i@60Hz */
709 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
710 3204, 3432, 0, 480, 488, 494, 525, 0,
711 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
712 DRM_MODE_FLAG_INTERLACE),
713 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
714 /* 11 - 2880x480i@60Hz */
715 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
716 3204, 3432, 0, 480, 488, 494, 525, 0,
717 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
718 DRM_MODE_FLAG_INTERLACE),
719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
720 /* 12 - 2880x240@60Hz */
721 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
722 3204, 3432, 0, 240, 244, 247, 262, 0,
723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
724 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
725 /* 13 - 2880x240@60Hz */
726 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
727 3204, 3432, 0, 240, 244, 247, 262, 0,
728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
729 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
730 /* 14 - 1440x480@60Hz */
731 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
732 1596, 1716, 0, 480, 489, 495, 525, 0,
733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
735 /* 15 - 1440x480@60Hz */
736 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
737 1596, 1716, 0, 480, 489, 495, 525, 0,
738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
739 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
740 /* 16 - 1920x1080@60Hz */
741 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
742 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
744 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
745 /* 17 - 720x576@50Hz */
746 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
747 796, 864, 0, 576, 581, 586, 625, 0,
748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
749 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
750 /* 18 - 720x576@50Hz */
751 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
752 796, 864, 0, 576, 581, 586, 625, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
754 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
755 /* 19 - 1280x720@50Hz */
756 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
757 1760, 1980, 0, 720, 725, 730, 750, 0,
758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
759 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
760 /* 20 - 1920x1080i@50Hz */
761 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
762 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
763 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
764 DRM_MODE_FLAG_INTERLACE),
765 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
766 /* 21 - 720(1440)x576i@50Hz */
767 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
768 795, 864, 0, 576, 580, 586, 625, 0,
769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
770 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
771 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
772 /* 22 - 720(1440)x576i@50Hz */
773 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
774 795, 864, 0, 576, 580, 586, 625, 0,
775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
776 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
778 /* 23 - 720(1440)x288@50Hz */
779 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
780 795, 864, 0, 288, 290, 293, 312, 0,
781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
782 DRM_MODE_FLAG_DBLCLK),
783 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
784 /* 24 - 720(1440)x288@50Hz */
785 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
786 795, 864, 0, 288, 290, 293, 312, 0,
787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
788 DRM_MODE_FLAG_DBLCLK),
789 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
790 /* 25 - 2880x576i@50Hz */
791 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
792 3180, 3456, 0, 576, 580, 586, 625, 0,
793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
794 DRM_MODE_FLAG_INTERLACE),
795 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
796 /* 26 - 2880x576i@50Hz */
797 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
798 3180, 3456, 0, 576, 580, 586, 625, 0,
799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
800 DRM_MODE_FLAG_INTERLACE),
801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
802 /* 27 - 2880x288@50Hz */
803 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
804 3180, 3456, 0, 288, 290, 293, 312, 0,
805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
806 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
807 /* 28 - 2880x288@50Hz */
808 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
809 3180, 3456, 0, 288, 290, 293, 312, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
811 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
812 /* 29 - 1440x576@50Hz */
813 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
814 1592, 1728, 0, 576, 581, 586, 625, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
817 /* 30 - 1440x576@50Hz */
818 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
819 1592, 1728, 0, 576, 581, 586, 625, 0,
820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
821 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 31 - 1920x1080@50Hz */
823 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
824 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
826 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
827 /* 32 - 1920x1080@24Hz */
828 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
829 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
831 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 33 - 1920x1080@25Hz */
833 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
834 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
836 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
837 /* 34 - 1920x1080@30Hz */
838 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
839 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
841 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
842 /* 35 - 2880x480@60Hz */
843 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
844 3192, 3432, 0, 480, 489, 495, 525, 0,
845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
846 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
847 /* 36 - 2880x480@60Hz */
848 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
849 3192, 3432, 0, 480, 489, 495, 525, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
851 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
852 /* 37 - 2880x576@50Hz */
853 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
854 3184, 3456, 0, 576, 581, 586, 625, 0,
855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
856 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
857 /* 38 - 2880x576@50Hz */
858 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
859 3184, 3456, 0, 576, 581, 586, 625, 0,
860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
862 /* 39 - 1920x1080i@50Hz */
863 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
864 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
866 DRM_MODE_FLAG_INTERLACE),
867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
868 /* 40 - 1920x1080i@100Hz */
869 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
870 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
872 DRM_MODE_FLAG_INTERLACE),
873 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
874 /* 41 - 1280x720@100Hz */
875 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
876 1760, 1980, 0, 720, 725, 730, 750, 0,
877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
878 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
879 /* 42 - 720x576@100Hz */
880 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
881 796, 864, 0, 576, 581, 586, 625, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
883 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
884 /* 43 - 720x576@100Hz */
885 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
886 796, 864, 0, 576, 581, 586, 625, 0,
887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
888 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
889 /* 44 - 720(1440)x576i@100Hz */
890 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
891 795, 864, 0, 576, 580, 586, 625, 0,
892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
893 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
895 /* 45 - 720(1440)x576i@100Hz */
896 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
897 795, 864, 0, 576, 580, 586, 625, 0,
898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
899 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
900 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 46 - 1920x1080i@120Hz */
902 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
903 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
905 DRM_MODE_FLAG_INTERLACE),
906 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
907 /* 47 - 1280x720@120Hz */
908 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
909 1430, 1650, 0, 720, 725, 730, 750, 0,
910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
911 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912 /* 48 - 720x480@120Hz */
913 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
914 798, 858, 0, 480, 489, 495, 525, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
916 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
917 /* 49 - 720x480@120Hz */
918 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
919 798, 858, 0, 480, 489, 495, 525, 0,
920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
921 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 50 - 720(1440)x480i@120Hz */
923 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
924 801, 858, 0, 480, 488, 494, 525, 0,
925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
926 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
928 /* 51 - 720(1440)x480i@120Hz */
929 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
930 801, 858, 0, 480, 488, 494, 525, 0,
931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
932 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
933 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 52 - 720x576@200Hz */
935 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
936 796, 864, 0, 576, 581, 586, 625, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
938 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
939 /* 53 - 720x576@200Hz */
940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
941 796, 864, 0, 576, 581, 586, 625, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
944 /* 54 - 720(1440)x576i@200Hz */
945 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
946 795, 864, 0, 576, 580, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
948 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
949 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
950 /* 55 - 720(1440)x576i@200Hz */
951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
952 795, 864, 0, 576, 580, 586, 625, 0,
953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
955 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
956 /* 56 - 720x480@240Hz */
957 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
958 798, 858, 0, 480, 489, 495, 525, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
960 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
961 /* 57 - 720x480@240Hz */
962 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
963 798, 858, 0, 480, 489, 495, 525, 0,
964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
965 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
966 /* 58 - 720(1440)x480i@240Hz */
967 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
968 801, 858, 0, 480, 488, 494, 525, 0,
969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
971 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
972 /* 59 - 720(1440)x480i@240Hz */
973 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
974 801, 858, 0, 480, 488, 494, 525, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
977 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978 /* 60 - 1280x720@24Hz */
979 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
980 3080, 3300, 0, 720, 725, 730, 750, 0,
981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
982 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
983 /* 61 - 1280x720@25Hz */
984 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
985 3740, 3960, 0, 720, 725, 730, 750, 0,
986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
987 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
988 /* 62 - 1280x720@30Hz */
989 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
990 3080, 3300, 0, 720, 725, 730, 750, 0,
991 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
992 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
993 /* 63 - 1920x1080@120Hz */
994 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
995 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
997 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
998 /* 64 - 1920x1080@100Hz */
999 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1000 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1001 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1002 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1003 };
1004
1005 /*
1006 * HDMI 1.4 4k modes. Index using the VIC.
1007 */
1008 static const struct drm_display_mode edid_4k_modes[] = {
1009 /* 0 - dummy, VICs start at 1 */
1010 { },
1011 /* 1 - 3840x2160@30Hz */
1012 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1013 3840, 4016, 4104, 4400, 0,
1014 2160, 2168, 2178, 2250, 0,
1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1016 .vrefresh = 30, },
1017 /* 2 - 3840x2160@25Hz */
1018 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1019 3840, 4896, 4984, 5280, 0,
1020 2160, 2168, 2178, 2250, 0,
1021 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1022 .vrefresh = 25, },
1023 /* 3 - 3840x2160@24Hz */
1024 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1025 3840, 5116, 5204, 5500, 0,
1026 2160, 2168, 2178, 2250, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 24, },
1029 /* 4 - 4096x2160@24Hz (SMPTE) */
1030 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1031 4096, 5116, 5204, 5500, 0,
1032 2160, 2168, 2178, 2250, 0,
1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1034 .vrefresh = 24, },
1035 };
1036
1037 /*** DDC fetch and block validation ***/
1038
1039 static const u8 edid_header[] = {
1040 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1041 };
1042
1043 /**
1044 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1045 * @raw_edid: pointer to raw base EDID block
1046 *
1047 * Sanity check the header of the base EDID block.
1048 *
1049 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1050 */
1051 int drm_edid_header_is_valid(const u8 *raw_edid)
1052 {
1053 int i, score = 0;
1054
1055 for (i = 0; i < sizeof(edid_header); i++)
1056 if (raw_edid[i] == edid_header[i])
1057 score++;
1058
1059 return score;
1060 }
1061 EXPORT_SYMBOL(drm_edid_header_is_valid);
1062
1063 static int edid_fixup __read_mostly = 6;
1064 module_param_named(edid_fixup, edid_fixup, int, 0400);
1065 MODULE_PARM_DESC(edid_fixup,
1066 "Minimum number of valid EDID header bytes (0-8, default 6)");
1067
1068 static void drm_get_displayid(struct drm_connector *connector,
1069 struct edid *edid);
1070
1071 static int drm_edid_block_checksum(const u8 *raw_edid)
1072 {
1073 int i;
1074 u8 csum = 0;
1075 for (i = 0; i < EDID_LENGTH; i++)
1076 csum += raw_edid[i];
1077
1078 return csum;
1079 }
1080
1081 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1082 {
1083 if (memchr_inv(in_edid, 0, length))
1084 return false;
1085
1086 return true;
1087 }
1088
1089 /**
1090 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1091 * @raw_edid: pointer to raw EDID block
1092 * @block: type of block to validate (0 for base, extension otherwise)
1093 * @print_bad_edid: if true, dump bad EDID blocks to the console
1094 * @edid_corrupt: if true, the header or checksum is invalid
1095 *
1096 * Validate a base or extension EDID block and optionally dump bad blocks to
1097 * the console.
1098 *
1099 * Return: True if the block is valid, false otherwise.
1100 */
1101 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1102 bool *edid_corrupt)
1103 {
1104 u8 csum;
1105 struct edid *edid = (struct edid *)raw_edid;
1106
1107 if (WARN_ON(!raw_edid))
1108 return false;
1109
1110 if (edid_fixup > 8 || edid_fixup < 0)
1111 edid_fixup = 6;
1112
1113 if (block == 0) {
1114 int score = drm_edid_header_is_valid(raw_edid);
1115 if (score == 8) {
1116 if (edid_corrupt)
1117 *edid_corrupt = false;
1118 } else if (score >= edid_fixup) {
1119 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1120 * The corrupt flag needs to be set here otherwise, the
1121 * fix-up code here will correct the problem, the
1122 * checksum is correct and the test fails
1123 */
1124 if (edid_corrupt)
1125 *edid_corrupt = true;
1126 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1127 memcpy(raw_edid, edid_header, sizeof(edid_header));
1128 } else {
1129 if (edid_corrupt)
1130 *edid_corrupt = true;
1131 goto bad;
1132 }
1133 }
1134
1135 csum = drm_edid_block_checksum(raw_edid);
1136 if (csum) {
1137 if (print_bad_edid) {
1138 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1139 }
1140
1141 if (edid_corrupt)
1142 *edid_corrupt = true;
1143
1144 /* allow CEA to slide through, switches mangle this */
1145 if (raw_edid[0] != 0x02)
1146 goto bad;
1147 }
1148
1149 /* per-block-type checks */
1150 switch (raw_edid[0]) {
1151 case 0: /* base */
1152 if (edid->version != 1) {
1153 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1154 goto bad;
1155 }
1156
1157 if (edid->revision > 4)
1158 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1159 break;
1160
1161 default:
1162 break;
1163 }
1164
1165 return true;
1166
1167 bad:
1168 if (print_bad_edid) {
1169 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1170 printk(KERN_ERR "EDID block is all zeroes\n");
1171 } else {
1172 printk(KERN_ERR "Raw EDID:\n");
1173 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1174 raw_edid, EDID_LENGTH, false);
1175 }
1176 }
1177 return false;
1178 }
1179 EXPORT_SYMBOL(drm_edid_block_valid);
1180
1181 /**
1182 * drm_edid_is_valid - sanity check EDID data
1183 * @edid: EDID data
1184 *
1185 * Sanity-check an entire EDID record (including extensions)
1186 *
1187 * Return: True if the EDID data is valid, false otherwise.
1188 */
1189 bool drm_edid_is_valid(struct edid *edid)
1190 {
1191 int i;
1192 u8 *raw = (u8 *)edid;
1193
1194 if (!edid)
1195 return false;
1196
1197 for (i = 0; i <= edid->extensions; i++)
1198 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1199 return false;
1200
1201 return true;
1202 }
1203 EXPORT_SYMBOL(drm_edid_is_valid);
1204
1205 #define DDC_SEGMENT_ADDR 0x30
1206 /**
1207 * drm_do_probe_ddc_edid() - get EDID information via I2C
1208 * @data: I2C device adapter
1209 * @buf: EDID data buffer to be filled
1210 * @block: 128 byte EDID block to start fetching from
1211 * @len: EDID data buffer length to fetch
1212 *
1213 * Try to fetch EDID information by calling I2C driver functions.
1214 *
1215 * Return: 0 on success or -1 on failure.
1216 */
1217 static int
1218 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1219 {
1220 struct i2c_adapter *adapter = data;
1221 unsigned char start = block * EDID_LENGTH;
1222 unsigned char segment = block >> 1;
1223 unsigned char xfers = segment ? 3 : 2;
1224 int ret, retries = 5;
1225
1226 /*
1227 * The core I2C driver will automatically retry the transfer if the
1228 * adapter reports EAGAIN. However, we find that bit-banging transfers
1229 * are susceptible to errors under a heavily loaded machine and
1230 * generate spurious NAKs and timeouts. Retrying the transfer
1231 * of the individual block a few times seems to overcome this.
1232 */
1233 do {
1234 struct i2c_msg msgs[] = {
1235 {
1236 .addr = DDC_SEGMENT_ADDR,
1237 .flags = 0,
1238 .len = 1,
1239 .buf = &segment,
1240 }, {
1241 .addr = DDC_ADDR,
1242 .flags = 0,
1243 .len = 1,
1244 .buf = &start,
1245 }, {
1246 .addr = DDC_ADDR,
1247 .flags = I2C_M_RD,
1248 .len = len,
1249 .buf = buf,
1250 }
1251 };
1252
1253 /*
1254 * Avoid sending the segment addr to not upset non-compliant
1255 * DDC monitors.
1256 */
1257 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1258
1259 if (ret == -ENXIO) {
1260 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1261 adapter->name);
1262 break;
1263 }
1264 } while (ret != xfers && --retries);
1265
1266 return ret == xfers ? 0 : -1;
1267 }
1268
1269 static void connector_bad_edid(struct drm_connector *connector,
1270 u8 *edid, int num_blocks)
1271 {
1272 int i;
1273
1274 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1275 return;
1276
1277 dev_warn(connector->dev->dev,
1278 "%s: EDID is invalid:\n",
1279 connector->name);
1280 for (i = 0; i < num_blocks; i++) {
1281 u8 *block = edid + i * EDID_LENGTH;
1282 char prefix[20];
1283
1284 if (drm_edid_is_zero(block, EDID_LENGTH))
1285 sprintf(prefix, "\t[%02x] ZERO ", i);
1286 else if (!drm_edid_block_valid(block, i, false, NULL))
1287 sprintf(prefix, "\t[%02x] BAD ", i);
1288 else
1289 sprintf(prefix, "\t[%02x] GOOD ", i);
1290
1291 print_hex_dump(KERN_WARNING,
1292 prefix, DUMP_PREFIX_NONE, 16, 1,
1293 block, EDID_LENGTH, false);
1294 }
1295 }
1296
1297 /**
1298 * drm_do_get_edid - get EDID data using a custom EDID block read function
1299 * @connector: connector we're probing
1300 * @get_edid_block: EDID block read function
1301 * @data: private data passed to the block read function
1302 *
1303 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1304 * exposes a different interface to read EDID blocks this function can be used
1305 * to get EDID data using a custom block read function.
1306 *
1307 * As in the general case the DDC bus is accessible by the kernel at the I2C
1308 * level, drivers must make all reasonable efforts to expose it as an I2C
1309 * adapter and use drm_get_edid() instead of abusing this function.
1310 *
1311 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1312 */
1313 struct edid *drm_do_get_edid(struct drm_connector *connector,
1314 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1315 size_t len),
1316 void *data)
1317 {
1318 int i, j = 0, valid_extensions = 0;
1319 u8 *edid, *new;
1320
1321 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1322 return NULL;
1323
1324 /* base block fetch */
1325 for (i = 0; i < 4; i++) {
1326 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1327 goto out;
1328 if (drm_edid_block_valid(edid, 0, false,
1329 &connector->edid_corrupt))
1330 break;
1331 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1332 connector->null_edid_counter++;
1333 goto carp;
1334 }
1335 }
1336 if (i == 4)
1337 goto carp;
1338
1339 /* if there's no extensions, we're done */
1340 valid_extensions = edid[0x7e];
1341 if (valid_extensions == 0)
1342 return (struct edid *)edid;
1343
1344 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1345 if (!new)
1346 goto out;
1347 edid = new;
1348
1349 for (j = 1; j <= edid[0x7e]; j++) {
1350 u8 *block = edid + j * EDID_LENGTH;
1351
1352 for (i = 0; i < 4; i++) {
1353 if (get_edid_block(data, block, j, EDID_LENGTH))
1354 goto out;
1355 if (drm_edid_block_valid(block, j, false, NULL))
1356 break;
1357 }
1358
1359 if (i == 4)
1360 valid_extensions--;
1361 }
1362
1363 if (valid_extensions != edid[0x7e]) {
1364 u8 *base;
1365
1366 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1367
1368 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1369 edid[0x7e] = valid_extensions;
1370
1371 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1372 if (!new)
1373 goto out;
1374
1375 base = new;
1376 for (i = 0; i <= edid[0x7e]; i++) {
1377 u8 *block = edid + i * EDID_LENGTH;
1378
1379 if (!drm_edid_block_valid(block, i, false, NULL))
1380 continue;
1381
1382 memcpy(base, block, EDID_LENGTH);
1383 base += EDID_LENGTH;
1384 }
1385
1386 kfree(edid);
1387 edid = new;
1388 }
1389
1390 return (struct edid *)edid;
1391
1392 carp:
1393 connector_bad_edid(connector, edid, 1);
1394 out:
1395 kfree(edid);
1396 return NULL;
1397 }
1398 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1399
1400 /**
1401 * drm_probe_ddc() - probe DDC presence
1402 * @adapter: I2C adapter to probe
1403 *
1404 * Return: True on success, false on failure.
1405 */
1406 bool
1407 drm_probe_ddc(struct i2c_adapter *adapter)
1408 {
1409 unsigned char out;
1410
1411 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1412 }
1413 EXPORT_SYMBOL(drm_probe_ddc);
1414
1415 /**
1416 * drm_get_edid - get EDID data, if available
1417 * @connector: connector we're probing
1418 * @adapter: I2C adapter to use for DDC
1419 *
1420 * Poke the given I2C channel to grab EDID data if possible. If found,
1421 * attach it to the connector.
1422 *
1423 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1424 */
1425 struct edid *drm_get_edid(struct drm_connector *connector,
1426 struct i2c_adapter *adapter)
1427 {
1428 struct edid *edid;
1429
1430 if (!drm_probe_ddc(adapter))
1431 return NULL;
1432
1433 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1434 if (edid)
1435 drm_get_displayid(connector, edid);
1436 return edid;
1437 }
1438 EXPORT_SYMBOL(drm_get_edid);
1439
1440 /**
1441 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1442 * @connector: connector we're probing
1443 * @adapter: I2C adapter to use for DDC
1444 *
1445 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1446 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1447 * switch DDC to the GPU which is retrieving EDID.
1448 *
1449 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1450 */
1451 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1452 struct i2c_adapter *adapter)
1453 {
1454 struct pci_dev *pdev = connector->dev->pdev;
1455 struct edid *edid;
1456
1457 vga_switcheroo_lock_ddc(pdev);
1458 edid = drm_get_edid(connector, adapter);
1459 vga_switcheroo_unlock_ddc(pdev);
1460
1461 return edid;
1462 }
1463 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1464
1465 /**
1466 * drm_edid_duplicate - duplicate an EDID and the extensions
1467 * @edid: EDID to duplicate
1468 *
1469 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1470 */
1471 struct edid *drm_edid_duplicate(const struct edid *edid)
1472 {
1473 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1474 }
1475 EXPORT_SYMBOL(drm_edid_duplicate);
1476
1477 /*** EDID parsing ***/
1478
1479 /**
1480 * edid_vendor - match a string against EDID's obfuscated vendor field
1481 * @edid: EDID to match
1482 * @vendor: vendor string
1483 *
1484 * Returns true if @vendor is in @edid, false otherwise
1485 */
1486 static bool edid_vendor(struct edid *edid, const char *vendor)
1487 {
1488 char edid_vendor[3];
1489
1490 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1491 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1492 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1493 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1494
1495 return !strncmp(edid_vendor, vendor, 3);
1496 }
1497
1498 /**
1499 * edid_get_quirks - return quirk flags for a given EDID
1500 * @edid: EDID to process
1501 *
1502 * This tells subsequent routines what fixes they need to apply.
1503 */
1504 static u32 edid_get_quirks(struct edid *edid)
1505 {
1506 const struct edid_quirk *quirk;
1507 int i;
1508
1509 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1510 quirk = &edid_quirk_list[i];
1511
1512 if (edid_vendor(edid, quirk->vendor) &&
1513 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1514 return quirk->quirks;
1515 }
1516
1517 return 0;
1518 }
1519
1520 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1521 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1522
1523 /**
1524 * edid_fixup_preferred - set preferred modes based on quirk list
1525 * @connector: has mode list to fix up
1526 * @quirks: quirks list
1527 *
1528 * Walk the mode list for @connector, clearing the preferred status
1529 * on existing modes and setting it anew for the right mode ala @quirks.
1530 */
1531 static void edid_fixup_preferred(struct drm_connector *connector,
1532 u32 quirks)
1533 {
1534 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1535 int target_refresh = 0;
1536 int cur_vrefresh, preferred_vrefresh;
1537
1538 if (list_empty(&connector->probed_modes))
1539 return;
1540
1541 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1542 target_refresh = 60;
1543 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1544 target_refresh = 75;
1545
1546 preferred_mode = list_first_entry(&connector->probed_modes,
1547 struct drm_display_mode, head);
1548
1549 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1550 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1551
1552 if (cur_mode == preferred_mode)
1553 continue;
1554
1555 /* Largest mode is preferred */
1556 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1557 preferred_mode = cur_mode;
1558
1559 cur_vrefresh = cur_mode->vrefresh ?
1560 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1561 preferred_vrefresh = preferred_mode->vrefresh ?
1562 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1563 /* At a given size, try to get closest to target refresh */
1564 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1565 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1566 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1567 preferred_mode = cur_mode;
1568 }
1569 }
1570
1571 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1572 }
1573
1574 static bool
1575 mode_is_rb(const struct drm_display_mode *mode)
1576 {
1577 return (mode->htotal - mode->hdisplay == 160) &&
1578 (mode->hsync_end - mode->hdisplay == 80) &&
1579 (mode->hsync_end - mode->hsync_start == 32) &&
1580 (mode->vsync_start - mode->vdisplay == 3);
1581 }
1582
1583 /*
1584 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1585 * @dev: Device to duplicate against
1586 * @hsize: Mode width
1587 * @vsize: Mode height
1588 * @fresh: Mode refresh rate
1589 * @rb: Mode reduced-blanking-ness
1590 *
1591 * Walk the DMT mode list looking for a match for the given parameters.
1592 *
1593 * Return: A newly allocated copy of the mode, or NULL if not found.
1594 */
1595 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1596 int hsize, int vsize, int fresh,
1597 bool rb)
1598 {
1599 int i;
1600
1601 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1602 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1603 if (hsize != ptr->hdisplay)
1604 continue;
1605 if (vsize != ptr->vdisplay)
1606 continue;
1607 if (fresh != drm_mode_vrefresh(ptr))
1608 continue;
1609 if (rb != mode_is_rb(ptr))
1610 continue;
1611
1612 return drm_mode_duplicate(dev, ptr);
1613 }
1614
1615 return NULL;
1616 }
1617 EXPORT_SYMBOL(drm_mode_find_dmt);
1618
1619 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1620
1621 static void
1622 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1623 {
1624 int i, n = 0;
1625 u8 d = ext[0x02];
1626 u8 *det_base = ext + d;
1627
1628 n = (127 - d) / 18;
1629 for (i = 0; i < n; i++)
1630 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1631 }
1632
1633 static void
1634 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1635 {
1636 unsigned int i, n = min((int)ext[0x02], 6);
1637 u8 *det_base = ext + 5;
1638
1639 if (ext[0x01] != 1)
1640 return; /* unknown version */
1641
1642 for (i = 0; i < n; i++)
1643 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1644 }
1645
1646 static void
1647 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1648 {
1649 int i;
1650 struct edid *edid = (struct edid *)raw_edid;
1651
1652 if (edid == NULL)
1653 return;
1654
1655 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1656 cb(&(edid->detailed_timings[i]), closure);
1657
1658 for (i = 1; i <= raw_edid[0x7e]; i++) {
1659 u8 *ext = raw_edid + (i * EDID_LENGTH);
1660 switch (*ext) {
1661 case CEA_EXT:
1662 cea_for_each_detailed_block(ext, cb, closure);
1663 break;
1664 case VTB_EXT:
1665 vtb_for_each_detailed_block(ext, cb, closure);
1666 break;
1667 default:
1668 break;
1669 }
1670 }
1671 }
1672
1673 static void
1674 is_rb(struct detailed_timing *t, void *data)
1675 {
1676 u8 *r = (u8 *)t;
1677 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1678 if (r[15] & 0x10)
1679 *(bool *)data = true;
1680 }
1681
1682 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1683 static bool
1684 drm_monitor_supports_rb(struct edid *edid)
1685 {
1686 if (edid->revision >= 4) {
1687 bool ret = false;
1688 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1689 return ret;
1690 }
1691
1692 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1693 }
1694
1695 static void
1696 find_gtf2(struct detailed_timing *t, void *data)
1697 {
1698 u8 *r = (u8 *)t;
1699 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1700 *(u8 **)data = r;
1701 }
1702
1703 /* Secondary GTF curve kicks in above some break frequency */
1704 static int
1705 drm_gtf2_hbreak(struct edid *edid)
1706 {
1707 u8 *r = NULL;
1708 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1709 return r ? (r[12] * 2) : 0;
1710 }
1711
1712 static int
1713 drm_gtf2_2c(struct edid *edid)
1714 {
1715 u8 *r = NULL;
1716 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1717 return r ? r[13] : 0;
1718 }
1719
1720 static int
1721 drm_gtf2_m(struct edid *edid)
1722 {
1723 u8 *r = NULL;
1724 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1725 return r ? (r[15] << 8) + r[14] : 0;
1726 }
1727
1728 static int
1729 drm_gtf2_k(struct edid *edid)
1730 {
1731 u8 *r = NULL;
1732 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1733 return r ? r[16] : 0;
1734 }
1735
1736 static int
1737 drm_gtf2_2j(struct edid *edid)
1738 {
1739 u8 *r = NULL;
1740 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1741 return r ? r[17] : 0;
1742 }
1743
1744 /**
1745 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1746 * @edid: EDID block to scan
1747 */
1748 static int standard_timing_level(struct edid *edid)
1749 {
1750 if (edid->revision >= 2) {
1751 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1752 return LEVEL_CVT;
1753 if (drm_gtf2_hbreak(edid))
1754 return LEVEL_GTF2;
1755 return LEVEL_GTF;
1756 }
1757 return LEVEL_DMT;
1758 }
1759
1760 /*
1761 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1762 * monitors fill with ascii space (0x20) instead.
1763 */
1764 static int
1765 bad_std_timing(u8 a, u8 b)
1766 {
1767 return (a == 0x00 && b == 0x00) ||
1768 (a == 0x01 && b == 0x01) ||
1769 (a == 0x20 && b == 0x20);
1770 }
1771
1772 /**
1773 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1774 * @connector: connector of for the EDID block
1775 * @edid: EDID block to scan
1776 * @t: standard timing params
1777 *
1778 * Take the standard timing params (in this case width, aspect, and refresh)
1779 * and convert them into a real mode using CVT/GTF/DMT.
1780 */
1781 static struct drm_display_mode *
1782 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1783 struct std_timing *t)
1784 {
1785 struct drm_device *dev = connector->dev;
1786 struct drm_display_mode *m, *mode = NULL;
1787 int hsize, vsize;
1788 int vrefresh_rate;
1789 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1790 >> EDID_TIMING_ASPECT_SHIFT;
1791 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1792 >> EDID_TIMING_VFREQ_SHIFT;
1793 int timing_level = standard_timing_level(edid);
1794
1795 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1796 return NULL;
1797
1798 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1799 hsize = t->hsize * 8 + 248;
1800 /* vrefresh_rate = vfreq + 60 */
1801 vrefresh_rate = vfreq + 60;
1802 /* the vdisplay is calculated based on the aspect ratio */
1803 if (aspect_ratio == 0) {
1804 if (edid->revision < 3)
1805 vsize = hsize;
1806 else
1807 vsize = (hsize * 10) / 16;
1808 } else if (aspect_ratio == 1)
1809 vsize = (hsize * 3) / 4;
1810 else if (aspect_ratio == 2)
1811 vsize = (hsize * 4) / 5;
1812 else
1813 vsize = (hsize * 9) / 16;
1814
1815 /* HDTV hack, part 1 */
1816 if (vrefresh_rate == 60 &&
1817 ((hsize == 1360 && vsize == 765) ||
1818 (hsize == 1368 && vsize == 769))) {
1819 hsize = 1366;
1820 vsize = 768;
1821 }
1822
1823 /*
1824 * If this connector already has a mode for this size and refresh
1825 * rate (because it came from detailed or CVT info), use that
1826 * instead. This way we don't have to guess at interlace or
1827 * reduced blanking.
1828 */
1829 list_for_each_entry(m, &connector->probed_modes, head)
1830 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1831 drm_mode_vrefresh(m) == vrefresh_rate)
1832 return NULL;
1833
1834 /* HDTV hack, part 2 */
1835 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1836 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1837 false);
1838 mode->hdisplay = 1366;
1839 mode->hsync_start = mode->hsync_start - 1;
1840 mode->hsync_end = mode->hsync_end - 1;
1841 return mode;
1842 }
1843
1844 /* check whether it can be found in default mode table */
1845 if (drm_monitor_supports_rb(edid)) {
1846 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1847 true);
1848 if (mode)
1849 return mode;
1850 }
1851 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1852 if (mode)
1853 return mode;
1854
1855 /* okay, generate it */
1856 switch (timing_level) {
1857 case LEVEL_DMT:
1858 break;
1859 case LEVEL_GTF:
1860 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1861 break;
1862 case LEVEL_GTF2:
1863 /*
1864 * This is potentially wrong if there's ever a monitor with
1865 * more than one ranges section, each claiming a different
1866 * secondary GTF curve. Please don't do that.
1867 */
1868 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1869 if (!mode)
1870 return NULL;
1871 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1872 drm_mode_destroy(dev, mode);
1873 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1874 vrefresh_rate, 0, 0,
1875 drm_gtf2_m(edid),
1876 drm_gtf2_2c(edid),
1877 drm_gtf2_k(edid),
1878 drm_gtf2_2j(edid));
1879 }
1880 break;
1881 case LEVEL_CVT:
1882 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1883 false);
1884 break;
1885 }
1886 return mode;
1887 }
1888
1889 /*
1890 * EDID is delightfully ambiguous about how interlaced modes are to be
1891 * encoded. Our internal representation is of frame height, but some
1892 * HDTV detailed timings are encoded as field height.
1893 *
1894 * The format list here is from CEA, in frame size. Technically we
1895 * should be checking refresh rate too. Whatever.
1896 */
1897 static void
1898 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1899 struct detailed_pixel_timing *pt)
1900 {
1901 int i;
1902 static const struct {
1903 int w, h;
1904 } cea_interlaced[] = {
1905 { 1920, 1080 },
1906 { 720, 480 },
1907 { 1440, 480 },
1908 { 2880, 480 },
1909 { 720, 576 },
1910 { 1440, 576 },
1911 { 2880, 576 },
1912 };
1913
1914 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1915 return;
1916
1917 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1918 if ((mode->hdisplay == cea_interlaced[i].w) &&
1919 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1920 mode->vdisplay *= 2;
1921 mode->vsync_start *= 2;
1922 mode->vsync_end *= 2;
1923 mode->vtotal *= 2;
1924 mode->vtotal |= 1;
1925 }
1926 }
1927
1928 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1929 }
1930
1931 /**
1932 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1933 * @dev: DRM device (needed to create new mode)
1934 * @edid: EDID block
1935 * @timing: EDID detailed timing info
1936 * @quirks: quirks to apply
1937 *
1938 * An EDID detailed timing block contains enough info for us to create and
1939 * return a new struct drm_display_mode.
1940 */
1941 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1942 struct edid *edid,
1943 struct detailed_timing *timing,
1944 u32 quirks)
1945 {
1946 struct drm_display_mode *mode;
1947 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
1948 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1949 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1950 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1951 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
1952 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1953 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1954 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
1955 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1956
1957 /* ignore tiny modes */
1958 if (hactive < 64 || vactive < 64)
1959 return NULL;
1960
1961 if (pt->misc & DRM_EDID_PT_STEREO) {
1962 DRM_DEBUG_KMS("stereo mode not supported\n");
1963 return NULL;
1964 }
1965 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
1966 DRM_DEBUG_KMS("composite sync not supported\n");
1967 }
1968
1969 /* it is incorrect if hsync/vsync width is zero */
1970 if (!hsync_pulse_width || !vsync_pulse_width) {
1971 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1972 "Wrong Hsync/Vsync pulse width\n");
1973 return NULL;
1974 }
1975
1976 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1977 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1978 if (!mode)
1979 return NULL;
1980
1981 goto set_size;
1982 }
1983
1984 mode = drm_mode_create(dev);
1985 if (!mode)
1986 return NULL;
1987
1988 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
1989 timing->pixel_clock = cpu_to_le16(1088);
1990
1991 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1992
1993 mode->hdisplay = hactive;
1994 mode->hsync_start = mode->hdisplay + hsync_offset;
1995 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1996 mode->htotal = mode->hdisplay + hblank;
1997
1998 mode->vdisplay = vactive;
1999 mode->vsync_start = mode->vdisplay + vsync_offset;
2000 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2001 mode->vtotal = mode->vdisplay + vblank;
2002
2003 /* Some EDIDs have bogus h/vtotal values */
2004 if (mode->hsync_end > mode->htotal)
2005 mode->htotal = mode->hsync_end + 1;
2006 if (mode->vsync_end > mode->vtotal)
2007 mode->vtotal = mode->vsync_end + 1;
2008
2009 drm_mode_do_interlace_quirk(mode, pt);
2010
2011 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2012 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2013 }
2014
2015 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2016 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2017 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2018 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2019
2020 set_size:
2021 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2022 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2023
2024 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2025 mode->width_mm *= 10;
2026 mode->height_mm *= 10;
2027 }
2028
2029 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2030 mode->width_mm = edid->width_cm * 10;
2031 mode->height_mm = edid->height_cm * 10;
2032 }
2033
2034 mode->type = DRM_MODE_TYPE_DRIVER;
2035 mode->vrefresh = drm_mode_vrefresh(mode);
2036 drm_mode_set_name(mode);
2037
2038 return mode;
2039 }
2040
2041 static bool
2042 mode_in_hsync_range(const struct drm_display_mode *mode,
2043 struct edid *edid, u8 *t)
2044 {
2045 int hsync, hmin, hmax;
2046
2047 hmin = t[7];
2048 if (edid->revision >= 4)
2049 hmin += ((t[4] & 0x04) ? 255 : 0);
2050 hmax = t[8];
2051 if (edid->revision >= 4)
2052 hmax += ((t[4] & 0x08) ? 255 : 0);
2053 hsync = drm_mode_hsync(mode);
2054
2055 return (hsync <= hmax && hsync >= hmin);
2056 }
2057
2058 static bool
2059 mode_in_vsync_range(const struct drm_display_mode *mode,
2060 struct edid *edid, u8 *t)
2061 {
2062 int vsync, vmin, vmax;
2063
2064 vmin = t[5];
2065 if (edid->revision >= 4)
2066 vmin += ((t[4] & 0x01) ? 255 : 0);
2067 vmax = t[6];
2068 if (edid->revision >= 4)
2069 vmax += ((t[4] & 0x02) ? 255 : 0);
2070 vsync = drm_mode_vrefresh(mode);
2071
2072 return (vsync <= vmax && vsync >= vmin);
2073 }
2074
2075 static u32
2076 range_pixel_clock(struct edid *edid, u8 *t)
2077 {
2078 /* unspecified */
2079 if (t[9] == 0 || t[9] == 255)
2080 return 0;
2081
2082 /* 1.4 with CVT support gives us real precision, yay */
2083 if (edid->revision >= 4 && t[10] == 0x04)
2084 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2085
2086 /* 1.3 is pathetic, so fuzz up a bit */
2087 return t[9] * 10000 + 5001;
2088 }
2089
2090 static bool
2091 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2092 struct detailed_timing *timing)
2093 {
2094 u32 max_clock;
2095 u8 *t = (u8 *)timing;
2096
2097 if (!mode_in_hsync_range(mode, edid, t))
2098 return false;
2099
2100 if (!mode_in_vsync_range(mode, edid, t))
2101 return false;
2102
2103 if ((max_clock = range_pixel_clock(edid, t)))
2104 if (mode->clock > max_clock)
2105 return false;
2106
2107 /* 1.4 max horizontal check */
2108 if (edid->revision >= 4 && t[10] == 0x04)
2109 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2110 return false;
2111
2112 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2113 return false;
2114
2115 return true;
2116 }
2117
2118 static bool valid_inferred_mode(const struct drm_connector *connector,
2119 const struct drm_display_mode *mode)
2120 {
2121 const struct drm_display_mode *m;
2122 bool ok = false;
2123
2124 list_for_each_entry(m, &connector->probed_modes, head) {
2125 if (mode->hdisplay == m->hdisplay &&
2126 mode->vdisplay == m->vdisplay &&
2127 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2128 return false; /* duplicated */
2129 if (mode->hdisplay <= m->hdisplay &&
2130 mode->vdisplay <= m->vdisplay)
2131 ok = true;
2132 }
2133 return ok;
2134 }
2135
2136 static int
2137 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2138 struct detailed_timing *timing)
2139 {
2140 int i, modes = 0;
2141 struct drm_display_mode *newmode;
2142 struct drm_device *dev = connector->dev;
2143
2144 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2145 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2146 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2147 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2148 if (newmode) {
2149 drm_mode_probed_add(connector, newmode);
2150 modes++;
2151 }
2152 }
2153 }
2154
2155 return modes;
2156 }
2157
2158 /* fix up 1366x768 mode from 1368x768;
2159 * GFT/CVT can't express 1366 width which isn't dividable by 8
2160 */
2161 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2162 {
2163 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2164 mode->hdisplay = 1366;
2165 mode->hsync_start--;
2166 mode->hsync_end--;
2167 drm_mode_set_name(mode);
2168 }
2169 }
2170
2171 static int
2172 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2173 struct detailed_timing *timing)
2174 {
2175 int i, modes = 0;
2176 struct drm_display_mode *newmode;
2177 struct drm_device *dev = connector->dev;
2178
2179 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2180 const struct minimode *m = &extra_modes[i];
2181 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2182 if (!newmode)
2183 return modes;
2184
2185 drm_mode_fixup_1366x768(newmode);
2186 if (!mode_in_range(newmode, edid, timing) ||
2187 !valid_inferred_mode(connector, newmode)) {
2188 drm_mode_destroy(dev, newmode);
2189 continue;
2190 }
2191
2192 drm_mode_probed_add(connector, newmode);
2193 modes++;
2194 }
2195
2196 return modes;
2197 }
2198
2199 static int
2200 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2201 struct detailed_timing *timing)
2202 {
2203 int i, modes = 0;
2204 struct drm_display_mode *newmode;
2205 struct drm_device *dev = connector->dev;
2206 bool rb = drm_monitor_supports_rb(edid);
2207
2208 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2209 const struct minimode *m = &extra_modes[i];
2210 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2211 if (!newmode)
2212 return modes;
2213
2214 drm_mode_fixup_1366x768(newmode);
2215 if (!mode_in_range(newmode, edid, timing) ||
2216 !valid_inferred_mode(connector, newmode)) {
2217 drm_mode_destroy(dev, newmode);
2218 continue;
2219 }
2220
2221 drm_mode_probed_add(connector, newmode);
2222 modes++;
2223 }
2224
2225 return modes;
2226 }
2227
2228 static void
2229 do_inferred_modes(struct detailed_timing *timing, void *c)
2230 {
2231 struct detailed_mode_closure *closure = c;
2232 struct detailed_non_pixel *data = &timing->data.other_data;
2233 struct detailed_data_monitor_range *range = &data->data.range;
2234
2235 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2236 return;
2237
2238 closure->modes += drm_dmt_modes_for_range(closure->connector,
2239 closure->edid,
2240 timing);
2241
2242 if (!version_greater(closure->edid, 1, 1))
2243 return; /* GTF not defined yet */
2244
2245 switch (range->flags) {
2246 case 0x02: /* secondary gtf, XXX could do more */
2247 case 0x00: /* default gtf */
2248 closure->modes += drm_gtf_modes_for_range(closure->connector,
2249 closure->edid,
2250 timing);
2251 break;
2252 case 0x04: /* cvt, only in 1.4+ */
2253 if (!version_greater(closure->edid, 1, 3))
2254 break;
2255
2256 closure->modes += drm_cvt_modes_for_range(closure->connector,
2257 closure->edid,
2258 timing);
2259 break;
2260 case 0x01: /* just the ranges, no formula */
2261 default:
2262 break;
2263 }
2264 }
2265
2266 static int
2267 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2268 {
2269 struct detailed_mode_closure closure = {
2270 .connector = connector,
2271 .edid = edid,
2272 };
2273
2274 if (version_greater(edid, 1, 0))
2275 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2276 &closure);
2277
2278 return closure.modes;
2279 }
2280
2281 static int
2282 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2283 {
2284 int i, j, m, modes = 0;
2285 struct drm_display_mode *mode;
2286 u8 *est = ((u8 *)timing) + 6;
2287
2288 for (i = 0; i < 6; i++) {
2289 for (j = 7; j >= 0; j--) {
2290 m = (i * 8) + (7 - j);
2291 if (m >= ARRAY_SIZE(est3_modes))
2292 break;
2293 if (est[i] & (1 << j)) {
2294 mode = drm_mode_find_dmt(connector->dev,
2295 est3_modes[m].w,
2296 est3_modes[m].h,
2297 est3_modes[m].r,
2298 est3_modes[m].rb);
2299 if (mode) {
2300 drm_mode_probed_add(connector, mode);
2301 modes++;
2302 }
2303 }
2304 }
2305 }
2306
2307 return modes;
2308 }
2309
2310 static void
2311 do_established_modes(struct detailed_timing *timing, void *c)
2312 {
2313 struct detailed_mode_closure *closure = c;
2314 struct detailed_non_pixel *data = &timing->data.other_data;
2315
2316 if (data->type == EDID_DETAIL_EST_TIMINGS)
2317 closure->modes += drm_est3_modes(closure->connector, timing);
2318 }
2319
2320 /**
2321 * add_established_modes - get est. modes from EDID and add them
2322 * @connector: connector to add mode(s) to
2323 * @edid: EDID block to scan
2324 *
2325 * Each EDID block contains a bitmap of the supported "established modes" list
2326 * (defined above). Tease them out and add them to the global modes list.
2327 */
2328 static int
2329 add_established_modes(struct drm_connector *connector, struct edid *edid)
2330 {
2331 struct drm_device *dev = connector->dev;
2332 unsigned long est_bits = edid->established_timings.t1 |
2333 (edid->established_timings.t2 << 8) |
2334 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2335 int i, modes = 0;
2336 struct detailed_mode_closure closure = {
2337 .connector = connector,
2338 .edid = edid,
2339 };
2340
2341 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2342 if (est_bits & (1<<i)) {
2343 struct drm_display_mode *newmode;
2344 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2345 if (newmode) {
2346 drm_mode_probed_add(connector, newmode);
2347 modes++;
2348 }
2349 }
2350 }
2351
2352 if (version_greater(edid, 1, 0))
2353 drm_for_each_detailed_block((u8 *)edid,
2354 do_established_modes, &closure);
2355
2356 return modes + closure.modes;
2357 }
2358
2359 static void
2360 do_standard_modes(struct detailed_timing *timing, void *c)
2361 {
2362 struct detailed_mode_closure *closure = c;
2363 struct detailed_non_pixel *data = &timing->data.other_data;
2364 struct drm_connector *connector = closure->connector;
2365 struct edid *edid = closure->edid;
2366
2367 if (data->type == EDID_DETAIL_STD_MODES) {
2368 int i;
2369 for (i = 0; i < 6; i++) {
2370 struct std_timing *std;
2371 struct drm_display_mode *newmode;
2372
2373 std = &data->data.timings[i];
2374 newmode = drm_mode_std(connector, edid, std);
2375 if (newmode) {
2376 drm_mode_probed_add(connector, newmode);
2377 closure->modes++;
2378 }
2379 }
2380 }
2381 }
2382
2383 /**
2384 * add_standard_modes - get std. modes from EDID and add them
2385 * @connector: connector to add mode(s) to
2386 * @edid: EDID block to scan
2387 *
2388 * Standard modes can be calculated using the appropriate standard (DMT,
2389 * GTF or CVT. Grab them from @edid and add them to the list.
2390 */
2391 static int
2392 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2393 {
2394 int i, modes = 0;
2395 struct detailed_mode_closure closure = {
2396 .connector = connector,
2397 .edid = edid,
2398 };
2399
2400 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2401 struct drm_display_mode *newmode;
2402
2403 newmode = drm_mode_std(connector, edid,
2404 &edid->standard_timings[i]);
2405 if (newmode) {
2406 drm_mode_probed_add(connector, newmode);
2407 modes++;
2408 }
2409 }
2410
2411 if (version_greater(edid, 1, 0))
2412 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2413 &closure);
2414
2415 /* XXX should also look for standard codes in VTB blocks */
2416
2417 return modes + closure.modes;
2418 }
2419
2420 static int drm_cvt_modes(struct drm_connector *connector,
2421 struct detailed_timing *timing)
2422 {
2423 int i, j, modes = 0;
2424 struct drm_display_mode *newmode;
2425 struct drm_device *dev = connector->dev;
2426 struct cvt_timing *cvt;
2427 const int rates[] = { 60, 85, 75, 60, 50 };
2428 const u8 empty[3] = { 0, 0, 0 };
2429
2430 for (i = 0; i < 4; i++) {
2431 int uninitialized_var(width), height;
2432 cvt = &(timing->data.other_data.data.cvt[i]);
2433
2434 if (!memcmp(cvt->code, empty, 3))
2435 continue;
2436
2437 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2438 switch (cvt->code[1] & 0x0c) {
2439 case 0x00:
2440 width = height * 4 / 3;
2441 break;
2442 case 0x04:
2443 width = height * 16 / 9;
2444 break;
2445 case 0x08:
2446 width = height * 16 / 10;
2447 break;
2448 case 0x0c:
2449 width = height * 15 / 9;
2450 break;
2451 }
2452
2453 for (j = 1; j < 5; j++) {
2454 if (cvt->code[2] & (1 << j)) {
2455 newmode = drm_cvt_mode(dev, width, height,
2456 rates[j], j == 0,
2457 false, false);
2458 if (newmode) {
2459 drm_mode_probed_add(connector, newmode);
2460 modes++;
2461 }
2462 }
2463 }
2464 }
2465
2466 return modes;
2467 }
2468
2469 static void
2470 do_cvt_mode(struct detailed_timing *timing, void *c)
2471 {
2472 struct detailed_mode_closure *closure = c;
2473 struct detailed_non_pixel *data = &timing->data.other_data;
2474
2475 if (data->type == EDID_DETAIL_CVT_3BYTE)
2476 closure->modes += drm_cvt_modes(closure->connector, timing);
2477 }
2478
2479 static int
2480 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2481 {
2482 struct detailed_mode_closure closure = {
2483 .connector = connector,
2484 .edid = edid,
2485 };
2486
2487 if (version_greater(edid, 1, 2))
2488 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2489
2490 /* XXX should also look for CVT codes in VTB blocks */
2491
2492 return closure.modes;
2493 }
2494
2495 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2496
2497 static void
2498 do_detailed_mode(struct detailed_timing *timing, void *c)
2499 {
2500 struct detailed_mode_closure *closure = c;
2501 struct drm_display_mode *newmode;
2502
2503 if (timing->pixel_clock) {
2504 newmode = drm_mode_detailed(closure->connector->dev,
2505 closure->edid, timing,
2506 closure->quirks);
2507 if (!newmode)
2508 return;
2509
2510 if (closure->preferred)
2511 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2512
2513 /*
2514 * Detailed modes are limited to 10kHz pixel clock resolution,
2515 * so fix up anything that looks like CEA/HDMI mode, but the clock
2516 * is just slightly off.
2517 */
2518 fixup_detailed_cea_mode_clock(newmode);
2519
2520 drm_mode_probed_add(closure->connector, newmode);
2521 closure->modes++;
2522 closure->preferred = 0;
2523 }
2524 }
2525
2526 /*
2527 * add_detailed_modes - Add modes from detailed timings
2528 * @connector: attached connector
2529 * @edid: EDID block to scan
2530 * @quirks: quirks to apply
2531 */
2532 static int
2533 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2534 u32 quirks)
2535 {
2536 struct detailed_mode_closure closure = {
2537 .connector = connector,
2538 .edid = edid,
2539 .preferred = 1,
2540 .quirks = quirks,
2541 };
2542
2543 if (closure.preferred && !version_greater(edid, 1, 3))
2544 closure.preferred =
2545 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2546
2547 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2548
2549 return closure.modes;
2550 }
2551
2552 #define AUDIO_BLOCK 0x01
2553 #define VIDEO_BLOCK 0x02
2554 #define VENDOR_BLOCK 0x03
2555 #define SPEAKER_BLOCK 0x04
2556 #define VIDEO_CAPABILITY_BLOCK 0x07
2557 #define EDID_BASIC_AUDIO (1 << 6)
2558 #define EDID_CEA_YCRCB444 (1 << 5)
2559 #define EDID_CEA_YCRCB422 (1 << 4)
2560 #define EDID_CEA_VCDB_QS (1 << 6)
2561
2562 /*
2563 * Search EDID for CEA extension block.
2564 */
2565 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2566 {
2567 u8 *edid_ext = NULL;
2568 int i;
2569
2570 /* No EDID or EDID extensions */
2571 if (edid == NULL || edid->extensions == 0)
2572 return NULL;
2573
2574 /* Find CEA extension */
2575 for (i = 0; i < edid->extensions; i++) {
2576 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2577 if (edid_ext[0] == ext_id)
2578 break;
2579 }
2580
2581 if (i == edid->extensions)
2582 return NULL;
2583
2584 return edid_ext;
2585 }
2586
2587 static u8 *drm_find_cea_extension(struct edid *edid)
2588 {
2589 return drm_find_edid_extension(edid, CEA_EXT);
2590 }
2591
2592 static u8 *drm_find_displayid_extension(struct edid *edid)
2593 {
2594 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2595 }
2596
2597 /*
2598 * Calculate the alternate clock for the CEA mode
2599 * (60Hz vs. 59.94Hz etc.)
2600 */
2601 static unsigned int
2602 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2603 {
2604 unsigned int clock = cea_mode->clock;
2605
2606 if (cea_mode->vrefresh % 6 != 0)
2607 return clock;
2608
2609 /*
2610 * edid_cea_modes contains the 59.94Hz
2611 * variant for 240 and 480 line modes,
2612 * and the 60Hz variant otherwise.
2613 */
2614 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2615 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2616 else
2617 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2618
2619 return clock;
2620 }
2621
2622 static bool
2623 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2624 {
2625 /*
2626 * For certain VICs the spec allows the vertical
2627 * front porch to vary by one or two lines.
2628 *
2629 * cea_modes[] stores the variant with the shortest
2630 * vertical front porch. We can adjust the mode to
2631 * get the other variants by simply increasing the
2632 * vertical front porch length.
2633 */
2634 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2635 edid_cea_modes[9].vtotal != 262 ||
2636 edid_cea_modes[12].vtotal != 262 ||
2637 edid_cea_modes[13].vtotal != 262 ||
2638 edid_cea_modes[23].vtotal != 312 ||
2639 edid_cea_modes[24].vtotal != 312 ||
2640 edid_cea_modes[27].vtotal != 312 ||
2641 edid_cea_modes[28].vtotal != 312);
2642
2643 if (((vic == 8 || vic == 9 ||
2644 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2645 ((vic == 23 || vic == 24 ||
2646 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2647 mode->vsync_start++;
2648 mode->vsync_end++;
2649 mode->vtotal++;
2650
2651 return true;
2652 }
2653
2654 return false;
2655 }
2656
2657 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2658 unsigned int clock_tolerance)
2659 {
2660 u8 vic;
2661
2662 if (!to_match->clock)
2663 return 0;
2664
2665 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2666 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2667 unsigned int clock1, clock2;
2668
2669 /* Check both 60Hz and 59.94Hz */
2670 clock1 = cea_mode.clock;
2671 clock2 = cea_mode_alternate_clock(&cea_mode);
2672
2673 if (abs(to_match->clock - clock1) > clock_tolerance &&
2674 abs(to_match->clock - clock2) > clock_tolerance)
2675 continue;
2676
2677 do {
2678 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2679 return vic;
2680 } while (cea_mode_alternate_timings(vic, &cea_mode));
2681 }
2682
2683 return 0;
2684 }
2685
2686 /**
2687 * drm_match_cea_mode - look for a CEA mode matching given mode
2688 * @to_match: display mode
2689 *
2690 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2691 * mode.
2692 */
2693 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2694 {
2695 u8 vic;
2696
2697 if (!to_match->clock)
2698 return 0;
2699
2700 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2701 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2702 unsigned int clock1, clock2;
2703
2704 /* Check both 60Hz and 59.94Hz */
2705 clock1 = cea_mode.clock;
2706 clock2 = cea_mode_alternate_clock(&cea_mode);
2707
2708 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2709 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2710 continue;
2711
2712 do {
2713 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2714 return vic;
2715 } while (cea_mode_alternate_timings(vic, &cea_mode));
2716 }
2717
2718 return 0;
2719 }
2720 EXPORT_SYMBOL(drm_match_cea_mode);
2721
2722 static bool drm_valid_cea_vic(u8 vic)
2723 {
2724 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2725 }
2726
2727 /**
2728 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2729 * the input VIC from the CEA mode list
2730 * @video_code: ID given to each of the CEA modes
2731 *
2732 * Returns picture aspect ratio
2733 */
2734 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2735 {
2736 return edid_cea_modes[video_code].picture_aspect_ratio;
2737 }
2738 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2739
2740 /*
2741 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2742 * specific block).
2743 *
2744 * It's almost like cea_mode_alternate_clock(), we just need to add an
2745 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2746 * one.
2747 */
2748 static unsigned int
2749 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2750 {
2751 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2752 return hdmi_mode->clock;
2753
2754 return cea_mode_alternate_clock(hdmi_mode);
2755 }
2756
2757 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2758 unsigned int clock_tolerance)
2759 {
2760 u8 vic;
2761
2762 if (!to_match->clock)
2763 return 0;
2764
2765 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2766 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2767 unsigned int clock1, clock2;
2768
2769 /* Make sure to also match alternate clocks */
2770 clock1 = hdmi_mode->clock;
2771 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2772
2773 if (abs(to_match->clock - clock1) > clock_tolerance &&
2774 abs(to_match->clock - clock2) > clock_tolerance)
2775 continue;
2776
2777 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2778 return vic;
2779 }
2780
2781 return 0;
2782 }
2783
2784 /*
2785 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2786 * @to_match: display mode
2787 *
2788 * An HDMI mode is one defined in the HDMI vendor specific block.
2789 *
2790 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2791 */
2792 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2793 {
2794 u8 vic;
2795
2796 if (!to_match->clock)
2797 return 0;
2798
2799 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2800 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2801 unsigned int clock1, clock2;
2802
2803 /* Make sure to also match alternate clocks */
2804 clock1 = hdmi_mode->clock;
2805 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2806
2807 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2808 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2809 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2810 return vic;
2811 }
2812 return 0;
2813 }
2814
2815 static bool drm_valid_hdmi_vic(u8 vic)
2816 {
2817 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2818 }
2819
2820 static int
2821 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2822 {
2823 struct drm_device *dev = connector->dev;
2824 struct drm_display_mode *mode, *tmp;
2825 LIST_HEAD(list);
2826 int modes = 0;
2827
2828 /* Don't add CEA modes if the CEA extension block is missing */
2829 if (!drm_find_cea_extension(edid))
2830 return 0;
2831
2832 /*
2833 * Go through all probed modes and create a new mode
2834 * with the alternate clock for certain CEA modes.
2835 */
2836 list_for_each_entry(mode, &connector->probed_modes, head) {
2837 const struct drm_display_mode *cea_mode = NULL;
2838 struct drm_display_mode *newmode;
2839 u8 vic = drm_match_cea_mode(mode);
2840 unsigned int clock1, clock2;
2841
2842 if (drm_valid_cea_vic(vic)) {
2843 cea_mode = &edid_cea_modes[vic];
2844 clock2 = cea_mode_alternate_clock(cea_mode);
2845 } else {
2846 vic = drm_match_hdmi_mode(mode);
2847 if (drm_valid_hdmi_vic(vic)) {
2848 cea_mode = &edid_4k_modes[vic];
2849 clock2 = hdmi_mode_alternate_clock(cea_mode);
2850 }
2851 }
2852
2853 if (!cea_mode)
2854 continue;
2855
2856 clock1 = cea_mode->clock;
2857
2858 if (clock1 == clock2)
2859 continue;
2860
2861 if (mode->clock != clock1 && mode->clock != clock2)
2862 continue;
2863
2864 newmode = drm_mode_duplicate(dev, cea_mode);
2865 if (!newmode)
2866 continue;
2867
2868 /* Carry over the stereo flags */
2869 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2870
2871 /*
2872 * The current mode could be either variant. Make
2873 * sure to pick the "other" clock for the new mode.
2874 */
2875 if (mode->clock != clock1)
2876 newmode->clock = clock1;
2877 else
2878 newmode->clock = clock2;
2879
2880 list_add_tail(&newmode->head, &list);
2881 }
2882
2883 list_for_each_entry_safe(mode, tmp, &list, head) {
2884 list_del(&mode->head);
2885 drm_mode_probed_add(connector, mode);
2886 modes++;
2887 }
2888
2889 return modes;
2890 }
2891
2892 static struct drm_display_mode *
2893 drm_display_mode_from_vic_index(struct drm_connector *connector,
2894 const u8 *video_db, u8 video_len,
2895 u8 video_index)
2896 {
2897 struct drm_device *dev = connector->dev;
2898 struct drm_display_mode *newmode;
2899 u8 vic;
2900
2901 if (video_db == NULL || video_index >= video_len)
2902 return NULL;
2903
2904 /* CEA modes are numbered 1..127 */
2905 vic = (video_db[video_index] & 127);
2906 if (!drm_valid_cea_vic(vic))
2907 return NULL;
2908
2909 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
2910 if (!newmode)
2911 return NULL;
2912
2913 newmode->vrefresh = 0;
2914
2915 return newmode;
2916 }
2917
2918 static int
2919 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2920 {
2921 int i, modes = 0;
2922
2923 for (i = 0; i < len; i++) {
2924 struct drm_display_mode *mode;
2925 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2926 if (mode) {
2927 drm_mode_probed_add(connector, mode);
2928 modes++;
2929 }
2930 }
2931
2932 return modes;
2933 }
2934
2935 struct stereo_mandatory_mode {
2936 int width, height, vrefresh;
2937 unsigned int flags;
2938 };
2939
2940 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2941 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2942 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2943 { 1920, 1080, 50,
2944 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2945 { 1920, 1080, 60,
2946 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2947 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2948 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2949 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2950 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2951 };
2952
2953 static bool
2954 stereo_match_mandatory(const struct drm_display_mode *mode,
2955 const struct stereo_mandatory_mode *stereo_mode)
2956 {
2957 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2958
2959 return mode->hdisplay == stereo_mode->width &&
2960 mode->vdisplay == stereo_mode->height &&
2961 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2962 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2963 }
2964
2965 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2966 {
2967 struct drm_device *dev = connector->dev;
2968 const struct drm_display_mode *mode;
2969 struct list_head stereo_modes;
2970 int modes = 0, i;
2971
2972 INIT_LIST_HEAD(&stereo_modes);
2973
2974 list_for_each_entry(mode, &connector->probed_modes, head) {
2975 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2976 const struct stereo_mandatory_mode *mandatory;
2977 struct drm_display_mode *new_mode;
2978
2979 if (!stereo_match_mandatory(mode,
2980 &stereo_mandatory_modes[i]))
2981 continue;
2982
2983 mandatory = &stereo_mandatory_modes[i];
2984 new_mode = drm_mode_duplicate(dev, mode);
2985 if (!new_mode)
2986 continue;
2987
2988 new_mode->flags |= mandatory->flags;
2989 list_add_tail(&new_mode->head, &stereo_modes);
2990 modes++;
2991 }
2992 }
2993
2994 list_splice_tail(&stereo_modes, &connector->probed_modes);
2995
2996 return modes;
2997 }
2998
2999 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3000 {
3001 struct drm_device *dev = connector->dev;
3002 struct drm_display_mode *newmode;
3003
3004 if (!drm_valid_hdmi_vic(vic)) {
3005 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3006 return 0;
3007 }
3008
3009 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3010 if (!newmode)
3011 return 0;
3012
3013 drm_mode_probed_add(connector, newmode);
3014
3015 return 1;
3016 }
3017
3018 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3019 const u8 *video_db, u8 video_len, u8 video_index)
3020 {
3021 struct drm_display_mode *newmode;
3022 int modes = 0;
3023
3024 if (structure & (1 << 0)) {
3025 newmode = drm_display_mode_from_vic_index(connector, video_db,
3026 video_len,
3027 video_index);
3028 if (newmode) {
3029 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3030 drm_mode_probed_add(connector, newmode);
3031 modes++;
3032 }
3033 }
3034 if (structure & (1 << 6)) {
3035 newmode = drm_display_mode_from_vic_index(connector, video_db,
3036 video_len,
3037 video_index);
3038 if (newmode) {
3039 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3040 drm_mode_probed_add(connector, newmode);
3041 modes++;
3042 }
3043 }
3044 if (structure & (1 << 8)) {
3045 newmode = drm_display_mode_from_vic_index(connector, video_db,
3046 video_len,
3047 video_index);
3048 if (newmode) {
3049 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3050 drm_mode_probed_add(connector, newmode);
3051 modes++;
3052 }
3053 }
3054
3055 return modes;
3056 }
3057
3058 /*
3059 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3060 * @connector: connector corresponding to the HDMI sink
3061 * @db: start of the CEA vendor specific block
3062 * @len: length of the CEA block payload, ie. one can access up to db[len]
3063 *
3064 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3065 * also adds the stereo 3d modes when applicable.
3066 */
3067 static int
3068 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3069 const u8 *video_db, u8 video_len)
3070 {
3071 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3072 u8 vic_len, hdmi_3d_len = 0;
3073 u16 mask;
3074 u16 structure_all;
3075
3076 if (len < 8)
3077 goto out;
3078
3079 /* no HDMI_Video_Present */
3080 if (!(db[8] & (1 << 5)))
3081 goto out;
3082
3083 /* Latency_Fields_Present */
3084 if (db[8] & (1 << 7))
3085 offset += 2;
3086
3087 /* I_Latency_Fields_Present */
3088 if (db[8] & (1 << 6))
3089 offset += 2;
3090
3091 /* the declared length is not long enough for the 2 first bytes
3092 * of additional video format capabilities */
3093 if (len < (8 + offset + 2))
3094 goto out;
3095
3096 /* 3D_Present */
3097 offset++;
3098 if (db[8 + offset] & (1 << 7)) {
3099 modes += add_hdmi_mandatory_stereo_modes(connector);
3100
3101 /* 3D_Multi_present */
3102 multi_present = (db[8 + offset] & 0x60) >> 5;
3103 }
3104
3105 offset++;
3106 vic_len = db[8 + offset] >> 5;
3107 hdmi_3d_len = db[8 + offset] & 0x1f;
3108
3109 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3110 u8 vic;
3111
3112 vic = db[9 + offset + i];
3113 modes += add_hdmi_mode(connector, vic);
3114 }
3115 offset += 1 + vic_len;
3116
3117 if (multi_present == 1)
3118 multi_len = 2;
3119 else if (multi_present == 2)
3120 multi_len = 4;
3121 else
3122 multi_len = 0;
3123
3124 if (len < (8 + offset + hdmi_3d_len - 1))
3125 goto out;
3126
3127 if (hdmi_3d_len < multi_len)
3128 goto out;
3129
3130 if (multi_present == 1 || multi_present == 2) {
3131 /* 3D_Structure_ALL */
3132 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3133
3134 /* check if 3D_MASK is present */
3135 if (multi_present == 2)
3136 mask = (db[10 + offset] << 8) | db[11 + offset];
3137 else
3138 mask = 0xffff;
3139
3140 for (i = 0; i < 16; i++) {
3141 if (mask & (1 << i))
3142 modes += add_3d_struct_modes(connector,
3143 structure_all,
3144 video_db,
3145 video_len, i);
3146 }
3147 }
3148
3149 offset += multi_len;
3150
3151 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3152 int vic_index;
3153 struct drm_display_mode *newmode = NULL;
3154 unsigned int newflag = 0;
3155 bool detail_present;
3156
3157 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3158
3159 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3160 break;
3161
3162 /* 2D_VIC_order_X */
3163 vic_index = db[8 + offset + i] >> 4;
3164
3165 /* 3D_Structure_X */
3166 switch (db[8 + offset + i] & 0x0f) {
3167 case 0:
3168 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3169 break;
3170 case 6:
3171 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3172 break;
3173 case 8:
3174 /* 3D_Detail_X */
3175 if ((db[9 + offset + i] >> 4) == 1)
3176 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3177 break;
3178 }
3179
3180 if (newflag != 0) {
3181 newmode = drm_display_mode_from_vic_index(connector,
3182 video_db,
3183 video_len,
3184 vic_index);
3185
3186 if (newmode) {
3187 newmode->flags |= newflag;
3188 drm_mode_probed_add(connector, newmode);
3189 modes++;
3190 }
3191 }
3192
3193 if (detail_present)
3194 i++;
3195 }
3196
3197 out:
3198 return modes;
3199 }
3200
3201 static int
3202 cea_db_payload_len(const u8 *db)
3203 {
3204 return db[0] & 0x1f;
3205 }
3206
3207 static int
3208 cea_db_tag(const u8 *db)
3209 {
3210 return db[0] >> 5;
3211 }
3212
3213 static int
3214 cea_revision(const u8 *cea)
3215 {
3216 return cea[1];
3217 }
3218
3219 static int
3220 cea_db_offsets(const u8 *cea, int *start, int *end)
3221 {
3222 /* Data block offset in CEA extension block */
3223 *start = 4;
3224 *end = cea[2];
3225 if (*end == 0)
3226 *end = 127;
3227 if (*end < 4 || *end > 127)
3228 return -ERANGE;
3229 return 0;
3230 }
3231
3232 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3233 {
3234 int hdmi_id;
3235
3236 if (cea_db_tag(db) != VENDOR_BLOCK)
3237 return false;
3238
3239 if (cea_db_payload_len(db) < 5)
3240 return false;
3241
3242 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3243
3244 return hdmi_id == HDMI_IEEE_OUI;
3245 }
3246
3247 #define for_each_cea_db(cea, i, start, end) \
3248 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3249
3250 static int
3251 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3252 {
3253 const u8 *cea = drm_find_cea_extension(edid);
3254 const u8 *db, *hdmi = NULL, *video = NULL;
3255 u8 dbl, hdmi_len, video_len = 0;
3256 int modes = 0;
3257
3258 if (cea && cea_revision(cea) >= 3) {
3259 int i, start, end;
3260
3261 if (cea_db_offsets(cea, &start, &end))
3262 return 0;
3263
3264 for_each_cea_db(cea, i, start, end) {
3265 db = &cea[i];
3266 dbl = cea_db_payload_len(db);
3267
3268 if (cea_db_tag(db) == VIDEO_BLOCK) {
3269 video = db + 1;
3270 video_len = dbl;
3271 modes += do_cea_modes(connector, video, dbl);
3272 }
3273 else if (cea_db_is_hdmi_vsdb(db)) {
3274 hdmi = db;
3275 hdmi_len = dbl;
3276 }
3277 }
3278 }
3279
3280 /*
3281 * We parse the HDMI VSDB after having added the cea modes as we will
3282 * be patching their flags when the sink supports stereo 3D.
3283 */
3284 if (hdmi)
3285 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3286 video_len);
3287
3288 return modes;
3289 }
3290
3291 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3292 {
3293 const struct drm_display_mode *cea_mode;
3294 int clock1, clock2, clock;
3295 u8 vic;
3296 const char *type;
3297
3298 /*
3299 * allow 5kHz clock difference either way to account for
3300 * the 10kHz clock resolution limit of detailed timings.
3301 */
3302 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3303 if (drm_valid_cea_vic(vic)) {
3304 type = "CEA";
3305 cea_mode = &edid_cea_modes[vic];
3306 clock1 = cea_mode->clock;
3307 clock2 = cea_mode_alternate_clock(cea_mode);
3308 } else {
3309 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3310 if (drm_valid_hdmi_vic(vic)) {
3311 type = "HDMI";
3312 cea_mode = &edid_4k_modes[vic];
3313 clock1 = cea_mode->clock;
3314 clock2 = hdmi_mode_alternate_clock(cea_mode);
3315 } else {
3316 return;
3317 }
3318 }
3319
3320 /* pick whichever is closest */
3321 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3322 clock = clock1;
3323 else
3324 clock = clock2;
3325
3326 if (mode->clock == clock)
3327 return;
3328
3329 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3330 type, vic, mode->clock, clock);
3331 mode->clock = clock;
3332 }
3333
3334 static void
3335 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3336 {
3337 u8 len = cea_db_payload_len(db);
3338
3339 if (len >= 6)
3340 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3341 if (len >= 8) {
3342 connector->latency_present[0] = db[8] >> 7;
3343 connector->latency_present[1] = (db[8] >> 6) & 1;
3344 }
3345 if (len >= 9)
3346 connector->video_latency[0] = db[9];
3347 if (len >= 10)
3348 connector->audio_latency[0] = db[10];
3349 if (len >= 11)
3350 connector->video_latency[1] = db[11];
3351 if (len >= 12)
3352 connector->audio_latency[1] = db[12];
3353
3354 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3355 "video latency %d %d, "
3356 "audio latency %d %d\n",
3357 connector->latency_present[0],
3358 connector->latency_present[1],
3359 connector->video_latency[0],
3360 connector->video_latency[1],
3361 connector->audio_latency[0],
3362 connector->audio_latency[1]);
3363 }
3364
3365 static void
3366 monitor_name(struct detailed_timing *t, void *data)
3367 {
3368 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3369 *(u8 **)data = t->data.other_data.data.str.str;
3370 }
3371
3372 static int get_monitor_name(struct edid *edid, char name[13])
3373 {
3374 char *edid_name = NULL;
3375 int mnl;
3376
3377 if (!edid || !name)
3378 return 0;
3379
3380 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3381 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3382 if (edid_name[mnl] == 0x0a)
3383 break;
3384
3385 name[mnl] = edid_name[mnl];
3386 }
3387
3388 return mnl;
3389 }
3390
3391 /**
3392 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3393 * @edid: monitor EDID information
3394 * @name: pointer to a character array to hold the name of the monitor
3395 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3396 *
3397 */
3398 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3399 {
3400 int name_length;
3401 char buf[13];
3402
3403 if (bufsize <= 0)
3404 return;
3405
3406 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3407 memcpy(name, buf, name_length);
3408 name[name_length] = '\0';
3409 }
3410 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3411
3412 /**
3413 * drm_edid_to_eld - build ELD from EDID
3414 * @connector: connector corresponding to the HDMI/DP sink
3415 * @edid: EDID to parse
3416 *
3417 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3418 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3419 * fill in.
3420 */
3421 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3422 {
3423 uint8_t *eld = connector->eld;
3424 u8 *cea;
3425 u8 *db;
3426 int total_sad_count = 0;
3427 int mnl;
3428 int dbl;
3429
3430 memset(eld, 0, sizeof(connector->eld));
3431
3432 connector->latency_present[0] = false;
3433 connector->latency_present[1] = false;
3434 connector->video_latency[0] = 0;
3435 connector->audio_latency[0] = 0;
3436 connector->video_latency[1] = 0;
3437 connector->audio_latency[1] = 0;
3438
3439 cea = drm_find_cea_extension(edid);
3440 if (!cea) {
3441 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3442 return;
3443 }
3444
3445 mnl = get_monitor_name(edid, eld + 20);
3446
3447 eld[4] = (cea[1] << 5) | mnl;
3448 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3449
3450 eld[0] = 2 << 3; /* ELD version: 2 */
3451
3452 eld[16] = edid->mfg_id[0];
3453 eld[17] = edid->mfg_id[1];
3454 eld[18] = edid->prod_code[0];
3455 eld[19] = edid->prod_code[1];
3456
3457 if (cea_revision(cea) >= 3) {
3458 int i, start, end;
3459
3460 if (cea_db_offsets(cea, &start, &end)) {
3461 start = 0;
3462 end = 0;
3463 }
3464
3465 for_each_cea_db(cea, i, start, end) {
3466 db = &cea[i];
3467 dbl = cea_db_payload_len(db);
3468
3469 switch (cea_db_tag(db)) {
3470 int sad_count;
3471
3472 case AUDIO_BLOCK:
3473 /* Audio Data Block, contains SADs */
3474 sad_count = min(dbl / 3, 15 - total_sad_count);
3475 if (sad_count >= 1)
3476 memcpy(eld + 20 + mnl + total_sad_count * 3,
3477 &db[1], sad_count * 3);
3478 total_sad_count += sad_count;
3479 break;
3480 case SPEAKER_BLOCK:
3481 /* Speaker Allocation Data Block */
3482 if (dbl >= 1)
3483 eld[7] = db[1];
3484 break;
3485 case VENDOR_BLOCK:
3486 /* HDMI Vendor-Specific Data Block */
3487 if (cea_db_is_hdmi_vsdb(db))
3488 drm_parse_hdmi_vsdb_audio(connector, db);
3489 break;
3490 default:
3491 break;
3492 }
3493 }
3494 }
3495 eld[5] |= total_sad_count << 4;
3496
3497 eld[DRM_ELD_BASELINE_ELD_LEN] =
3498 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3499
3500 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3501 drm_eld_size(eld), total_sad_count);
3502 }
3503 EXPORT_SYMBOL(drm_edid_to_eld);
3504
3505 /**
3506 * drm_edid_to_sad - extracts SADs from EDID
3507 * @edid: EDID to parse
3508 * @sads: pointer that will be set to the extracted SADs
3509 *
3510 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3511 *
3512 * Note: The returned pointer needs to be freed using kfree().
3513 *
3514 * Return: The number of found SADs or negative number on error.
3515 */
3516 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3517 {
3518 int count = 0;
3519 int i, start, end, dbl;
3520 u8 *cea;
3521
3522 cea = drm_find_cea_extension(edid);
3523 if (!cea) {
3524 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3525 return -ENOENT;
3526 }
3527
3528 if (cea_revision(cea) < 3) {
3529 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3530 return -ENOTSUPP;
3531 }
3532
3533 if (cea_db_offsets(cea, &start, &end)) {
3534 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3535 return -EPROTO;
3536 }
3537
3538 for_each_cea_db(cea, i, start, end) {
3539 u8 *db = &cea[i];
3540
3541 if (cea_db_tag(db) == AUDIO_BLOCK) {
3542 int j;
3543 dbl = cea_db_payload_len(db);
3544
3545 count = dbl / 3; /* SAD is 3B */
3546 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3547 if (!*sads)
3548 return -ENOMEM;
3549 for (j = 0; j < count; j++) {
3550 u8 *sad = &db[1 + j * 3];
3551
3552 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3553 (*sads)[j].channels = sad[0] & 0x7;
3554 (*sads)[j].freq = sad[1] & 0x7F;
3555 (*sads)[j].byte2 = sad[2];
3556 }
3557 break;
3558 }
3559 }
3560
3561 return count;
3562 }
3563 EXPORT_SYMBOL(drm_edid_to_sad);
3564
3565 /**
3566 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3567 * @edid: EDID to parse
3568 * @sadb: pointer to the speaker block
3569 *
3570 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3571 *
3572 * Note: The returned pointer needs to be freed using kfree().
3573 *
3574 * Return: The number of found Speaker Allocation Blocks or negative number on
3575 * error.
3576 */
3577 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3578 {
3579 int count = 0;
3580 int i, start, end, dbl;
3581 const u8 *cea;
3582
3583 cea = drm_find_cea_extension(edid);
3584 if (!cea) {
3585 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3586 return -ENOENT;
3587 }
3588
3589 if (cea_revision(cea) < 3) {
3590 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3591 return -ENOTSUPP;
3592 }
3593
3594 if (cea_db_offsets(cea, &start, &end)) {
3595 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3596 return -EPROTO;
3597 }
3598
3599 for_each_cea_db(cea, i, start, end) {
3600 const u8 *db = &cea[i];
3601
3602 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3603 dbl = cea_db_payload_len(db);
3604
3605 /* Speaker Allocation Data Block */
3606 if (dbl == 3) {
3607 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3608 if (!*sadb)
3609 return -ENOMEM;
3610 count = dbl;
3611 break;
3612 }
3613 }
3614 }
3615
3616 return count;
3617 }
3618 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3619
3620 /**
3621 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3622 * @connector: connector associated with the HDMI/DP sink
3623 * @mode: the display mode
3624 *
3625 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3626 * the sink doesn't support audio or video.
3627 */
3628 int drm_av_sync_delay(struct drm_connector *connector,
3629 const struct drm_display_mode *mode)
3630 {
3631 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3632 int a, v;
3633
3634 if (!connector->latency_present[0])
3635 return 0;
3636 if (!connector->latency_present[1])
3637 i = 0;
3638
3639 a = connector->audio_latency[i];
3640 v = connector->video_latency[i];
3641
3642 /*
3643 * HDMI/DP sink doesn't support audio or video?
3644 */
3645 if (a == 255 || v == 255)
3646 return 0;
3647
3648 /*
3649 * Convert raw EDID values to millisecond.
3650 * Treat unknown latency as 0ms.
3651 */
3652 if (a)
3653 a = min(2 * (a - 1), 500);
3654 if (v)
3655 v = min(2 * (v - 1), 500);
3656
3657 return max(v - a, 0);
3658 }
3659 EXPORT_SYMBOL(drm_av_sync_delay);
3660
3661 /**
3662 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3663 * @edid: monitor EDID information
3664 *
3665 * Parse the CEA extension according to CEA-861-B.
3666 *
3667 * Return: True if the monitor is HDMI, false if not or unknown.
3668 */
3669 bool drm_detect_hdmi_monitor(struct edid *edid)
3670 {
3671 u8 *edid_ext;
3672 int i;
3673 int start_offset, end_offset;
3674
3675 edid_ext = drm_find_cea_extension(edid);
3676 if (!edid_ext)
3677 return false;
3678
3679 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3680 return false;
3681
3682 /*
3683 * Because HDMI identifier is in Vendor Specific Block,
3684 * search it from all data blocks of CEA extension.
3685 */
3686 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3687 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3688 return true;
3689 }
3690
3691 return false;
3692 }
3693 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3694
3695 /**
3696 * drm_detect_monitor_audio - check monitor audio capability
3697 * @edid: EDID block to scan
3698 *
3699 * Monitor should have CEA extension block.
3700 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3701 * audio' only. If there is any audio extension block and supported
3702 * audio format, assume at least 'basic audio' support, even if 'basic
3703 * audio' is not defined in EDID.
3704 *
3705 * Return: True if the monitor supports audio, false otherwise.
3706 */
3707 bool drm_detect_monitor_audio(struct edid *edid)
3708 {
3709 u8 *edid_ext;
3710 int i, j;
3711 bool has_audio = false;
3712 int start_offset, end_offset;
3713
3714 edid_ext = drm_find_cea_extension(edid);
3715 if (!edid_ext)
3716 goto end;
3717
3718 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3719
3720 if (has_audio) {
3721 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3722 goto end;
3723 }
3724
3725 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3726 goto end;
3727
3728 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3729 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3730 has_audio = true;
3731 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3732 DRM_DEBUG_KMS("CEA audio format %d\n",
3733 (edid_ext[i + j] >> 3) & 0xf);
3734 goto end;
3735 }
3736 }
3737 end:
3738 return has_audio;
3739 }
3740 EXPORT_SYMBOL(drm_detect_monitor_audio);
3741
3742 /**
3743 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3744 * @edid: EDID block to scan
3745 *
3746 * Check whether the monitor reports the RGB quantization range selection
3747 * as supported. The AVI infoframe can then be used to inform the monitor
3748 * which quantization range (full or limited) is used.
3749 *
3750 * Return: True if the RGB quantization range is selectable, false otherwise.
3751 */
3752 bool drm_rgb_quant_range_selectable(struct edid *edid)
3753 {
3754 u8 *edid_ext;
3755 int i, start, end;
3756
3757 edid_ext = drm_find_cea_extension(edid);
3758 if (!edid_ext)
3759 return false;
3760
3761 if (cea_db_offsets(edid_ext, &start, &end))
3762 return false;
3763
3764 for_each_cea_db(edid_ext, i, start, end) {
3765 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3766 cea_db_payload_len(&edid_ext[i]) == 2) {
3767 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3768 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3769 }
3770 }
3771
3772 return false;
3773 }
3774 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3775
3776 /**
3777 * drm_default_rgb_quant_range - default RGB quantization range
3778 * @mode: display mode
3779 *
3780 * Determine the default RGB quantization range for the mode,
3781 * as specified in CEA-861.
3782 *
3783 * Return: The default RGB quantization range for the mode
3784 */
3785 enum hdmi_quantization_range
3786 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
3787 {
3788 /* All CEA modes other than VIC 1 use limited quantization range. */
3789 return drm_match_cea_mode(mode) > 1 ?
3790 HDMI_QUANTIZATION_RANGE_LIMITED :
3791 HDMI_QUANTIZATION_RANGE_FULL;
3792 }
3793 EXPORT_SYMBOL(drm_default_rgb_quant_range);
3794
3795 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
3796 const u8 *hdmi)
3797 {
3798 struct drm_display_info *info = &connector->display_info;
3799 unsigned int dc_bpc = 0;
3800
3801 /* HDMI supports at least 8 bpc */
3802 info->bpc = 8;
3803
3804 if (cea_db_payload_len(hdmi) < 6)
3805 return;
3806
3807 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3808 dc_bpc = 10;
3809 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3810 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3811 connector->name);
3812 }
3813
3814 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3815 dc_bpc = 12;
3816 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3817 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3818 connector->name);
3819 }
3820
3821 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3822 dc_bpc = 16;
3823 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3824 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3825 connector->name);
3826 }
3827
3828 if (dc_bpc == 0) {
3829 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3830 connector->name);
3831 return;
3832 }
3833
3834 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3835 connector->name, dc_bpc);
3836 info->bpc = dc_bpc;
3837
3838 /*
3839 * Deep color support mandates RGB444 support for all video
3840 * modes and forbids YCRCB422 support for all video modes per
3841 * HDMI 1.3 spec.
3842 */
3843 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3844
3845 /* YCRCB444 is optional according to spec. */
3846 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3847 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3848 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3849 connector->name);
3850 }
3851
3852 /*
3853 * Spec says that if any deep color mode is supported at all,
3854 * then deep color 36 bit must be supported.
3855 */
3856 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3857 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3858 connector->name);
3859 }
3860 }
3861
3862 static void
3863 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
3864 {
3865 struct drm_display_info *info = &connector->display_info;
3866 u8 len = cea_db_payload_len(db);
3867
3868 if (len >= 6)
3869 info->dvi_dual = db[6] & 1;
3870 if (len >= 7)
3871 info->max_tmds_clock = db[7] * 5000;
3872
3873 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3874 "max TMDS clock %d kHz\n",
3875 info->dvi_dual,
3876 info->max_tmds_clock);
3877
3878 drm_parse_hdmi_deep_color_info(connector, db);
3879 }
3880
3881 static void drm_parse_cea_ext(struct drm_connector *connector,
3882 struct edid *edid)
3883 {
3884 struct drm_display_info *info = &connector->display_info;
3885 const u8 *edid_ext;
3886 int i, start, end;
3887
3888 edid_ext = drm_find_cea_extension(edid);
3889 if (!edid_ext)
3890 return;
3891
3892 info->cea_rev = edid_ext[1];
3893
3894 /* The existence of a CEA block should imply RGB support */
3895 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3896 if (edid_ext[3] & EDID_CEA_YCRCB444)
3897 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3898 if (edid_ext[3] & EDID_CEA_YCRCB422)
3899 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3900
3901 if (cea_db_offsets(edid_ext, &start, &end))
3902 return;
3903
3904 for_each_cea_db(edid_ext, i, start, end) {
3905 const u8 *db = &edid_ext[i];
3906
3907 if (cea_db_is_hdmi_vsdb(db))
3908 drm_parse_hdmi_vsdb_video(connector, db);
3909 }
3910 }
3911
3912 static void drm_add_display_info(struct drm_connector *connector,
3913 struct edid *edid)
3914 {
3915 struct drm_display_info *info = &connector->display_info;
3916
3917 info->width_mm = edid->width_cm * 10;
3918 info->height_mm = edid->height_cm * 10;
3919
3920 /* driver figures it out in this case */
3921 info->bpc = 0;
3922 info->color_formats = 0;
3923 info->cea_rev = 0;
3924 info->max_tmds_clock = 0;
3925 info->dvi_dual = false;
3926
3927 if (edid->revision < 3)
3928 return;
3929
3930 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3931 return;
3932
3933 drm_parse_cea_ext(connector, edid);
3934
3935 /*
3936 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
3937 *
3938 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
3939 * tells us to assume 8 bpc color depth if the EDID doesn't have
3940 * extensions which tell otherwise.
3941 */
3942 if ((info->bpc == 0) && (edid->revision < 4) &&
3943 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
3944 info->bpc = 8;
3945 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
3946 connector->name, info->bpc);
3947 }
3948
3949 /* Only defined for 1.4 with digital displays */
3950 if (edid->revision < 4)
3951 return;
3952
3953 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3954 case DRM_EDID_DIGITAL_DEPTH_6:
3955 info->bpc = 6;
3956 break;
3957 case DRM_EDID_DIGITAL_DEPTH_8:
3958 info->bpc = 8;
3959 break;
3960 case DRM_EDID_DIGITAL_DEPTH_10:
3961 info->bpc = 10;
3962 break;
3963 case DRM_EDID_DIGITAL_DEPTH_12:
3964 info->bpc = 12;
3965 break;
3966 case DRM_EDID_DIGITAL_DEPTH_14:
3967 info->bpc = 14;
3968 break;
3969 case DRM_EDID_DIGITAL_DEPTH_16:
3970 info->bpc = 16;
3971 break;
3972 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3973 default:
3974 info->bpc = 0;
3975 break;
3976 }
3977
3978 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
3979 connector->name, info->bpc);
3980
3981 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
3982 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3983 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3984 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3985 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3986 }
3987
3988 static int validate_displayid(u8 *displayid, int length, int idx)
3989 {
3990 int i;
3991 u8 csum = 0;
3992 struct displayid_hdr *base;
3993
3994 base = (struct displayid_hdr *)&displayid[idx];
3995
3996 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
3997 base->rev, base->bytes, base->prod_id, base->ext_count);
3998
3999 if (base->bytes + 5 > length - idx)
4000 return -EINVAL;
4001 for (i = idx; i <= base->bytes + 5; i++) {
4002 csum += displayid[i];
4003 }
4004 if (csum) {
4005 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
4006 return -EINVAL;
4007 }
4008 return 0;
4009 }
4010
4011 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4012 struct displayid_detailed_timings_1 *timings)
4013 {
4014 struct drm_display_mode *mode;
4015 unsigned pixel_clock = (timings->pixel_clock[0] |
4016 (timings->pixel_clock[1] << 8) |
4017 (timings->pixel_clock[2] << 16));
4018 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4019 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4020 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4021 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4022 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4023 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4024 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4025 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4026 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4027 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4028 mode = drm_mode_create(dev);
4029 if (!mode)
4030 return NULL;
4031
4032 mode->clock = pixel_clock * 10;
4033 mode->hdisplay = hactive;
4034 mode->hsync_start = mode->hdisplay + hsync;
4035 mode->hsync_end = mode->hsync_start + hsync_width;
4036 mode->htotal = mode->hdisplay + hblank;
4037
4038 mode->vdisplay = vactive;
4039 mode->vsync_start = mode->vdisplay + vsync;
4040 mode->vsync_end = mode->vsync_start + vsync_width;
4041 mode->vtotal = mode->vdisplay + vblank;
4042
4043 mode->flags = 0;
4044 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4045 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4046 mode->type = DRM_MODE_TYPE_DRIVER;
4047
4048 if (timings->flags & 0x80)
4049 mode->type |= DRM_MODE_TYPE_PREFERRED;
4050 mode->vrefresh = drm_mode_vrefresh(mode);
4051 drm_mode_set_name(mode);
4052
4053 return mode;
4054 }
4055
4056 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4057 struct displayid_block *block)
4058 {
4059 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4060 int i;
4061 int num_timings;
4062 struct drm_display_mode *newmode;
4063 int num_modes = 0;
4064 /* blocks must be multiple of 20 bytes length */
4065 if (block->num_bytes % 20)
4066 return 0;
4067
4068 num_timings = block->num_bytes / 20;
4069 for (i = 0; i < num_timings; i++) {
4070 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4071
4072 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4073 if (!newmode)
4074 continue;
4075
4076 drm_mode_probed_add(connector, newmode);
4077 num_modes++;
4078 }
4079 return num_modes;
4080 }
4081
4082 static int add_displayid_detailed_modes(struct drm_connector *connector,
4083 struct edid *edid)
4084 {
4085 u8 *displayid;
4086 int ret;
4087 int idx = 1;
4088 int length = EDID_LENGTH;
4089 struct displayid_block *block;
4090 int num_modes = 0;
4091
4092 displayid = drm_find_displayid_extension(edid);
4093 if (!displayid)
4094 return 0;
4095
4096 ret = validate_displayid(displayid, length, idx);
4097 if (ret)
4098 return 0;
4099
4100 idx += sizeof(struct displayid_hdr);
4101 while (block = (struct displayid_block *)&displayid[idx],
4102 idx + sizeof(struct displayid_block) <= length &&
4103 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4104 block->num_bytes > 0) {
4105 idx += block->num_bytes + sizeof(struct displayid_block);
4106 switch (block->tag) {
4107 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4108 num_modes += add_displayid_detailed_1_modes(connector, block);
4109 break;
4110 }
4111 }
4112 return num_modes;
4113 }
4114
4115 /**
4116 * drm_add_edid_modes - add modes from EDID data, if available
4117 * @connector: connector we're probing
4118 * @edid: EDID data
4119 *
4120 * Add the specified modes to the connector's mode list. Also fills out the
4121 * &drm_display_info structure in @connector with any information which can be
4122 * derived from the edid.
4123 *
4124 * Return: The number of modes added or 0 if we couldn't find any.
4125 */
4126 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4127 {
4128 int num_modes = 0;
4129 u32 quirks;
4130
4131 if (edid == NULL) {
4132 return 0;
4133 }
4134 if (!drm_edid_is_valid(edid)) {
4135 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4136 connector->name);
4137 return 0;
4138 }
4139
4140 quirks = edid_get_quirks(edid);
4141
4142 /*
4143 * EDID spec says modes should be preferred in this order:
4144 * - preferred detailed mode
4145 * - other detailed modes from base block
4146 * - detailed modes from extension blocks
4147 * - CVT 3-byte code modes
4148 * - standard timing codes
4149 * - established timing codes
4150 * - modes inferred from GTF or CVT range information
4151 *
4152 * We get this pretty much right.
4153 *
4154 * XXX order for additional mode types in extension blocks?
4155 */
4156 num_modes += add_detailed_modes(connector, edid, quirks);
4157 num_modes += add_cvt_modes(connector, edid);
4158 num_modes += add_standard_modes(connector, edid);
4159 num_modes += add_established_modes(connector, edid);
4160 num_modes += add_cea_modes(connector, edid);
4161 num_modes += add_alternate_cea_modes(connector, edid);
4162 num_modes += add_displayid_detailed_modes(connector, edid);
4163 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4164 num_modes += add_inferred_modes(connector, edid);
4165
4166 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4167 edid_fixup_preferred(connector, quirks);
4168
4169 drm_add_display_info(connector, edid);
4170
4171 if (quirks & EDID_QUIRK_FORCE_6BPC)
4172 connector->display_info.bpc = 6;
4173
4174 if (quirks & EDID_QUIRK_FORCE_8BPC)
4175 connector->display_info.bpc = 8;
4176
4177 if (quirks & EDID_QUIRK_FORCE_12BPC)
4178 connector->display_info.bpc = 12;
4179
4180 return num_modes;
4181 }
4182 EXPORT_SYMBOL(drm_add_edid_modes);
4183
4184 /**
4185 * drm_add_modes_noedid - add modes for the connectors without EDID
4186 * @connector: connector we're probing
4187 * @hdisplay: the horizontal display limit
4188 * @vdisplay: the vertical display limit
4189 *
4190 * Add the specified modes to the connector's mode list. Only when the
4191 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4192 *
4193 * Return: The number of modes added or 0 if we couldn't find any.
4194 */
4195 int drm_add_modes_noedid(struct drm_connector *connector,
4196 int hdisplay, int vdisplay)
4197 {
4198 int i, count, num_modes = 0;
4199 struct drm_display_mode *mode;
4200 struct drm_device *dev = connector->dev;
4201
4202 count = ARRAY_SIZE(drm_dmt_modes);
4203 if (hdisplay < 0)
4204 hdisplay = 0;
4205 if (vdisplay < 0)
4206 vdisplay = 0;
4207
4208 for (i = 0; i < count; i++) {
4209 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4210 if (hdisplay && vdisplay) {
4211 /*
4212 * Only when two are valid, they will be used to check
4213 * whether the mode should be added to the mode list of
4214 * the connector.
4215 */
4216 if (ptr->hdisplay > hdisplay ||
4217 ptr->vdisplay > vdisplay)
4218 continue;
4219 }
4220 if (drm_mode_vrefresh(ptr) > 61)
4221 continue;
4222 mode = drm_mode_duplicate(dev, ptr);
4223 if (mode) {
4224 drm_mode_probed_add(connector, mode);
4225 num_modes++;
4226 }
4227 }
4228 return num_modes;
4229 }
4230 EXPORT_SYMBOL(drm_add_modes_noedid);
4231
4232 /**
4233 * drm_set_preferred_mode - Sets the preferred mode of a connector
4234 * @connector: connector whose mode list should be processed
4235 * @hpref: horizontal resolution of preferred mode
4236 * @vpref: vertical resolution of preferred mode
4237 *
4238 * Marks a mode as preferred if it matches the resolution specified by @hpref
4239 * and @vpref.
4240 */
4241 void drm_set_preferred_mode(struct drm_connector *connector,
4242 int hpref, int vpref)
4243 {
4244 struct drm_display_mode *mode;
4245
4246 list_for_each_entry(mode, &connector->probed_modes, head) {
4247 if (mode->hdisplay == hpref &&
4248 mode->vdisplay == vpref)
4249 mode->type |= DRM_MODE_TYPE_PREFERRED;
4250 }
4251 }
4252 EXPORT_SYMBOL(drm_set_preferred_mode);
4253
4254 /**
4255 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4256 * data from a DRM display mode
4257 * @frame: HDMI AVI infoframe
4258 * @mode: DRM display mode
4259 *
4260 * Return: 0 on success or a negative error code on failure.
4261 */
4262 int
4263 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4264 const struct drm_display_mode *mode)
4265 {
4266 int err;
4267
4268 if (!frame || !mode)
4269 return -EINVAL;
4270
4271 err = hdmi_avi_infoframe_init(frame);
4272 if (err < 0)
4273 return err;
4274
4275 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4276 frame->pixel_repeat = 1;
4277
4278 frame->video_code = drm_match_cea_mode(mode);
4279
4280 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4281
4282 /*
4283 * Populate picture aspect ratio from either
4284 * user input (if specified) or from the CEA mode list.
4285 */
4286 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4287 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4288 frame->picture_aspect = mode->picture_aspect_ratio;
4289 else if (frame->video_code > 0)
4290 frame->picture_aspect = drm_get_cea_aspect_ratio(
4291 frame->video_code);
4292
4293 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4294 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4295
4296 return 0;
4297 }
4298 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4299
4300 /**
4301 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4302 * quantization range information
4303 * @frame: HDMI AVI infoframe
4304 * @mode: DRM display mode
4305 * @rgb_quant_range: RGB quantization range (Q)
4306 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4307 */
4308 void
4309 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4310 const struct drm_display_mode *mode,
4311 enum hdmi_quantization_range rgb_quant_range,
4312 bool rgb_quant_range_selectable)
4313 {
4314 /*
4315 * CEA-861:
4316 * "A Source shall not send a non-zero Q value that does not correspond
4317 * to the default RGB Quantization Range for the transmitted Picture
4318 * unless the Sink indicates support for the Q bit in a Video
4319 * Capabilities Data Block."
4320 *
4321 * HDMI 2.0 recommends sending non-zero Q when it does match the
4322 * default RGB quantization range for the mode, even when QS=0.
4323 */
4324 if (rgb_quant_range_selectable ||
4325 rgb_quant_range == drm_default_rgb_quant_range(mode))
4326 frame->quantization_range = rgb_quant_range;
4327 else
4328 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4329
4330 /*
4331 * CEA-861-F:
4332 * "When transmitting any RGB colorimetry, the Source should set the
4333 * YQ-field to match the RGB Quantization Range being transmitted
4334 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4335 * set YQ=1) and the Sink shall ignore the YQ-field."
4336 */
4337 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4338 frame->ycc_quantization_range =
4339 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4340 else
4341 frame->ycc_quantization_range =
4342 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4343 }
4344 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4345
4346 static enum hdmi_3d_structure
4347 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4348 {
4349 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4350
4351 switch (layout) {
4352 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4353 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4354 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4355 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4356 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4357 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4358 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4359 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4360 case DRM_MODE_FLAG_3D_L_DEPTH:
4361 return HDMI_3D_STRUCTURE_L_DEPTH;
4362 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4363 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4364 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4365 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4366 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4367 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4368 default:
4369 return HDMI_3D_STRUCTURE_INVALID;
4370 }
4371 }
4372
4373 /**
4374 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4375 * data from a DRM display mode
4376 * @frame: HDMI vendor infoframe
4377 * @mode: DRM display mode
4378 *
4379 * Note that there's is a need to send HDMI vendor infoframes only when using a
4380 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4381 * function will return -EINVAL, error that can be safely ignored.
4382 *
4383 * Return: 0 on success or a negative error code on failure.
4384 */
4385 int
4386 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4387 const struct drm_display_mode *mode)
4388 {
4389 int err;
4390 u32 s3d_flags;
4391 u8 vic;
4392
4393 if (!frame || !mode)
4394 return -EINVAL;
4395
4396 vic = drm_match_hdmi_mode(mode);
4397 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4398
4399 if (!vic && !s3d_flags)
4400 return -EINVAL;
4401
4402 if (vic && s3d_flags)
4403 return -EINVAL;
4404
4405 err = hdmi_vendor_infoframe_init(frame);
4406 if (err < 0)
4407 return err;
4408
4409 if (vic)
4410 frame->vic = vic;
4411 else
4412 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4413
4414 return 0;
4415 }
4416 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4417
4418 static int drm_parse_tiled_block(struct drm_connector *connector,
4419 struct displayid_block *block)
4420 {
4421 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4422 u16 w, h;
4423 u8 tile_v_loc, tile_h_loc;
4424 u8 num_v_tile, num_h_tile;
4425 struct drm_tile_group *tg;
4426
4427 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4428 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4429
4430 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4431 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4432 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4433 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4434
4435 connector->has_tile = true;
4436 if (tile->tile_cap & 0x80)
4437 connector->tile_is_single_monitor = true;
4438
4439 connector->num_h_tile = num_h_tile + 1;
4440 connector->num_v_tile = num_v_tile + 1;
4441 connector->tile_h_loc = tile_h_loc;
4442 connector->tile_v_loc = tile_v_loc;
4443 connector->tile_h_size = w + 1;
4444 connector->tile_v_size = h + 1;
4445
4446 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4447 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4448 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4449 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4450 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4451
4452 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4453 if (!tg) {
4454 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4455 }
4456 if (!tg)
4457 return -ENOMEM;
4458
4459 if (connector->tile_group != tg) {
4460 /* if we haven't got a pointer,
4461 take the reference, drop ref to old tile group */
4462 if (connector->tile_group) {
4463 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4464 }
4465 connector->tile_group = tg;
4466 } else
4467 /* if same tile group, then release the ref we just took. */
4468 drm_mode_put_tile_group(connector->dev, tg);
4469 return 0;
4470 }
4471
4472 static int drm_parse_display_id(struct drm_connector *connector,
4473 u8 *displayid, int length,
4474 bool is_edid_extension)
4475 {
4476 /* if this is an EDID extension the first byte will be 0x70 */
4477 int idx = 0;
4478 struct displayid_block *block;
4479 int ret;
4480
4481 if (is_edid_extension)
4482 idx = 1;
4483
4484 ret = validate_displayid(displayid, length, idx);
4485 if (ret)
4486 return ret;
4487
4488 idx += sizeof(struct displayid_hdr);
4489 while (block = (struct displayid_block *)&displayid[idx],
4490 idx + sizeof(struct displayid_block) <= length &&
4491 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4492 block->num_bytes > 0) {
4493 idx += block->num_bytes + sizeof(struct displayid_block);
4494 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4495 block->tag, block->rev, block->num_bytes);
4496
4497 switch (block->tag) {
4498 case DATA_BLOCK_TILED_DISPLAY:
4499 ret = drm_parse_tiled_block(connector, block);
4500 if (ret)
4501 return ret;
4502 break;
4503 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4504 /* handled in mode gathering code. */
4505 break;
4506 default:
4507 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
4508 break;
4509 }
4510 }
4511 return 0;
4512 }
4513
4514 static void drm_get_displayid(struct drm_connector *connector,
4515 struct edid *edid)
4516 {
4517 void *displayid = NULL;
4518 int ret;
4519 connector->has_tile = false;
4520 displayid = drm_find_displayid_extension(edid);
4521 if (!displayid) {
4522 /* drop reference to any tile group we had */
4523 goto out_drop_ref;
4524 }
4525
4526 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4527 if (ret < 0)
4528 goto out_drop_ref;
4529 if (!connector->has_tile)
4530 goto out_drop_ref;
4531 return;
4532 out_drop_ref:
4533 if (connector->tile_group) {
4534 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4535 connector->tile_group = NULL;
4536 }
4537 return;
4538 }
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