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drm/edid: VSDB yCBCr420 Deep Color mode bit definitions
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / drm_edid.c
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
36 #include <drm/drmP.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
41
42 #include "drm_crtc_internal.h"
43
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
47
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
51
52 /*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
77 /* Force 8bpc */
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
79 /* Force 12bpc */
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
81 /* Force 6bpc */
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
83 /* Force 10bpc */
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
87
88 struct detailed_mode_closure {
89 struct drm_connector *connector;
90 struct edid *edid;
91 bool preferred;
92 u32 quirks;
93 int modes;
94 };
95
96 #define LEVEL_DMT 0
97 #define LEVEL_GTF 1
98 #define LEVEL_GTF2 2
99 #define LEVEL_CVT 3
100
101 static const struct edid_quirk {
102 char vendor[4];
103 int product_id;
104 u32 quirks;
105 } edid_quirk_list[] = {
106 /* Acer AL1706 */
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
108 /* Acer F51 */
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
110 /* Unknown Acer */
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
112
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115
116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
118
119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
121
122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124
125 /* Belinea 10 15 55 */
126 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
127 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
128
129 /* Envision Peripherals, Inc. EN-7100e */
130 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
131 /* Envision EN2028 */
132 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
133
134 /* Funai Electronics PM36B */
135 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
136 EDID_QUIRK_DETAILED_IN_CM },
137
138 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
139 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
140
141 /* LG Philips LCD LP154W01-A5 */
142 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
143 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
144
145 /* Philips 107p5 CRT */
146 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
147
148 /* Proview AY765C */
149 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
150
151 /* Samsung SyncMaster 205BW. Note: irony */
152 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
153 /* Samsung SyncMaster 22[5-6]BW */
154 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
155 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
156
157 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
158 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
159
160 /* ViewSonic VA2026w */
161 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
162
163 /* Medion MD 30217 PG */
164 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
165
166 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
167 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
168
169 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
170 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
171
172 /* HTC Vive and Vive Pro VR Headsets */
173 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
174 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
175 };
176
177 /*
178 * Autogenerated from the DMT spec.
179 * This table is copied from xfree86/modes/xf86EdidModes.c.
180 */
181 static const struct drm_display_mode drm_dmt_modes[] = {
182 /* 0x01 - 640x350@85Hz */
183 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
184 736, 832, 0, 350, 382, 385, 445, 0,
185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
186 /* 0x02 - 640x400@85Hz */
187 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
188 736, 832, 0, 400, 401, 404, 445, 0,
189 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
190 /* 0x03 - 720x400@85Hz */
191 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
192 828, 936, 0, 400, 401, 404, 446, 0,
193 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
194 /* 0x04 - 640x480@60Hz */
195 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
196 752, 800, 0, 480, 490, 492, 525, 0,
197 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
198 /* 0x05 - 640x480@72Hz */
199 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
200 704, 832, 0, 480, 489, 492, 520, 0,
201 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
202 /* 0x06 - 640x480@75Hz */
203 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
204 720, 840, 0, 480, 481, 484, 500, 0,
205 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
206 /* 0x07 - 640x480@85Hz */
207 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
208 752, 832, 0, 480, 481, 484, 509, 0,
209 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
210 /* 0x08 - 800x600@56Hz */
211 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
212 896, 1024, 0, 600, 601, 603, 625, 0,
213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
214 /* 0x09 - 800x600@60Hz */
215 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
216 968, 1056, 0, 600, 601, 605, 628, 0,
217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
218 /* 0x0a - 800x600@72Hz */
219 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
220 976, 1040, 0, 600, 637, 643, 666, 0,
221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
222 /* 0x0b - 800x600@75Hz */
223 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
224 896, 1056, 0, 600, 601, 604, 625, 0,
225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
226 /* 0x0c - 800x600@85Hz */
227 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
228 896, 1048, 0, 600, 601, 604, 631, 0,
229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
230 /* 0x0d - 800x600@120Hz RB */
231 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
232 880, 960, 0, 600, 603, 607, 636, 0,
233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
234 /* 0x0e - 848x480@60Hz */
235 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
236 976, 1088, 0, 480, 486, 494, 517, 0,
237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
238 /* 0x0f - 1024x768@43Hz, interlace */
239 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
240 1208, 1264, 0, 768, 768, 776, 817, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
242 DRM_MODE_FLAG_INTERLACE) },
243 /* 0x10 - 1024x768@60Hz */
244 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
245 1184, 1344, 0, 768, 771, 777, 806, 0,
246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
247 /* 0x11 - 1024x768@70Hz */
248 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
249 1184, 1328, 0, 768, 771, 777, 806, 0,
250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
251 /* 0x12 - 1024x768@75Hz */
252 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
253 1136, 1312, 0, 768, 769, 772, 800, 0,
254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
255 /* 0x13 - 1024x768@85Hz */
256 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
257 1168, 1376, 0, 768, 769, 772, 808, 0,
258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x14 - 1024x768@120Hz RB */
260 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
261 1104, 1184, 0, 768, 771, 775, 813, 0,
262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
263 /* 0x15 - 1152x864@75Hz */
264 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
265 1344, 1600, 0, 864, 865, 868, 900, 0,
266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
267 /* 0x55 - 1280x720@60Hz */
268 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
269 1430, 1650, 0, 720, 725, 730, 750, 0,
270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
271 /* 0x16 - 1280x768@60Hz RB */
272 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
273 1360, 1440, 0, 768, 771, 778, 790, 0,
274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
275 /* 0x17 - 1280x768@60Hz */
276 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
277 1472, 1664, 0, 768, 771, 778, 798, 0,
278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
279 /* 0x18 - 1280x768@75Hz */
280 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
281 1488, 1696, 0, 768, 771, 778, 805, 0,
282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
283 /* 0x19 - 1280x768@85Hz */
284 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
285 1496, 1712, 0, 768, 771, 778, 809, 0,
286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
287 /* 0x1a - 1280x768@120Hz RB */
288 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
289 1360, 1440, 0, 768, 771, 778, 813, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
291 /* 0x1b - 1280x800@60Hz RB */
292 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
293 1360, 1440, 0, 800, 803, 809, 823, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
295 /* 0x1c - 1280x800@60Hz */
296 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
297 1480, 1680, 0, 800, 803, 809, 831, 0,
298 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
299 /* 0x1d - 1280x800@75Hz */
300 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
301 1488, 1696, 0, 800, 803, 809, 838, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x1e - 1280x800@85Hz */
304 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
305 1496, 1712, 0, 800, 803, 809, 843, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
307 /* 0x1f - 1280x800@120Hz RB */
308 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
309 1360, 1440, 0, 800, 803, 809, 847, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
311 /* 0x20 - 1280x960@60Hz */
312 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
313 1488, 1800, 0, 960, 961, 964, 1000, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x21 - 1280x960@85Hz */
316 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
317 1504, 1728, 0, 960, 961, 964, 1011, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
319 /* 0x22 - 1280x960@120Hz RB */
320 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
321 1360, 1440, 0, 960, 963, 967, 1017, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
323 /* 0x23 - 1280x1024@60Hz */
324 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
325 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
327 /* 0x24 - 1280x1024@75Hz */
328 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
329 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
331 /* 0x25 - 1280x1024@85Hz */
332 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
333 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x26 - 1280x1024@120Hz RB */
336 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
337 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
339 /* 0x27 - 1360x768@60Hz */
340 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
341 1536, 1792, 0, 768, 771, 777, 795, 0,
342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x28 - 1360x768@120Hz RB */
344 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
345 1440, 1520, 0, 768, 771, 776, 813, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
347 /* 0x51 - 1366x768@60Hz */
348 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
349 1579, 1792, 0, 768, 771, 774, 798, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
351 /* 0x56 - 1366x768@60Hz */
352 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
353 1436, 1500, 0, 768, 769, 772, 800, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
355 /* 0x29 - 1400x1050@60Hz RB */
356 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
357 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
359 /* 0x2a - 1400x1050@60Hz */
360 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
361 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x2b - 1400x1050@75Hz */
364 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
365 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x2c - 1400x1050@85Hz */
368 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
369 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
370 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x2d - 1400x1050@120Hz RB */
372 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
373 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
375 /* 0x2e - 1440x900@60Hz RB */
376 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
377 1520, 1600, 0, 900, 903, 909, 926, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
379 /* 0x2f - 1440x900@60Hz */
380 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
381 1672, 1904, 0, 900, 903, 909, 934, 0,
382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
383 /* 0x30 - 1440x900@75Hz */
384 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
385 1688, 1936, 0, 900, 903, 909, 942, 0,
386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x31 - 1440x900@85Hz */
388 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
389 1696, 1952, 0, 900, 903, 909, 948, 0,
390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x32 - 1440x900@120Hz RB */
392 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
393 1520, 1600, 0, 900, 903, 909, 953, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
395 /* 0x53 - 1600x900@60Hz */
396 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
397 1704, 1800, 0, 900, 901, 904, 1000, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
399 /* 0x33 - 1600x1200@60Hz */
400 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
401 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
403 /* 0x34 - 1600x1200@65Hz */
404 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
405 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x35 - 1600x1200@70Hz */
408 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
409 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x36 - 1600x1200@75Hz */
412 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
413 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
415 /* 0x37 - 1600x1200@85Hz */
416 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
417 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x38 - 1600x1200@120Hz RB */
420 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
421 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
423 /* 0x39 - 1680x1050@60Hz RB */
424 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
425 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
427 /* 0x3a - 1680x1050@60Hz */
428 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
429 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
431 /* 0x3b - 1680x1050@75Hz */
432 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
433 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
435 /* 0x3c - 1680x1050@85Hz */
436 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
437 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 0x3d - 1680x1050@120Hz RB */
440 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
441 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
443 /* 0x3e - 1792x1344@60Hz */
444 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
445 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
447 /* 0x3f - 1792x1344@75Hz */
448 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
449 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
451 /* 0x40 - 1792x1344@120Hz RB */
452 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
453 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
455 /* 0x41 - 1856x1392@60Hz */
456 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
457 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x42 - 1856x1392@75Hz */
460 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
461 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x43 - 1856x1392@120Hz RB */
464 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
465 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
467 /* 0x52 - 1920x1080@60Hz */
468 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
469 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
471 /* 0x44 - 1920x1200@60Hz RB */
472 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
473 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
475 /* 0x45 - 1920x1200@60Hz */
476 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
477 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 0x46 - 1920x1200@75Hz */
480 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
481 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
483 /* 0x47 - 1920x1200@85Hz */
484 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
485 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x48 - 1920x1200@120Hz RB */
488 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
489 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
491 /* 0x49 - 1920x1440@60Hz */
492 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
493 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x4a - 1920x1440@75Hz */
496 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
497 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
499 /* 0x4b - 1920x1440@120Hz RB */
500 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
501 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
503 /* 0x54 - 2048x1152@60Hz */
504 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
505 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
507 /* 0x4c - 2560x1600@60Hz RB */
508 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
509 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
511 /* 0x4d - 2560x1600@60Hz */
512 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
513 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
515 /* 0x4e - 2560x1600@75Hz */
516 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
517 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
519 /* 0x4f - 2560x1600@85Hz */
520 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
521 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
523 /* 0x50 - 2560x1600@120Hz RB */
524 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
525 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
527 /* 0x57 - 4096x2160@60Hz RB */
528 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
529 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
531 /* 0x58 - 4096x2160@59.94Hz RB */
532 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
533 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
535 };
536
537 /*
538 * These more or less come from the DMT spec. The 720x400 modes are
539 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
540 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
541 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
542 * mode.
543 *
544 * The DMT modes have been fact-checked; the rest are mild guesses.
545 */
546 static const struct drm_display_mode edid_est_modes[] = {
547 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
548 968, 1056, 0, 600, 601, 605, 628, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
550 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
551 896, 1024, 0, 600, 601, 603, 625, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
553 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
554 720, 840, 0, 480, 481, 484, 500, 0,
555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
556 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
557 704, 832, 0, 480, 489, 492, 520, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
559 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
560 768, 864, 0, 480, 483, 486, 525, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
562 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
563 752, 800, 0, 480, 490, 492, 525, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
565 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
566 846, 900, 0, 400, 421, 423, 449, 0,
567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
568 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
569 846, 900, 0, 400, 412, 414, 449, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
571 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
572 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
574 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
575 1136, 1312, 0, 768, 769, 772, 800, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
577 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
578 1184, 1328, 0, 768, 771, 777, 806, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
580 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
581 1184, 1344, 0, 768, 771, 777, 806, 0,
582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
583 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
584 1208, 1264, 0, 768, 768, 776, 817, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
586 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
587 928, 1152, 0, 624, 625, 628, 667, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
590 896, 1056, 0, 600, 601, 604, 625, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
593 976, 1040, 0, 600, 637, 643, 666, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
595 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
596 1344, 1600, 0, 864, 865, 868, 900, 0,
597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
598 };
599
600 struct minimode {
601 short w;
602 short h;
603 short r;
604 short rb;
605 };
606
607 static const struct minimode est3_modes[] = {
608 /* byte 6 */
609 { 640, 350, 85, 0 },
610 { 640, 400, 85, 0 },
611 { 720, 400, 85, 0 },
612 { 640, 480, 85, 0 },
613 { 848, 480, 60, 0 },
614 { 800, 600, 85, 0 },
615 { 1024, 768, 85, 0 },
616 { 1152, 864, 75, 0 },
617 /* byte 7 */
618 { 1280, 768, 60, 1 },
619 { 1280, 768, 60, 0 },
620 { 1280, 768, 75, 0 },
621 { 1280, 768, 85, 0 },
622 { 1280, 960, 60, 0 },
623 { 1280, 960, 85, 0 },
624 { 1280, 1024, 60, 0 },
625 { 1280, 1024, 85, 0 },
626 /* byte 8 */
627 { 1360, 768, 60, 0 },
628 { 1440, 900, 60, 1 },
629 { 1440, 900, 60, 0 },
630 { 1440, 900, 75, 0 },
631 { 1440, 900, 85, 0 },
632 { 1400, 1050, 60, 1 },
633 { 1400, 1050, 60, 0 },
634 { 1400, 1050, 75, 0 },
635 /* byte 9 */
636 { 1400, 1050, 85, 0 },
637 { 1680, 1050, 60, 1 },
638 { 1680, 1050, 60, 0 },
639 { 1680, 1050, 75, 0 },
640 { 1680, 1050, 85, 0 },
641 { 1600, 1200, 60, 0 },
642 { 1600, 1200, 65, 0 },
643 { 1600, 1200, 70, 0 },
644 /* byte 10 */
645 { 1600, 1200, 75, 0 },
646 { 1600, 1200, 85, 0 },
647 { 1792, 1344, 60, 0 },
648 { 1792, 1344, 75, 0 },
649 { 1856, 1392, 60, 0 },
650 { 1856, 1392, 75, 0 },
651 { 1920, 1200, 60, 1 },
652 { 1920, 1200, 60, 0 },
653 /* byte 11 */
654 { 1920, 1200, 75, 0 },
655 { 1920, 1200, 85, 0 },
656 { 1920, 1440, 60, 0 },
657 { 1920, 1440, 75, 0 },
658 };
659
660 static const struct minimode extra_modes[] = {
661 { 1024, 576, 60, 0 },
662 { 1366, 768, 60, 0 },
663 { 1600, 900, 60, 0 },
664 { 1680, 945, 60, 0 },
665 { 1920, 1080, 60, 0 },
666 { 2048, 1152, 60, 0 },
667 { 2048, 1536, 60, 0 },
668 };
669
670 /*
671 * Probably taken from CEA-861 spec.
672 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
673 *
674 * Index using the VIC.
675 */
676 static const struct drm_display_mode edid_cea_modes[] = {
677 /* 0 - dummy, VICs start at 1 */
678 { },
679 /* 1 - 640x480@60Hz */
680 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
681 752, 800, 0, 480, 490, 492, 525, 0,
682 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
684 /* 2 - 720x480@60Hz */
685 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
686 798, 858, 0, 480, 489, 495, 525, 0,
687 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
688 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
689 /* 3 - 720x480@60Hz */
690 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
691 798, 858, 0, 480, 489, 495, 525, 0,
692 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
693 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
694 /* 4 - 1280x720@60Hz */
695 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
696 1430, 1650, 0, 720, 725, 730, 750, 0,
697 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
698 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
699 /* 5 - 1920x1080i@60Hz */
700 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
701 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
702 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
703 DRM_MODE_FLAG_INTERLACE),
704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
705 /* 6 - 720(1440)x480i@60Hz */
706 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
707 801, 858, 0, 480, 488, 494, 525, 0,
708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
709 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
711 /* 7 - 720(1440)x480i@60Hz */
712 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
713 801, 858, 0, 480, 488, 494, 525, 0,
714 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
715 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
717 /* 8 - 720(1440)x240@60Hz */
718 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
719 801, 858, 0, 240, 244, 247, 262, 0,
720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
721 DRM_MODE_FLAG_DBLCLK),
722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
723 /* 9 - 720(1440)x240@60Hz */
724 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
725 801, 858, 0, 240, 244, 247, 262, 0,
726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
727 DRM_MODE_FLAG_DBLCLK),
728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
729 /* 10 - 2880x480i@60Hz */
730 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
731 3204, 3432, 0, 480, 488, 494, 525, 0,
732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
733 DRM_MODE_FLAG_INTERLACE),
734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
735 /* 11 - 2880x480i@60Hz */
736 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
737 3204, 3432, 0, 480, 488, 494, 525, 0,
738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
739 DRM_MODE_FLAG_INTERLACE),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741 /* 12 - 2880x240@60Hz */
742 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
743 3204, 3432, 0, 240, 244, 247, 262, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 13 - 2880x240@60Hz */
747 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
748 3204, 3432, 0, 240, 244, 247, 262, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
751 /* 14 - 1440x480@60Hz */
752 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
753 1596, 1716, 0, 480, 489, 495, 525, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
756 /* 15 - 1440x480@60Hz */
757 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
758 1596, 1716, 0, 480, 489, 495, 525, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
760 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 16 - 1920x1080@60Hz */
762 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
763 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
765 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
766 /* 17 - 720x576@50Hz */
767 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
768 796, 864, 0, 576, 581, 586, 625, 0,
769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
770 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 18 - 720x576@50Hz */
772 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
773 796, 864, 0, 576, 581, 586, 625, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
775 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776 /* 19 - 1280x720@50Hz */
777 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
778 1760, 1980, 0, 720, 725, 730, 750, 0,
779 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
780 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781 /* 20 - 1920x1080i@50Hz */
782 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
783 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
785 DRM_MODE_FLAG_INTERLACE),
786 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
787 /* 21 - 720(1440)x576i@50Hz */
788 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
789 795, 864, 0, 576, 580, 586, 625, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
791 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
792 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
793 /* 22 - 720(1440)x576i@50Hz */
794 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
795 795, 864, 0, 576, 580, 586, 625, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
797 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
798 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
799 /* 23 - 720(1440)x288@50Hz */
800 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
801 795, 864, 0, 288, 290, 293, 312, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
803 DRM_MODE_FLAG_DBLCLK),
804 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
805 /* 24 - 720(1440)x288@50Hz */
806 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
807 795, 864, 0, 288, 290, 293, 312, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
809 DRM_MODE_FLAG_DBLCLK),
810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
811 /* 25 - 2880x576i@50Hz */
812 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
813 3180, 3456, 0, 576, 580, 586, 625, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
815 DRM_MODE_FLAG_INTERLACE),
816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
817 /* 26 - 2880x576i@50Hz */
818 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
819 3180, 3456, 0, 576, 580, 586, 625, 0,
820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
821 DRM_MODE_FLAG_INTERLACE),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 27 - 2880x288@50Hz */
824 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
825 3180, 3456, 0, 288, 290, 293, 312, 0,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
828 /* 28 - 2880x288@50Hz */
829 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
830 3180, 3456, 0, 288, 290, 293, 312, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 29 - 1440x576@50Hz */
834 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
835 1592, 1728, 0, 576, 581, 586, 625, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
838 /* 30 - 1440x576@50Hz */
839 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
840 1592, 1728, 0, 576, 581, 586, 625, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
842 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 31 - 1920x1080@50Hz */
844 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
845 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
847 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
848 /* 32 - 1920x1080@24Hz */
849 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
850 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
852 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
853 /* 33 - 1920x1080@25Hz */
854 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
855 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
857 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 34 - 1920x1080@30Hz */
859 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
860 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
862 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 35 - 2880x480@60Hz */
864 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
865 3192, 3432, 0, 480, 489, 495, 525, 0,
866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
867 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
868 /* 36 - 2880x480@60Hz */
869 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
870 3192, 3432, 0, 480, 489, 495, 525, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
872 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 37 - 2880x576@50Hz */
874 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
875 3184, 3456, 0, 576, 581, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
877 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
878 /* 38 - 2880x576@50Hz */
879 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
880 3184, 3456, 0, 576, 581, 586, 625, 0,
881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
882 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
883 /* 39 - 1920x1080i@50Hz */
884 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
885 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
887 DRM_MODE_FLAG_INTERLACE),
888 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
889 /* 40 - 1920x1080i@100Hz */
890 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
891 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
893 DRM_MODE_FLAG_INTERLACE),
894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
895 /* 41 - 1280x720@100Hz */
896 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
897 1760, 1980, 0, 720, 725, 730, 750, 0,
898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
899 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 42 - 720x576@100Hz */
901 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
902 796, 864, 0, 576, 581, 586, 625, 0,
903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
904 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
905 /* 43 - 720x576@100Hz */
906 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
907 796, 864, 0, 576, 581, 586, 625, 0,
908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
909 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 44 - 720(1440)x576i@100Hz */
911 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
912 795, 864, 0, 576, 580, 586, 625, 0,
913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
914 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
915 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
916 /* 45 - 720(1440)x576i@100Hz */
917 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
918 795, 864, 0, 576, 580, 586, 625, 0,
919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
920 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
921 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 46 - 1920x1080i@120Hz */
923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
924 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
926 DRM_MODE_FLAG_INTERLACE),
927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
928 /* 47 - 1280x720@120Hz */
929 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
930 1430, 1650, 0, 720, 725, 730, 750, 0,
931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
932 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
933 /* 48 - 720x480@120Hz */
934 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
935 798, 858, 0, 480, 489, 495, 525, 0,
936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
937 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
938 /* 49 - 720x480@120Hz */
939 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
940 798, 858, 0, 480, 489, 495, 525, 0,
941 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
942 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 50 - 720(1440)x480i@120Hz */
944 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
945 801, 858, 0, 480, 488, 494, 525, 0,
946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
947 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
949 /* 51 - 720(1440)x480i@120Hz */
950 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
951 801, 858, 0, 480, 488, 494, 525, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
954 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955 /* 52 - 720x576@200Hz */
956 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
957 796, 864, 0, 576, 581, 586, 625, 0,
958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
959 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
960 /* 53 - 720x576@200Hz */
961 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
962 796, 864, 0, 576, 581, 586, 625, 0,
963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
964 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
965 /* 54 - 720(1440)x576i@200Hz */
966 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
967 795, 864, 0, 576, 580, 586, 625, 0,
968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
969 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
970 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
971 /* 55 - 720(1440)x576i@200Hz */
972 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
973 795, 864, 0, 576, 580, 586, 625, 0,
974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
975 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
976 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
977 /* 56 - 720x480@240Hz */
978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
979 798, 858, 0, 480, 489, 495, 525, 0,
980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
981 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
982 /* 57 - 720x480@240Hz */
983 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
984 798, 858, 0, 480, 489, 495, 525, 0,
985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
986 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
987 /* 58 - 720(1440)x480i@240Hz */
988 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
989 801, 858, 0, 480, 488, 494, 525, 0,
990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
991 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
992 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
993 /* 59 - 720(1440)x480i@240Hz */
994 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
995 801, 858, 0, 480, 488, 494, 525, 0,
996 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
997 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
998 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 60 - 1280x720@24Hz */
1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1001 3080, 3300, 0, 720, 725, 730, 750, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 61 - 1280x720@25Hz */
1005 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1006 3740, 3960, 0, 720, 725, 730, 750, 0,
1007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1008 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1009 /* 62 - 1280x720@30Hz */
1010 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1011 3080, 3300, 0, 720, 725, 730, 750, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1013 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 63 - 1920x1080@120Hz */
1015 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1016 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1019 /* 64 - 1920x1080@100Hz */
1020 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1021 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1024 /* 65 - 1280x720@24Hz */
1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1026 3080, 3300, 0, 720, 725, 730, 750, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1029 /* 66 - 1280x720@25Hz */
1030 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1031 3740, 3960, 0, 720, 725, 730, 750, 0,
1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1033 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1034 /* 67 - 1280x720@30Hz */
1035 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1036 3080, 3300, 0, 720, 725, 730, 750, 0,
1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1038 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1039 /* 68 - 1280x720@50Hz */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1041 1760, 1980, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1044 /* 69 - 1280x720@60Hz */
1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1046 1430, 1650, 0, 720, 725, 730, 750, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1049 /* 70 - 1280x720@100Hz */
1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1051 1760, 1980, 0, 720, 725, 730, 750, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1054 /* 71 - 1280x720@120Hz */
1055 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1056 1430, 1650, 0, 720, 725, 730, 750, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1059 /* 72 - 1920x1080@24Hz */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1061 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1064 /* 73 - 1920x1080@25Hz */
1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1066 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 74 - 1920x1080@30Hz */
1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1071 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 75 - 1920x1080@50Hz */
1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1076 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 76 - 1920x1080@60Hz */
1080 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1081 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 77 - 1920x1080@100Hz */
1085 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1086 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 78 - 1920x1080@120Hz */
1090 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1091 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 79 - 1680x720@24Hz */
1095 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1096 3080, 3300, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 80 - 1680x720@25Hz */
1100 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1101 2948, 3168, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 81 - 1680x720@30Hz */
1105 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1106 2420, 2640, 0, 720, 725, 730, 750, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 82 - 1680x720@50Hz */
1110 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1111 1980, 2200, 0, 720, 725, 730, 750, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 83 - 1680x720@60Hz */
1115 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1116 1980, 2200, 0, 720, 725, 730, 750, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 84 - 1680x720@100Hz */
1120 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1121 1780, 2000, 0, 720, 725, 730, 825, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 85 - 1680x720@120Hz */
1125 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1126 1780, 2000, 0, 720, 725, 730, 825, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 86 - 2560x1080@24Hz */
1130 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1131 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 87 - 2560x1080@25Hz */
1135 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1136 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 88 - 2560x1080@30Hz */
1140 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1141 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 89 - 2560x1080@50Hz */
1145 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1146 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 90 - 2560x1080@60Hz */
1150 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1151 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 91 - 2560x1080@100Hz */
1155 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1156 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 92 - 2560x1080@120Hz */
1160 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1161 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 93 - 3840x2160p@24Hz 16:9 */
1165 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1166 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1169 /* 94 - 3840x2160p@25Hz 16:9 */
1170 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1171 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1174 /* 95 - 3840x2160p@30Hz 16:9 */
1175 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1176 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1179 /* 96 - 3840x2160p@50Hz 16:9 */
1180 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1181 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1184 /* 97 - 3840x2160p@60Hz 16:9 */
1185 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1186 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1189 /* 98 - 4096x2160p@24Hz 256:135 */
1190 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1191 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1194 /* 99 - 4096x2160p@25Hz 256:135 */
1195 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1196 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1199 /* 100 - 4096x2160p@30Hz 256:135 */
1200 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1201 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1204 /* 101 - 4096x2160p@50Hz 256:135 */
1205 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1206 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1209 /* 102 - 4096x2160p@60Hz 256:135 */
1210 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1211 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1214 /* 103 - 3840x2160p@24Hz 64:27 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1216 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1219 /* 104 - 3840x2160p@25Hz 64:27 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1224 /* 105 - 3840x2160p@30Hz 64:27 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1229 /* 106 - 3840x2160p@50Hz 64:27 */
1230 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1231 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1234 /* 107 - 3840x2160p@60Hz 64:27 */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1236 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1239 };
1240
1241 /*
1242 * HDMI 1.4 4k modes. Index using the VIC.
1243 */
1244 static const struct drm_display_mode edid_4k_modes[] = {
1245 /* 0 - dummy, VICs start at 1 */
1246 { },
1247 /* 1 - 3840x2160@30Hz */
1248 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1249 3840, 4016, 4104, 4400, 0,
1250 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 .vrefresh = 30, },
1253 /* 2 - 3840x2160@25Hz */
1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1255 3840, 4896, 4984, 5280, 0,
1256 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258 .vrefresh = 25, },
1259 /* 3 - 3840x2160@24Hz */
1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1261 3840, 5116, 5204, 5500, 0,
1262 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1264 .vrefresh = 24, },
1265 /* 4 - 4096x2160@24Hz (SMPTE) */
1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1267 4096, 5116, 5204, 5500, 0,
1268 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 .vrefresh = 24, },
1271 };
1272
1273 /*** DDC fetch and block validation ***/
1274
1275 static const u8 edid_header[] = {
1276 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1277 };
1278
1279 /**
1280 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1281 * @raw_edid: pointer to raw base EDID block
1282 *
1283 * Sanity check the header of the base EDID block.
1284 *
1285 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1286 */
1287 int drm_edid_header_is_valid(const u8 *raw_edid)
1288 {
1289 int i, score = 0;
1290
1291 for (i = 0; i < sizeof(edid_header); i++)
1292 if (raw_edid[i] == edid_header[i])
1293 score++;
1294
1295 return score;
1296 }
1297 EXPORT_SYMBOL(drm_edid_header_is_valid);
1298
1299 static int edid_fixup __read_mostly = 6;
1300 module_param_named(edid_fixup, edid_fixup, int, 0400);
1301 MODULE_PARM_DESC(edid_fixup,
1302 "Minimum number of valid EDID header bytes (0-8, default 6)");
1303
1304 static void drm_get_displayid(struct drm_connector *connector,
1305 struct edid *edid);
1306
1307 static int drm_edid_block_checksum(const u8 *raw_edid)
1308 {
1309 int i;
1310 u8 csum = 0;
1311 for (i = 0; i < EDID_LENGTH; i++)
1312 csum += raw_edid[i];
1313
1314 return csum;
1315 }
1316
1317 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1318 {
1319 if (memchr_inv(in_edid, 0, length))
1320 return false;
1321
1322 return true;
1323 }
1324
1325 /**
1326 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1327 * @raw_edid: pointer to raw EDID block
1328 * @block: type of block to validate (0 for base, extension otherwise)
1329 * @print_bad_edid: if true, dump bad EDID blocks to the console
1330 * @edid_corrupt: if true, the header or checksum is invalid
1331 *
1332 * Validate a base or extension EDID block and optionally dump bad blocks to
1333 * the console.
1334 *
1335 * Return: True if the block is valid, false otherwise.
1336 */
1337 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1338 bool *edid_corrupt)
1339 {
1340 u8 csum;
1341 struct edid *edid = (struct edid *)raw_edid;
1342
1343 if (WARN_ON(!raw_edid))
1344 return false;
1345
1346 if (edid_fixup > 8 || edid_fixup < 0)
1347 edid_fixup = 6;
1348
1349 if (block == 0) {
1350 int score = drm_edid_header_is_valid(raw_edid);
1351 if (score == 8) {
1352 if (edid_corrupt)
1353 *edid_corrupt = false;
1354 } else if (score >= edid_fixup) {
1355 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1356 * The corrupt flag needs to be set here otherwise, the
1357 * fix-up code here will correct the problem, the
1358 * checksum is correct and the test fails
1359 */
1360 if (edid_corrupt)
1361 *edid_corrupt = true;
1362 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1363 memcpy(raw_edid, edid_header, sizeof(edid_header));
1364 } else {
1365 if (edid_corrupt)
1366 *edid_corrupt = true;
1367 goto bad;
1368 }
1369 }
1370
1371 csum = drm_edid_block_checksum(raw_edid);
1372 if (csum) {
1373 if (edid_corrupt)
1374 *edid_corrupt = true;
1375
1376 /* allow CEA to slide through, switches mangle this */
1377 if (raw_edid[0] == CEA_EXT) {
1378 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1379 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1380 } else {
1381 if (print_bad_edid)
1382 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1383
1384 goto bad;
1385 }
1386 }
1387
1388 /* per-block-type checks */
1389 switch (raw_edid[0]) {
1390 case 0: /* base */
1391 if (edid->version != 1) {
1392 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1393 goto bad;
1394 }
1395
1396 if (edid->revision > 4)
1397 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1398 break;
1399
1400 default:
1401 break;
1402 }
1403
1404 return true;
1405
1406 bad:
1407 if (print_bad_edid) {
1408 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1409 pr_notice("EDID block is all zeroes\n");
1410 } else {
1411 pr_notice("Raw EDID:\n");
1412 print_hex_dump(KERN_NOTICE,
1413 " \t", DUMP_PREFIX_NONE, 16, 1,
1414 raw_edid, EDID_LENGTH, false);
1415 }
1416 }
1417 return false;
1418 }
1419 EXPORT_SYMBOL(drm_edid_block_valid);
1420
1421 /**
1422 * drm_edid_is_valid - sanity check EDID data
1423 * @edid: EDID data
1424 *
1425 * Sanity-check an entire EDID record (including extensions)
1426 *
1427 * Return: True if the EDID data is valid, false otherwise.
1428 */
1429 bool drm_edid_is_valid(struct edid *edid)
1430 {
1431 int i;
1432 u8 *raw = (u8 *)edid;
1433
1434 if (!edid)
1435 return false;
1436
1437 for (i = 0; i <= edid->extensions; i++)
1438 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1439 return false;
1440
1441 return true;
1442 }
1443 EXPORT_SYMBOL(drm_edid_is_valid);
1444
1445 #define DDC_SEGMENT_ADDR 0x30
1446 /**
1447 * drm_do_probe_ddc_edid() - get EDID information via I2C
1448 * @data: I2C device adapter
1449 * @buf: EDID data buffer to be filled
1450 * @block: 128 byte EDID block to start fetching from
1451 * @len: EDID data buffer length to fetch
1452 *
1453 * Try to fetch EDID information by calling I2C driver functions.
1454 *
1455 * Return: 0 on success or -1 on failure.
1456 */
1457 static int
1458 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1459 {
1460 struct i2c_adapter *adapter = data;
1461 unsigned char start = block * EDID_LENGTH;
1462 unsigned char segment = block >> 1;
1463 unsigned char xfers = segment ? 3 : 2;
1464 int ret, retries = 5;
1465
1466 /*
1467 * The core I2C driver will automatically retry the transfer if the
1468 * adapter reports EAGAIN. However, we find that bit-banging transfers
1469 * are susceptible to errors under a heavily loaded machine and
1470 * generate spurious NAKs and timeouts. Retrying the transfer
1471 * of the individual block a few times seems to overcome this.
1472 */
1473 do {
1474 struct i2c_msg msgs[] = {
1475 {
1476 .addr = DDC_SEGMENT_ADDR,
1477 .flags = 0,
1478 .len = 1,
1479 .buf = &segment,
1480 }, {
1481 .addr = DDC_ADDR,
1482 .flags = 0,
1483 .len = 1,
1484 .buf = &start,
1485 }, {
1486 .addr = DDC_ADDR,
1487 .flags = I2C_M_RD,
1488 .len = len,
1489 .buf = buf,
1490 }
1491 };
1492
1493 /*
1494 * Avoid sending the segment addr to not upset non-compliant
1495 * DDC monitors.
1496 */
1497 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1498
1499 if (ret == -ENXIO) {
1500 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1501 adapter->name);
1502 break;
1503 }
1504 } while (ret != xfers && --retries);
1505
1506 return ret == xfers ? 0 : -1;
1507 }
1508
1509 static void connector_bad_edid(struct drm_connector *connector,
1510 u8 *edid, int num_blocks)
1511 {
1512 int i;
1513
1514 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1515 return;
1516
1517 dev_warn(connector->dev->dev,
1518 "%s: EDID is invalid:\n",
1519 connector->name);
1520 for (i = 0; i < num_blocks; i++) {
1521 u8 *block = edid + i * EDID_LENGTH;
1522 char prefix[20];
1523
1524 if (drm_edid_is_zero(block, EDID_LENGTH))
1525 sprintf(prefix, "\t[%02x] ZERO ", i);
1526 else if (!drm_edid_block_valid(block, i, false, NULL))
1527 sprintf(prefix, "\t[%02x] BAD ", i);
1528 else
1529 sprintf(prefix, "\t[%02x] GOOD ", i);
1530
1531 print_hex_dump(KERN_WARNING,
1532 prefix, DUMP_PREFIX_NONE, 16, 1,
1533 block, EDID_LENGTH, false);
1534 }
1535 }
1536
1537 /**
1538 * drm_do_get_edid - get EDID data using a custom EDID block read function
1539 * @connector: connector we're probing
1540 * @get_edid_block: EDID block read function
1541 * @data: private data passed to the block read function
1542 *
1543 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1544 * exposes a different interface to read EDID blocks this function can be used
1545 * to get EDID data using a custom block read function.
1546 *
1547 * As in the general case the DDC bus is accessible by the kernel at the I2C
1548 * level, drivers must make all reasonable efforts to expose it as an I2C
1549 * adapter and use drm_get_edid() instead of abusing this function.
1550 *
1551 * The EDID may be overridden using debugfs override_edid or firmare EDID
1552 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1553 * order. Having either of them bypasses actual EDID reads.
1554 *
1555 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1556 */
1557 struct edid *drm_do_get_edid(struct drm_connector *connector,
1558 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1559 size_t len),
1560 void *data)
1561 {
1562 int i, j = 0, valid_extensions = 0;
1563 u8 *edid, *new;
1564 struct edid *override = NULL;
1565
1566 if (connector->override_edid)
1567 override = drm_edid_duplicate((const struct edid *)
1568 connector->edid_blob_ptr->data);
1569
1570 if (!override)
1571 override = drm_load_edid_firmware(connector);
1572
1573 if (!IS_ERR_OR_NULL(override))
1574 return override;
1575
1576 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1577 return NULL;
1578
1579 /* base block fetch */
1580 for (i = 0; i < 4; i++) {
1581 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1582 goto out;
1583 if (drm_edid_block_valid(edid, 0, false,
1584 &connector->edid_corrupt))
1585 break;
1586 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1587 connector->null_edid_counter++;
1588 goto carp;
1589 }
1590 }
1591 if (i == 4)
1592 goto carp;
1593
1594 /* if there's no extensions, we're done */
1595 valid_extensions = edid[0x7e];
1596 if (valid_extensions == 0)
1597 return (struct edid *)edid;
1598
1599 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1600 if (!new)
1601 goto out;
1602 edid = new;
1603
1604 for (j = 1; j <= edid[0x7e]; j++) {
1605 u8 *block = edid + j * EDID_LENGTH;
1606
1607 for (i = 0; i < 4; i++) {
1608 if (get_edid_block(data, block, j, EDID_LENGTH))
1609 goto out;
1610 if (drm_edid_block_valid(block, j, false, NULL))
1611 break;
1612 }
1613
1614 if (i == 4)
1615 valid_extensions--;
1616 }
1617
1618 if (valid_extensions != edid[0x7e]) {
1619 u8 *base;
1620
1621 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1622
1623 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1624 edid[0x7e] = valid_extensions;
1625
1626 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1627 if (!new)
1628 goto out;
1629
1630 base = new;
1631 for (i = 0; i <= edid[0x7e]; i++) {
1632 u8 *block = edid + i * EDID_LENGTH;
1633
1634 if (!drm_edid_block_valid(block, i, false, NULL))
1635 continue;
1636
1637 memcpy(base, block, EDID_LENGTH);
1638 base += EDID_LENGTH;
1639 }
1640
1641 kfree(edid);
1642 edid = new;
1643 }
1644
1645 return (struct edid *)edid;
1646
1647 carp:
1648 connector_bad_edid(connector, edid, 1);
1649 out:
1650 kfree(edid);
1651 return NULL;
1652 }
1653 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1654
1655 /**
1656 * drm_probe_ddc() - probe DDC presence
1657 * @adapter: I2C adapter to probe
1658 *
1659 * Return: True on success, false on failure.
1660 */
1661 bool
1662 drm_probe_ddc(struct i2c_adapter *adapter)
1663 {
1664 unsigned char out;
1665
1666 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1667 }
1668 EXPORT_SYMBOL(drm_probe_ddc);
1669
1670 /**
1671 * drm_get_edid - get EDID data, if available
1672 * @connector: connector we're probing
1673 * @adapter: I2C adapter to use for DDC
1674 *
1675 * Poke the given I2C channel to grab EDID data if possible. If found,
1676 * attach it to the connector.
1677 *
1678 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1679 */
1680 struct edid *drm_get_edid(struct drm_connector *connector,
1681 struct i2c_adapter *adapter)
1682 {
1683 struct edid *edid;
1684
1685 if (connector->force == DRM_FORCE_OFF)
1686 return NULL;
1687
1688 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1689 return NULL;
1690
1691 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1692 if (edid)
1693 drm_get_displayid(connector, edid);
1694 return edid;
1695 }
1696 EXPORT_SYMBOL(drm_get_edid);
1697
1698 /**
1699 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1700 * @connector: connector we're probing
1701 * @adapter: I2C adapter to use for DDC
1702 *
1703 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1704 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1705 * switch DDC to the GPU which is retrieving EDID.
1706 *
1707 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1708 */
1709 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1710 struct i2c_adapter *adapter)
1711 {
1712 struct pci_dev *pdev = connector->dev->pdev;
1713 struct edid *edid;
1714
1715 vga_switcheroo_lock_ddc(pdev);
1716 edid = drm_get_edid(connector, adapter);
1717 vga_switcheroo_unlock_ddc(pdev);
1718
1719 return edid;
1720 }
1721 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1722
1723 /**
1724 * drm_edid_duplicate - duplicate an EDID and the extensions
1725 * @edid: EDID to duplicate
1726 *
1727 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1728 */
1729 struct edid *drm_edid_duplicate(const struct edid *edid)
1730 {
1731 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1732 }
1733 EXPORT_SYMBOL(drm_edid_duplicate);
1734
1735 /*** EDID parsing ***/
1736
1737 /**
1738 * edid_vendor - match a string against EDID's obfuscated vendor field
1739 * @edid: EDID to match
1740 * @vendor: vendor string
1741 *
1742 * Returns true if @vendor is in @edid, false otherwise
1743 */
1744 static bool edid_vendor(const struct edid *edid, const char *vendor)
1745 {
1746 char edid_vendor[3];
1747
1748 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1749 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1750 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1751 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1752
1753 return !strncmp(edid_vendor, vendor, 3);
1754 }
1755
1756 /**
1757 * edid_get_quirks - return quirk flags for a given EDID
1758 * @edid: EDID to process
1759 *
1760 * This tells subsequent routines what fixes they need to apply.
1761 */
1762 static u32 edid_get_quirks(const struct edid *edid)
1763 {
1764 const struct edid_quirk *quirk;
1765 int i;
1766
1767 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1768 quirk = &edid_quirk_list[i];
1769
1770 if (edid_vendor(edid, quirk->vendor) &&
1771 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1772 return quirk->quirks;
1773 }
1774
1775 return 0;
1776 }
1777
1778 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1779 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1780
1781 /**
1782 * edid_fixup_preferred - set preferred modes based on quirk list
1783 * @connector: has mode list to fix up
1784 * @quirks: quirks list
1785 *
1786 * Walk the mode list for @connector, clearing the preferred status
1787 * on existing modes and setting it anew for the right mode ala @quirks.
1788 */
1789 static void edid_fixup_preferred(struct drm_connector *connector,
1790 u32 quirks)
1791 {
1792 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1793 int target_refresh = 0;
1794 int cur_vrefresh, preferred_vrefresh;
1795
1796 if (list_empty(&connector->probed_modes))
1797 return;
1798
1799 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1800 target_refresh = 60;
1801 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1802 target_refresh = 75;
1803
1804 preferred_mode = list_first_entry(&connector->probed_modes,
1805 struct drm_display_mode, head);
1806
1807 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1808 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1809
1810 if (cur_mode == preferred_mode)
1811 continue;
1812
1813 /* Largest mode is preferred */
1814 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1815 preferred_mode = cur_mode;
1816
1817 cur_vrefresh = cur_mode->vrefresh ?
1818 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1819 preferred_vrefresh = preferred_mode->vrefresh ?
1820 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1821 /* At a given size, try to get closest to target refresh */
1822 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1823 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1824 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1825 preferred_mode = cur_mode;
1826 }
1827 }
1828
1829 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1830 }
1831
1832 static bool
1833 mode_is_rb(const struct drm_display_mode *mode)
1834 {
1835 return (mode->htotal - mode->hdisplay == 160) &&
1836 (mode->hsync_end - mode->hdisplay == 80) &&
1837 (mode->hsync_end - mode->hsync_start == 32) &&
1838 (mode->vsync_start - mode->vdisplay == 3);
1839 }
1840
1841 /*
1842 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1843 * @dev: Device to duplicate against
1844 * @hsize: Mode width
1845 * @vsize: Mode height
1846 * @fresh: Mode refresh rate
1847 * @rb: Mode reduced-blanking-ness
1848 *
1849 * Walk the DMT mode list looking for a match for the given parameters.
1850 *
1851 * Return: A newly allocated copy of the mode, or NULL if not found.
1852 */
1853 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1854 int hsize, int vsize, int fresh,
1855 bool rb)
1856 {
1857 int i;
1858
1859 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1860 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1861 if (hsize != ptr->hdisplay)
1862 continue;
1863 if (vsize != ptr->vdisplay)
1864 continue;
1865 if (fresh != drm_mode_vrefresh(ptr))
1866 continue;
1867 if (rb != mode_is_rb(ptr))
1868 continue;
1869
1870 return drm_mode_duplicate(dev, ptr);
1871 }
1872
1873 return NULL;
1874 }
1875 EXPORT_SYMBOL(drm_mode_find_dmt);
1876
1877 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1878
1879 static void
1880 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1881 {
1882 int i, n = 0;
1883 u8 d = ext[0x02];
1884 u8 *det_base = ext + d;
1885
1886 n = (127 - d) / 18;
1887 for (i = 0; i < n; i++)
1888 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1889 }
1890
1891 static void
1892 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1893 {
1894 unsigned int i, n = min((int)ext[0x02], 6);
1895 u8 *det_base = ext + 5;
1896
1897 if (ext[0x01] != 1)
1898 return; /* unknown version */
1899
1900 for (i = 0; i < n; i++)
1901 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1902 }
1903
1904 static void
1905 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1906 {
1907 int i;
1908 struct edid *edid = (struct edid *)raw_edid;
1909
1910 if (edid == NULL)
1911 return;
1912
1913 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1914 cb(&(edid->detailed_timings[i]), closure);
1915
1916 for (i = 1; i <= raw_edid[0x7e]; i++) {
1917 u8 *ext = raw_edid + (i * EDID_LENGTH);
1918 switch (*ext) {
1919 case CEA_EXT:
1920 cea_for_each_detailed_block(ext, cb, closure);
1921 break;
1922 case VTB_EXT:
1923 vtb_for_each_detailed_block(ext, cb, closure);
1924 break;
1925 default:
1926 break;
1927 }
1928 }
1929 }
1930
1931 static void
1932 is_rb(struct detailed_timing *t, void *data)
1933 {
1934 u8 *r = (u8 *)t;
1935 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1936 if (r[15] & 0x10)
1937 *(bool *)data = true;
1938 }
1939
1940 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1941 static bool
1942 drm_monitor_supports_rb(struct edid *edid)
1943 {
1944 if (edid->revision >= 4) {
1945 bool ret = false;
1946 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1947 return ret;
1948 }
1949
1950 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1951 }
1952
1953 static void
1954 find_gtf2(struct detailed_timing *t, void *data)
1955 {
1956 u8 *r = (u8 *)t;
1957 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1958 *(u8 **)data = r;
1959 }
1960
1961 /* Secondary GTF curve kicks in above some break frequency */
1962 static int
1963 drm_gtf2_hbreak(struct edid *edid)
1964 {
1965 u8 *r = NULL;
1966 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1967 return r ? (r[12] * 2) : 0;
1968 }
1969
1970 static int
1971 drm_gtf2_2c(struct edid *edid)
1972 {
1973 u8 *r = NULL;
1974 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1975 return r ? r[13] : 0;
1976 }
1977
1978 static int
1979 drm_gtf2_m(struct edid *edid)
1980 {
1981 u8 *r = NULL;
1982 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1983 return r ? (r[15] << 8) + r[14] : 0;
1984 }
1985
1986 static int
1987 drm_gtf2_k(struct edid *edid)
1988 {
1989 u8 *r = NULL;
1990 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1991 return r ? r[16] : 0;
1992 }
1993
1994 static int
1995 drm_gtf2_2j(struct edid *edid)
1996 {
1997 u8 *r = NULL;
1998 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1999 return r ? r[17] : 0;
2000 }
2001
2002 /**
2003 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2004 * @edid: EDID block to scan
2005 */
2006 static int standard_timing_level(struct edid *edid)
2007 {
2008 if (edid->revision >= 2) {
2009 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2010 return LEVEL_CVT;
2011 if (drm_gtf2_hbreak(edid))
2012 return LEVEL_GTF2;
2013 return LEVEL_GTF;
2014 }
2015 return LEVEL_DMT;
2016 }
2017
2018 /*
2019 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2020 * monitors fill with ascii space (0x20) instead.
2021 */
2022 static int
2023 bad_std_timing(u8 a, u8 b)
2024 {
2025 return (a == 0x00 && b == 0x00) ||
2026 (a == 0x01 && b == 0x01) ||
2027 (a == 0x20 && b == 0x20);
2028 }
2029
2030 /**
2031 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2032 * @connector: connector of for the EDID block
2033 * @edid: EDID block to scan
2034 * @t: standard timing params
2035 *
2036 * Take the standard timing params (in this case width, aspect, and refresh)
2037 * and convert them into a real mode using CVT/GTF/DMT.
2038 */
2039 static struct drm_display_mode *
2040 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2041 struct std_timing *t)
2042 {
2043 struct drm_device *dev = connector->dev;
2044 struct drm_display_mode *m, *mode = NULL;
2045 int hsize, vsize;
2046 int vrefresh_rate;
2047 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2048 >> EDID_TIMING_ASPECT_SHIFT;
2049 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2050 >> EDID_TIMING_VFREQ_SHIFT;
2051 int timing_level = standard_timing_level(edid);
2052
2053 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2054 return NULL;
2055
2056 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2057 hsize = t->hsize * 8 + 248;
2058 /* vrefresh_rate = vfreq + 60 */
2059 vrefresh_rate = vfreq + 60;
2060 /* the vdisplay is calculated based on the aspect ratio */
2061 if (aspect_ratio == 0) {
2062 if (edid->revision < 3)
2063 vsize = hsize;
2064 else
2065 vsize = (hsize * 10) / 16;
2066 } else if (aspect_ratio == 1)
2067 vsize = (hsize * 3) / 4;
2068 else if (aspect_ratio == 2)
2069 vsize = (hsize * 4) / 5;
2070 else
2071 vsize = (hsize * 9) / 16;
2072
2073 /* HDTV hack, part 1 */
2074 if (vrefresh_rate == 60 &&
2075 ((hsize == 1360 && vsize == 765) ||
2076 (hsize == 1368 && vsize == 769))) {
2077 hsize = 1366;
2078 vsize = 768;
2079 }
2080
2081 /*
2082 * If this connector already has a mode for this size and refresh
2083 * rate (because it came from detailed or CVT info), use that
2084 * instead. This way we don't have to guess at interlace or
2085 * reduced blanking.
2086 */
2087 list_for_each_entry(m, &connector->probed_modes, head)
2088 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2089 drm_mode_vrefresh(m) == vrefresh_rate)
2090 return NULL;
2091
2092 /* HDTV hack, part 2 */
2093 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2094 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2095 false);
2096 mode->hdisplay = 1366;
2097 mode->hsync_start = mode->hsync_start - 1;
2098 mode->hsync_end = mode->hsync_end - 1;
2099 return mode;
2100 }
2101
2102 /* check whether it can be found in default mode table */
2103 if (drm_monitor_supports_rb(edid)) {
2104 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2105 true);
2106 if (mode)
2107 return mode;
2108 }
2109 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2110 if (mode)
2111 return mode;
2112
2113 /* okay, generate it */
2114 switch (timing_level) {
2115 case LEVEL_DMT:
2116 break;
2117 case LEVEL_GTF:
2118 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2119 break;
2120 case LEVEL_GTF2:
2121 /*
2122 * This is potentially wrong if there's ever a monitor with
2123 * more than one ranges section, each claiming a different
2124 * secondary GTF curve. Please don't do that.
2125 */
2126 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2127 if (!mode)
2128 return NULL;
2129 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2130 drm_mode_destroy(dev, mode);
2131 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2132 vrefresh_rate, 0, 0,
2133 drm_gtf2_m(edid),
2134 drm_gtf2_2c(edid),
2135 drm_gtf2_k(edid),
2136 drm_gtf2_2j(edid));
2137 }
2138 break;
2139 case LEVEL_CVT:
2140 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2141 false);
2142 break;
2143 }
2144 return mode;
2145 }
2146
2147 /*
2148 * EDID is delightfully ambiguous about how interlaced modes are to be
2149 * encoded. Our internal representation is of frame height, but some
2150 * HDTV detailed timings are encoded as field height.
2151 *
2152 * The format list here is from CEA, in frame size. Technically we
2153 * should be checking refresh rate too. Whatever.
2154 */
2155 static void
2156 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2157 struct detailed_pixel_timing *pt)
2158 {
2159 int i;
2160 static const struct {
2161 int w, h;
2162 } cea_interlaced[] = {
2163 { 1920, 1080 },
2164 { 720, 480 },
2165 { 1440, 480 },
2166 { 2880, 480 },
2167 { 720, 576 },
2168 { 1440, 576 },
2169 { 2880, 576 },
2170 };
2171
2172 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2173 return;
2174
2175 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2176 if ((mode->hdisplay == cea_interlaced[i].w) &&
2177 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2178 mode->vdisplay *= 2;
2179 mode->vsync_start *= 2;
2180 mode->vsync_end *= 2;
2181 mode->vtotal *= 2;
2182 mode->vtotal |= 1;
2183 }
2184 }
2185
2186 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2187 }
2188
2189 /**
2190 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2191 * @dev: DRM device (needed to create new mode)
2192 * @edid: EDID block
2193 * @timing: EDID detailed timing info
2194 * @quirks: quirks to apply
2195 *
2196 * An EDID detailed timing block contains enough info for us to create and
2197 * return a new struct drm_display_mode.
2198 */
2199 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2200 struct edid *edid,
2201 struct detailed_timing *timing,
2202 u32 quirks)
2203 {
2204 struct drm_display_mode *mode;
2205 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2206 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2207 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2208 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2209 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2210 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2211 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2212 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2213 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2214
2215 /* ignore tiny modes */
2216 if (hactive < 64 || vactive < 64)
2217 return NULL;
2218
2219 if (pt->misc & DRM_EDID_PT_STEREO) {
2220 DRM_DEBUG_KMS("stereo mode not supported\n");
2221 return NULL;
2222 }
2223 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2224 DRM_DEBUG_KMS("composite sync not supported\n");
2225 }
2226
2227 /* it is incorrect if hsync/vsync width is zero */
2228 if (!hsync_pulse_width || !vsync_pulse_width) {
2229 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2230 "Wrong Hsync/Vsync pulse width\n");
2231 return NULL;
2232 }
2233
2234 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2235 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2236 if (!mode)
2237 return NULL;
2238
2239 goto set_size;
2240 }
2241
2242 mode = drm_mode_create(dev);
2243 if (!mode)
2244 return NULL;
2245
2246 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2247 timing->pixel_clock = cpu_to_le16(1088);
2248
2249 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2250
2251 mode->hdisplay = hactive;
2252 mode->hsync_start = mode->hdisplay + hsync_offset;
2253 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2254 mode->htotal = mode->hdisplay + hblank;
2255
2256 mode->vdisplay = vactive;
2257 mode->vsync_start = mode->vdisplay + vsync_offset;
2258 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2259 mode->vtotal = mode->vdisplay + vblank;
2260
2261 /* Some EDIDs have bogus h/vtotal values */
2262 if (mode->hsync_end > mode->htotal)
2263 mode->htotal = mode->hsync_end + 1;
2264 if (mode->vsync_end > mode->vtotal)
2265 mode->vtotal = mode->vsync_end + 1;
2266
2267 drm_mode_do_interlace_quirk(mode, pt);
2268
2269 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2270 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2271 }
2272
2273 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2274 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2275 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2276 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2277
2278 set_size:
2279 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2280 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2281
2282 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2283 mode->width_mm *= 10;
2284 mode->height_mm *= 10;
2285 }
2286
2287 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2288 mode->width_mm = edid->width_cm * 10;
2289 mode->height_mm = edid->height_cm * 10;
2290 }
2291
2292 mode->type = DRM_MODE_TYPE_DRIVER;
2293 mode->vrefresh = drm_mode_vrefresh(mode);
2294 drm_mode_set_name(mode);
2295
2296 return mode;
2297 }
2298
2299 static bool
2300 mode_in_hsync_range(const struct drm_display_mode *mode,
2301 struct edid *edid, u8 *t)
2302 {
2303 int hsync, hmin, hmax;
2304
2305 hmin = t[7];
2306 if (edid->revision >= 4)
2307 hmin += ((t[4] & 0x04) ? 255 : 0);
2308 hmax = t[8];
2309 if (edid->revision >= 4)
2310 hmax += ((t[4] & 0x08) ? 255 : 0);
2311 hsync = drm_mode_hsync(mode);
2312
2313 return (hsync <= hmax && hsync >= hmin);
2314 }
2315
2316 static bool
2317 mode_in_vsync_range(const struct drm_display_mode *mode,
2318 struct edid *edid, u8 *t)
2319 {
2320 int vsync, vmin, vmax;
2321
2322 vmin = t[5];
2323 if (edid->revision >= 4)
2324 vmin += ((t[4] & 0x01) ? 255 : 0);
2325 vmax = t[6];
2326 if (edid->revision >= 4)
2327 vmax += ((t[4] & 0x02) ? 255 : 0);
2328 vsync = drm_mode_vrefresh(mode);
2329
2330 return (vsync <= vmax && vsync >= vmin);
2331 }
2332
2333 static u32
2334 range_pixel_clock(struct edid *edid, u8 *t)
2335 {
2336 /* unspecified */
2337 if (t[9] == 0 || t[9] == 255)
2338 return 0;
2339
2340 /* 1.4 with CVT support gives us real precision, yay */
2341 if (edid->revision >= 4 && t[10] == 0x04)
2342 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2343
2344 /* 1.3 is pathetic, so fuzz up a bit */
2345 return t[9] * 10000 + 5001;
2346 }
2347
2348 static bool
2349 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2350 struct detailed_timing *timing)
2351 {
2352 u32 max_clock;
2353 u8 *t = (u8 *)timing;
2354
2355 if (!mode_in_hsync_range(mode, edid, t))
2356 return false;
2357
2358 if (!mode_in_vsync_range(mode, edid, t))
2359 return false;
2360
2361 if ((max_clock = range_pixel_clock(edid, t)))
2362 if (mode->clock > max_clock)
2363 return false;
2364
2365 /* 1.4 max horizontal check */
2366 if (edid->revision >= 4 && t[10] == 0x04)
2367 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2368 return false;
2369
2370 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2371 return false;
2372
2373 return true;
2374 }
2375
2376 static bool valid_inferred_mode(const struct drm_connector *connector,
2377 const struct drm_display_mode *mode)
2378 {
2379 const struct drm_display_mode *m;
2380 bool ok = false;
2381
2382 list_for_each_entry(m, &connector->probed_modes, head) {
2383 if (mode->hdisplay == m->hdisplay &&
2384 mode->vdisplay == m->vdisplay &&
2385 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2386 return false; /* duplicated */
2387 if (mode->hdisplay <= m->hdisplay &&
2388 mode->vdisplay <= m->vdisplay)
2389 ok = true;
2390 }
2391 return ok;
2392 }
2393
2394 static int
2395 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2396 struct detailed_timing *timing)
2397 {
2398 int i, modes = 0;
2399 struct drm_display_mode *newmode;
2400 struct drm_device *dev = connector->dev;
2401
2402 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2403 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2404 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2405 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2406 if (newmode) {
2407 drm_mode_probed_add(connector, newmode);
2408 modes++;
2409 }
2410 }
2411 }
2412
2413 return modes;
2414 }
2415
2416 /* fix up 1366x768 mode from 1368x768;
2417 * GFT/CVT can't express 1366 width which isn't dividable by 8
2418 */
2419 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2420 {
2421 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2422 mode->hdisplay = 1366;
2423 mode->hsync_start--;
2424 mode->hsync_end--;
2425 drm_mode_set_name(mode);
2426 }
2427 }
2428
2429 static int
2430 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2431 struct detailed_timing *timing)
2432 {
2433 int i, modes = 0;
2434 struct drm_display_mode *newmode;
2435 struct drm_device *dev = connector->dev;
2436
2437 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2438 const struct minimode *m = &extra_modes[i];
2439 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2440 if (!newmode)
2441 return modes;
2442
2443 drm_mode_fixup_1366x768(newmode);
2444 if (!mode_in_range(newmode, edid, timing) ||
2445 !valid_inferred_mode(connector, newmode)) {
2446 drm_mode_destroy(dev, newmode);
2447 continue;
2448 }
2449
2450 drm_mode_probed_add(connector, newmode);
2451 modes++;
2452 }
2453
2454 return modes;
2455 }
2456
2457 static int
2458 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2459 struct detailed_timing *timing)
2460 {
2461 int i, modes = 0;
2462 struct drm_display_mode *newmode;
2463 struct drm_device *dev = connector->dev;
2464 bool rb = drm_monitor_supports_rb(edid);
2465
2466 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2467 const struct minimode *m = &extra_modes[i];
2468 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2469 if (!newmode)
2470 return modes;
2471
2472 drm_mode_fixup_1366x768(newmode);
2473 if (!mode_in_range(newmode, edid, timing) ||
2474 !valid_inferred_mode(connector, newmode)) {
2475 drm_mode_destroy(dev, newmode);
2476 continue;
2477 }
2478
2479 drm_mode_probed_add(connector, newmode);
2480 modes++;
2481 }
2482
2483 return modes;
2484 }
2485
2486 static void
2487 do_inferred_modes(struct detailed_timing *timing, void *c)
2488 {
2489 struct detailed_mode_closure *closure = c;
2490 struct detailed_non_pixel *data = &timing->data.other_data;
2491 struct detailed_data_monitor_range *range = &data->data.range;
2492
2493 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2494 return;
2495
2496 closure->modes += drm_dmt_modes_for_range(closure->connector,
2497 closure->edid,
2498 timing);
2499
2500 if (!version_greater(closure->edid, 1, 1))
2501 return; /* GTF not defined yet */
2502
2503 switch (range->flags) {
2504 case 0x02: /* secondary gtf, XXX could do more */
2505 case 0x00: /* default gtf */
2506 closure->modes += drm_gtf_modes_for_range(closure->connector,
2507 closure->edid,
2508 timing);
2509 break;
2510 case 0x04: /* cvt, only in 1.4+ */
2511 if (!version_greater(closure->edid, 1, 3))
2512 break;
2513
2514 closure->modes += drm_cvt_modes_for_range(closure->connector,
2515 closure->edid,
2516 timing);
2517 break;
2518 case 0x01: /* just the ranges, no formula */
2519 default:
2520 break;
2521 }
2522 }
2523
2524 static int
2525 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2526 {
2527 struct detailed_mode_closure closure = {
2528 .connector = connector,
2529 .edid = edid,
2530 };
2531
2532 if (version_greater(edid, 1, 0))
2533 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2534 &closure);
2535
2536 return closure.modes;
2537 }
2538
2539 static int
2540 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2541 {
2542 int i, j, m, modes = 0;
2543 struct drm_display_mode *mode;
2544 u8 *est = ((u8 *)timing) + 6;
2545
2546 for (i = 0; i < 6; i++) {
2547 for (j = 7; j >= 0; j--) {
2548 m = (i * 8) + (7 - j);
2549 if (m >= ARRAY_SIZE(est3_modes))
2550 break;
2551 if (est[i] & (1 << j)) {
2552 mode = drm_mode_find_dmt(connector->dev,
2553 est3_modes[m].w,
2554 est3_modes[m].h,
2555 est3_modes[m].r,
2556 est3_modes[m].rb);
2557 if (mode) {
2558 drm_mode_probed_add(connector, mode);
2559 modes++;
2560 }
2561 }
2562 }
2563 }
2564
2565 return modes;
2566 }
2567
2568 static void
2569 do_established_modes(struct detailed_timing *timing, void *c)
2570 {
2571 struct detailed_mode_closure *closure = c;
2572 struct detailed_non_pixel *data = &timing->data.other_data;
2573
2574 if (data->type == EDID_DETAIL_EST_TIMINGS)
2575 closure->modes += drm_est3_modes(closure->connector, timing);
2576 }
2577
2578 /**
2579 * add_established_modes - get est. modes from EDID and add them
2580 * @connector: connector to add mode(s) to
2581 * @edid: EDID block to scan
2582 *
2583 * Each EDID block contains a bitmap of the supported "established modes" list
2584 * (defined above). Tease them out and add them to the global modes list.
2585 */
2586 static int
2587 add_established_modes(struct drm_connector *connector, struct edid *edid)
2588 {
2589 struct drm_device *dev = connector->dev;
2590 unsigned long est_bits = edid->established_timings.t1 |
2591 (edid->established_timings.t2 << 8) |
2592 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2593 int i, modes = 0;
2594 struct detailed_mode_closure closure = {
2595 .connector = connector,
2596 .edid = edid,
2597 };
2598
2599 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2600 if (est_bits & (1<<i)) {
2601 struct drm_display_mode *newmode;
2602 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2603 if (newmode) {
2604 drm_mode_probed_add(connector, newmode);
2605 modes++;
2606 }
2607 }
2608 }
2609
2610 if (version_greater(edid, 1, 0))
2611 drm_for_each_detailed_block((u8 *)edid,
2612 do_established_modes, &closure);
2613
2614 return modes + closure.modes;
2615 }
2616
2617 static void
2618 do_standard_modes(struct detailed_timing *timing, void *c)
2619 {
2620 struct detailed_mode_closure *closure = c;
2621 struct detailed_non_pixel *data = &timing->data.other_data;
2622 struct drm_connector *connector = closure->connector;
2623 struct edid *edid = closure->edid;
2624
2625 if (data->type == EDID_DETAIL_STD_MODES) {
2626 int i;
2627 for (i = 0; i < 6; i++) {
2628 struct std_timing *std;
2629 struct drm_display_mode *newmode;
2630
2631 std = &data->data.timings[i];
2632 newmode = drm_mode_std(connector, edid, std);
2633 if (newmode) {
2634 drm_mode_probed_add(connector, newmode);
2635 closure->modes++;
2636 }
2637 }
2638 }
2639 }
2640
2641 /**
2642 * add_standard_modes - get std. modes from EDID and add them
2643 * @connector: connector to add mode(s) to
2644 * @edid: EDID block to scan
2645 *
2646 * Standard modes can be calculated using the appropriate standard (DMT,
2647 * GTF or CVT. Grab them from @edid and add them to the list.
2648 */
2649 static int
2650 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2651 {
2652 int i, modes = 0;
2653 struct detailed_mode_closure closure = {
2654 .connector = connector,
2655 .edid = edid,
2656 };
2657
2658 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2659 struct drm_display_mode *newmode;
2660
2661 newmode = drm_mode_std(connector, edid,
2662 &edid->standard_timings[i]);
2663 if (newmode) {
2664 drm_mode_probed_add(connector, newmode);
2665 modes++;
2666 }
2667 }
2668
2669 if (version_greater(edid, 1, 0))
2670 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2671 &closure);
2672
2673 /* XXX should also look for standard codes in VTB blocks */
2674
2675 return modes + closure.modes;
2676 }
2677
2678 static int drm_cvt_modes(struct drm_connector *connector,
2679 struct detailed_timing *timing)
2680 {
2681 int i, j, modes = 0;
2682 struct drm_display_mode *newmode;
2683 struct drm_device *dev = connector->dev;
2684 struct cvt_timing *cvt;
2685 const int rates[] = { 60, 85, 75, 60, 50 };
2686 const u8 empty[3] = { 0, 0, 0 };
2687
2688 for (i = 0; i < 4; i++) {
2689 int uninitialized_var(width), height;
2690 cvt = &(timing->data.other_data.data.cvt[i]);
2691
2692 if (!memcmp(cvt->code, empty, 3))
2693 continue;
2694
2695 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2696 switch (cvt->code[1] & 0x0c) {
2697 case 0x00:
2698 width = height * 4 / 3;
2699 break;
2700 case 0x04:
2701 width = height * 16 / 9;
2702 break;
2703 case 0x08:
2704 width = height * 16 / 10;
2705 break;
2706 case 0x0c:
2707 width = height * 15 / 9;
2708 break;
2709 }
2710
2711 for (j = 1; j < 5; j++) {
2712 if (cvt->code[2] & (1 << j)) {
2713 newmode = drm_cvt_mode(dev, width, height,
2714 rates[j], j == 0,
2715 false, false);
2716 if (newmode) {
2717 drm_mode_probed_add(connector, newmode);
2718 modes++;
2719 }
2720 }
2721 }
2722 }
2723
2724 return modes;
2725 }
2726
2727 static void
2728 do_cvt_mode(struct detailed_timing *timing, void *c)
2729 {
2730 struct detailed_mode_closure *closure = c;
2731 struct detailed_non_pixel *data = &timing->data.other_data;
2732
2733 if (data->type == EDID_DETAIL_CVT_3BYTE)
2734 closure->modes += drm_cvt_modes(closure->connector, timing);
2735 }
2736
2737 static int
2738 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2739 {
2740 struct detailed_mode_closure closure = {
2741 .connector = connector,
2742 .edid = edid,
2743 };
2744
2745 if (version_greater(edid, 1, 2))
2746 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2747
2748 /* XXX should also look for CVT codes in VTB blocks */
2749
2750 return closure.modes;
2751 }
2752
2753 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2754
2755 static void
2756 do_detailed_mode(struct detailed_timing *timing, void *c)
2757 {
2758 struct detailed_mode_closure *closure = c;
2759 struct drm_display_mode *newmode;
2760
2761 if (timing->pixel_clock) {
2762 newmode = drm_mode_detailed(closure->connector->dev,
2763 closure->edid, timing,
2764 closure->quirks);
2765 if (!newmode)
2766 return;
2767
2768 if (closure->preferred)
2769 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2770
2771 /*
2772 * Detailed modes are limited to 10kHz pixel clock resolution,
2773 * so fix up anything that looks like CEA/HDMI mode, but the clock
2774 * is just slightly off.
2775 */
2776 fixup_detailed_cea_mode_clock(newmode);
2777
2778 drm_mode_probed_add(closure->connector, newmode);
2779 closure->modes++;
2780 closure->preferred = 0;
2781 }
2782 }
2783
2784 /*
2785 * add_detailed_modes - Add modes from detailed timings
2786 * @connector: attached connector
2787 * @edid: EDID block to scan
2788 * @quirks: quirks to apply
2789 */
2790 static int
2791 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2792 u32 quirks)
2793 {
2794 struct detailed_mode_closure closure = {
2795 .connector = connector,
2796 .edid = edid,
2797 .preferred = 1,
2798 .quirks = quirks,
2799 };
2800
2801 if (closure.preferred && !version_greater(edid, 1, 3))
2802 closure.preferred =
2803 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2804
2805 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2806
2807 return closure.modes;
2808 }
2809
2810 #define AUDIO_BLOCK 0x01
2811 #define VIDEO_BLOCK 0x02
2812 #define VENDOR_BLOCK 0x03
2813 #define SPEAKER_BLOCK 0x04
2814 #define USE_EXTENDED_TAG 0x07
2815 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2816 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2817 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2818 #define EDID_BASIC_AUDIO (1 << 6)
2819 #define EDID_CEA_YCRCB444 (1 << 5)
2820 #define EDID_CEA_YCRCB422 (1 << 4)
2821 #define EDID_CEA_VCDB_QS (1 << 6)
2822
2823 /*
2824 * Search EDID for CEA extension block.
2825 */
2826 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2827 {
2828 u8 *edid_ext = NULL;
2829 int i;
2830
2831 /* No EDID or EDID extensions */
2832 if (edid == NULL || edid->extensions == 0)
2833 return NULL;
2834
2835 /* Find CEA extension */
2836 for (i = 0; i < edid->extensions; i++) {
2837 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2838 if (edid_ext[0] == ext_id)
2839 break;
2840 }
2841
2842 if (i == edid->extensions)
2843 return NULL;
2844
2845 return edid_ext;
2846 }
2847
2848 static u8 *drm_find_cea_extension(const struct edid *edid)
2849 {
2850 return drm_find_edid_extension(edid, CEA_EXT);
2851 }
2852
2853 static u8 *drm_find_displayid_extension(const struct edid *edid)
2854 {
2855 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2856 }
2857
2858 /*
2859 * Calculate the alternate clock for the CEA mode
2860 * (60Hz vs. 59.94Hz etc.)
2861 */
2862 static unsigned int
2863 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2864 {
2865 unsigned int clock = cea_mode->clock;
2866
2867 if (cea_mode->vrefresh % 6 != 0)
2868 return clock;
2869
2870 /*
2871 * edid_cea_modes contains the 59.94Hz
2872 * variant for 240 and 480 line modes,
2873 * and the 60Hz variant otherwise.
2874 */
2875 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2876 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2877 else
2878 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2879
2880 return clock;
2881 }
2882
2883 static bool
2884 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2885 {
2886 /*
2887 * For certain VICs the spec allows the vertical
2888 * front porch to vary by one or two lines.
2889 *
2890 * cea_modes[] stores the variant with the shortest
2891 * vertical front porch. We can adjust the mode to
2892 * get the other variants by simply increasing the
2893 * vertical front porch length.
2894 */
2895 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2896 edid_cea_modes[9].vtotal != 262 ||
2897 edid_cea_modes[12].vtotal != 262 ||
2898 edid_cea_modes[13].vtotal != 262 ||
2899 edid_cea_modes[23].vtotal != 312 ||
2900 edid_cea_modes[24].vtotal != 312 ||
2901 edid_cea_modes[27].vtotal != 312 ||
2902 edid_cea_modes[28].vtotal != 312);
2903
2904 if (((vic == 8 || vic == 9 ||
2905 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2906 ((vic == 23 || vic == 24 ||
2907 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2908 mode->vsync_start++;
2909 mode->vsync_end++;
2910 mode->vtotal++;
2911
2912 return true;
2913 }
2914
2915 return false;
2916 }
2917
2918 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2919 unsigned int clock_tolerance)
2920 {
2921 u8 vic;
2922
2923 if (!to_match->clock)
2924 return 0;
2925
2926 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2927 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2928 unsigned int clock1, clock2;
2929
2930 /* Check both 60Hz and 59.94Hz */
2931 clock1 = cea_mode.clock;
2932 clock2 = cea_mode_alternate_clock(&cea_mode);
2933
2934 if (abs(to_match->clock - clock1) > clock_tolerance &&
2935 abs(to_match->clock - clock2) > clock_tolerance)
2936 continue;
2937
2938 do {
2939 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2940 return vic;
2941 } while (cea_mode_alternate_timings(vic, &cea_mode));
2942 }
2943
2944 return 0;
2945 }
2946
2947 /**
2948 * drm_match_cea_mode - look for a CEA mode matching given mode
2949 * @to_match: display mode
2950 *
2951 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2952 * mode.
2953 */
2954 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2955 {
2956 u8 vic;
2957
2958 if (!to_match->clock)
2959 return 0;
2960
2961 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2962 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2963 unsigned int clock1, clock2;
2964
2965 /* Check both 60Hz and 59.94Hz */
2966 clock1 = cea_mode.clock;
2967 clock2 = cea_mode_alternate_clock(&cea_mode);
2968
2969 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2970 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2971 continue;
2972
2973 do {
2974 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2975 return vic;
2976 } while (cea_mode_alternate_timings(vic, &cea_mode));
2977 }
2978
2979 return 0;
2980 }
2981 EXPORT_SYMBOL(drm_match_cea_mode);
2982
2983 static bool drm_valid_cea_vic(u8 vic)
2984 {
2985 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2986 }
2987
2988 /**
2989 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2990 * the input VIC from the CEA mode list
2991 * @video_code: ID given to each of the CEA modes
2992 *
2993 * Returns picture aspect ratio
2994 */
2995 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2996 {
2997 return edid_cea_modes[video_code].picture_aspect_ratio;
2998 }
2999 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3000
3001 /*
3002 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3003 * specific block).
3004 *
3005 * It's almost like cea_mode_alternate_clock(), we just need to add an
3006 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3007 * one.
3008 */
3009 static unsigned int
3010 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3011 {
3012 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3013 return hdmi_mode->clock;
3014
3015 return cea_mode_alternate_clock(hdmi_mode);
3016 }
3017
3018 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3019 unsigned int clock_tolerance)
3020 {
3021 u8 vic;
3022
3023 if (!to_match->clock)
3024 return 0;
3025
3026 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3027 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3028 unsigned int clock1, clock2;
3029
3030 /* Make sure to also match alternate clocks */
3031 clock1 = hdmi_mode->clock;
3032 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3033
3034 if (abs(to_match->clock - clock1) > clock_tolerance &&
3035 abs(to_match->clock - clock2) > clock_tolerance)
3036 continue;
3037
3038 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
3039 return vic;
3040 }
3041
3042 return 0;
3043 }
3044
3045 /*
3046 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3047 * @to_match: display mode
3048 *
3049 * An HDMI mode is one defined in the HDMI vendor specific block.
3050 *
3051 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3052 */
3053 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3054 {
3055 u8 vic;
3056
3057 if (!to_match->clock)
3058 return 0;
3059
3060 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3061 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3062 unsigned int clock1, clock2;
3063
3064 /* Make sure to also match alternate clocks */
3065 clock1 = hdmi_mode->clock;
3066 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3067
3068 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3069 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3070 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3071 return vic;
3072 }
3073 return 0;
3074 }
3075
3076 static bool drm_valid_hdmi_vic(u8 vic)
3077 {
3078 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3079 }
3080
3081 static int
3082 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3083 {
3084 struct drm_device *dev = connector->dev;
3085 struct drm_display_mode *mode, *tmp;
3086 LIST_HEAD(list);
3087 int modes = 0;
3088
3089 /* Don't add CEA modes if the CEA extension block is missing */
3090 if (!drm_find_cea_extension(edid))
3091 return 0;
3092
3093 /*
3094 * Go through all probed modes and create a new mode
3095 * with the alternate clock for certain CEA modes.
3096 */
3097 list_for_each_entry(mode, &connector->probed_modes, head) {
3098 const struct drm_display_mode *cea_mode = NULL;
3099 struct drm_display_mode *newmode;
3100 u8 vic = drm_match_cea_mode(mode);
3101 unsigned int clock1, clock2;
3102
3103 if (drm_valid_cea_vic(vic)) {
3104 cea_mode = &edid_cea_modes[vic];
3105 clock2 = cea_mode_alternate_clock(cea_mode);
3106 } else {
3107 vic = drm_match_hdmi_mode(mode);
3108 if (drm_valid_hdmi_vic(vic)) {
3109 cea_mode = &edid_4k_modes[vic];
3110 clock2 = hdmi_mode_alternate_clock(cea_mode);
3111 }
3112 }
3113
3114 if (!cea_mode)
3115 continue;
3116
3117 clock1 = cea_mode->clock;
3118
3119 if (clock1 == clock2)
3120 continue;
3121
3122 if (mode->clock != clock1 && mode->clock != clock2)
3123 continue;
3124
3125 newmode = drm_mode_duplicate(dev, cea_mode);
3126 if (!newmode)
3127 continue;
3128
3129 /* Carry over the stereo flags */
3130 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3131
3132 /*
3133 * The current mode could be either variant. Make
3134 * sure to pick the "other" clock for the new mode.
3135 */
3136 if (mode->clock != clock1)
3137 newmode->clock = clock1;
3138 else
3139 newmode->clock = clock2;
3140
3141 list_add_tail(&newmode->head, &list);
3142 }
3143
3144 list_for_each_entry_safe(mode, tmp, &list, head) {
3145 list_del(&mode->head);
3146 drm_mode_probed_add(connector, mode);
3147 modes++;
3148 }
3149
3150 return modes;
3151 }
3152
3153 static u8 svd_to_vic(u8 svd)
3154 {
3155 /* 0-6 bit vic, 7th bit native mode indicator */
3156 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3157 return svd & 127;
3158
3159 return svd;
3160 }
3161
3162 static struct drm_display_mode *
3163 drm_display_mode_from_vic_index(struct drm_connector *connector,
3164 const u8 *video_db, u8 video_len,
3165 u8 video_index)
3166 {
3167 struct drm_device *dev = connector->dev;
3168 struct drm_display_mode *newmode;
3169 u8 vic;
3170
3171 if (video_db == NULL || video_index >= video_len)
3172 return NULL;
3173
3174 /* CEA modes are numbered 1..127 */
3175 vic = svd_to_vic(video_db[video_index]);
3176 if (!drm_valid_cea_vic(vic))
3177 return NULL;
3178
3179 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3180 if (!newmode)
3181 return NULL;
3182
3183 newmode->vrefresh = 0;
3184
3185 return newmode;
3186 }
3187
3188 /*
3189 * do_y420vdb_modes - Parse YCBCR 420 only modes
3190 * @connector: connector corresponding to the HDMI sink
3191 * @svds: start of the data block of CEA YCBCR 420 VDB
3192 * @len: length of the CEA YCBCR 420 VDB
3193 *
3194 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3195 * which contains modes which can be supported in YCBCR 420
3196 * output format only.
3197 */
3198 static int do_y420vdb_modes(struct drm_connector *connector,
3199 const u8 *svds, u8 svds_len)
3200 {
3201 int modes = 0, i;
3202 struct drm_device *dev = connector->dev;
3203 struct drm_display_info *info = &connector->display_info;
3204 struct drm_hdmi_info *hdmi = &info->hdmi;
3205
3206 for (i = 0; i < svds_len; i++) {
3207 u8 vic = svd_to_vic(svds[i]);
3208 struct drm_display_mode *newmode;
3209
3210 if (!drm_valid_cea_vic(vic))
3211 continue;
3212
3213 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3214 if (!newmode)
3215 break;
3216 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3217 drm_mode_probed_add(connector, newmode);
3218 modes++;
3219 }
3220
3221 if (modes > 0)
3222 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3223 return modes;
3224 }
3225
3226 /*
3227 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3228 * @connector: connector corresponding to the HDMI sink
3229 * @vic: CEA vic for the video mode to be added in the map
3230 *
3231 * Makes an entry for a videomode in the YCBCR 420 bitmap
3232 */
3233 static void
3234 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3235 {
3236 u8 vic = svd_to_vic(svd);
3237 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3238
3239 if (!drm_valid_cea_vic(vic))
3240 return;
3241
3242 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3243 }
3244
3245 static int
3246 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3247 {
3248 int i, modes = 0;
3249 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3250
3251 for (i = 0; i < len; i++) {
3252 struct drm_display_mode *mode;
3253 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3254 if (mode) {
3255 /*
3256 * YCBCR420 capability block contains a bitmap which
3257 * gives the index of CEA modes from CEA VDB, which
3258 * can support YCBCR 420 sampling output also (apart
3259 * from RGB/YCBCR444 etc).
3260 * For example, if the bit 0 in bitmap is set,
3261 * first mode in VDB can support YCBCR420 output too.
3262 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3263 */
3264 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3265 drm_add_cmdb_modes(connector, db[i]);
3266
3267 drm_mode_probed_add(connector, mode);
3268 modes++;
3269 }
3270 }
3271
3272 return modes;
3273 }
3274
3275 struct stereo_mandatory_mode {
3276 int width, height, vrefresh;
3277 unsigned int flags;
3278 };
3279
3280 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3281 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3282 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3283 { 1920, 1080, 50,
3284 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3285 { 1920, 1080, 60,
3286 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3287 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3288 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3289 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3290 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3291 };
3292
3293 static bool
3294 stereo_match_mandatory(const struct drm_display_mode *mode,
3295 const struct stereo_mandatory_mode *stereo_mode)
3296 {
3297 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3298
3299 return mode->hdisplay == stereo_mode->width &&
3300 mode->vdisplay == stereo_mode->height &&
3301 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3302 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3303 }
3304
3305 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3306 {
3307 struct drm_device *dev = connector->dev;
3308 const struct drm_display_mode *mode;
3309 struct list_head stereo_modes;
3310 int modes = 0, i;
3311
3312 INIT_LIST_HEAD(&stereo_modes);
3313
3314 list_for_each_entry(mode, &connector->probed_modes, head) {
3315 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3316 const struct stereo_mandatory_mode *mandatory;
3317 struct drm_display_mode *new_mode;
3318
3319 if (!stereo_match_mandatory(mode,
3320 &stereo_mandatory_modes[i]))
3321 continue;
3322
3323 mandatory = &stereo_mandatory_modes[i];
3324 new_mode = drm_mode_duplicate(dev, mode);
3325 if (!new_mode)
3326 continue;
3327
3328 new_mode->flags |= mandatory->flags;
3329 list_add_tail(&new_mode->head, &stereo_modes);
3330 modes++;
3331 }
3332 }
3333
3334 list_splice_tail(&stereo_modes, &connector->probed_modes);
3335
3336 return modes;
3337 }
3338
3339 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3340 {
3341 struct drm_device *dev = connector->dev;
3342 struct drm_display_mode *newmode;
3343
3344 if (!drm_valid_hdmi_vic(vic)) {
3345 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3346 return 0;
3347 }
3348
3349 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3350 if (!newmode)
3351 return 0;
3352
3353 drm_mode_probed_add(connector, newmode);
3354
3355 return 1;
3356 }
3357
3358 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3359 const u8 *video_db, u8 video_len, u8 video_index)
3360 {
3361 struct drm_display_mode *newmode;
3362 int modes = 0;
3363
3364 if (structure & (1 << 0)) {
3365 newmode = drm_display_mode_from_vic_index(connector, video_db,
3366 video_len,
3367 video_index);
3368 if (newmode) {
3369 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3370 drm_mode_probed_add(connector, newmode);
3371 modes++;
3372 }
3373 }
3374 if (structure & (1 << 6)) {
3375 newmode = drm_display_mode_from_vic_index(connector, video_db,
3376 video_len,
3377 video_index);
3378 if (newmode) {
3379 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3380 drm_mode_probed_add(connector, newmode);
3381 modes++;
3382 }
3383 }
3384 if (structure & (1 << 8)) {
3385 newmode = drm_display_mode_from_vic_index(connector, video_db,
3386 video_len,
3387 video_index);
3388 if (newmode) {
3389 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3390 drm_mode_probed_add(connector, newmode);
3391 modes++;
3392 }
3393 }
3394
3395 return modes;
3396 }
3397
3398 /*
3399 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3400 * @connector: connector corresponding to the HDMI sink
3401 * @db: start of the CEA vendor specific block
3402 * @len: length of the CEA block payload, ie. one can access up to db[len]
3403 *
3404 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3405 * also adds the stereo 3d modes when applicable.
3406 */
3407 static int
3408 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3409 const u8 *video_db, u8 video_len)
3410 {
3411 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3412 u8 vic_len, hdmi_3d_len = 0;
3413 u16 mask;
3414 u16 structure_all;
3415
3416 if (len < 8)
3417 goto out;
3418
3419 /* no HDMI_Video_Present */
3420 if (!(db[8] & (1 << 5)))
3421 goto out;
3422
3423 /* Latency_Fields_Present */
3424 if (db[8] & (1 << 7))
3425 offset += 2;
3426
3427 /* I_Latency_Fields_Present */
3428 if (db[8] & (1 << 6))
3429 offset += 2;
3430
3431 /* the declared length is not long enough for the 2 first bytes
3432 * of additional video format capabilities */
3433 if (len < (8 + offset + 2))
3434 goto out;
3435
3436 /* 3D_Present */
3437 offset++;
3438 if (db[8 + offset] & (1 << 7)) {
3439 modes += add_hdmi_mandatory_stereo_modes(connector);
3440
3441 /* 3D_Multi_present */
3442 multi_present = (db[8 + offset] & 0x60) >> 5;
3443 }
3444
3445 offset++;
3446 vic_len = db[8 + offset] >> 5;
3447 hdmi_3d_len = db[8 + offset] & 0x1f;
3448
3449 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3450 u8 vic;
3451
3452 vic = db[9 + offset + i];
3453 modes += add_hdmi_mode(connector, vic);
3454 }
3455 offset += 1 + vic_len;
3456
3457 if (multi_present == 1)
3458 multi_len = 2;
3459 else if (multi_present == 2)
3460 multi_len = 4;
3461 else
3462 multi_len = 0;
3463
3464 if (len < (8 + offset + hdmi_3d_len - 1))
3465 goto out;
3466
3467 if (hdmi_3d_len < multi_len)
3468 goto out;
3469
3470 if (multi_present == 1 || multi_present == 2) {
3471 /* 3D_Structure_ALL */
3472 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3473
3474 /* check if 3D_MASK is present */
3475 if (multi_present == 2)
3476 mask = (db[10 + offset] << 8) | db[11 + offset];
3477 else
3478 mask = 0xffff;
3479
3480 for (i = 0; i < 16; i++) {
3481 if (mask & (1 << i))
3482 modes += add_3d_struct_modes(connector,
3483 structure_all,
3484 video_db,
3485 video_len, i);
3486 }
3487 }
3488
3489 offset += multi_len;
3490
3491 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3492 int vic_index;
3493 struct drm_display_mode *newmode = NULL;
3494 unsigned int newflag = 0;
3495 bool detail_present;
3496
3497 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3498
3499 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3500 break;
3501
3502 /* 2D_VIC_order_X */
3503 vic_index = db[8 + offset + i] >> 4;
3504
3505 /* 3D_Structure_X */
3506 switch (db[8 + offset + i] & 0x0f) {
3507 case 0:
3508 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3509 break;
3510 case 6:
3511 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3512 break;
3513 case 8:
3514 /* 3D_Detail_X */
3515 if ((db[9 + offset + i] >> 4) == 1)
3516 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3517 break;
3518 }
3519
3520 if (newflag != 0) {
3521 newmode = drm_display_mode_from_vic_index(connector,
3522 video_db,
3523 video_len,
3524 vic_index);
3525
3526 if (newmode) {
3527 newmode->flags |= newflag;
3528 drm_mode_probed_add(connector, newmode);
3529 modes++;
3530 }
3531 }
3532
3533 if (detail_present)
3534 i++;
3535 }
3536
3537 out:
3538 return modes;
3539 }
3540
3541 static int
3542 cea_db_payload_len(const u8 *db)
3543 {
3544 return db[0] & 0x1f;
3545 }
3546
3547 static int
3548 cea_db_extended_tag(const u8 *db)
3549 {
3550 return db[1];
3551 }
3552
3553 static int
3554 cea_db_tag(const u8 *db)
3555 {
3556 return db[0] >> 5;
3557 }
3558
3559 static int
3560 cea_revision(const u8 *cea)
3561 {
3562 return cea[1];
3563 }
3564
3565 static int
3566 cea_db_offsets(const u8 *cea, int *start, int *end)
3567 {
3568 /* Data block offset in CEA extension block */
3569 *start = 4;
3570 *end = cea[2];
3571 if (*end == 0)
3572 *end = 127;
3573 if (*end < 4 || *end > 127)
3574 return -ERANGE;
3575 return 0;
3576 }
3577
3578 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3579 {
3580 int hdmi_id;
3581
3582 if (cea_db_tag(db) != VENDOR_BLOCK)
3583 return false;
3584
3585 if (cea_db_payload_len(db) < 5)
3586 return false;
3587
3588 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3589
3590 return hdmi_id == HDMI_IEEE_OUI;
3591 }
3592
3593 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3594 {
3595 unsigned int oui;
3596
3597 if (cea_db_tag(db) != VENDOR_BLOCK)
3598 return false;
3599
3600 if (cea_db_payload_len(db) < 7)
3601 return false;
3602
3603 oui = db[3] << 16 | db[2] << 8 | db[1];
3604
3605 return oui == HDMI_FORUM_IEEE_OUI;
3606 }
3607
3608 static bool cea_db_is_y420cmdb(const u8 *db)
3609 {
3610 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3611 return false;
3612
3613 if (!cea_db_payload_len(db))
3614 return false;
3615
3616 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3617 return false;
3618
3619 return true;
3620 }
3621
3622 static bool cea_db_is_y420vdb(const u8 *db)
3623 {
3624 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3625 return false;
3626
3627 if (!cea_db_payload_len(db))
3628 return false;
3629
3630 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3631 return false;
3632
3633 return true;
3634 }
3635
3636 #define for_each_cea_db(cea, i, start, end) \
3637 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3638
3639 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3640 const u8 *db)
3641 {
3642 struct drm_display_info *info = &connector->display_info;
3643 struct drm_hdmi_info *hdmi = &info->hdmi;
3644 u8 map_len = cea_db_payload_len(db) - 1;
3645 u8 count;
3646 u64 map = 0;
3647
3648 if (map_len == 0) {
3649 /* All CEA modes support ycbcr420 sampling also.*/
3650 hdmi->y420_cmdb_map = U64_MAX;
3651 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3652 return;
3653 }
3654
3655 /*
3656 * This map indicates which of the existing CEA block modes
3657 * from VDB can support YCBCR420 output too. So if bit=0 is
3658 * set, first mode from VDB can support YCBCR420 output too.
3659 * We will parse and keep this map, before parsing VDB itself
3660 * to avoid going through the same block again and again.
3661 *
3662 * Spec is not clear about max possible size of this block.
3663 * Clamping max bitmap block size at 8 bytes. Every byte can
3664 * address 8 CEA modes, in this way this map can address
3665 * 8*8 = first 64 SVDs.
3666 */
3667 if (WARN_ON_ONCE(map_len > 8))
3668 map_len = 8;
3669
3670 for (count = 0; count < map_len; count++)
3671 map |= (u64)db[2 + count] << (8 * count);
3672
3673 if (map)
3674 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3675
3676 hdmi->y420_cmdb_map = map;
3677 }
3678
3679 static int
3680 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3681 {
3682 const u8 *cea = drm_find_cea_extension(edid);
3683 const u8 *db, *hdmi = NULL, *video = NULL;
3684 u8 dbl, hdmi_len, video_len = 0;
3685 int modes = 0;
3686
3687 if (cea && cea_revision(cea) >= 3) {
3688 int i, start, end;
3689
3690 if (cea_db_offsets(cea, &start, &end))
3691 return 0;
3692
3693 for_each_cea_db(cea, i, start, end) {
3694 db = &cea[i];
3695 dbl = cea_db_payload_len(db);
3696
3697 if (cea_db_tag(db) == VIDEO_BLOCK) {
3698 video = db + 1;
3699 video_len = dbl;
3700 modes += do_cea_modes(connector, video, dbl);
3701 } else if (cea_db_is_hdmi_vsdb(db)) {
3702 hdmi = db;
3703 hdmi_len = dbl;
3704 } else if (cea_db_is_y420vdb(db)) {
3705 const u8 *vdb420 = &db[2];
3706
3707 /* Add 4:2:0(only) modes present in EDID */
3708 modes += do_y420vdb_modes(connector,
3709 vdb420,
3710 dbl - 1);
3711 }
3712 }
3713 }
3714
3715 /*
3716 * We parse the HDMI VSDB after having added the cea modes as we will
3717 * be patching their flags when the sink supports stereo 3D.
3718 */
3719 if (hdmi)
3720 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3721 video_len);
3722
3723 return modes;
3724 }
3725
3726 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3727 {
3728 const struct drm_display_mode *cea_mode;
3729 int clock1, clock2, clock;
3730 u8 vic;
3731 const char *type;
3732
3733 /*
3734 * allow 5kHz clock difference either way to account for
3735 * the 10kHz clock resolution limit of detailed timings.
3736 */
3737 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3738 if (drm_valid_cea_vic(vic)) {
3739 type = "CEA";
3740 cea_mode = &edid_cea_modes[vic];
3741 clock1 = cea_mode->clock;
3742 clock2 = cea_mode_alternate_clock(cea_mode);
3743 } else {
3744 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3745 if (drm_valid_hdmi_vic(vic)) {
3746 type = "HDMI";
3747 cea_mode = &edid_4k_modes[vic];
3748 clock1 = cea_mode->clock;
3749 clock2 = hdmi_mode_alternate_clock(cea_mode);
3750 } else {
3751 return;
3752 }
3753 }
3754
3755 /* pick whichever is closest */
3756 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3757 clock = clock1;
3758 else
3759 clock = clock2;
3760
3761 if (mode->clock == clock)
3762 return;
3763
3764 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3765 type, vic, mode->clock, clock);
3766 mode->clock = clock;
3767 }
3768
3769 static void
3770 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3771 {
3772 u8 len = cea_db_payload_len(db);
3773
3774 if (len >= 6)
3775 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3776 if (len >= 8) {
3777 connector->latency_present[0] = db[8] >> 7;
3778 connector->latency_present[1] = (db[8] >> 6) & 1;
3779 }
3780 if (len >= 9)
3781 connector->video_latency[0] = db[9];
3782 if (len >= 10)
3783 connector->audio_latency[0] = db[10];
3784 if (len >= 11)
3785 connector->video_latency[1] = db[11];
3786 if (len >= 12)
3787 connector->audio_latency[1] = db[12];
3788
3789 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3790 "video latency %d %d, "
3791 "audio latency %d %d\n",
3792 connector->latency_present[0],
3793 connector->latency_present[1],
3794 connector->video_latency[0],
3795 connector->video_latency[1],
3796 connector->audio_latency[0],
3797 connector->audio_latency[1]);
3798 }
3799
3800 static void
3801 monitor_name(struct detailed_timing *t, void *data)
3802 {
3803 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3804 *(u8 **)data = t->data.other_data.data.str.str;
3805 }
3806
3807 static int get_monitor_name(struct edid *edid, char name[13])
3808 {
3809 char *edid_name = NULL;
3810 int mnl;
3811
3812 if (!edid || !name)
3813 return 0;
3814
3815 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3816 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3817 if (edid_name[mnl] == 0x0a)
3818 break;
3819
3820 name[mnl] = edid_name[mnl];
3821 }
3822
3823 return mnl;
3824 }
3825
3826 /**
3827 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3828 * @edid: monitor EDID information
3829 * @name: pointer to a character array to hold the name of the monitor
3830 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3831 *
3832 */
3833 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3834 {
3835 int name_length;
3836 char buf[13];
3837
3838 if (bufsize <= 0)
3839 return;
3840
3841 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3842 memcpy(name, buf, name_length);
3843 name[name_length] = '\0';
3844 }
3845 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3846
3847 /**
3848 * drm_edid_to_eld - build ELD from EDID
3849 * @connector: connector corresponding to the HDMI/DP sink
3850 * @edid: EDID to parse
3851 *
3852 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3853 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3854 */
3855 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3856 {
3857 uint8_t *eld = connector->eld;
3858 u8 *cea;
3859 u8 *db;
3860 int total_sad_count = 0;
3861 int mnl;
3862 int dbl;
3863
3864 memset(eld, 0, sizeof(connector->eld));
3865
3866 connector->latency_present[0] = false;
3867 connector->latency_present[1] = false;
3868 connector->video_latency[0] = 0;
3869 connector->audio_latency[0] = 0;
3870 connector->video_latency[1] = 0;
3871 connector->audio_latency[1] = 0;
3872
3873 if (!edid)
3874 return;
3875
3876 cea = drm_find_cea_extension(edid);
3877 if (!cea) {
3878 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3879 return;
3880 }
3881
3882 mnl = get_monitor_name(edid, eld + 20);
3883
3884 eld[4] = (cea[1] << 5) | mnl;
3885 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3886
3887 eld[0] = 2 << 3; /* ELD version: 2 */
3888
3889 eld[16] = edid->mfg_id[0];
3890 eld[17] = edid->mfg_id[1];
3891 eld[18] = edid->prod_code[0];
3892 eld[19] = edid->prod_code[1];
3893
3894 if (cea_revision(cea) >= 3) {
3895 int i, start, end;
3896
3897 if (cea_db_offsets(cea, &start, &end)) {
3898 start = 0;
3899 end = 0;
3900 }
3901
3902 for_each_cea_db(cea, i, start, end) {
3903 db = &cea[i];
3904 dbl = cea_db_payload_len(db);
3905
3906 switch (cea_db_tag(db)) {
3907 int sad_count;
3908
3909 case AUDIO_BLOCK:
3910 /* Audio Data Block, contains SADs */
3911 sad_count = min(dbl / 3, 15 - total_sad_count);
3912 if (sad_count >= 1)
3913 memcpy(eld + 20 + mnl + total_sad_count * 3,
3914 &db[1], sad_count * 3);
3915 total_sad_count += sad_count;
3916 break;
3917 case SPEAKER_BLOCK:
3918 /* Speaker Allocation Data Block */
3919 if (dbl >= 1)
3920 eld[7] = db[1];
3921 break;
3922 case VENDOR_BLOCK:
3923 /* HDMI Vendor-Specific Data Block */
3924 if (cea_db_is_hdmi_vsdb(db))
3925 drm_parse_hdmi_vsdb_audio(connector, db);
3926 break;
3927 default:
3928 break;
3929 }
3930 }
3931 }
3932 eld[5] |= total_sad_count << 4;
3933
3934 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3935 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3936 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3937 else
3938 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
3939
3940 eld[DRM_ELD_BASELINE_ELD_LEN] =
3941 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3942
3943 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3944 drm_eld_size(eld), total_sad_count);
3945 }
3946 EXPORT_SYMBOL(drm_edid_to_eld);
3947
3948 /**
3949 * drm_edid_to_sad - extracts SADs from EDID
3950 * @edid: EDID to parse
3951 * @sads: pointer that will be set to the extracted SADs
3952 *
3953 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3954 *
3955 * Note: The returned pointer needs to be freed using kfree().
3956 *
3957 * Return: The number of found SADs or negative number on error.
3958 */
3959 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3960 {
3961 int count = 0;
3962 int i, start, end, dbl;
3963 u8 *cea;
3964
3965 cea = drm_find_cea_extension(edid);
3966 if (!cea) {
3967 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3968 return -ENOENT;
3969 }
3970
3971 if (cea_revision(cea) < 3) {
3972 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3973 return -ENOTSUPP;
3974 }
3975
3976 if (cea_db_offsets(cea, &start, &end)) {
3977 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3978 return -EPROTO;
3979 }
3980
3981 for_each_cea_db(cea, i, start, end) {
3982 u8 *db = &cea[i];
3983
3984 if (cea_db_tag(db) == AUDIO_BLOCK) {
3985 int j;
3986 dbl = cea_db_payload_len(db);
3987
3988 count = dbl / 3; /* SAD is 3B */
3989 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3990 if (!*sads)
3991 return -ENOMEM;
3992 for (j = 0; j < count; j++) {
3993 u8 *sad = &db[1 + j * 3];
3994
3995 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3996 (*sads)[j].channels = sad[0] & 0x7;
3997 (*sads)[j].freq = sad[1] & 0x7F;
3998 (*sads)[j].byte2 = sad[2];
3999 }
4000 break;
4001 }
4002 }
4003
4004 return count;
4005 }
4006 EXPORT_SYMBOL(drm_edid_to_sad);
4007
4008 /**
4009 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4010 * @edid: EDID to parse
4011 * @sadb: pointer to the speaker block
4012 *
4013 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4014 *
4015 * Note: The returned pointer needs to be freed using kfree().
4016 *
4017 * Return: The number of found Speaker Allocation Blocks or negative number on
4018 * error.
4019 */
4020 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4021 {
4022 int count = 0;
4023 int i, start, end, dbl;
4024 const u8 *cea;
4025
4026 cea = drm_find_cea_extension(edid);
4027 if (!cea) {
4028 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4029 return -ENOENT;
4030 }
4031
4032 if (cea_revision(cea) < 3) {
4033 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4034 return -ENOTSUPP;
4035 }
4036
4037 if (cea_db_offsets(cea, &start, &end)) {
4038 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4039 return -EPROTO;
4040 }
4041
4042 for_each_cea_db(cea, i, start, end) {
4043 const u8 *db = &cea[i];
4044
4045 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4046 dbl = cea_db_payload_len(db);
4047
4048 /* Speaker Allocation Data Block */
4049 if (dbl == 3) {
4050 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4051 if (!*sadb)
4052 return -ENOMEM;
4053 count = dbl;
4054 break;
4055 }
4056 }
4057 }
4058
4059 return count;
4060 }
4061 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4062
4063 /**
4064 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4065 * @connector: connector associated with the HDMI/DP sink
4066 * @mode: the display mode
4067 *
4068 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4069 * the sink doesn't support audio or video.
4070 */
4071 int drm_av_sync_delay(struct drm_connector *connector,
4072 const struct drm_display_mode *mode)
4073 {
4074 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4075 int a, v;
4076
4077 if (!connector->latency_present[0])
4078 return 0;
4079 if (!connector->latency_present[1])
4080 i = 0;
4081
4082 a = connector->audio_latency[i];
4083 v = connector->video_latency[i];
4084
4085 /*
4086 * HDMI/DP sink doesn't support audio or video?
4087 */
4088 if (a == 255 || v == 255)
4089 return 0;
4090
4091 /*
4092 * Convert raw EDID values to millisecond.
4093 * Treat unknown latency as 0ms.
4094 */
4095 if (a)
4096 a = min(2 * (a - 1), 500);
4097 if (v)
4098 v = min(2 * (v - 1), 500);
4099
4100 return max(v - a, 0);
4101 }
4102 EXPORT_SYMBOL(drm_av_sync_delay);
4103
4104 /**
4105 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4106 * @edid: monitor EDID information
4107 *
4108 * Parse the CEA extension according to CEA-861-B.
4109 *
4110 * Return: True if the monitor is HDMI, false if not or unknown.
4111 */
4112 bool drm_detect_hdmi_monitor(struct edid *edid)
4113 {
4114 u8 *edid_ext;
4115 int i;
4116 int start_offset, end_offset;
4117
4118 edid_ext = drm_find_cea_extension(edid);
4119 if (!edid_ext)
4120 return false;
4121
4122 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4123 return false;
4124
4125 /*
4126 * Because HDMI identifier is in Vendor Specific Block,
4127 * search it from all data blocks of CEA extension.
4128 */
4129 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4130 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4131 return true;
4132 }
4133
4134 return false;
4135 }
4136 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4137
4138 /**
4139 * drm_detect_monitor_audio - check monitor audio capability
4140 * @edid: EDID block to scan
4141 *
4142 * Monitor should have CEA extension block.
4143 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4144 * audio' only. If there is any audio extension block and supported
4145 * audio format, assume at least 'basic audio' support, even if 'basic
4146 * audio' is not defined in EDID.
4147 *
4148 * Return: True if the monitor supports audio, false otherwise.
4149 */
4150 bool drm_detect_monitor_audio(struct edid *edid)
4151 {
4152 u8 *edid_ext;
4153 int i, j;
4154 bool has_audio = false;
4155 int start_offset, end_offset;
4156
4157 edid_ext = drm_find_cea_extension(edid);
4158 if (!edid_ext)
4159 goto end;
4160
4161 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4162
4163 if (has_audio) {
4164 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4165 goto end;
4166 }
4167
4168 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4169 goto end;
4170
4171 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4172 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4173 has_audio = true;
4174 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4175 DRM_DEBUG_KMS("CEA audio format %d\n",
4176 (edid_ext[i + j] >> 3) & 0xf);
4177 goto end;
4178 }
4179 }
4180 end:
4181 return has_audio;
4182 }
4183 EXPORT_SYMBOL(drm_detect_monitor_audio);
4184
4185 /**
4186 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4187 * @edid: EDID block to scan
4188 *
4189 * Check whether the monitor reports the RGB quantization range selection
4190 * as supported. The AVI infoframe can then be used to inform the monitor
4191 * which quantization range (full or limited) is used.
4192 *
4193 * Return: True if the RGB quantization range is selectable, false otherwise.
4194 */
4195 bool drm_rgb_quant_range_selectable(struct edid *edid)
4196 {
4197 u8 *edid_ext;
4198 int i, start, end;
4199
4200 edid_ext = drm_find_cea_extension(edid);
4201 if (!edid_ext)
4202 return false;
4203
4204 if (cea_db_offsets(edid_ext, &start, &end))
4205 return false;
4206
4207 for_each_cea_db(edid_ext, i, start, end) {
4208 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4209 cea_db_payload_len(&edid_ext[i]) == 2 &&
4210 cea_db_extended_tag(&edid_ext[i]) ==
4211 EXT_VIDEO_CAPABILITY_BLOCK) {
4212 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4213 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4214 }
4215 }
4216
4217 return false;
4218 }
4219 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4220
4221 /**
4222 * drm_default_rgb_quant_range - default RGB quantization range
4223 * @mode: display mode
4224 *
4225 * Determine the default RGB quantization range for the mode,
4226 * as specified in CEA-861.
4227 *
4228 * Return: The default RGB quantization range for the mode
4229 */
4230 enum hdmi_quantization_range
4231 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4232 {
4233 /* All CEA modes other than VIC 1 use limited quantization range. */
4234 return drm_match_cea_mode(mode) > 1 ?
4235 HDMI_QUANTIZATION_RANGE_LIMITED :
4236 HDMI_QUANTIZATION_RANGE_FULL;
4237 }
4238 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4239
4240 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4241 const u8 *db)
4242 {
4243 u8 dc_mask;
4244 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4245
4246 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4247 hdmi->y420_dc_modes = dc_mask;
4248 }
4249
4250 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4251 const u8 *hf_vsdb)
4252 {
4253 struct drm_display_info *display = &connector->display_info;
4254 struct drm_hdmi_info *hdmi = &display->hdmi;
4255
4256 if (hf_vsdb[6] & 0x80) {
4257 hdmi->scdc.supported = true;
4258 if (hf_vsdb[6] & 0x40)
4259 hdmi->scdc.read_request = true;
4260 }
4261
4262 /*
4263 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4264 * And as per the spec, three factors confirm this:
4265 * * Availability of a HF-VSDB block in EDID (check)
4266 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4267 * * SCDC support available (let's check)
4268 * Lets check it out.
4269 */
4270
4271 if (hf_vsdb[5]) {
4272 /* max clock is 5000 KHz times block value */
4273 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4274 struct drm_scdc *scdc = &hdmi->scdc;
4275
4276 if (max_tmds_clock > 340000) {
4277 display->max_tmds_clock = max_tmds_clock;
4278 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4279 display->max_tmds_clock);
4280 }
4281
4282 if (scdc->supported) {
4283 scdc->scrambling.supported = true;
4284
4285 /* Few sinks support scrambling for cloks < 340M */
4286 if ((hf_vsdb[6] & 0x8))
4287 scdc->scrambling.low_rates = true;
4288 }
4289 }
4290
4291 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4292 }
4293
4294 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4295 const u8 *hdmi)
4296 {
4297 struct drm_display_info *info = &connector->display_info;
4298 unsigned int dc_bpc = 0;
4299
4300 /* HDMI supports at least 8 bpc */
4301 info->bpc = 8;
4302
4303 if (cea_db_payload_len(hdmi) < 6)
4304 return;
4305
4306 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4307 dc_bpc = 10;
4308 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4309 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4310 connector->name);
4311 }
4312
4313 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4314 dc_bpc = 12;
4315 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4316 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4317 connector->name);
4318 }
4319
4320 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4321 dc_bpc = 16;
4322 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4323 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4324 connector->name);
4325 }
4326
4327 if (dc_bpc == 0) {
4328 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4329 connector->name);
4330 return;
4331 }
4332
4333 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4334 connector->name, dc_bpc);
4335 info->bpc = dc_bpc;
4336
4337 /*
4338 * Deep color support mandates RGB444 support for all video
4339 * modes and forbids YCRCB422 support for all video modes per
4340 * HDMI 1.3 spec.
4341 */
4342 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4343
4344 /* YCRCB444 is optional according to spec. */
4345 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4346 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4347 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4348 connector->name);
4349 }
4350
4351 /*
4352 * Spec says that if any deep color mode is supported at all,
4353 * then deep color 36 bit must be supported.
4354 */
4355 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4356 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4357 connector->name);
4358 }
4359 }
4360
4361 static void
4362 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4363 {
4364 struct drm_display_info *info = &connector->display_info;
4365 u8 len = cea_db_payload_len(db);
4366
4367 if (len >= 6)
4368 info->dvi_dual = db[6] & 1;
4369 if (len >= 7)
4370 info->max_tmds_clock = db[7] * 5000;
4371
4372 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4373 "max TMDS clock %d kHz\n",
4374 info->dvi_dual,
4375 info->max_tmds_clock);
4376
4377 drm_parse_hdmi_deep_color_info(connector, db);
4378 }
4379
4380 static void drm_parse_cea_ext(struct drm_connector *connector,
4381 const struct edid *edid)
4382 {
4383 struct drm_display_info *info = &connector->display_info;
4384 const u8 *edid_ext;
4385 int i, start, end;
4386
4387 edid_ext = drm_find_cea_extension(edid);
4388 if (!edid_ext)
4389 return;
4390
4391 info->cea_rev = edid_ext[1];
4392
4393 /* The existence of a CEA block should imply RGB support */
4394 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4395 if (edid_ext[3] & EDID_CEA_YCRCB444)
4396 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4397 if (edid_ext[3] & EDID_CEA_YCRCB422)
4398 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4399
4400 if (cea_db_offsets(edid_ext, &start, &end))
4401 return;
4402
4403 for_each_cea_db(edid_ext, i, start, end) {
4404 const u8 *db = &edid_ext[i];
4405
4406 if (cea_db_is_hdmi_vsdb(db))
4407 drm_parse_hdmi_vsdb_video(connector, db);
4408 if (cea_db_is_hdmi_forum_vsdb(db))
4409 drm_parse_hdmi_forum_vsdb(connector, db);
4410 if (cea_db_is_y420cmdb(db))
4411 drm_parse_y420cmdb_bitmap(connector, db);
4412 }
4413 }
4414
4415 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4416 * all of the values which would have been set from EDID
4417 */
4418 void
4419 drm_reset_display_info(struct drm_connector *connector)
4420 {
4421 struct drm_display_info *info = &connector->display_info;
4422
4423 info->width_mm = 0;
4424 info->height_mm = 0;
4425
4426 info->bpc = 0;
4427 info->color_formats = 0;
4428 info->cea_rev = 0;
4429 info->max_tmds_clock = 0;
4430 info->dvi_dual = false;
4431 memset(&info->hdmi, 0, sizeof(info->hdmi));
4432
4433 info->non_desktop = 0;
4434 }
4435 EXPORT_SYMBOL_GPL(drm_reset_display_info);
4436
4437 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4438 {
4439 struct drm_display_info *info = &connector->display_info;
4440
4441 u32 quirks = edid_get_quirks(edid);
4442
4443 drm_reset_display_info(connector);
4444
4445 info->width_mm = edid->width_cm * 10;
4446 info->height_mm = edid->height_cm * 10;
4447
4448 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4449
4450 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4451
4452 if (edid->revision < 3)
4453 return quirks;
4454
4455 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4456 return quirks;
4457
4458 drm_parse_cea_ext(connector, edid);
4459
4460 /*
4461 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4462 *
4463 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4464 * tells us to assume 8 bpc color depth if the EDID doesn't have
4465 * extensions which tell otherwise.
4466 */
4467 if ((info->bpc == 0) && (edid->revision < 4) &&
4468 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4469 info->bpc = 8;
4470 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4471 connector->name, info->bpc);
4472 }
4473
4474 /* Only defined for 1.4 with digital displays */
4475 if (edid->revision < 4)
4476 return quirks;
4477
4478 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4479 case DRM_EDID_DIGITAL_DEPTH_6:
4480 info->bpc = 6;
4481 break;
4482 case DRM_EDID_DIGITAL_DEPTH_8:
4483 info->bpc = 8;
4484 break;
4485 case DRM_EDID_DIGITAL_DEPTH_10:
4486 info->bpc = 10;
4487 break;
4488 case DRM_EDID_DIGITAL_DEPTH_12:
4489 info->bpc = 12;
4490 break;
4491 case DRM_EDID_DIGITAL_DEPTH_14:
4492 info->bpc = 14;
4493 break;
4494 case DRM_EDID_DIGITAL_DEPTH_16:
4495 info->bpc = 16;
4496 break;
4497 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4498 default:
4499 info->bpc = 0;
4500 break;
4501 }
4502
4503 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4504 connector->name, info->bpc);
4505
4506 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4507 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4508 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4509 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4510 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4511 return quirks;
4512 }
4513 EXPORT_SYMBOL_GPL(drm_add_display_info);
4514
4515 static int validate_displayid(u8 *displayid, int length, int idx)
4516 {
4517 int i;
4518 u8 csum = 0;
4519 struct displayid_hdr *base;
4520
4521 base = (struct displayid_hdr *)&displayid[idx];
4522
4523 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4524 base->rev, base->bytes, base->prod_id, base->ext_count);
4525
4526 if (base->bytes + 5 > length - idx)
4527 return -EINVAL;
4528 for (i = idx; i <= base->bytes + 5; i++) {
4529 csum += displayid[i];
4530 }
4531 if (csum) {
4532 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4533 return -EINVAL;
4534 }
4535 return 0;
4536 }
4537
4538 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4539 struct displayid_detailed_timings_1 *timings)
4540 {
4541 struct drm_display_mode *mode;
4542 unsigned pixel_clock = (timings->pixel_clock[0] |
4543 (timings->pixel_clock[1] << 8) |
4544 (timings->pixel_clock[2] << 16));
4545 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4546 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4547 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4548 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4549 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4550 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4551 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4552 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4553 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4554 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4555 mode = drm_mode_create(dev);
4556 if (!mode)
4557 return NULL;
4558
4559 mode->clock = pixel_clock * 10;
4560 mode->hdisplay = hactive;
4561 mode->hsync_start = mode->hdisplay + hsync;
4562 mode->hsync_end = mode->hsync_start + hsync_width;
4563 mode->htotal = mode->hdisplay + hblank;
4564
4565 mode->vdisplay = vactive;
4566 mode->vsync_start = mode->vdisplay + vsync;
4567 mode->vsync_end = mode->vsync_start + vsync_width;
4568 mode->vtotal = mode->vdisplay + vblank;
4569
4570 mode->flags = 0;
4571 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4572 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4573 mode->type = DRM_MODE_TYPE_DRIVER;
4574
4575 if (timings->flags & 0x80)
4576 mode->type |= DRM_MODE_TYPE_PREFERRED;
4577 mode->vrefresh = drm_mode_vrefresh(mode);
4578 drm_mode_set_name(mode);
4579
4580 return mode;
4581 }
4582
4583 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4584 struct displayid_block *block)
4585 {
4586 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4587 int i;
4588 int num_timings;
4589 struct drm_display_mode *newmode;
4590 int num_modes = 0;
4591 /* blocks must be multiple of 20 bytes length */
4592 if (block->num_bytes % 20)
4593 return 0;
4594
4595 num_timings = block->num_bytes / 20;
4596 for (i = 0; i < num_timings; i++) {
4597 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4598
4599 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4600 if (!newmode)
4601 continue;
4602
4603 drm_mode_probed_add(connector, newmode);
4604 num_modes++;
4605 }
4606 return num_modes;
4607 }
4608
4609 static int add_displayid_detailed_modes(struct drm_connector *connector,
4610 struct edid *edid)
4611 {
4612 u8 *displayid;
4613 int ret;
4614 int idx = 1;
4615 int length = EDID_LENGTH;
4616 struct displayid_block *block;
4617 int num_modes = 0;
4618
4619 displayid = drm_find_displayid_extension(edid);
4620 if (!displayid)
4621 return 0;
4622
4623 ret = validate_displayid(displayid, length, idx);
4624 if (ret)
4625 return 0;
4626
4627 idx += sizeof(struct displayid_hdr);
4628 while (block = (struct displayid_block *)&displayid[idx],
4629 idx + sizeof(struct displayid_block) <= length &&
4630 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4631 block->num_bytes > 0) {
4632 idx += block->num_bytes + sizeof(struct displayid_block);
4633 switch (block->tag) {
4634 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4635 num_modes += add_displayid_detailed_1_modes(connector, block);
4636 break;
4637 }
4638 }
4639 return num_modes;
4640 }
4641
4642 /**
4643 * drm_add_edid_modes - add modes from EDID data, if available
4644 * @connector: connector we're probing
4645 * @edid: EDID data
4646 *
4647 * Add the specified modes to the connector's mode list. Also fills out the
4648 * &drm_display_info structure in @connector with any information which can be
4649 * derived from the edid.
4650 *
4651 * Return: The number of modes added or 0 if we couldn't find any.
4652 */
4653 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4654 {
4655 int num_modes = 0;
4656 u32 quirks;
4657
4658 if (edid == NULL) {
4659 return 0;
4660 }
4661 if (!drm_edid_is_valid(edid)) {
4662 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4663 connector->name);
4664 return 0;
4665 }
4666
4667 /*
4668 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4669 * To avoid multiple parsing of same block, lets parse that map
4670 * from sink info, before parsing CEA modes.
4671 */
4672 quirks = drm_add_display_info(connector, edid);
4673
4674 /*
4675 * EDID spec says modes should be preferred in this order:
4676 * - preferred detailed mode
4677 * - other detailed modes from base block
4678 * - detailed modes from extension blocks
4679 * - CVT 3-byte code modes
4680 * - standard timing codes
4681 * - established timing codes
4682 * - modes inferred from GTF or CVT range information
4683 *
4684 * We get this pretty much right.
4685 *
4686 * XXX order for additional mode types in extension blocks?
4687 */
4688 num_modes += add_detailed_modes(connector, edid, quirks);
4689 num_modes += add_cvt_modes(connector, edid);
4690 num_modes += add_standard_modes(connector, edid);
4691 num_modes += add_established_modes(connector, edid);
4692 num_modes += add_cea_modes(connector, edid);
4693 num_modes += add_alternate_cea_modes(connector, edid);
4694 num_modes += add_displayid_detailed_modes(connector, edid);
4695 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4696 num_modes += add_inferred_modes(connector, edid);
4697
4698 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4699 edid_fixup_preferred(connector, quirks);
4700
4701 if (quirks & EDID_QUIRK_FORCE_6BPC)
4702 connector->display_info.bpc = 6;
4703
4704 if (quirks & EDID_QUIRK_FORCE_8BPC)
4705 connector->display_info.bpc = 8;
4706
4707 if (quirks & EDID_QUIRK_FORCE_10BPC)
4708 connector->display_info.bpc = 10;
4709
4710 if (quirks & EDID_QUIRK_FORCE_12BPC)
4711 connector->display_info.bpc = 12;
4712
4713 return num_modes;
4714 }
4715 EXPORT_SYMBOL(drm_add_edid_modes);
4716
4717 /**
4718 * drm_add_modes_noedid - add modes for the connectors without EDID
4719 * @connector: connector we're probing
4720 * @hdisplay: the horizontal display limit
4721 * @vdisplay: the vertical display limit
4722 *
4723 * Add the specified modes to the connector's mode list. Only when the
4724 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4725 *
4726 * Return: The number of modes added or 0 if we couldn't find any.
4727 */
4728 int drm_add_modes_noedid(struct drm_connector *connector,
4729 int hdisplay, int vdisplay)
4730 {
4731 int i, count, num_modes = 0;
4732 struct drm_display_mode *mode;
4733 struct drm_device *dev = connector->dev;
4734
4735 count = ARRAY_SIZE(drm_dmt_modes);
4736 if (hdisplay < 0)
4737 hdisplay = 0;
4738 if (vdisplay < 0)
4739 vdisplay = 0;
4740
4741 for (i = 0; i < count; i++) {
4742 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4743 if (hdisplay && vdisplay) {
4744 /*
4745 * Only when two are valid, they will be used to check
4746 * whether the mode should be added to the mode list of
4747 * the connector.
4748 */
4749 if (ptr->hdisplay > hdisplay ||
4750 ptr->vdisplay > vdisplay)
4751 continue;
4752 }
4753 if (drm_mode_vrefresh(ptr) > 61)
4754 continue;
4755 mode = drm_mode_duplicate(dev, ptr);
4756 if (mode) {
4757 drm_mode_probed_add(connector, mode);
4758 num_modes++;
4759 }
4760 }
4761 return num_modes;
4762 }
4763 EXPORT_SYMBOL(drm_add_modes_noedid);
4764
4765 /**
4766 * drm_set_preferred_mode - Sets the preferred mode of a connector
4767 * @connector: connector whose mode list should be processed
4768 * @hpref: horizontal resolution of preferred mode
4769 * @vpref: vertical resolution of preferred mode
4770 *
4771 * Marks a mode as preferred if it matches the resolution specified by @hpref
4772 * and @vpref.
4773 */
4774 void drm_set_preferred_mode(struct drm_connector *connector,
4775 int hpref, int vpref)
4776 {
4777 struct drm_display_mode *mode;
4778
4779 list_for_each_entry(mode, &connector->probed_modes, head) {
4780 if (mode->hdisplay == hpref &&
4781 mode->vdisplay == vpref)
4782 mode->type |= DRM_MODE_TYPE_PREFERRED;
4783 }
4784 }
4785 EXPORT_SYMBOL(drm_set_preferred_mode);
4786
4787 /**
4788 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4789 * data from a DRM display mode
4790 * @frame: HDMI AVI infoframe
4791 * @mode: DRM display mode
4792 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4793 *
4794 * Return: 0 on success or a negative error code on failure.
4795 */
4796 int
4797 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4798 const struct drm_display_mode *mode,
4799 bool is_hdmi2_sink)
4800 {
4801 int err;
4802
4803 if (!frame || !mode)
4804 return -EINVAL;
4805
4806 err = hdmi_avi_infoframe_init(frame);
4807 if (err < 0)
4808 return err;
4809
4810 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4811 frame->pixel_repeat = 1;
4812
4813 frame->video_code = drm_match_cea_mode(mode);
4814
4815 /*
4816 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4817 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4818 * have to make sure we dont break HDMI 1.4 sinks.
4819 */
4820 if (!is_hdmi2_sink && frame->video_code > 64)
4821 frame->video_code = 0;
4822
4823 /*
4824 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4825 * we should send its VIC in vendor infoframes, else send the
4826 * VIC in AVI infoframes. Lets check if this mode is present in
4827 * HDMI 1.4b 4K modes
4828 */
4829 if (frame->video_code) {
4830 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4831 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4832
4833 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4834 frame->video_code = 0;
4835 }
4836
4837 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4838
4839 /*
4840 * Populate picture aspect ratio from either
4841 * user input (if specified) or from the CEA mode list.
4842 */
4843 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4844 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4845 frame->picture_aspect = mode->picture_aspect_ratio;
4846 else if (frame->video_code > 0)
4847 frame->picture_aspect = drm_get_cea_aspect_ratio(
4848 frame->video_code);
4849
4850 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4851 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4852
4853 return 0;
4854 }
4855 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4856
4857 /**
4858 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4859 * quantization range information
4860 * @frame: HDMI AVI infoframe
4861 * @mode: DRM display mode
4862 * @rgb_quant_range: RGB quantization range (Q)
4863 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4864 */
4865 void
4866 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4867 const struct drm_display_mode *mode,
4868 enum hdmi_quantization_range rgb_quant_range,
4869 bool rgb_quant_range_selectable,
4870 bool is_hdmi2_sink)
4871 {
4872 /*
4873 * CEA-861:
4874 * "A Source shall not send a non-zero Q value that does not correspond
4875 * to the default RGB Quantization Range for the transmitted Picture
4876 * unless the Sink indicates support for the Q bit in a Video
4877 * Capabilities Data Block."
4878 *
4879 * HDMI 2.0 recommends sending non-zero Q when it does match the
4880 * default RGB quantization range for the mode, even when QS=0.
4881 */
4882 if (rgb_quant_range_selectable ||
4883 rgb_quant_range == drm_default_rgb_quant_range(mode))
4884 frame->quantization_range = rgb_quant_range;
4885 else
4886 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4887
4888 /*
4889 * CEA-861-F:
4890 * "When transmitting any RGB colorimetry, the Source should set the
4891 * YQ-field to match the RGB Quantization Range being transmitted
4892 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4893 * set YQ=1) and the Sink shall ignore the YQ-field."
4894 *
4895 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4896 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4897 * good way to tell which version of CEA-861 the sink supports, so
4898 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4899 * on on CEA-861-F.
4900 */
4901 if (!is_hdmi2_sink ||
4902 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4903 frame->ycc_quantization_range =
4904 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4905 else
4906 frame->ycc_quantization_range =
4907 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4908 }
4909 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4910
4911 static enum hdmi_3d_structure
4912 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4913 {
4914 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4915
4916 switch (layout) {
4917 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4918 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4919 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4920 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4921 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4922 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4923 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4924 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4925 case DRM_MODE_FLAG_3D_L_DEPTH:
4926 return HDMI_3D_STRUCTURE_L_DEPTH;
4927 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4928 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4929 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4930 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4931 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4932 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4933 default:
4934 return HDMI_3D_STRUCTURE_INVALID;
4935 }
4936 }
4937
4938 /**
4939 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4940 * data from a DRM display mode
4941 * @frame: HDMI vendor infoframe
4942 * @mode: DRM display mode
4943 *
4944 * Note that there's is a need to send HDMI vendor infoframes only when using a
4945 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4946 * function will return -EINVAL, error that can be safely ignored.
4947 *
4948 * Return: 0 on success or a negative error code on failure.
4949 */
4950 int
4951 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4952 const struct drm_display_mode *mode)
4953 {
4954 int err;
4955 u32 s3d_flags;
4956 u8 vic;
4957
4958 if (!frame || !mode)
4959 return -EINVAL;
4960
4961 vic = drm_match_hdmi_mode(mode);
4962 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4963
4964 if (!vic && !s3d_flags)
4965 return -EINVAL;
4966
4967 if (vic && s3d_flags)
4968 return -EINVAL;
4969
4970 err = hdmi_vendor_infoframe_init(frame);
4971 if (err < 0)
4972 return err;
4973
4974 if (vic)
4975 frame->vic = vic;
4976 else
4977 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4978
4979 return 0;
4980 }
4981 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4982
4983 static int drm_parse_tiled_block(struct drm_connector *connector,
4984 struct displayid_block *block)
4985 {
4986 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4987 u16 w, h;
4988 u8 tile_v_loc, tile_h_loc;
4989 u8 num_v_tile, num_h_tile;
4990 struct drm_tile_group *tg;
4991
4992 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4993 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4994
4995 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4996 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4997 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4998 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4999
5000 connector->has_tile = true;
5001 if (tile->tile_cap & 0x80)
5002 connector->tile_is_single_monitor = true;
5003
5004 connector->num_h_tile = num_h_tile + 1;
5005 connector->num_v_tile = num_v_tile + 1;
5006 connector->tile_h_loc = tile_h_loc;
5007 connector->tile_v_loc = tile_v_loc;
5008 connector->tile_h_size = w + 1;
5009 connector->tile_v_size = h + 1;
5010
5011 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5012 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5013 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5014 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5015 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5016
5017 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5018 if (!tg) {
5019 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5020 }
5021 if (!tg)
5022 return -ENOMEM;
5023
5024 if (connector->tile_group != tg) {
5025 /* if we haven't got a pointer,
5026 take the reference, drop ref to old tile group */
5027 if (connector->tile_group) {
5028 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5029 }
5030 connector->tile_group = tg;
5031 } else
5032 /* if same tile group, then release the ref we just took. */
5033 drm_mode_put_tile_group(connector->dev, tg);
5034 return 0;
5035 }
5036
5037 static int drm_parse_display_id(struct drm_connector *connector,
5038 u8 *displayid, int length,
5039 bool is_edid_extension)
5040 {
5041 /* if this is an EDID extension the first byte will be 0x70 */
5042 int idx = 0;
5043 struct displayid_block *block;
5044 int ret;
5045
5046 if (is_edid_extension)
5047 idx = 1;
5048
5049 ret = validate_displayid(displayid, length, idx);
5050 if (ret)
5051 return ret;
5052
5053 idx += sizeof(struct displayid_hdr);
5054 while (block = (struct displayid_block *)&displayid[idx],
5055 idx + sizeof(struct displayid_block) <= length &&
5056 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5057 block->num_bytes > 0) {
5058 idx += block->num_bytes + sizeof(struct displayid_block);
5059 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5060 block->tag, block->rev, block->num_bytes);
5061
5062 switch (block->tag) {
5063 case DATA_BLOCK_TILED_DISPLAY:
5064 ret = drm_parse_tiled_block(connector, block);
5065 if (ret)
5066 return ret;
5067 break;
5068 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5069 /* handled in mode gathering code. */
5070 break;
5071 default:
5072 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5073 break;
5074 }
5075 }
5076 return 0;
5077 }
5078
5079 static void drm_get_displayid(struct drm_connector *connector,
5080 struct edid *edid)
5081 {
5082 void *displayid = NULL;
5083 int ret;
5084 connector->has_tile = false;
5085 displayid = drm_find_displayid_extension(edid);
5086 if (!displayid) {
5087 /* drop reference to any tile group we had */
5088 goto out_drop_ref;
5089 }
5090
5091 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5092 if (ret < 0)
5093 goto out_drop_ref;
5094 if (!connector->has_tile)
5095 goto out_drop_ref;
5096 return;
5097 out_drop_ref:
5098 if (connector->tile_group) {
5099 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5100 connector->tile_group = NULL;
5101 }
5102 return;
5103 }
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