2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
42 #include "drm_crtc_internal.h"
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 struct detailed_mode_closure
{
87 struct drm_connector
*connector
;
99 static const struct edid_quirk
{
103 } edid_quirk_list
[] = {
105 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60
},
107 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60
},
109 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED
},
111 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
112 { "AEO", 0, EDID_QUIRK_FORCE_6BPC
},
114 /* Belinea 10 15 55 */
115 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60
},
116 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60
},
118 /* Envision Peripherals, Inc. EN-7100e */
119 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH
},
120 /* Envision EN2028 */
121 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60
},
123 /* Funai Electronics PM36B */
124 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75
|
125 EDID_QUIRK_DETAILED_IN_CM
},
127 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
128 { "LGD", 764, EDID_QUIRK_FORCE_10BPC
},
130 /* LG Philips LCD LP154W01-A5 */
131 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE
},
132 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE
},
134 /* Philips 107p5 CRT */
135 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED
},
138 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED
},
140 /* Samsung SyncMaster 205BW. Note: irony */
141 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP
},
142 /* Samsung SyncMaster 22[5-6]BW */
143 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60
},
144 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60
},
146 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
147 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC
},
149 /* ViewSonic VA2026w */
150 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING
},
152 /* Medion MD 30217 PG */
153 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75
},
155 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
156 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC
},
158 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
159 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC
},
163 * Autogenerated from the DMT spec.
164 * This table is copied from xfree86/modes/xf86EdidModes.c.
166 static const struct drm_display_mode drm_dmt_modes
[] = {
167 /* 0x01 - 640x350@85Hz */
168 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER
, 31500, 640, 672,
169 736, 832, 0, 350, 382, 385, 445, 0,
170 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
171 /* 0x02 - 640x400@85Hz */
172 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER
, 31500, 640, 672,
173 736, 832, 0, 400, 401, 404, 445, 0,
174 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
175 /* 0x03 - 720x400@85Hz */
176 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER
, 35500, 720, 756,
177 828, 936, 0, 400, 401, 404, 446, 0,
178 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
179 /* 0x04 - 640x480@60Hz */
180 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 25175, 640, 656,
181 752, 800, 0, 480, 490, 492, 525, 0,
182 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
183 /* 0x05 - 640x480@72Hz */
184 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 31500, 640, 664,
185 704, 832, 0, 480, 489, 492, 520, 0,
186 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
187 /* 0x06 - 640x480@75Hz */
188 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 31500, 640, 656,
189 720, 840, 0, 480, 481, 484, 500, 0,
190 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
191 /* 0x07 - 640x480@85Hz */
192 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 36000, 640, 696,
193 752, 832, 0, 480, 481, 484, 509, 0,
194 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
195 /* 0x08 - 800x600@56Hz */
196 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 36000, 800, 824,
197 896, 1024, 0, 600, 601, 603, 625, 0,
198 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
199 /* 0x09 - 800x600@60Hz */
200 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 40000, 800, 840,
201 968, 1056, 0, 600, 601, 605, 628, 0,
202 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
203 /* 0x0a - 800x600@72Hz */
204 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 50000, 800, 856,
205 976, 1040, 0, 600, 637, 643, 666, 0,
206 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
207 /* 0x0b - 800x600@75Hz */
208 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 49500, 800, 816,
209 896, 1056, 0, 600, 601, 604, 625, 0,
210 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
211 /* 0x0c - 800x600@85Hz */
212 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 56250, 800, 832,
213 896, 1048, 0, 600, 601, 604, 631, 0,
214 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
215 /* 0x0d - 800x600@120Hz RB */
216 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 73250, 800, 848,
217 880, 960, 0, 600, 603, 607, 636, 0,
218 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
219 /* 0x0e - 848x480@60Hz */
220 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER
, 33750, 848, 864,
221 976, 1088, 0, 480, 486, 494, 517, 0,
222 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
223 /* 0x0f - 1024x768@43Hz, interlace */
224 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER
, 44900, 1024, 1032,
225 1208, 1264, 0, 768, 768, 776, 817, 0,
226 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
227 DRM_MODE_FLAG_INTERLACE
) },
228 /* 0x10 - 1024x768@60Hz */
229 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 65000, 1024, 1048,
230 1184, 1344, 0, 768, 771, 777, 806, 0,
231 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
232 /* 0x11 - 1024x768@70Hz */
233 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 75000, 1024, 1048,
234 1184, 1328, 0, 768, 771, 777, 806, 0,
235 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
236 /* 0x12 - 1024x768@75Hz */
237 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 78750, 1024, 1040,
238 1136, 1312, 0, 768, 769, 772, 800, 0,
239 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
240 /* 0x13 - 1024x768@85Hz */
241 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 94500, 1024, 1072,
242 1168, 1376, 0, 768, 769, 772, 808, 0,
243 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
244 /* 0x14 - 1024x768@120Hz RB */
245 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 115500, 1024, 1072,
246 1104, 1184, 0, 768, 771, 775, 813, 0,
247 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
248 /* 0x15 - 1152x864@75Hz */
249 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER
, 108000, 1152, 1216,
250 1344, 1600, 0, 864, 865, 868, 900, 0,
251 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
252 /* 0x55 - 1280x720@60Hz */
253 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1390,
254 1430, 1650, 0, 720, 725, 730, 750, 0,
255 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
256 /* 0x16 - 1280x768@60Hz RB */
257 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 68250, 1280, 1328,
258 1360, 1440, 0, 768, 771, 778, 790, 0,
259 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
260 /* 0x17 - 1280x768@60Hz */
261 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 79500, 1280, 1344,
262 1472, 1664, 0, 768, 771, 778, 798, 0,
263 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
264 /* 0x18 - 1280x768@75Hz */
265 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 102250, 1280, 1360,
266 1488, 1696, 0, 768, 771, 778, 805, 0,
267 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
268 /* 0x19 - 1280x768@85Hz */
269 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 117500, 1280, 1360,
270 1496, 1712, 0, 768, 771, 778, 809, 0,
271 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
272 /* 0x1a - 1280x768@120Hz RB */
273 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 140250, 1280, 1328,
274 1360, 1440, 0, 768, 771, 778, 813, 0,
275 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
276 /* 0x1b - 1280x800@60Hz RB */
277 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 71000, 1280, 1328,
278 1360, 1440, 0, 800, 803, 809, 823, 0,
279 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
280 /* 0x1c - 1280x800@60Hz */
281 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 83500, 1280, 1352,
282 1480, 1680, 0, 800, 803, 809, 831, 0,
283 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
284 /* 0x1d - 1280x800@75Hz */
285 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 106500, 1280, 1360,
286 1488, 1696, 0, 800, 803, 809, 838, 0,
287 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
288 /* 0x1e - 1280x800@85Hz */
289 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 122500, 1280, 1360,
290 1496, 1712, 0, 800, 803, 809, 843, 0,
291 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
292 /* 0x1f - 1280x800@120Hz RB */
293 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 146250, 1280, 1328,
294 1360, 1440, 0, 800, 803, 809, 847, 0,
295 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
296 /* 0x20 - 1280x960@60Hz */
297 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER
, 108000, 1280, 1376,
298 1488, 1800, 0, 960, 961, 964, 1000, 0,
299 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
300 /* 0x21 - 1280x960@85Hz */
301 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER
, 148500, 1280, 1344,
302 1504, 1728, 0, 960, 961, 964, 1011, 0,
303 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
304 /* 0x22 - 1280x960@120Hz RB */
305 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER
, 175500, 1280, 1328,
306 1360, 1440, 0, 960, 963, 967, 1017, 0,
307 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
308 /* 0x23 - 1280x1024@60Hz */
309 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 108000, 1280, 1328,
310 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
311 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
312 /* 0x24 - 1280x1024@75Hz */
313 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 135000, 1280, 1296,
314 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
315 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
316 /* 0x25 - 1280x1024@85Hz */
317 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 157500, 1280, 1344,
318 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
319 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
320 /* 0x26 - 1280x1024@120Hz RB */
321 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 187250, 1280, 1328,
322 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
323 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
324 /* 0x27 - 1360x768@60Hz */
325 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER
, 85500, 1360, 1424,
326 1536, 1792, 0, 768, 771, 777, 795, 0,
327 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
328 /* 0x28 - 1360x768@120Hz RB */
329 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER
, 148250, 1360, 1408,
330 1440, 1520, 0, 768, 771, 776, 813, 0,
331 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
332 /* 0x51 - 1366x768@60Hz */
333 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER
, 85500, 1366, 1436,
334 1579, 1792, 0, 768, 771, 774, 798, 0,
335 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
336 /* 0x56 - 1366x768@60Hz */
337 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER
, 72000, 1366, 1380,
338 1436, 1500, 0, 768, 769, 772, 800, 0,
339 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
340 /* 0x29 - 1400x1050@60Hz RB */
341 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 101000, 1400, 1448,
342 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
343 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
344 /* 0x2a - 1400x1050@60Hz */
345 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 121750, 1400, 1488,
346 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
347 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
348 /* 0x2b - 1400x1050@75Hz */
349 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 156000, 1400, 1504,
350 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
351 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
352 /* 0x2c - 1400x1050@85Hz */
353 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 179500, 1400, 1504,
354 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
355 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
356 /* 0x2d - 1400x1050@120Hz RB */
357 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 208000, 1400, 1448,
358 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
359 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
360 /* 0x2e - 1440x900@60Hz RB */
361 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 88750, 1440, 1488,
362 1520, 1600, 0, 900, 903, 909, 926, 0,
363 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
364 /* 0x2f - 1440x900@60Hz */
365 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 106500, 1440, 1520,
366 1672, 1904, 0, 900, 903, 909, 934, 0,
367 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
368 /* 0x30 - 1440x900@75Hz */
369 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 136750, 1440, 1536,
370 1688, 1936, 0, 900, 903, 909, 942, 0,
371 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
372 /* 0x31 - 1440x900@85Hz */
373 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 157000, 1440, 1544,
374 1696, 1952, 0, 900, 903, 909, 948, 0,
375 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
376 /* 0x32 - 1440x900@120Hz RB */
377 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 182750, 1440, 1488,
378 1520, 1600, 0, 900, 903, 909, 953, 0,
379 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
380 /* 0x53 - 1600x900@60Hz */
381 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER
, 108000, 1600, 1624,
382 1704, 1800, 0, 900, 901, 904, 1000, 0,
383 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
384 /* 0x33 - 1600x1200@60Hz */
385 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 162000, 1600, 1664,
386 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
387 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
388 /* 0x34 - 1600x1200@65Hz */
389 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 175500, 1600, 1664,
390 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
391 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
392 /* 0x35 - 1600x1200@70Hz */
393 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 189000, 1600, 1664,
394 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
395 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
396 /* 0x36 - 1600x1200@75Hz */
397 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 202500, 1600, 1664,
398 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
399 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
400 /* 0x37 - 1600x1200@85Hz */
401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 229500, 1600, 1664,
402 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
403 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
404 /* 0x38 - 1600x1200@120Hz RB */
405 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 268250, 1600, 1648,
406 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
407 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
408 /* 0x39 - 1680x1050@60Hz RB */
409 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 119000, 1680, 1728,
410 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
411 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
412 /* 0x3a - 1680x1050@60Hz */
413 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 146250, 1680, 1784,
414 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
415 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
416 /* 0x3b - 1680x1050@75Hz */
417 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 187000, 1680, 1800,
418 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
419 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
420 /* 0x3c - 1680x1050@85Hz */
421 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 214750, 1680, 1808,
422 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
423 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
424 /* 0x3d - 1680x1050@120Hz RB */
425 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 245500, 1680, 1728,
426 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
427 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
428 /* 0x3e - 1792x1344@60Hz */
429 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER
, 204750, 1792, 1920,
430 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
431 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
432 /* 0x3f - 1792x1344@75Hz */
433 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER
, 261000, 1792, 1888,
434 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
435 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
436 /* 0x40 - 1792x1344@120Hz RB */
437 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER
, 333250, 1792, 1840,
438 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
439 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
440 /* 0x41 - 1856x1392@60Hz */
441 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER
, 218250, 1856, 1952,
442 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
443 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
444 /* 0x42 - 1856x1392@75Hz */
445 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER
, 288000, 1856, 1984,
446 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
447 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
448 /* 0x43 - 1856x1392@120Hz RB */
449 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER
, 356500, 1856, 1904,
450 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
451 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
452 /* 0x52 - 1920x1080@60Hz */
453 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2008,
454 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
455 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
456 /* 0x44 - 1920x1200@60Hz RB */
457 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 154000, 1920, 1968,
458 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
459 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
460 /* 0x45 - 1920x1200@60Hz */
461 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 193250, 1920, 2056,
462 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
463 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
464 /* 0x46 - 1920x1200@75Hz */
465 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 245250, 1920, 2056,
466 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
467 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
468 /* 0x47 - 1920x1200@85Hz */
469 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 281250, 1920, 2064,
470 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
471 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
472 /* 0x48 - 1920x1200@120Hz RB */
473 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 317000, 1920, 1968,
474 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
475 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
476 /* 0x49 - 1920x1440@60Hz */
477 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER
, 234000, 1920, 2048,
478 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
479 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
480 /* 0x4a - 1920x1440@75Hz */
481 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER
, 297000, 1920, 2064,
482 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
483 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
484 /* 0x4b - 1920x1440@120Hz RB */
485 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER
, 380500, 1920, 1968,
486 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
487 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
488 /* 0x54 - 2048x1152@60Hz */
489 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER
, 162000, 2048, 2074,
490 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
491 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
492 /* 0x4c - 2560x1600@60Hz RB */
493 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 268500, 2560, 2608,
494 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
495 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
496 /* 0x4d - 2560x1600@60Hz */
497 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 348500, 2560, 2752,
498 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
499 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
500 /* 0x4e - 2560x1600@75Hz */
501 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 443250, 2560, 2768,
502 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
503 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
504 /* 0x4f - 2560x1600@85Hz */
505 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 505250, 2560, 2768,
506 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
507 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
508 /* 0x50 - 2560x1600@120Hz RB */
509 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 552750, 2560, 2608,
510 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
511 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
512 /* 0x57 - 4096x2160@60Hz RB */
513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 556744, 4096, 4104,
514 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
515 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
516 /* 0x58 - 4096x2160@59.94Hz RB */
517 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 556188, 4096, 4104,
518 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
519 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
523 * These more or less come from the DMT spec. The 720x400 modes are
524 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
525 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
526 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
529 * The DMT modes have been fact-checked; the rest are mild guesses.
531 static const struct drm_display_mode edid_est_modes
[] = {
532 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 40000, 800, 840,
533 968, 1056, 0, 600, 601, 605, 628, 0,
534 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 800x600@60Hz */
535 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 36000, 800, 824,
536 896, 1024, 0, 600, 601, 603, 625, 0,
537 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 800x600@56Hz */
538 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 31500, 640, 656,
539 720, 840, 0, 480, 481, 484, 500, 0,
540 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 640x480@75Hz */
541 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 31500, 640, 664,
542 704, 832, 0, 480, 489, 492, 520, 0,
543 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 640x480@72Hz */
544 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 30240, 640, 704,
545 768, 864, 0, 480, 483, 486, 525, 0,
546 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 640x480@67Hz */
547 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 25175, 640, 656,
548 752, 800, 0, 480, 490, 492, 525, 0,
549 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 640x480@60Hz */
550 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER
, 35500, 720, 738,
551 846, 900, 0, 400, 421, 423, 449, 0,
552 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 720x400@88Hz */
553 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER
, 28320, 720, 738,
554 846, 900, 0, 400, 412, 414, 449, 0,
555 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 720x400@70Hz */
556 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 135000, 1280, 1296,
557 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
558 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 1280x1024@75Hz */
559 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 78750, 1024, 1040,
560 1136, 1312, 0, 768, 769, 772, 800, 0,
561 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 1024x768@75Hz */
562 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 75000, 1024, 1048,
563 1184, 1328, 0, 768, 771, 777, 806, 0,
564 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 1024x768@70Hz */
565 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 65000, 1024, 1048,
566 1184, 1344, 0, 768, 771, 777, 806, 0,
567 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 1024x768@60Hz */
568 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER
,44900, 1024, 1032,
569 1208, 1264, 0, 768, 768, 776, 817, 0,
570 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_INTERLACE
) }, /* 1024x768@43Hz */
571 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER
, 57284, 832, 864,
572 928, 1152, 0, 624, 625, 628, 667, 0,
573 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 832x624@75Hz */
574 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 49500, 800, 816,
575 896, 1056, 0, 600, 601, 604, 625, 0,
576 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 800x600@75Hz */
577 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 50000, 800, 856,
578 976, 1040, 0, 600, 637, 643, 666, 0,
579 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 800x600@72Hz */
580 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER
, 108000, 1152, 1216,
581 1344, 1600, 0, 864, 865, 868, 900, 0,
582 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 1152x864@75Hz */
592 static const struct minimode est3_modes
[] = {
600 { 1024, 768, 85, 0 },
601 { 1152, 864, 75, 0 },
603 { 1280, 768, 60, 1 },
604 { 1280, 768, 60, 0 },
605 { 1280, 768, 75, 0 },
606 { 1280, 768, 85, 0 },
607 { 1280, 960, 60, 0 },
608 { 1280, 960, 85, 0 },
609 { 1280, 1024, 60, 0 },
610 { 1280, 1024, 85, 0 },
612 { 1360, 768, 60, 0 },
613 { 1440, 900, 60, 1 },
614 { 1440, 900, 60, 0 },
615 { 1440, 900, 75, 0 },
616 { 1440, 900, 85, 0 },
617 { 1400, 1050, 60, 1 },
618 { 1400, 1050, 60, 0 },
619 { 1400, 1050, 75, 0 },
621 { 1400, 1050, 85, 0 },
622 { 1680, 1050, 60, 1 },
623 { 1680, 1050, 60, 0 },
624 { 1680, 1050, 75, 0 },
625 { 1680, 1050, 85, 0 },
626 { 1600, 1200, 60, 0 },
627 { 1600, 1200, 65, 0 },
628 { 1600, 1200, 70, 0 },
630 { 1600, 1200, 75, 0 },
631 { 1600, 1200, 85, 0 },
632 { 1792, 1344, 60, 0 },
633 { 1792, 1344, 75, 0 },
634 { 1856, 1392, 60, 0 },
635 { 1856, 1392, 75, 0 },
636 { 1920, 1200, 60, 1 },
637 { 1920, 1200, 60, 0 },
639 { 1920, 1200, 75, 0 },
640 { 1920, 1200, 85, 0 },
641 { 1920, 1440, 60, 0 },
642 { 1920, 1440, 75, 0 },
645 static const struct minimode extra_modes
[] = {
646 { 1024, 576, 60, 0 },
647 { 1366, 768, 60, 0 },
648 { 1600, 900, 60, 0 },
649 { 1680, 945, 60, 0 },
650 { 1920, 1080, 60, 0 },
651 { 2048, 1152, 60, 0 },
652 { 2048, 1536, 60, 0 },
656 * Probably taken from CEA-861 spec.
657 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
659 * Index using the VIC.
661 static const struct drm_display_mode edid_cea_modes
[] = {
662 /* 0 - dummy, VICs start at 1 */
664 /* 1 - 640x480@60Hz */
665 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 25175, 640, 656,
666 752, 800, 0, 480, 490, 492, 525, 0,
667 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
668 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
669 /* 2 - 720x480@60Hz */
670 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 27000, 720, 736,
671 798, 858, 0, 480, 489, 495, 525, 0,
672 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
673 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
674 /* 3 - 720x480@60Hz */
675 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 27000, 720, 736,
676 798, 858, 0, 480, 489, 495, 525, 0,
677 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
678 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
679 /* 4 - 1280x720@60Hz */
680 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1390,
681 1430, 1650, 0, 720, 725, 730, 750, 0,
682 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
683 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
684 /* 5 - 1920x1080i@60Hz */
685 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2008,
686 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
687 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
688 DRM_MODE_FLAG_INTERLACE
),
689 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
690 /* 6 - 720(1440)x480i@60Hz */
691 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 13500, 720, 739,
692 801, 858, 0, 480, 488, 494, 525, 0,
693 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
694 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
695 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
696 /* 7 - 720(1440)x480i@60Hz */
697 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 13500, 720, 739,
698 801, 858, 0, 480, 488, 494, 525, 0,
699 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
700 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
701 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
702 /* 8 - 720(1440)x240@60Hz */
703 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER
, 13500, 720, 739,
704 801, 858, 0, 240, 244, 247, 262, 0,
705 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
706 DRM_MODE_FLAG_DBLCLK
),
707 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
708 /* 9 - 720(1440)x240@60Hz */
709 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER
, 13500, 720, 739,
710 801, 858, 0, 240, 244, 247, 262, 0,
711 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
712 DRM_MODE_FLAG_DBLCLK
),
713 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
714 /* 10 - 2880x480i@60Hz */
715 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2956,
716 3204, 3432, 0, 480, 488, 494, 525, 0,
717 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
718 DRM_MODE_FLAG_INTERLACE
),
719 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
720 /* 11 - 2880x480i@60Hz */
721 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2956,
722 3204, 3432, 0, 480, 488, 494, 525, 0,
723 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
724 DRM_MODE_FLAG_INTERLACE
),
725 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
726 /* 12 - 2880x240@60Hz */
727 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2956,
728 3204, 3432, 0, 240, 244, 247, 262, 0,
729 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
730 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
731 /* 13 - 2880x240@60Hz */
732 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2956,
733 3204, 3432, 0, 240, 244, 247, 262, 0,
734 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
735 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
736 /* 14 - 1440x480@60Hz */
737 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER
, 54000, 1440, 1472,
738 1596, 1716, 0, 480, 489, 495, 525, 0,
739 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
740 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
741 /* 15 - 1440x480@60Hz */
742 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER
, 54000, 1440, 1472,
743 1596, 1716, 0, 480, 489, 495, 525, 0,
744 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
745 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
746 /* 16 - 1920x1080@60Hz */
747 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2008,
748 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
749 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
750 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
751 /* 17 - 720x576@50Hz */
752 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 27000, 720, 732,
753 796, 864, 0, 576, 581, 586, 625, 0,
754 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
755 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
756 /* 18 - 720x576@50Hz */
757 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 27000, 720, 732,
758 796, 864, 0, 576, 581, 586, 625, 0,
759 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
760 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
761 /* 19 - 1280x720@50Hz */
762 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1720,
763 1760, 1980, 0, 720, 725, 730, 750, 0,
764 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
765 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
766 /* 20 - 1920x1080i@50Hz */
767 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2448,
768 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
769 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
770 DRM_MODE_FLAG_INTERLACE
),
771 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
772 /* 21 - 720(1440)x576i@50Hz */
773 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 13500, 720, 732,
774 795, 864, 0, 576, 580, 586, 625, 0,
775 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
776 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
777 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
778 /* 22 - 720(1440)x576i@50Hz */
779 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 13500, 720, 732,
780 795, 864, 0, 576, 580, 586, 625, 0,
781 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
782 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
783 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
784 /* 23 - 720(1440)x288@50Hz */
785 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER
, 13500, 720, 732,
786 795, 864, 0, 288, 290, 293, 312, 0,
787 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
788 DRM_MODE_FLAG_DBLCLK
),
789 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
790 /* 24 - 720(1440)x288@50Hz */
791 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER
, 13500, 720, 732,
792 795, 864, 0, 288, 290, 293, 312, 0,
793 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
794 DRM_MODE_FLAG_DBLCLK
),
795 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
796 /* 25 - 2880x576i@50Hz */
797 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2928,
798 3180, 3456, 0, 576, 580, 586, 625, 0,
799 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
800 DRM_MODE_FLAG_INTERLACE
),
801 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
802 /* 26 - 2880x576i@50Hz */
803 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2928,
804 3180, 3456, 0, 576, 580, 586, 625, 0,
805 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
806 DRM_MODE_FLAG_INTERLACE
),
807 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
808 /* 27 - 2880x288@50Hz */
809 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2928,
810 3180, 3456, 0, 288, 290, 293, 312, 0,
811 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
812 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
813 /* 28 - 2880x288@50Hz */
814 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2928,
815 3180, 3456, 0, 288, 290, 293, 312, 0,
816 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
817 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
818 /* 29 - 1440x576@50Hz */
819 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER
, 54000, 1440, 1464,
820 1592, 1728, 0, 576, 581, 586, 625, 0,
821 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
822 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
823 /* 30 - 1440x576@50Hz */
824 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER
, 54000, 1440, 1464,
825 1592, 1728, 0, 576, 581, 586, 625, 0,
826 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
827 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
828 /* 31 - 1920x1080@50Hz */
829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2448,
830 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
831 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
832 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
833 /* 32 - 1920x1080@24Hz */
834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2558,
835 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
836 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
837 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
838 /* 33 - 1920x1080@25Hz */
839 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2448,
840 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
841 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
842 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
843 /* 34 - 1920x1080@30Hz */
844 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2008,
845 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
846 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
847 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
848 /* 35 - 2880x480@60Hz */
849 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER
, 108000, 2880, 2944,
850 3192, 3432, 0, 480, 489, 495, 525, 0,
851 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
852 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
853 /* 36 - 2880x480@60Hz */
854 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER
, 108000, 2880, 2944,
855 3192, 3432, 0, 480, 489, 495, 525, 0,
856 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
857 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
858 /* 37 - 2880x576@50Hz */
859 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER
, 108000, 2880, 2928,
860 3184, 3456, 0, 576, 581, 586, 625, 0,
861 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
862 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
863 /* 38 - 2880x576@50Hz */
864 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER
, 108000, 2880, 2928,
865 3184, 3456, 0, 576, 581, 586, 625, 0,
866 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
867 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
868 /* 39 - 1920x1080i@50Hz */
869 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 72000, 1920, 1952,
870 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
871 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
|
872 DRM_MODE_FLAG_INTERLACE
),
873 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
874 /* 40 - 1920x1080i@100Hz */
875 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2448,
876 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
877 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
878 DRM_MODE_FLAG_INTERLACE
),
879 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
880 /* 41 - 1280x720@100Hz */
881 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 148500, 1280, 1720,
882 1760, 1980, 0, 720, 725, 730, 750, 0,
883 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
884 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
885 /* 42 - 720x576@100Hz */
886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 54000, 720, 732,
887 796, 864, 0, 576, 581, 586, 625, 0,
888 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
889 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
890 /* 43 - 720x576@100Hz */
891 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 54000, 720, 732,
892 796, 864, 0, 576, 581, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
894 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
895 /* 44 - 720(1440)x576i@100Hz */
896 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 27000, 720, 732,
897 795, 864, 0, 576, 580, 586, 625, 0,
898 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
899 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
900 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
901 /* 45 - 720(1440)x576i@100Hz */
902 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 27000, 720, 732,
903 795, 864, 0, 576, 580, 586, 625, 0,
904 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
905 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
906 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
907 /* 46 - 1920x1080i@120Hz */
908 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2008,
909 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
910 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
911 DRM_MODE_FLAG_INTERLACE
),
912 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
913 /* 47 - 1280x720@120Hz */
914 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 148500, 1280, 1390,
915 1430, 1650, 0, 720, 725, 730, 750, 0,
916 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
917 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
918 /* 48 - 720x480@120Hz */
919 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 54000, 720, 736,
920 798, 858, 0, 480, 489, 495, 525, 0,
921 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
922 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
923 /* 49 - 720x480@120Hz */
924 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 54000, 720, 736,
925 798, 858, 0, 480, 489, 495, 525, 0,
926 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
927 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
928 /* 50 - 720(1440)x480i@120Hz */
929 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 27000, 720, 739,
930 801, 858, 0, 480, 488, 494, 525, 0,
931 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
932 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
933 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
934 /* 51 - 720(1440)x480i@120Hz */
935 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 27000, 720, 739,
936 801, 858, 0, 480, 488, 494, 525, 0,
937 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
938 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
939 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
940 /* 52 - 720x576@200Hz */
941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 108000, 720, 732,
942 796, 864, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
944 .vrefresh
= 200, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
945 /* 53 - 720x576@200Hz */
946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 108000, 720, 732,
947 796, 864, 0, 576, 581, 586, 625, 0,
948 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
949 .vrefresh
= 200, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
950 /* 54 - 720(1440)x576i@200Hz */
951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 54000, 720, 732,
952 795, 864, 0, 576, 580, 586, 625, 0,
953 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
954 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
955 .vrefresh
= 200, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
956 /* 55 - 720(1440)x576i@200Hz */
957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 54000, 720, 732,
958 795, 864, 0, 576, 580, 586, 625, 0,
959 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
960 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
961 .vrefresh
= 200, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
962 /* 56 - 720x480@240Hz */
963 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 108000, 720, 736,
964 798, 858, 0, 480, 489, 495, 525, 0,
965 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
966 .vrefresh
= 240, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
967 /* 57 - 720x480@240Hz */
968 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 108000, 720, 736,
969 798, 858, 0, 480, 489, 495, 525, 0,
970 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
971 .vrefresh
= 240, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
972 /* 58 - 720(1440)x480i@240Hz */
973 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 54000, 720, 739,
974 801, 858, 0, 480, 488, 494, 525, 0,
975 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
976 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
977 .vrefresh
= 240, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
978 /* 59 - 720(1440)x480i@240Hz */
979 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 54000, 720, 739,
980 801, 858, 0, 480, 488, 494, 525, 0,
981 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
982 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
983 .vrefresh
= 240, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
984 /* 60 - 1280x720@24Hz */
985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 59400, 1280, 3040,
986 3080, 3300, 0, 720, 725, 730, 750, 0,
987 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
988 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
989 /* 61 - 1280x720@25Hz */
990 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 3700,
991 3740, 3960, 0, 720, 725, 730, 750, 0,
992 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
993 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
994 /* 62 - 1280x720@30Hz */
995 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 3040,
996 3080, 3300, 0, 720, 725, 730, 750, 0,
997 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
998 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
999 /* 63 - 1920x1080@120Hz */
1000 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 297000, 1920, 2008,
1001 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1002 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1003 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1004 /* 64 - 1920x1080@100Hz */
1005 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 297000, 1920, 2448,
1006 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1007 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1008 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1012 * HDMI 1.4 4k modes. Index using the VIC.
1014 static const struct drm_display_mode edid_4k_modes
[] = {
1015 /* 0 - dummy, VICs start at 1 */
1017 /* 1 - 3840x2160@30Hz */
1018 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000,
1019 3840, 4016, 4104, 4400, 0,
1020 2160, 2168, 2178, 2250, 0,
1021 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1023 /* 2 - 3840x2160@25Hz */
1024 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000,
1025 3840, 4896, 4984, 5280, 0,
1026 2160, 2168, 2178, 2250, 0,
1027 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1029 /* 3 - 3840x2160@24Hz */
1030 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000,
1031 3840, 5116, 5204, 5500, 0,
1032 2160, 2168, 2178, 2250, 0,
1033 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1035 /* 4 - 4096x2160@24Hz (SMPTE) */
1036 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 297000,
1037 4096, 5116, 5204, 5500, 0,
1038 2160, 2168, 2178, 2250, 0,
1039 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1043 /*** DDC fetch and block validation ***/
1045 static const u8 edid_header
[] = {
1046 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1050 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1051 * @raw_edid: pointer to raw base EDID block
1053 * Sanity check the header of the base EDID block.
1055 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1057 int drm_edid_header_is_valid(const u8
*raw_edid
)
1061 for (i
= 0; i
< sizeof(edid_header
); i
++)
1062 if (raw_edid
[i
] == edid_header
[i
])
1067 EXPORT_SYMBOL(drm_edid_header_is_valid
);
1069 static int edid_fixup __read_mostly
= 6;
1070 module_param_named(edid_fixup
, edid_fixup
, int, 0400);
1071 MODULE_PARM_DESC(edid_fixup
,
1072 "Minimum number of valid EDID header bytes (0-8, default 6)");
1074 static void drm_get_displayid(struct drm_connector
*connector
,
1077 static int drm_edid_block_checksum(const u8
*raw_edid
)
1081 for (i
= 0; i
< EDID_LENGTH
; i
++)
1082 csum
+= raw_edid
[i
];
1087 static bool drm_edid_is_zero(const u8
*in_edid
, int length
)
1089 if (memchr_inv(in_edid
, 0, length
))
1096 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1097 * @raw_edid: pointer to raw EDID block
1098 * @block: type of block to validate (0 for base, extension otherwise)
1099 * @print_bad_edid: if true, dump bad EDID blocks to the console
1100 * @edid_corrupt: if true, the header or checksum is invalid
1102 * Validate a base or extension EDID block and optionally dump bad blocks to
1105 * Return: True if the block is valid, false otherwise.
1107 bool drm_edid_block_valid(u8
*raw_edid
, int block
, bool print_bad_edid
,
1111 struct edid
*edid
= (struct edid
*)raw_edid
;
1113 if (WARN_ON(!raw_edid
))
1116 if (edid_fixup
> 8 || edid_fixup
< 0)
1120 int score
= drm_edid_header_is_valid(raw_edid
);
1123 *edid_corrupt
= false;
1124 } else if (score
>= edid_fixup
) {
1125 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1126 * The corrupt flag needs to be set here otherwise, the
1127 * fix-up code here will correct the problem, the
1128 * checksum is correct and the test fails
1131 *edid_corrupt
= true;
1132 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1133 memcpy(raw_edid
, edid_header
, sizeof(edid_header
));
1136 *edid_corrupt
= true;
1141 csum
= drm_edid_block_checksum(raw_edid
);
1144 *edid_corrupt
= true;
1146 /* allow CEA to slide through, switches mangle this */
1147 if (raw_edid
[0] == CEA_EXT
) {
1148 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum
);
1149 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1152 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum
);
1158 /* per-block-type checks */
1159 switch (raw_edid
[0]) {
1161 if (edid
->version
!= 1) {
1162 DRM_NOTE("EDID has major version %d, instead of 1\n", edid
->version
);
1166 if (edid
->revision
> 4)
1167 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1177 if (print_bad_edid
) {
1178 if (drm_edid_is_zero(raw_edid
, EDID_LENGTH
)) {
1179 pr_notice("EDID block is all zeroes\n");
1181 pr_notice("Raw EDID:\n");
1182 print_hex_dump(KERN_NOTICE
,
1183 " \t", DUMP_PREFIX_NONE
, 16, 1,
1184 raw_edid
, EDID_LENGTH
, false);
1189 EXPORT_SYMBOL(drm_edid_block_valid
);
1192 * drm_edid_is_valid - sanity check EDID data
1195 * Sanity-check an entire EDID record (including extensions)
1197 * Return: True if the EDID data is valid, false otherwise.
1199 bool drm_edid_is_valid(struct edid
*edid
)
1202 u8
*raw
= (u8
*)edid
;
1207 for (i
= 0; i
<= edid
->extensions
; i
++)
1208 if (!drm_edid_block_valid(raw
+ i
* EDID_LENGTH
, i
, true, NULL
))
1213 EXPORT_SYMBOL(drm_edid_is_valid
);
1215 #define DDC_SEGMENT_ADDR 0x30
1217 * drm_do_probe_ddc_edid() - get EDID information via I2C
1218 * @data: I2C device adapter
1219 * @buf: EDID data buffer to be filled
1220 * @block: 128 byte EDID block to start fetching from
1221 * @len: EDID data buffer length to fetch
1223 * Try to fetch EDID information by calling I2C driver functions.
1225 * Return: 0 on success or -1 on failure.
1228 drm_do_probe_ddc_edid(void *data
, u8
*buf
, unsigned int block
, size_t len
)
1230 struct i2c_adapter
*adapter
= data
;
1231 unsigned char start
= block
* EDID_LENGTH
;
1232 unsigned char segment
= block
>> 1;
1233 unsigned char xfers
= segment
? 3 : 2;
1234 int ret
, retries
= 5;
1237 * The core I2C driver will automatically retry the transfer if the
1238 * adapter reports EAGAIN. However, we find that bit-banging transfers
1239 * are susceptible to errors under a heavily loaded machine and
1240 * generate spurious NAKs and timeouts. Retrying the transfer
1241 * of the individual block a few times seems to overcome this.
1244 struct i2c_msg msgs
[] = {
1246 .addr
= DDC_SEGMENT_ADDR
,
1264 * Avoid sending the segment addr to not upset non-compliant
1267 ret
= i2c_transfer(adapter
, &msgs
[3 - xfers
], xfers
);
1269 if (ret
== -ENXIO
) {
1270 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1274 } while (ret
!= xfers
&& --retries
);
1276 return ret
== xfers
? 0 : -1;
1279 static void connector_bad_edid(struct drm_connector
*connector
,
1280 u8
*edid
, int num_blocks
)
1284 if (connector
->bad_edid_counter
++ && !(drm_debug
& DRM_UT_KMS
))
1287 dev_warn(connector
->dev
->dev
,
1288 "%s: EDID is invalid:\n",
1290 for (i
= 0; i
< num_blocks
; i
++) {
1291 u8
*block
= edid
+ i
* EDID_LENGTH
;
1294 if (drm_edid_is_zero(block
, EDID_LENGTH
))
1295 sprintf(prefix
, "\t[%02x] ZERO ", i
);
1296 else if (!drm_edid_block_valid(block
, i
, false, NULL
))
1297 sprintf(prefix
, "\t[%02x] BAD ", i
);
1299 sprintf(prefix
, "\t[%02x] GOOD ", i
);
1301 print_hex_dump(KERN_WARNING
,
1302 prefix
, DUMP_PREFIX_NONE
, 16, 1,
1303 block
, EDID_LENGTH
, false);
1308 * drm_do_get_edid - get EDID data using a custom EDID block read function
1309 * @connector: connector we're probing
1310 * @get_edid_block: EDID block read function
1311 * @data: private data passed to the block read function
1313 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1314 * exposes a different interface to read EDID blocks this function can be used
1315 * to get EDID data using a custom block read function.
1317 * As in the general case the DDC bus is accessible by the kernel at the I2C
1318 * level, drivers must make all reasonable efforts to expose it as an I2C
1319 * adapter and use drm_get_edid() instead of abusing this function.
1321 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1323 struct edid
*drm_do_get_edid(struct drm_connector
*connector
,
1324 int (*get_edid_block
)(void *data
, u8
*buf
, unsigned int block
,
1328 int i
, j
= 0, valid_extensions
= 0;
1331 if ((edid
= kmalloc(EDID_LENGTH
, GFP_KERNEL
)) == NULL
)
1334 /* base block fetch */
1335 for (i
= 0; i
< 4; i
++) {
1336 if (get_edid_block(data
, edid
, 0, EDID_LENGTH
))
1338 if (drm_edid_block_valid(edid
, 0, false,
1339 &connector
->edid_corrupt
))
1341 if (i
== 0 && drm_edid_is_zero(edid
, EDID_LENGTH
)) {
1342 connector
->null_edid_counter
++;
1349 /* if there's no extensions, we're done */
1350 valid_extensions
= edid
[0x7e];
1351 if (valid_extensions
== 0)
1352 return (struct edid
*)edid
;
1354 new = krealloc(edid
, (valid_extensions
+ 1) * EDID_LENGTH
, GFP_KERNEL
);
1359 for (j
= 1; j
<= edid
[0x7e]; j
++) {
1360 u8
*block
= edid
+ j
* EDID_LENGTH
;
1362 for (i
= 0; i
< 4; i
++) {
1363 if (get_edid_block(data
, block
, j
, EDID_LENGTH
))
1365 if (drm_edid_block_valid(block
, j
, false, NULL
))
1373 if (valid_extensions
!= edid
[0x7e]) {
1376 connector_bad_edid(connector
, edid
, edid
[0x7e] + 1);
1378 edid
[EDID_LENGTH
-1] += edid
[0x7e] - valid_extensions
;
1379 edid
[0x7e] = valid_extensions
;
1381 new = kmalloc((valid_extensions
+ 1) * EDID_LENGTH
, GFP_KERNEL
);
1386 for (i
= 0; i
<= edid
[0x7e]; i
++) {
1387 u8
*block
= edid
+ i
* EDID_LENGTH
;
1389 if (!drm_edid_block_valid(block
, i
, false, NULL
))
1392 memcpy(base
, block
, EDID_LENGTH
);
1393 base
+= EDID_LENGTH
;
1400 return (struct edid
*)edid
;
1403 connector_bad_edid(connector
, edid
, 1);
1408 EXPORT_SYMBOL_GPL(drm_do_get_edid
);
1411 * drm_probe_ddc() - probe DDC presence
1412 * @adapter: I2C adapter to probe
1414 * Return: True on success, false on failure.
1417 drm_probe_ddc(struct i2c_adapter
*adapter
)
1421 return (drm_do_probe_ddc_edid(adapter
, &out
, 0, 1) == 0);
1423 EXPORT_SYMBOL(drm_probe_ddc
);
1426 * drm_get_edid - get EDID data, if available
1427 * @connector: connector we're probing
1428 * @adapter: I2C adapter to use for DDC
1430 * Poke the given I2C channel to grab EDID data if possible. If found,
1431 * attach it to the connector.
1433 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1435 struct edid
*drm_get_edid(struct drm_connector
*connector
,
1436 struct i2c_adapter
*adapter
)
1440 if (connector
->force
== DRM_FORCE_OFF
)
1443 if (connector
->force
== DRM_FORCE_UNSPECIFIED
&& !drm_probe_ddc(adapter
))
1446 edid
= drm_do_get_edid(connector
, drm_do_probe_ddc_edid
, adapter
);
1448 drm_get_displayid(connector
, edid
);
1451 EXPORT_SYMBOL(drm_get_edid
);
1454 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1455 * @connector: connector we're probing
1456 * @adapter: I2C adapter to use for DDC
1458 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1459 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1460 * switch DDC to the GPU which is retrieving EDID.
1462 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1464 struct edid
*drm_get_edid_switcheroo(struct drm_connector
*connector
,
1465 struct i2c_adapter
*adapter
)
1467 struct pci_dev
*pdev
= connector
->dev
->pdev
;
1470 vga_switcheroo_lock_ddc(pdev
);
1471 edid
= drm_get_edid(connector
, adapter
);
1472 vga_switcheroo_unlock_ddc(pdev
);
1476 EXPORT_SYMBOL(drm_get_edid_switcheroo
);
1479 * drm_edid_duplicate - duplicate an EDID and the extensions
1480 * @edid: EDID to duplicate
1482 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1484 struct edid
*drm_edid_duplicate(const struct edid
*edid
)
1486 return kmemdup(edid
, (edid
->extensions
+ 1) * EDID_LENGTH
, GFP_KERNEL
);
1488 EXPORT_SYMBOL(drm_edid_duplicate
);
1490 /*** EDID parsing ***/
1493 * edid_vendor - match a string against EDID's obfuscated vendor field
1494 * @edid: EDID to match
1495 * @vendor: vendor string
1497 * Returns true if @vendor is in @edid, false otherwise
1499 static bool edid_vendor(struct edid
*edid
, const char *vendor
)
1501 char edid_vendor
[3];
1503 edid_vendor
[0] = ((edid
->mfg_id
[0] & 0x7c) >> 2) + '@';
1504 edid_vendor
[1] = (((edid
->mfg_id
[0] & 0x3) << 3) |
1505 ((edid
->mfg_id
[1] & 0xe0) >> 5)) + '@';
1506 edid_vendor
[2] = (edid
->mfg_id
[1] & 0x1f) + '@';
1508 return !strncmp(edid_vendor
, vendor
, 3);
1512 * edid_get_quirks - return quirk flags for a given EDID
1513 * @edid: EDID to process
1515 * This tells subsequent routines what fixes they need to apply.
1517 static u32
edid_get_quirks(struct edid
*edid
)
1519 const struct edid_quirk
*quirk
;
1522 for (i
= 0; i
< ARRAY_SIZE(edid_quirk_list
); i
++) {
1523 quirk
= &edid_quirk_list
[i
];
1525 if (edid_vendor(edid
, quirk
->vendor
) &&
1526 (EDID_PRODUCT_ID(edid
) == quirk
->product_id
))
1527 return quirk
->quirks
;
1533 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1534 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1537 * edid_fixup_preferred - set preferred modes based on quirk list
1538 * @connector: has mode list to fix up
1539 * @quirks: quirks list
1541 * Walk the mode list for @connector, clearing the preferred status
1542 * on existing modes and setting it anew for the right mode ala @quirks.
1544 static void edid_fixup_preferred(struct drm_connector
*connector
,
1547 struct drm_display_mode
*t
, *cur_mode
, *preferred_mode
;
1548 int target_refresh
= 0;
1549 int cur_vrefresh
, preferred_vrefresh
;
1551 if (list_empty(&connector
->probed_modes
))
1554 if (quirks
& EDID_QUIRK_PREFER_LARGE_60
)
1555 target_refresh
= 60;
1556 if (quirks
& EDID_QUIRK_PREFER_LARGE_75
)
1557 target_refresh
= 75;
1559 preferred_mode
= list_first_entry(&connector
->probed_modes
,
1560 struct drm_display_mode
, head
);
1562 list_for_each_entry_safe(cur_mode
, t
, &connector
->probed_modes
, head
) {
1563 cur_mode
->type
&= ~DRM_MODE_TYPE_PREFERRED
;
1565 if (cur_mode
== preferred_mode
)
1568 /* Largest mode is preferred */
1569 if (MODE_SIZE(cur_mode
) > MODE_SIZE(preferred_mode
))
1570 preferred_mode
= cur_mode
;
1572 cur_vrefresh
= cur_mode
->vrefresh
?
1573 cur_mode
->vrefresh
: drm_mode_vrefresh(cur_mode
);
1574 preferred_vrefresh
= preferred_mode
->vrefresh
?
1575 preferred_mode
->vrefresh
: drm_mode_vrefresh(preferred_mode
);
1576 /* At a given size, try to get closest to target refresh */
1577 if ((MODE_SIZE(cur_mode
) == MODE_SIZE(preferred_mode
)) &&
1578 MODE_REFRESH_DIFF(cur_vrefresh
, target_refresh
) <
1579 MODE_REFRESH_DIFF(preferred_vrefresh
, target_refresh
)) {
1580 preferred_mode
= cur_mode
;
1584 preferred_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
1588 mode_is_rb(const struct drm_display_mode
*mode
)
1590 return (mode
->htotal
- mode
->hdisplay
== 160) &&
1591 (mode
->hsync_end
- mode
->hdisplay
== 80) &&
1592 (mode
->hsync_end
- mode
->hsync_start
== 32) &&
1593 (mode
->vsync_start
- mode
->vdisplay
== 3);
1597 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1598 * @dev: Device to duplicate against
1599 * @hsize: Mode width
1600 * @vsize: Mode height
1601 * @fresh: Mode refresh rate
1602 * @rb: Mode reduced-blanking-ness
1604 * Walk the DMT mode list looking for a match for the given parameters.
1606 * Return: A newly allocated copy of the mode, or NULL if not found.
1608 struct drm_display_mode
*drm_mode_find_dmt(struct drm_device
*dev
,
1609 int hsize
, int vsize
, int fresh
,
1614 for (i
= 0; i
< ARRAY_SIZE(drm_dmt_modes
); i
++) {
1615 const struct drm_display_mode
*ptr
= &drm_dmt_modes
[i
];
1616 if (hsize
!= ptr
->hdisplay
)
1618 if (vsize
!= ptr
->vdisplay
)
1620 if (fresh
!= drm_mode_vrefresh(ptr
))
1622 if (rb
!= mode_is_rb(ptr
))
1625 return drm_mode_duplicate(dev
, ptr
);
1630 EXPORT_SYMBOL(drm_mode_find_dmt
);
1632 typedef void detailed_cb(struct detailed_timing
*timing
, void *closure
);
1635 cea_for_each_detailed_block(u8
*ext
, detailed_cb
*cb
, void *closure
)
1639 u8
*det_base
= ext
+ d
;
1642 for (i
= 0; i
< n
; i
++)
1643 cb((struct detailed_timing
*)(det_base
+ 18 * i
), closure
);
1647 vtb_for_each_detailed_block(u8
*ext
, detailed_cb
*cb
, void *closure
)
1649 unsigned int i
, n
= min((int)ext
[0x02], 6);
1650 u8
*det_base
= ext
+ 5;
1653 return; /* unknown version */
1655 for (i
= 0; i
< n
; i
++)
1656 cb((struct detailed_timing
*)(det_base
+ 18 * i
), closure
);
1660 drm_for_each_detailed_block(u8
*raw_edid
, detailed_cb
*cb
, void *closure
)
1663 struct edid
*edid
= (struct edid
*)raw_edid
;
1668 for (i
= 0; i
< EDID_DETAILED_TIMINGS
; i
++)
1669 cb(&(edid
->detailed_timings
[i
]), closure
);
1671 for (i
= 1; i
<= raw_edid
[0x7e]; i
++) {
1672 u8
*ext
= raw_edid
+ (i
* EDID_LENGTH
);
1675 cea_for_each_detailed_block(ext
, cb
, closure
);
1678 vtb_for_each_detailed_block(ext
, cb
, closure
);
1687 is_rb(struct detailed_timing
*t
, void *data
)
1690 if (r
[3] == EDID_DETAIL_MONITOR_RANGE
)
1692 *(bool *)data
= true;
1695 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1697 drm_monitor_supports_rb(struct edid
*edid
)
1699 if (edid
->revision
>= 4) {
1701 drm_for_each_detailed_block((u8
*)edid
, is_rb
, &ret
);
1705 return ((edid
->input
& DRM_EDID_INPUT_DIGITAL
) != 0);
1709 find_gtf2(struct detailed_timing
*t
, void *data
)
1712 if (r
[3] == EDID_DETAIL_MONITOR_RANGE
&& r
[10] == 0x02)
1716 /* Secondary GTF curve kicks in above some break frequency */
1718 drm_gtf2_hbreak(struct edid
*edid
)
1721 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
1722 return r
? (r
[12] * 2) : 0;
1726 drm_gtf2_2c(struct edid
*edid
)
1729 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
1730 return r
? r
[13] : 0;
1734 drm_gtf2_m(struct edid
*edid
)
1737 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
1738 return r
? (r
[15] << 8) + r
[14] : 0;
1742 drm_gtf2_k(struct edid
*edid
)
1745 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
1746 return r
? r
[16] : 0;
1750 drm_gtf2_2j(struct edid
*edid
)
1753 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
1754 return r
? r
[17] : 0;
1758 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1759 * @edid: EDID block to scan
1761 static int standard_timing_level(struct edid
*edid
)
1763 if (edid
->revision
>= 2) {
1764 if (edid
->revision
>= 4 && (edid
->features
& DRM_EDID_FEATURE_DEFAULT_GTF
))
1766 if (drm_gtf2_hbreak(edid
))
1774 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1775 * monitors fill with ascii space (0x20) instead.
1778 bad_std_timing(u8 a
, u8 b
)
1780 return (a
== 0x00 && b
== 0x00) ||
1781 (a
== 0x01 && b
== 0x01) ||
1782 (a
== 0x20 && b
== 0x20);
1786 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1787 * @connector: connector of for the EDID block
1788 * @edid: EDID block to scan
1789 * @t: standard timing params
1791 * Take the standard timing params (in this case width, aspect, and refresh)
1792 * and convert them into a real mode using CVT/GTF/DMT.
1794 static struct drm_display_mode
*
1795 drm_mode_std(struct drm_connector
*connector
, struct edid
*edid
,
1796 struct std_timing
*t
)
1798 struct drm_device
*dev
= connector
->dev
;
1799 struct drm_display_mode
*m
, *mode
= NULL
;
1802 unsigned aspect_ratio
= (t
->vfreq_aspect
& EDID_TIMING_ASPECT_MASK
)
1803 >> EDID_TIMING_ASPECT_SHIFT
;
1804 unsigned vfreq
= (t
->vfreq_aspect
& EDID_TIMING_VFREQ_MASK
)
1805 >> EDID_TIMING_VFREQ_SHIFT
;
1806 int timing_level
= standard_timing_level(edid
);
1808 if (bad_std_timing(t
->hsize
, t
->vfreq_aspect
))
1811 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1812 hsize
= t
->hsize
* 8 + 248;
1813 /* vrefresh_rate = vfreq + 60 */
1814 vrefresh_rate
= vfreq
+ 60;
1815 /* the vdisplay is calculated based on the aspect ratio */
1816 if (aspect_ratio
== 0) {
1817 if (edid
->revision
< 3)
1820 vsize
= (hsize
* 10) / 16;
1821 } else if (aspect_ratio
== 1)
1822 vsize
= (hsize
* 3) / 4;
1823 else if (aspect_ratio
== 2)
1824 vsize
= (hsize
* 4) / 5;
1826 vsize
= (hsize
* 9) / 16;
1828 /* HDTV hack, part 1 */
1829 if (vrefresh_rate
== 60 &&
1830 ((hsize
== 1360 && vsize
== 765) ||
1831 (hsize
== 1368 && vsize
== 769))) {
1837 * If this connector already has a mode for this size and refresh
1838 * rate (because it came from detailed or CVT info), use that
1839 * instead. This way we don't have to guess at interlace or
1842 list_for_each_entry(m
, &connector
->probed_modes
, head
)
1843 if (m
->hdisplay
== hsize
&& m
->vdisplay
== vsize
&&
1844 drm_mode_vrefresh(m
) == vrefresh_rate
)
1847 /* HDTV hack, part 2 */
1848 if (hsize
== 1366 && vsize
== 768 && vrefresh_rate
== 60) {
1849 mode
= drm_cvt_mode(dev
, 1366, 768, vrefresh_rate
, 0, 0,
1851 mode
->hdisplay
= 1366;
1852 mode
->hsync_start
= mode
->hsync_start
- 1;
1853 mode
->hsync_end
= mode
->hsync_end
- 1;
1857 /* check whether it can be found in default mode table */
1858 if (drm_monitor_supports_rb(edid
)) {
1859 mode
= drm_mode_find_dmt(dev
, hsize
, vsize
, vrefresh_rate
,
1864 mode
= drm_mode_find_dmt(dev
, hsize
, vsize
, vrefresh_rate
, false);
1868 /* okay, generate it */
1869 switch (timing_level
) {
1873 mode
= drm_gtf_mode(dev
, hsize
, vsize
, vrefresh_rate
, 0, 0);
1877 * This is potentially wrong if there's ever a monitor with
1878 * more than one ranges section, each claiming a different
1879 * secondary GTF curve. Please don't do that.
1881 mode
= drm_gtf_mode(dev
, hsize
, vsize
, vrefresh_rate
, 0, 0);
1884 if (drm_mode_hsync(mode
) > drm_gtf2_hbreak(edid
)) {
1885 drm_mode_destroy(dev
, mode
);
1886 mode
= drm_gtf_mode_complex(dev
, hsize
, vsize
,
1887 vrefresh_rate
, 0, 0,
1895 mode
= drm_cvt_mode(dev
, hsize
, vsize
, vrefresh_rate
, 0, 0,
1903 * EDID is delightfully ambiguous about how interlaced modes are to be
1904 * encoded. Our internal representation is of frame height, but some
1905 * HDTV detailed timings are encoded as field height.
1907 * The format list here is from CEA, in frame size. Technically we
1908 * should be checking refresh rate too. Whatever.
1911 drm_mode_do_interlace_quirk(struct drm_display_mode
*mode
,
1912 struct detailed_pixel_timing
*pt
)
1915 static const struct {
1917 } cea_interlaced
[] = {
1927 if (!(pt
->misc
& DRM_EDID_PT_INTERLACED
))
1930 for (i
= 0; i
< ARRAY_SIZE(cea_interlaced
); i
++) {
1931 if ((mode
->hdisplay
== cea_interlaced
[i
].w
) &&
1932 (mode
->vdisplay
== cea_interlaced
[i
].h
/ 2)) {
1933 mode
->vdisplay
*= 2;
1934 mode
->vsync_start
*= 2;
1935 mode
->vsync_end
*= 2;
1941 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1945 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1946 * @dev: DRM device (needed to create new mode)
1948 * @timing: EDID detailed timing info
1949 * @quirks: quirks to apply
1951 * An EDID detailed timing block contains enough info for us to create and
1952 * return a new struct drm_display_mode.
1954 static struct drm_display_mode
*drm_mode_detailed(struct drm_device
*dev
,
1956 struct detailed_timing
*timing
,
1959 struct drm_display_mode
*mode
;
1960 struct detailed_pixel_timing
*pt
= &timing
->data
.pixel_data
;
1961 unsigned hactive
= (pt
->hactive_hblank_hi
& 0xf0) << 4 | pt
->hactive_lo
;
1962 unsigned vactive
= (pt
->vactive_vblank_hi
& 0xf0) << 4 | pt
->vactive_lo
;
1963 unsigned hblank
= (pt
->hactive_hblank_hi
& 0xf) << 8 | pt
->hblank_lo
;
1964 unsigned vblank
= (pt
->vactive_vblank_hi
& 0xf) << 8 | pt
->vblank_lo
;
1965 unsigned hsync_offset
= (pt
->hsync_vsync_offset_pulse_width_hi
& 0xc0) << 2 | pt
->hsync_offset_lo
;
1966 unsigned hsync_pulse_width
= (pt
->hsync_vsync_offset_pulse_width_hi
& 0x30) << 4 | pt
->hsync_pulse_width_lo
;
1967 unsigned vsync_offset
= (pt
->hsync_vsync_offset_pulse_width_hi
& 0xc) << 2 | pt
->vsync_offset_pulse_width_lo
>> 4;
1968 unsigned vsync_pulse_width
= (pt
->hsync_vsync_offset_pulse_width_hi
& 0x3) << 4 | (pt
->vsync_offset_pulse_width_lo
& 0xf);
1970 /* ignore tiny modes */
1971 if (hactive
< 64 || vactive
< 64)
1974 if (pt
->misc
& DRM_EDID_PT_STEREO
) {
1975 DRM_DEBUG_KMS("stereo mode not supported\n");
1978 if (!(pt
->misc
& DRM_EDID_PT_SEPARATE_SYNC
)) {
1979 DRM_DEBUG_KMS("composite sync not supported\n");
1982 /* it is incorrect if hsync/vsync width is zero */
1983 if (!hsync_pulse_width
|| !vsync_pulse_width
) {
1984 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1985 "Wrong Hsync/Vsync pulse width\n");
1989 if (quirks
& EDID_QUIRK_FORCE_REDUCED_BLANKING
) {
1990 mode
= drm_cvt_mode(dev
, hactive
, vactive
, 60, true, false, false);
1997 mode
= drm_mode_create(dev
);
2001 if (quirks
& EDID_QUIRK_135_CLOCK_TOO_HIGH
)
2002 timing
->pixel_clock
= cpu_to_le16(1088);
2004 mode
->clock
= le16_to_cpu(timing
->pixel_clock
) * 10;
2006 mode
->hdisplay
= hactive
;
2007 mode
->hsync_start
= mode
->hdisplay
+ hsync_offset
;
2008 mode
->hsync_end
= mode
->hsync_start
+ hsync_pulse_width
;
2009 mode
->htotal
= mode
->hdisplay
+ hblank
;
2011 mode
->vdisplay
= vactive
;
2012 mode
->vsync_start
= mode
->vdisplay
+ vsync_offset
;
2013 mode
->vsync_end
= mode
->vsync_start
+ vsync_pulse_width
;
2014 mode
->vtotal
= mode
->vdisplay
+ vblank
;
2016 /* Some EDIDs have bogus h/vtotal values */
2017 if (mode
->hsync_end
> mode
->htotal
)
2018 mode
->htotal
= mode
->hsync_end
+ 1;
2019 if (mode
->vsync_end
> mode
->vtotal
)
2020 mode
->vtotal
= mode
->vsync_end
+ 1;
2022 drm_mode_do_interlace_quirk(mode
, pt
);
2024 if (quirks
& EDID_QUIRK_DETAILED_SYNC_PP
) {
2025 pt
->misc
|= DRM_EDID_PT_HSYNC_POSITIVE
| DRM_EDID_PT_VSYNC_POSITIVE
;
2028 mode
->flags
|= (pt
->misc
& DRM_EDID_PT_HSYNC_POSITIVE
) ?
2029 DRM_MODE_FLAG_PHSYNC
: DRM_MODE_FLAG_NHSYNC
;
2030 mode
->flags
|= (pt
->misc
& DRM_EDID_PT_VSYNC_POSITIVE
) ?
2031 DRM_MODE_FLAG_PVSYNC
: DRM_MODE_FLAG_NVSYNC
;
2034 mode
->width_mm
= pt
->width_mm_lo
| (pt
->width_height_mm_hi
& 0xf0) << 4;
2035 mode
->height_mm
= pt
->height_mm_lo
| (pt
->width_height_mm_hi
& 0xf) << 8;
2037 if (quirks
& EDID_QUIRK_DETAILED_IN_CM
) {
2038 mode
->width_mm
*= 10;
2039 mode
->height_mm
*= 10;
2042 if (quirks
& EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE
) {
2043 mode
->width_mm
= edid
->width_cm
* 10;
2044 mode
->height_mm
= edid
->height_cm
* 10;
2047 mode
->type
= DRM_MODE_TYPE_DRIVER
;
2048 mode
->vrefresh
= drm_mode_vrefresh(mode
);
2049 drm_mode_set_name(mode
);
2055 mode_in_hsync_range(const struct drm_display_mode
*mode
,
2056 struct edid
*edid
, u8
*t
)
2058 int hsync
, hmin
, hmax
;
2061 if (edid
->revision
>= 4)
2062 hmin
+= ((t
[4] & 0x04) ? 255 : 0);
2064 if (edid
->revision
>= 4)
2065 hmax
+= ((t
[4] & 0x08) ? 255 : 0);
2066 hsync
= drm_mode_hsync(mode
);
2068 return (hsync
<= hmax
&& hsync
>= hmin
);
2072 mode_in_vsync_range(const struct drm_display_mode
*mode
,
2073 struct edid
*edid
, u8
*t
)
2075 int vsync
, vmin
, vmax
;
2078 if (edid
->revision
>= 4)
2079 vmin
+= ((t
[4] & 0x01) ? 255 : 0);
2081 if (edid
->revision
>= 4)
2082 vmax
+= ((t
[4] & 0x02) ? 255 : 0);
2083 vsync
= drm_mode_vrefresh(mode
);
2085 return (vsync
<= vmax
&& vsync
>= vmin
);
2089 range_pixel_clock(struct edid
*edid
, u8
*t
)
2092 if (t
[9] == 0 || t
[9] == 255)
2095 /* 1.4 with CVT support gives us real precision, yay */
2096 if (edid
->revision
>= 4 && t
[10] == 0x04)
2097 return (t
[9] * 10000) - ((t
[12] >> 2) * 250);
2099 /* 1.3 is pathetic, so fuzz up a bit */
2100 return t
[9] * 10000 + 5001;
2104 mode_in_range(const struct drm_display_mode
*mode
, struct edid
*edid
,
2105 struct detailed_timing
*timing
)
2108 u8
*t
= (u8
*)timing
;
2110 if (!mode_in_hsync_range(mode
, edid
, t
))
2113 if (!mode_in_vsync_range(mode
, edid
, t
))
2116 if ((max_clock
= range_pixel_clock(edid
, t
)))
2117 if (mode
->clock
> max_clock
)
2120 /* 1.4 max horizontal check */
2121 if (edid
->revision
>= 4 && t
[10] == 0x04)
2122 if (t
[13] && mode
->hdisplay
> 8 * (t
[13] + (256 * (t
[12]&0x3))))
2125 if (mode_is_rb(mode
) && !drm_monitor_supports_rb(edid
))
2131 static bool valid_inferred_mode(const struct drm_connector
*connector
,
2132 const struct drm_display_mode
*mode
)
2134 const struct drm_display_mode
*m
;
2137 list_for_each_entry(m
, &connector
->probed_modes
, head
) {
2138 if (mode
->hdisplay
== m
->hdisplay
&&
2139 mode
->vdisplay
== m
->vdisplay
&&
2140 drm_mode_vrefresh(mode
) == drm_mode_vrefresh(m
))
2141 return false; /* duplicated */
2142 if (mode
->hdisplay
<= m
->hdisplay
&&
2143 mode
->vdisplay
<= m
->vdisplay
)
2150 drm_dmt_modes_for_range(struct drm_connector
*connector
, struct edid
*edid
,
2151 struct detailed_timing
*timing
)
2154 struct drm_display_mode
*newmode
;
2155 struct drm_device
*dev
= connector
->dev
;
2157 for (i
= 0; i
< ARRAY_SIZE(drm_dmt_modes
); i
++) {
2158 if (mode_in_range(drm_dmt_modes
+ i
, edid
, timing
) &&
2159 valid_inferred_mode(connector
, drm_dmt_modes
+ i
)) {
2160 newmode
= drm_mode_duplicate(dev
, &drm_dmt_modes
[i
]);
2162 drm_mode_probed_add(connector
, newmode
);
2171 /* fix up 1366x768 mode from 1368x768;
2172 * GFT/CVT can't express 1366 width which isn't dividable by 8
2174 void drm_mode_fixup_1366x768(struct drm_display_mode
*mode
)
2176 if (mode
->hdisplay
== 1368 && mode
->vdisplay
== 768) {
2177 mode
->hdisplay
= 1366;
2178 mode
->hsync_start
--;
2180 drm_mode_set_name(mode
);
2185 drm_gtf_modes_for_range(struct drm_connector
*connector
, struct edid
*edid
,
2186 struct detailed_timing
*timing
)
2189 struct drm_display_mode
*newmode
;
2190 struct drm_device
*dev
= connector
->dev
;
2192 for (i
= 0; i
< ARRAY_SIZE(extra_modes
); i
++) {
2193 const struct minimode
*m
= &extra_modes
[i
];
2194 newmode
= drm_gtf_mode(dev
, m
->w
, m
->h
, m
->r
, 0, 0);
2198 drm_mode_fixup_1366x768(newmode
);
2199 if (!mode_in_range(newmode
, edid
, timing
) ||
2200 !valid_inferred_mode(connector
, newmode
)) {
2201 drm_mode_destroy(dev
, newmode
);
2205 drm_mode_probed_add(connector
, newmode
);
2213 drm_cvt_modes_for_range(struct drm_connector
*connector
, struct edid
*edid
,
2214 struct detailed_timing
*timing
)
2217 struct drm_display_mode
*newmode
;
2218 struct drm_device
*dev
= connector
->dev
;
2219 bool rb
= drm_monitor_supports_rb(edid
);
2221 for (i
= 0; i
< ARRAY_SIZE(extra_modes
); i
++) {
2222 const struct minimode
*m
= &extra_modes
[i
];
2223 newmode
= drm_cvt_mode(dev
, m
->w
, m
->h
, m
->r
, rb
, 0, 0);
2227 drm_mode_fixup_1366x768(newmode
);
2228 if (!mode_in_range(newmode
, edid
, timing
) ||
2229 !valid_inferred_mode(connector
, newmode
)) {
2230 drm_mode_destroy(dev
, newmode
);
2234 drm_mode_probed_add(connector
, newmode
);
2242 do_inferred_modes(struct detailed_timing
*timing
, void *c
)
2244 struct detailed_mode_closure
*closure
= c
;
2245 struct detailed_non_pixel
*data
= &timing
->data
.other_data
;
2246 struct detailed_data_monitor_range
*range
= &data
->data
.range
;
2248 if (data
->type
!= EDID_DETAIL_MONITOR_RANGE
)
2251 closure
->modes
+= drm_dmt_modes_for_range(closure
->connector
,
2255 if (!version_greater(closure
->edid
, 1, 1))
2256 return; /* GTF not defined yet */
2258 switch (range
->flags
) {
2259 case 0x02: /* secondary gtf, XXX could do more */
2260 case 0x00: /* default gtf */
2261 closure
->modes
+= drm_gtf_modes_for_range(closure
->connector
,
2265 case 0x04: /* cvt, only in 1.4+ */
2266 if (!version_greater(closure
->edid
, 1, 3))
2269 closure
->modes
+= drm_cvt_modes_for_range(closure
->connector
,
2273 case 0x01: /* just the ranges, no formula */
2280 add_inferred_modes(struct drm_connector
*connector
, struct edid
*edid
)
2282 struct detailed_mode_closure closure
= {
2283 .connector
= connector
,
2287 if (version_greater(edid
, 1, 0))
2288 drm_for_each_detailed_block((u8
*)edid
, do_inferred_modes
,
2291 return closure
.modes
;
2295 drm_est3_modes(struct drm_connector
*connector
, struct detailed_timing
*timing
)
2297 int i
, j
, m
, modes
= 0;
2298 struct drm_display_mode
*mode
;
2299 u8
*est
= ((u8
*)timing
) + 6;
2301 for (i
= 0; i
< 6; i
++) {
2302 for (j
= 7; j
>= 0; j
--) {
2303 m
= (i
* 8) + (7 - j
);
2304 if (m
>= ARRAY_SIZE(est3_modes
))
2306 if (est
[i
] & (1 << j
)) {
2307 mode
= drm_mode_find_dmt(connector
->dev
,
2313 drm_mode_probed_add(connector
, mode
);
2324 do_established_modes(struct detailed_timing
*timing
, void *c
)
2326 struct detailed_mode_closure
*closure
= c
;
2327 struct detailed_non_pixel
*data
= &timing
->data
.other_data
;
2329 if (data
->type
== EDID_DETAIL_EST_TIMINGS
)
2330 closure
->modes
+= drm_est3_modes(closure
->connector
, timing
);
2334 * add_established_modes - get est. modes from EDID and add them
2335 * @connector: connector to add mode(s) to
2336 * @edid: EDID block to scan
2338 * Each EDID block contains a bitmap of the supported "established modes" list
2339 * (defined above). Tease them out and add them to the global modes list.
2342 add_established_modes(struct drm_connector
*connector
, struct edid
*edid
)
2344 struct drm_device
*dev
= connector
->dev
;
2345 unsigned long est_bits
= edid
->established_timings
.t1
|
2346 (edid
->established_timings
.t2
<< 8) |
2347 ((edid
->established_timings
.mfg_rsvd
& 0x80) << 9);
2349 struct detailed_mode_closure closure
= {
2350 .connector
= connector
,
2354 for (i
= 0; i
<= EDID_EST_TIMINGS
; i
++) {
2355 if (est_bits
& (1<<i
)) {
2356 struct drm_display_mode
*newmode
;
2357 newmode
= drm_mode_duplicate(dev
, &edid_est_modes
[i
]);
2359 drm_mode_probed_add(connector
, newmode
);
2365 if (version_greater(edid
, 1, 0))
2366 drm_for_each_detailed_block((u8
*)edid
,
2367 do_established_modes
, &closure
);
2369 return modes
+ closure
.modes
;
2373 do_standard_modes(struct detailed_timing
*timing
, void *c
)
2375 struct detailed_mode_closure
*closure
= c
;
2376 struct detailed_non_pixel
*data
= &timing
->data
.other_data
;
2377 struct drm_connector
*connector
= closure
->connector
;
2378 struct edid
*edid
= closure
->edid
;
2380 if (data
->type
== EDID_DETAIL_STD_MODES
) {
2382 for (i
= 0; i
< 6; i
++) {
2383 struct std_timing
*std
;
2384 struct drm_display_mode
*newmode
;
2386 std
= &data
->data
.timings
[i
];
2387 newmode
= drm_mode_std(connector
, edid
, std
);
2389 drm_mode_probed_add(connector
, newmode
);
2397 * add_standard_modes - get std. modes from EDID and add them
2398 * @connector: connector to add mode(s) to
2399 * @edid: EDID block to scan
2401 * Standard modes can be calculated using the appropriate standard (DMT,
2402 * GTF or CVT. Grab them from @edid and add them to the list.
2405 add_standard_modes(struct drm_connector
*connector
, struct edid
*edid
)
2408 struct detailed_mode_closure closure
= {
2409 .connector
= connector
,
2413 for (i
= 0; i
< EDID_STD_TIMINGS
; i
++) {
2414 struct drm_display_mode
*newmode
;
2416 newmode
= drm_mode_std(connector
, edid
,
2417 &edid
->standard_timings
[i
]);
2419 drm_mode_probed_add(connector
, newmode
);
2424 if (version_greater(edid
, 1, 0))
2425 drm_for_each_detailed_block((u8
*)edid
, do_standard_modes
,
2428 /* XXX should also look for standard codes in VTB blocks */
2430 return modes
+ closure
.modes
;
2433 static int drm_cvt_modes(struct drm_connector
*connector
,
2434 struct detailed_timing
*timing
)
2436 int i
, j
, modes
= 0;
2437 struct drm_display_mode
*newmode
;
2438 struct drm_device
*dev
= connector
->dev
;
2439 struct cvt_timing
*cvt
;
2440 const int rates
[] = { 60, 85, 75, 60, 50 };
2441 const u8 empty
[3] = { 0, 0, 0 };
2443 for (i
= 0; i
< 4; i
++) {
2444 int uninitialized_var(width
), height
;
2445 cvt
= &(timing
->data
.other_data
.data
.cvt
[i
]);
2447 if (!memcmp(cvt
->code
, empty
, 3))
2450 height
= (cvt
->code
[0] + ((cvt
->code
[1] & 0xf0) << 4) + 1) * 2;
2451 switch (cvt
->code
[1] & 0x0c) {
2453 width
= height
* 4 / 3;
2456 width
= height
* 16 / 9;
2459 width
= height
* 16 / 10;
2462 width
= height
* 15 / 9;
2466 for (j
= 1; j
< 5; j
++) {
2467 if (cvt
->code
[2] & (1 << j
)) {
2468 newmode
= drm_cvt_mode(dev
, width
, height
,
2472 drm_mode_probed_add(connector
, newmode
);
2483 do_cvt_mode(struct detailed_timing
*timing
, void *c
)
2485 struct detailed_mode_closure
*closure
= c
;
2486 struct detailed_non_pixel
*data
= &timing
->data
.other_data
;
2488 if (data
->type
== EDID_DETAIL_CVT_3BYTE
)
2489 closure
->modes
+= drm_cvt_modes(closure
->connector
, timing
);
2493 add_cvt_modes(struct drm_connector
*connector
, struct edid
*edid
)
2495 struct detailed_mode_closure closure
= {
2496 .connector
= connector
,
2500 if (version_greater(edid
, 1, 2))
2501 drm_for_each_detailed_block((u8
*)edid
, do_cvt_mode
, &closure
);
2503 /* XXX should also look for CVT codes in VTB blocks */
2505 return closure
.modes
;
2508 static void fixup_detailed_cea_mode_clock(struct drm_display_mode
*mode
);
2511 do_detailed_mode(struct detailed_timing
*timing
, void *c
)
2513 struct detailed_mode_closure
*closure
= c
;
2514 struct drm_display_mode
*newmode
;
2516 if (timing
->pixel_clock
) {
2517 newmode
= drm_mode_detailed(closure
->connector
->dev
,
2518 closure
->edid
, timing
,
2523 if (closure
->preferred
)
2524 newmode
->type
|= DRM_MODE_TYPE_PREFERRED
;
2527 * Detailed modes are limited to 10kHz pixel clock resolution,
2528 * so fix up anything that looks like CEA/HDMI mode, but the clock
2529 * is just slightly off.
2531 fixup_detailed_cea_mode_clock(newmode
);
2533 drm_mode_probed_add(closure
->connector
, newmode
);
2535 closure
->preferred
= 0;
2540 * add_detailed_modes - Add modes from detailed timings
2541 * @connector: attached connector
2542 * @edid: EDID block to scan
2543 * @quirks: quirks to apply
2546 add_detailed_modes(struct drm_connector
*connector
, struct edid
*edid
,
2549 struct detailed_mode_closure closure
= {
2550 .connector
= connector
,
2556 if (closure
.preferred
&& !version_greater(edid
, 1, 3))
2558 (edid
->features
& DRM_EDID_FEATURE_PREFERRED_TIMING
);
2560 drm_for_each_detailed_block((u8
*)edid
, do_detailed_mode
, &closure
);
2562 return closure
.modes
;
2565 #define AUDIO_BLOCK 0x01
2566 #define VIDEO_BLOCK 0x02
2567 #define VENDOR_BLOCK 0x03
2568 #define SPEAKER_BLOCK 0x04
2569 #define VIDEO_CAPABILITY_BLOCK 0x07
2570 #define EDID_BASIC_AUDIO (1 << 6)
2571 #define EDID_CEA_YCRCB444 (1 << 5)
2572 #define EDID_CEA_YCRCB422 (1 << 4)
2573 #define EDID_CEA_VCDB_QS (1 << 6)
2576 * Search EDID for CEA extension block.
2578 static u8
*drm_find_edid_extension(struct edid
*edid
, int ext_id
)
2580 u8
*edid_ext
= NULL
;
2583 /* No EDID or EDID extensions */
2584 if (edid
== NULL
|| edid
->extensions
== 0)
2587 /* Find CEA extension */
2588 for (i
= 0; i
< edid
->extensions
; i
++) {
2589 edid_ext
= (u8
*)edid
+ EDID_LENGTH
* (i
+ 1);
2590 if (edid_ext
[0] == ext_id
)
2594 if (i
== edid
->extensions
)
2600 static u8
*drm_find_cea_extension(struct edid
*edid
)
2602 return drm_find_edid_extension(edid
, CEA_EXT
);
2605 static u8
*drm_find_displayid_extension(struct edid
*edid
)
2607 return drm_find_edid_extension(edid
, DISPLAYID_EXT
);
2611 * Calculate the alternate clock for the CEA mode
2612 * (60Hz vs. 59.94Hz etc.)
2615 cea_mode_alternate_clock(const struct drm_display_mode
*cea_mode
)
2617 unsigned int clock
= cea_mode
->clock
;
2619 if (cea_mode
->vrefresh
% 6 != 0)
2623 * edid_cea_modes contains the 59.94Hz
2624 * variant for 240 and 480 line modes,
2625 * and the 60Hz variant otherwise.
2627 if (cea_mode
->vdisplay
== 240 || cea_mode
->vdisplay
== 480)
2628 clock
= DIV_ROUND_CLOSEST(clock
* 1001, 1000);
2630 clock
= DIV_ROUND_CLOSEST(clock
* 1000, 1001);
2636 cea_mode_alternate_timings(u8 vic
, struct drm_display_mode
*mode
)
2639 * For certain VICs the spec allows the vertical
2640 * front porch to vary by one or two lines.
2642 * cea_modes[] stores the variant with the shortest
2643 * vertical front porch. We can adjust the mode to
2644 * get the other variants by simply increasing the
2645 * vertical front porch length.
2647 BUILD_BUG_ON(edid_cea_modes
[8].vtotal
!= 262 ||
2648 edid_cea_modes
[9].vtotal
!= 262 ||
2649 edid_cea_modes
[12].vtotal
!= 262 ||
2650 edid_cea_modes
[13].vtotal
!= 262 ||
2651 edid_cea_modes
[23].vtotal
!= 312 ||
2652 edid_cea_modes
[24].vtotal
!= 312 ||
2653 edid_cea_modes
[27].vtotal
!= 312 ||
2654 edid_cea_modes
[28].vtotal
!= 312);
2656 if (((vic
== 8 || vic
== 9 ||
2657 vic
== 12 || vic
== 13) && mode
->vtotal
< 263) ||
2658 ((vic
== 23 || vic
== 24 ||
2659 vic
== 27 || vic
== 28) && mode
->vtotal
< 314)) {
2660 mode
->vsync_start
++;
2670 static u8
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode
*to_match
,
2671 unsigned int clock_tolerance
)
2675 if (!to_match
->clock
)
2678 for (vic
= 1; vic
< ARRAY_SIZE(edid_cea_modes
); vic
++) {
2679 struct drm_display_mode cea_mode
= edid_cea_modes
[vic
];
2680 unsigned int clock1
, clock2
;
2682 /* Check both 60Hz and 59.94Hz */
2683 clock1
= cea_mode
.clock
;
2684 clock2
= cea_mode_alternate_clock(&cea_mode
);
2686 if (abs(to_match
->clock
- clock1
) > clock_tolerance
&&
2687 abs(to_match
->clock
- clock2
) > clock_tolerance
)
2691 if (drm_mode_equal_no_clocks_no_stereo(to_match
, &cea_mode
))
2693 } while (cea_mode_alternate_timings(vic
, &cea_mode
));
2700 * drm_match_cea_mode - look for a CEA mode matching given mode
2701 * @to_match: display mode
2703 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2706 u8
drm_match_cea_mode(const struct drm_display_mode
*to_match
)
2710 if (!to_match
->clock
)
2713 for (vic
= 1; vic
< ARRAY_SIZE(edid_cea_modes
); vic
++) {
2714 struct drm_display_mode cea_mode
= edid_cea_modes
[vic
];
2715 unsigned int clock1
, clock2
;
2717 /* Check both 60Hz and 59.94Hz */
2718 clock1
= cea_mode
.clock
;
2719 clock2
= cea_mode_alternate_clock(&cea_mode
);
2721 if (KHZ2PICOS(to_match
->clock
) != KHZ2PICOS(clock1
) &&
2722 KHZ2PICOS(to_match
->clock
) != KHZ2PICOS(clock2
))
2726 if (drm_mode_equal_no_clocks_no_stereo(to_match
, &cea_mode
))
2728 } while (cea_mode_alternate_timings(vic
, &cea_mode
));
2733 EXPORT_SYMBOL(drm_match_cea_mode
);
2735 static bool drm_valid_cea_vic(u8 vic
)
2737 return vic
> 0 && vic
< ARRAY_SIZE(edid_cea_modes
);
2741 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2742 * the input VIC from the CEA mode list
2743 * @video_code: ID given to each of the CEA modes
2745 * Returns picture aspect ratio
2747 enum hdmi_picture_aspect
drm_get_cea_aspect_ratio(const u8 video_code
)
2749 return edid_cea_modes
[video_code
].picture_aspect_ratio
;
2751 EXPORT_SYMBOL(drm_get_cea_aspect_ratio
);
2754 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2757 * It's almost like cea_mode_alternate_clock(), we just need to add an
2758 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2762 hdmi_mode_alternate_clock(const struct drm_display_mode
*hdmi_mode
)
2764 if (hdmi_mode
->vdisplay
== 4096 && hdmi_mode
->hdisplay
== 2160)
2765 return hdmi_mode
->clock
;
2767 return cea_mode_alternate_clock(hdmi_mode
);
2770 static u8
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode
*to_match
,
2771 unsigned int clock_tolerance
)
2775 if (!to_match
->clock
)
2778 for (vic
= 1; vic
< ARRAY_SIZE(edid_4k_modes
); vic
++) {
2779 const struct drm_display_mode
*hdmi_mode
= &edid_4k_modes
[vic
];
2780 unsigned int clock1
, clock2
;
2782 /* Make sure to also match alternate clocks */
2783 clock1
= hdmi_mode
->clock
;
2784 clock2
= hdmi_mode_alternate_clock(hdmi_mode
);
2786 if (abs(to_match
->clock
- clock1
) > clock_tolerance
&&
2787 abs(to_match
->clock
- clock2
) > clock_tolerance
)
2790 if (drm_mode_equal_no_clocks(to_match
, hdmi_mode
))
2798 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2799 * @to_match: display mode
2801 * An HDMI mode is one defined in the HDMI vendor specific block.
2803 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2805 static u8
drm_match_hdmi_mode(const struct drm_display_mode
*to_match
)
2809 if (!to_match
->clock
)
2812 for (vic
= 1; vic
< ARRAY_SIZE(edid_4k_modes
); vic
++) {
2813 const struct drm_display_mode
*hdmi_mode
= &edid_4k_modes
[vic
];
2814 unsigned int clock1
, clock2
;
2816 /* Make sure to also match alternate clocks */
2817 clock1
= hdmi_mode
->clock
;
2818 clock2
= hdmi_mode_alternate_clock(hdmi_mode
);
2820 if ((KHZ2PICOS(to_match
->clock
) == KHZ2PICOS(clock1
) ||
2821 KHZ2PICOS(to_match
->clock
) == KHZ2PICOS(clock2
)) &&
2822 drm_mode_equal_no_clocks_no_stereo(to_match
, hdmi_mode
))
2828 static bool drm_valid_hdmi_vic(u8 vic
)
2830 return vic
> 0 && vic
< ARRAY_SIZE(edid_4k_modes
);
2834 add_alternate_cea_modes(struct drm_connector
*connector
, struct edid
*edid
)
2836 struct drm_device
*dev
= connector
->dev
;
2837 struct drm_display_mode
*mode
, *tmp
;
2841 /* Don't add CEA modes if the CEA extension block is missing */
2842 if (!drm_find_cea_extension(edid
))
2846 * Go through all probed modes and create a new mode
2847 * with the alternate clock for certain CEA modes.
2849 list_for_each_entry(mode
, &connector
->probed_modes
, head
) {
2850 const struct drm_display_mode
*cea_mode
= NULL
;
2851 struct drm_display_mode
*newmode
;
2852 u8 vic
= drm_match_cea_mode(mode
);
2853 unsigned int clock1
, clock2
;
2855 if (drm_valid_cea_vic(vic
)) {
2856 cea_mode
= &edid_cea_modes
[vic
];
2857 clock2
= cea_mode_alternate_clock(cea_mode
);
2859 vic
= drm_match_hdmi_mode(mode
);
2860 if (drm_valid_hdmi_vic(vic
)) {
2861 cea_mode
= &edid_4k_modes
[vic
];
2862 clock2
= hdmi_mode_alternate_clock(cea_mode
);
2869 clock1
= cea_mode
->clock
;
2871 if (clock1
== clock2
)
2874 if (mode
->clock
!= clock1
&& mode
->clock
!= clock2
)
2877 newmode
= drm_mode_duplicate(dev
, cea_mode
);
2881 /* Carry over the stereo flags */
2882 newmode
->flags
|= mode
->flags
& DRM_MODE_FLAG_3D_MASK
;
2885 * The current mode could be either variant. Make
2886 * sure to pick the "other" clock for the new mode.
2888 if (mode
->clock
!= clock1
)
2889 newmode
->clock
= clock1
;
2891 newmode
->clock
= clock2
;
2893 list_add_tail(&newmode
->head
, &list
);
2896 list_for_each_entry_safe(mode
, tmp
, &list
, head
) {
2897 list_del(&mode
->head
);
2898 drm_mode_probed_add(connector
, mode
);
2905 static struct drm_display_mode
*
2906 drm_display_mode_from_vic_index(struct drm_connector
*connector
,
2907 const u8
*video_db
, u8 video_len
,
2910 struct drm_device
*dev
= connector
->dev
;
2911 struct drm_display_mode
*newmode
;
2914 if (video_db
== NULL
|| video_index
>= video_len
)
2917 /* CEA modes are numbered 1..127 */
2918 vic
= (video_db
[video_index
] & 127);
2919 if (!drm_valid_cea_vic(vic
))
2922 newmode
= drm_mode_duplicate(dev
, &edid_cea_modes
[vic
]);
2926 newmode
->vrefresh
= 0;
2932 do_cea_modes(struct drm_connector
*connector
, const u8
*db
, u8 len
)
2936 for (i
= 0; i
< len
; i
++) {
2937 struct drm_display_mode
*mode
;
2938 mode
= drm_display_mode_from_vic_index(connector
, db
, len
, i
);
2940 drm_mode_probed_add(connector
, mode
);
2948 struct stereo_mandatory_mode
{
2949 int width
, height
, vrefresh
;
2953 static const struct stereo_mandatory_mode stereo_mandatory_modes
[] = {
2954 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
},
2955 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING
},
2957 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
},
2959 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
},
2960 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
},
2961 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING
},
2962 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
},
2963 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING
}
2967 stereo_match_mandatory(const struct drm_display_mode
*mode
,
2968 const struct stereo_mandatory_mode
*stereo_mode
)
2970 unsigned int interlaced
= mode
->flags
& DRM_MODE_FLAG_INTERLACE
;
2972 return mode
->hdisplay
== stereo_mode
->width
&&
2973 mode
->vdisplay
== stereo_mode
->height
&&
2974 interlaced
== (stereo_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) &&
2975 drm_mode_vrefresh(mode
) == stereo_mode
->vrefresh
;
2978 static int add_hdmi_mandatory_stereo_modes(struct drm_connector
*connector
)
2980 struct drm_device
*dev
= connector
->dev
;
2981 const struct drm_display_mode
*mode
;
2982 struct list_head stereo_modes
;
2985 INIT_LIST_HEAD(&stereo_modes
);
2987 list_for_each_entry(mode
, &connector
->probed_modes
, head
) {
2988 for (i
= 0; i
< ARRAY_SIZE(stereo_mandatory_modes
); i
++) {
2989 const struct stereo_mandatory_mode
*mandatory
;
2990 struct drm_display_mode
*new_mode
;
2992 if (!stereo_match_mandatory(mode
,
2993 &stereo_mandatory_modes
[i
]))
2996 mandatory
= &stereo_mandatory_modes
[i
];
2997 new_mode
= drm_mode_duplicate(dev
, mode
);
3001 new_mode
->flags
|= mandatory
->flags
;
3002 list_add_tail(&new_mode
->head
, &stereo_modes
);
3007 list_splice_tail(&stereo_modes
, &connector
->probed_modes
);
3012 static int add_hdmi_mode(struct drm_connector
*connector
, u8 vic
)
3014 struct drm_device
*dev
= connector
->dev
;
3015 struct drm_display_mode
*newmode
;
3017 if (!drm_valid_hdmi_vic(vic
)) {
3018 DRM_ERROR("Unknown HDMI VIC: %d\n", vic
);
3022 newmode
= drm_mode_duplicate(dev
, &edid_4k_modes
[vic
]);
3026 drm_mode_probed_add(connector
, newmode
);
3031 static int add_3d_struct_modes(struct drm_connector
*connector
, u16 structure
,
3032 const u8
*video_db
, u8 video_len
, u8 video_index
)
3034 struct drm_display_mode
*newmode
;
3037 if (structure
& (1 << 0)) {
3038 newmode
= drm_display_mode_from_vic_index(connector
, video_db
,
3042 newmode
->flags
|= DRM_MODE_FLAG_3D_FRAME_PACKING
;
3043 drm_mode_probed_add(connector
, newmode
);
3047 if (structure
& (1 << 6)) {
3048 newmode
= drm_display_mode_from_vic_index(connector
, video_db
,
3052 newmode
->flags
|= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
;
3053 drm_mode_probed_add(connector
, newmode
);
3057 if (structure
& (1 << 8)) {
3058 newmode
= drm_display_mode_from_vic_index(connector
, video_db
,
3062 newmode
->flags
|= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
;
3063 drm_mode_probed_add(connector
, newmode
);
3072 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3073 * @connector: connector corresponding to the HDMI sink
3074 * @db: start of the CEA vendor specific block
3075 * @len: length of the CEA block payload, ie. one can access up to db[len]
3077 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3078 * also adds the stereo 3d modes when applicable.
3081 do_hdmi_vsdb_modes(struct drm_connector
*connector
, const u8
*db
, u8 len
,
3082 const u8
*video_db
, u8 video_len
)
3084 int modes
= 0, offset
= 0, i
, multi_present
= 0, multi_len
;
3085 u8 vic_len
, hdmi_3d_len
= 0;
3092 /* no HDMI_Video_Present */
3093 if (!(db
[8] & (1 << 5)))
3096 /* Latency_Fields_Present */
3097 if (db
[8] & (1 << 7))
3100 /* I_Latency_Fields_Present */
3101 if (db
[8] & (1 << 6))
3104 /* the declared length is not long enough for the 2 first bytes
3105 * of additional video format capabilities */
3106 if (len
< (8 + offset
+ 2))
3111 if (db
[8 + offset
] & (1 << 7)) {
3112 modes
+= add_hdmi_mandatory_stereo_modes(connector
);
3114 /* 3D_Multi_present */
3115 multi_present
= (db
[8 + offset
] & 0x60) >> 5;
3119 vic_len
= db
[8 + offset
] >> 5;
3120 hdmi_3d_len
= db
[8 + offset
] & 0x1f;
3122 for (i
= 0; i
< vic_len
&& len
>= (9 + offset
+ i
); i
++) {
3125 vic
= db
[9 + offset
+ i
];
3126 modes
+= add_hdmi_mode(connector
, vic
);
3128 offset
+= 1 + vic_len
;
3130 if (multi_present
== 1)
3132 else if (multi_present
== 2)
3137 if (len
< (8 + offset
+ hdmi_3d_len
- 1))
3140 if (hdmi_3d_len
< multi_len
)
3143 if (multi_present
== 1 || multi_present
== 2) {
3144 /* 3D_Structure_ALL */
3145 structure_all
= (db
[8 + offset
] << 8) | db
[9 + offset
];
3147 /* check if 3D_MASK is present */
3148 if (multi_present
== 2)
3149 mask
= (db
[10 + offset
] << 8) | db
[11 + offset
];
3153 for (i
= 0; i
< 16; i
++) {
3154 if (mask
& (1 << i
))
3155 modes
+= add_3d_struct_modes(connector
,
3162 offset
+= multi_len
;
3164 for (i
= 0; i
< (hdmi_3d_len
- multi_len
); i
++) {
3166 struct drm_display_mode
*newmode
= NULL
;
3167 unsigned int newflag
= 0;
3168 bool detail_present
;
3170 detail_present
= ((db
[8 + offset
+ i
] & 0x0f) > 7);
3172 if (detail_present
&& (i
+ 1 == hdmi_3d_len
- multi_len
))
3175 /* 2D_VIC_order_X */
3176 vic_index
= db
[8 + offset
+ i
] >> 4;
3178 /* 3D_Structure_X */
3179 switch (db
[8 + offset
+ i
] & 0x0f) {
3181 newflag
= DRM_MODE_FLAG_3D_FRAME_PACKING
;
3184 newflag
= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
;
3188 if ((db
[9 + offset
+ i
] >> 4) == 1)
3189 newflag
= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
;
3194 newmode
= drm_display_mode_from_vic_index(connector
,
3200 newmode
->flags
|= newflag
;
3201 drm_mode_probed_add(connector
, newmode
);
3215 cea_db_payload_len(const u8
*db
)
3217 return db
[0] & 0x1f;
3221 cea_db_tag(const u8
*db
)
3227 cea_revision(const u8
*cea
)
3233 cea_db_offsets(const u8
*cea
, int *start
, int *end
)
3235 /* Data block offset in CEA extension block */
3240 if (*end
< 4 || *end
> 127)
3245 static bool cea_db_is_hdmi_vsdb(const u8
*db
)
3249 if (cea_db_tag(db
) != VENDOR_BLOCK
)
3252 if (cea_db_payload_len(db
) < 5)
3255 hdmi_id
= db
[1] | (db
[2] << 8) | (db
[3] << 16);
3257 return hdmi_id
== HDMI_IEEE_OUI
;
3260 static bool cea_db_is_hdmi_forum_vsdb(const u8
*db
)
3264 if (cea_db_tag(db
) != VENDOR_BLOCK
)
3267 if (cea_db_payload_len(db
) < 7)
3270 oui
= db
[3] << 16 | db
[2] << 8 | db
[1];
3272 return oui
== HDMI_FORUM_IEEE_OUI
;
3275 #define for_each_cea_db(cea, i, start, end) \
3276 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3279 add_cea_modes(struct drm_connector
*connector
, struct edid
*edid
)
3281 const u8
*cea
= drm_find_cea_extension(edid
);
3282 const u8
*db
, *hdmi
= NULL
, *video
= NULL
;
3283 u8 dbl
, hdmi_len
, video_len
= 0;
3286 if (cea
&& cea_revision(cea
) >= 3) {
3289 if (cea_db_offsets(cea
, &start
, &end
))
3292 for_each_cea_db(cea
, i
, start
, end
) {
3294 dbl
= cea_db_payload_len(db
);
3296 if (cea_db_tag(db
) == VIDEO_BLOCK
) {
3299 modes
+= do_cea_modes(connector
, video
, dbl
);
3301 else if (cea_db_is_hdmi_vsdb(db
)) {
3309 * We parse the HDMI VSDB after having added the cea modes as we will
3310 * be patching their flags when the sink supports stereo 3D.
3313 modes
+= do_hdmi_vsdb_modes(connector
, hdmi
, hdmi_len
, video
,
3319 static void fixup_detailed_cea_mode_clock(struct drm_display_mode
*mode
)
3321 const struct drm_display_mode
*cea_mode
;
3322 int clock1
, clock2
, clock
;
3327 * allow 5kHz clock difference either way to account for
3328 * the 10kHz clock resolution limit of detailed timings.
3330 vic
= drm_match_cea_mode_clock_tolerance(mode
, 5);
3331 if (drm_valid_cea_vic(vic
)) {
3333 cea_mode
= &edid_cea_modes
[vic
];
3334 clock1
= cea_mode
->clock
;
3335 clock2
= cea_mode_alternate_clock(cea_mode
);
3337 vic
= drm_match_hdmi_mode_clock_tolerance(mode
, 5);
3338 if (drm_valid_hdmi_vic(vic
)) {
3340 cea_mode
= &edid_4k_modes
[vic
];
3341 clock1
= cea_mode
->clock
;
3342 clock2
= hdmi_mode_alternate_clock(cea_mode
);
3348 /* pick whichever is closest */
3349 if (abs(mode
->clock
- clock1
) < abs(mode
->clock
- clock2
))
3354 if (mode
->clock
== clock
)
3357 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3358 type
, vic
, mode
->clock
, clock
);
3359 mode
->clock
= clock
;
3363 drm_parse_hdmi_vsdb_audio(struct drm_connector
*connector
, const u8
*db
)
3365 u8 len
= cea_db_payload_len(db
);
3368 connector
->eld
[5] |= (db
[6] >> 7) << 1; /* Supports_AI */
3370 connector
->latency_present
[0] = db
[8] >> 7;
3371 connector
->latency_present
[1] = (db
[8] >> 6) & 1;
3374 connector
->video_latency
[0] = db
[9];
3376 connector
->audio_latency
[0] = db
[10];
3378 connector
->video_latency
[1] = db
[11];
3380 connector
->audio_latency
[1] = db
[12];
3382 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3383 "video latency %d %d, "
3384 "audio latency %d %d\n",
3385 connector
->latency_present
[0],
3386 connector
->latency_present
[1],
3387 connector
->video_latency
[0],
3388 connector
->video_latency
[1],
3389 connector
->audio_latency
[0],
3390 connector
->audio_latency
[1]);
3394 monitor_name(struct detailed_timing
*t
, void *data
)
3396 if (t
->data
.other_data
.type
== EDID_DETAIL_MONITOR_NAME
)
3397 *(u8
**)data
= t
->data
.other_data
.data
.str
.str
;
3400 static int get_monitor_name(struct edid
*edid
, char name
[13])
3402 char *edid_name
= NULL
;
3408 drm_for_each_detailed_block((u8
*)edid
, monitor_name
, &edid_name
);
3409 for (mnl
= 0; edid_name
&& mnl
< 13; mnl
++) {
3410 if (edid_name
[mnl
] == 0x0a)
3413 name
[mnl
] = edid_name
[mnl
];
3420 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3421 * @edid: monitor EDID information
3422 * @name: pointer to a character array to hold the name of the monitor
3423 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3426 void drm_edid_get_monitor_name(struct edid
*edid
, char *name
, int bufsize
)
3434 name_length
= min(get_monitor_name(edid
, buf
), bufsize
- 1);
3435 memcpy(name
, buf
, name_length
);
3436 name
[name_length
] = '\0';
3438 EXPORT_SYMBOL(drm_edid_get_monitor_name
);
3441 * drm_edid_to_eld - build ELD from EDID
3442 * @connector: connector corresponding to the HDMI/DP sink
3443 * @edid: EDID to parse
3445 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3446 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3449 void drm_edid_to_eld(struct drm_connector
*connector
, struct edid
*edid
)
3451 uint8_t *eld
= connector
->eld
;
3454 int total_sad_count
= 0;
3458 memset(eld
, 0, sizeof(connector
->eld
));
3460 connector
->latency_present
[0] = false;
3461 connector
->latency_present
[1] = false;
3462 connector
->video_latency
[0] = 0;
3463 connector
->audio_latency
[0] = 0;
3464 connector
->video_latency
[1] = 0;
3465 connector
->audio_latency
[1] = 0;
3470 cea
= drm_find_cea_extension(edid
);
3472 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3476 mnl
= get_monitor_name(edid
, eld
+ 20);
3478 eld
[4] = (cea
[1] << 5) | mnl
;
3479 DRM_DEBUG_KMS("ELD monitor %s\n", eld
+ 20);
3481 eld
[0] = 2 << 3; /* ELD version: 2 */
3483 eld
[16] = edid
->mfg_id
[0];
3484 eld
[17] = edid
->mfg_id
[1];
3485 eld
[18] = edid
->prod_code
[0];
3486 eld
[19] = edid
->prod_code
[1];
3488 if (cea_revision(cea
) >= 3) {
3491 if (cea_db_offsets(cea
, &start
, &end
)) {
3496 for_each_cea_db(cea
, i
, start
, end
) {
3498 dbl
= cea_db_payload_len(db
);
3500 switch (cea_db_tag(db
)) {
3504 /* Audio Data Block, contains SADs */
3505 sad_count
= min(dbl
/ 3, 15 - total_sad_count
);
3507 memcpy(eld
+ 20 + mnl
+ total_sad_count
* 3,
3508 &db
[1], sad_count
* 3);
3509 total_sad_count
+= sad_count
;
3512 /* Speaker Allocation Data Block */
3517 /* HDMI Vendor-Specific Data Block */
3518 if (cea_db_is_hdmi_vsdb(db
))
3519 drm_parse_hdmi_vsdb_audio(connector
, db
);
3526 eld
[5] |= total_sad_count
<< 4;
3528 eld
[DRM_ELD_BASELINE_ELD_LEN
] =
3529 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld
), 4);
3531 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3532 drm_eld_size(eld
), total_sad_count
);
3534 EXPORT_SYMBOL(drm_edid_to_eld
);
3537 * drm_edid_to_sad - extracts SADs from EDID
3538 * @edid: EDID to parse
3539 * @sads: pointer that will be set to the extracted SADs
3541 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3543 * Note: The returned pointer needs to be freed using kfree().
3545 * Return: The number of found SADs or negative number on error.
3547 int drm_edid_to_sad(struct edid
*edid
, struct cea_sad
**sads
)
3550 int i
, start
, end
, dbl
;
3553 cea
= drm_find_cea_extension(edid
);
3555 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3559 if (cea_revision(cea
) < 3) {
3560 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3564 if (cea_db_offsets(cea
, &start
, &end
)) {
3565 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3569 for_each_cea_db(cea
, i
, start
, end
) {
3572 if (cea_db_tag(db
) == AUDIO_BLOCK
) {
3574 dbl
= cea_db_payload_len(db
);
3576 count
= dbl
/ 3; /* SAD is 3B */
3577 *sads
= kcalloc(count
, sizeof(**sads
), GFP_KERNEL
);
3580 for (j
= 0; j
< count
; j
++) {
3581 u8
*sad
= &db
[1 + j
* 3];
3583 (*sads
)[j
].format
= (sad
[0] & 0x78) >> 3;
3584 (*sads
)[j
].channels
= sad
[0] & 0x7;
3585 (*sads
)[j
].freq
= sad
[1] & 0x7F;
3586 (*sads
)[j
].byte2
= sad
[2];
3594 EXPORT_SYMBOL(drm_edid_to_sad
);
3597 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3598 * @edid: EDID to parse
3599 * @sadb: pointer to the speaker block
3601 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3603 * Note: The returned pointer needs to be freed using kfree().
3605 * Return: The number of found Speaker Allocation Blocks or negative number on
3608 int drm_edid_to_speaker_allocation(struct edid
*edid
, u8
**sadb
)
3611 int i
, start
, end
, dbl
;
3614 cea
= drm_find_cea_extension(edid
);
3616 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3620 if (cea_revision(cea
) < 3) {
3621 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3625 if (cea_db_offsets(cea
, &start
, &end
)) {
3626 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3630 for_each_cea_db(cea
, i
, start
, end
) {
3631 const u8
*db
= &cea
[i
];
3633 if (cea_db_tag(db
) == SPEAKER_BLOCK
) {
3634 dbl
= cea_db_payload_len(db
);
3636 /* Speaker Allocation Data Block */
3638 *sadb
= kmemdup(&db
[1], dbl
, GFP_KERNEL
);
3649 EXPORT_SYMBOL(drm_edid_to_speaker_allocation
);
3652 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3653 * @connector: connector associated with the HDMI/DP sink
3654 * @mode: the display mode
3656 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3657 * the sink doesn't support audio or video.
3659 int drm_av_sync_delay(struct drm_connector
*connector
,
3660 const struct drm_display_mode
*mode
)
3662 int i
= !!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
);
3665 if (!connector
->latency_present
[0])
3667 if (!connector
->latency_present
[1])
3670 a
= connector
->audio_latency
[i
];
3671 v
= connector
->video_latency
[i
];
3674 * HDMI/DP sink doesn't support audio or video?
3676 if (a
== 255 || v
== 255)
3680 * Convert raw EDID values to millisecond.
3681 * Treat unknown latency as 0ms.
3684 a
= min(2 * (a
- 1), 500);
3686 v
= min(2 * (v
- 1), 500);
3688 return max(v
- a
, 0);
3690 EXPORT_SYMBOL(drm_av_sync_delay
);
3693 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3694 * @edid: monitor EDID information
3696 * Parse the CEA extension according to CEA-861-B.
3698 * Return: True if the monitor is HDMI, false if not or unknown.
3700 bool drm_detect_hdmi_monitor(struct edid
*edid
)
3704 int start_offset
, end_offset
;
3706 edid_ext
= drm_find_cea_extension(edid
);
3710 if (cea_db_offsets(edid_ext
, &start_offset
, &end_offset
))
3714 * Because HDMI identifier is in Vendor Specific Block,
3715 * search it from all data blocks of CEA extension.
3717 for_each_cea_db(edid_ext
, i
, start_offset
, end_offset
) {
3718 if (cea_db_is_hdmi_vsdb(&edid_ext
[i
]))
3724 EXPORT_SYMBOL(drm_detect_hdmi_monitor
);
3727 * drm_detect_monitor_audio - check monitor audio capability
3728 * @edid: EDID block to scan
3730 * Monitor should have CEA extension block.
3731 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3732 * audio' only. If there is any audio extension block and supported
3733 * audio format, assume at least 'basic audio' support, even if 'basic
3734 * audio' is not defined in EDID.
3736 * Return: True if the monitor supports audio, false otherwise.
3738 bool drm_detect_monitor_audio(struct edid
*edid
)
3742 bool has_audio
= false;
3743 int start_offset
, end_offset
;
3745 edid_ext
= drm_find_cea_extension(edid
);
3749 has_audio
= ((edid_ext
[3] & EDID_BASIC_AUDIO
) != 0);
3752 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3756 if (cea_db_offsets(edid_ext
, &start_offset
, &end_offset
))
3759 for_each_cea_db(edid_ext
, i
, start_offset
, end_offset
) {
3760 if (cea_db_tag(&edid_ext
[i
]) == AUDIO_BLOCK
) {
3762 for (j
= 1; j
< cea_db_payload_len(&edid_ext
[i
]) + 1; j
+= 3)
3763 DRM_DEBUG_KMS("CEA audio format %d\n",
3764 (edid_ext
[i
+ j
] >> 3) & 0xf);
3771 EXPORT_SYMBOL(drm_detect_monitor_audio
);
3774 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3775 * @edid: EDID block to scan
3777 * Check whether the monitor reports the RGB quantization range selection
3778 * as supported. The AVI infoframe can then be used to inform the monitor
3779 * which quantization range (full or limited) is used.
3781 * Return: True if the RGB quantization range is selectable, false otherwise.
3783 bool drm_rgb_quant_range_selectable(struct edid
*edid
)
3788 edid_ext
= drm_find_cea_extension(edid
);
3792 if (cea_db_offsets(edid_ext
, &start
, &end
))
3795 for_each_cea_db(edid_ext
, i
, start
, end
) {
3796 if (cea_db_tag(&edid_ext
[i
]) == VIDEO_CAPABILITY_BLOCK
&&
3797 cea_db_payload_len(&edid_ext
[i
]) == 2) {
3798 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext
[i
+ 2]);
3799 return edid_ext
[i
+ 2] & EDID_CEA_VCDB_QS
;
3805 EXPORT_SYMBOL(drm_rgb_quant_range_selectable
);
3808 * drm_default_rgb_quant_range - default RGB quantization range
3809 * @mode: display mode
3811 * Determine the default RGB quantization range for the mode,
3812 * as specified in CEA-861.
3814 * Return: The default RGB quantization range for the mode
3816 enum hdmi_quantization_range
3817 drm_default_rgb_quant_range(const struct drm_display_mode
*mode
)
3819 /* All CEA modes other than VIC 1 use limited quantization range. */
3820 return drm_match_cea_mode(mode
) > 1 ?
3821 HDMI_QUANTIZATION_RANGE_LIMITED
:
3822 HDMI_QUANTIZATION_RANGE_FULL
;
3824 EXPORT_SYMBOL(drm_default_rgb_quant_range
);
3826 static void drm_parse_hdmi_forum_vsdb(struct drm_connector
*connector
,
3829 struct drm_display_info
*display
= &connector
->display_info
;
3830 struct drm_hdmi_info
*hdmi
= &display
->hdmi
;
3832 if (hf_vsdb
[6] & 0x80) {
3833 hdmi
->scdc
.supported
= true;
3834 if (hf_vsdb
[6] & 0x40)
3835 hdmi
->scdc
.read_request
= true;
3839 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
3840 * And as per the spec, three factors confirm this:
3841 * * Availability of a HF-VSDB block in EDID (check)
3842 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
3843 * * SCDC support available (let's check)
3844 * Lets check it out.
3848 /* max clock is 5000 KHz times block value */
3849 u32 max_tmds_clock
= hf_vsdb
[5] * 5000;
3850 struct drm_scdc
*scdc
= &hdmi
->scdc
;
3852 if (max_tmds_clock
> 340000) {
3853 display
->max_tmds_clock
= max_tmds_clock
;
3854 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
3855 display
->max_tmds_clock
);
3858 if (scdc
->supported
) {
3859 scdc
->scrambling
.supported
= true;
3861 /* Few sinks support scrambling for cloks < 340M */
3862 if ((hf_vsdb
[6] & 0x8))
3863 scdc
->scrambling
.low_rates
= true;
3868 static void drm_parse_hdmi_deep_color_info(struct drm_connector
*connector
,
3871 struct drm_display_info
*info
= &connector
->display_info
;
3872 unsigned int dc_bpc
= 0;
3874 /* HDMI supports at least 8 bpc */
3877 if (cea_db_payload_len(hdmi
) < 6)
3880 if (hdmi
[6] & DRM_EDID_HDMI_DC_30
) {
3882 info
->edid_hdmi_dc_modes
|= DRM_EDID_HDMI_DC_30
;
3883 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3887 if (hdmi
[6] & DRM_EDID_HDMI_DC_36
) {
3889 info
->edid_hdmi_dc_modes
|= DRM_EDID_HDMI_DC_36
;
3890 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3894 if (hdmi
[6] & DRM_EDID_HDMI_DC_48
) {
3896 info
->edid_hdmi_dc_modes
|= DRM_EDID_HDMI_DC_48
;
3897 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3902 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3907 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3908 connector
->name
, dc_bpc
);
3912 * Deep color support mandates RGB444 support for all video
3913 * modes and forbids YCRCB422 support for all video modes per
3916 info
->color_formats
= DRM_COLOR_FORMAT_RGB444
;
3918 /* YCRCB444 is optional according to spec. */
3919 if (hdmi
[6] & DRM_EDID_HDMI_DC_Y444
) {
3920 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB444
;
3921 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3926 * Spec says that if any deep color mode is supported at all,
3927 * then deep color 36 bit must be supported.
3929 if (!(hdmi
[6] & DRM_EDID_HDMI_DC_36
)) {
3930 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3936 drm_parse_hdmi_vsdb_video(struct drm_connector
*connector
, const u8
*db
)
3938 struct drm_display_info
*info
= &connector
->display_info
;
3939 u8 len
= cea_db_payload_len(db
);
3942 info
->dvi_dual
= db
[6] & 1;
3944 info
->max_tmds_clock
= db
[7] * 5000;
3946 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3947 "max TMDS clock %d kHz\n",
3949 info
->max_tmds_clock
);
3951 drm_parse_hdmi_deep_color_info(connector
, db
);
3954 static void drm_parse_cea_ext(struct drm_connector
*connector
,
3957 struct drm_display_info
*info
= &connector
->display_info
;
3961 edid_ext
= drm_find_cea_extension(edid
);
3965 info
->cea_rev
= edid_ext
[1];
3967 /* The existence of a CEA block should imply RGB support */
3968 info
->color_formats
= DRM_COLOR_FORMAT_RGB444
;
3969 if (edid_ext
[3] & EDID_CEA_YCRCB444
)
3970 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB444
;
3971 if (edid_ext
[3] & EDID_CEA_YCRCB422
)
3972 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB422
;
3974 if (cea_db_offsets(edid_ext
, &start
, &end
))
3977 for_each_cea_db(edid_ext
, i
, start
, end
) {
3978 const u8
*db
= &edid_ext
[i
];
3980 if (cea_db_is_hdmi_vsdb(db
))
3981 drm_parse_hdmi_vsdb_video(connector
, db
);
3982 if (cea_db_is_hdmi_forum_vsdb(db
))
3983 drm_parse_hdmi_forum_vsdb(connector
, db
);
3987 static void drm_add_display_info(struct drm_connector
*connector
,
3990 struct drm_display_info
*info
= &connector
->display_info
;
3992 info
->width_mm
= edid
->width_cm
* 10;
3993 info
->height_mm
= edid
->height_cm
* 10;
3995 /* driver figures it out in this case */
3997 info
->color_formats
= 0;
3999 info
->max_tmds_clock
= 0;
4000 info
->dvi_dual
= false;
4002 if (edid
->revision
< 3)
4005 if (!(edid
->input
& DRM_EDID_INPUT_DIGITAL
))
4008 drm_parse_cea_ext(connector
, edid
);
4011 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4013 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4014 * tells us to assume 8 bpc color depth if the EDID doesn't have
4015 * extensions which tell otherwise.
4017 if ((info
->bpc
== 0) && (edid
->revision
< 4) &&
4018 (edid
->input
& DRM_EDID_DIGITAL_TYPE_DVI
)) {
4020 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4021 connector
->name
, info
->bpc
);
4024 /* Only defined for 1.4 with digital displays */
4025 if (edid
->revision
< 4)
4028 switch (edid
->input
& DRM_EDID_DIGITAL_DEPTH_MASK
) {
4029 case DRM_EDID_DIGITAL_DEPTH_6
:
4032 case DRM_EDID_DIGITAL_DEPTH_8
:
4035 case DRM_EDID_DIGITAL_DEPTH_10
:
4038 case DRM_EDID_DIGITAL_DEPTH_12
:
4041 case DRM_EDID_DIGITAL_DEPTH_14
:
4044 case DRM_EDID_DIGITAL_DEPTH_16
:
4047 case DRM_EDID_DIGITAL_DEPTH_UNDEF
:
4053 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4054 connector
->name
, info
->bpc
);
4056 info
->color_formats
|= DRM_COLOR_FORMAT_RGB444
;
4057 if (edid
->features
& DRM_EDID_FEATURE_RGB_YCRCB444
)
4058 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB444
;
4059 if (edid
->features
& DRM_EDID_FEATURE_RGB_YCRCB422
)
4060 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB422
;
4063 static int validate_displayid(u8
*displayid
, int length
, int idx
)
4067 struct displayid_hdr
*base
;
4069 base
= (struct displayid_hdr
*)&displayid
[idx
];
4071 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4072 base
->rev
, base
->bytes
, base
->prod_id
, base
->ext_count
);
4074 if (base
->bytes
+ 5 > length
- idx
)
4076 for (i
= idx
; i
<= base
->bytes
+ 5; i
++) {
4077 csum
+= displayid
[i
];
4080 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum
);
4086 static struct drm_display_mode
*drm_mode_displayid_detailed(struct drm_device
*dev
,
4087 struct displayid_detailed_timings_1
*timings
)
4089 struct drm_display_mode
*mode
;
4090 unsigned pixel_clock
= (timings
->pixel_clock
[0] |
4091 (timings
->pixel_clock
[1] << 8) |
4092 (timings
->pixel_clock
[2] << 16));
4093 unsigned hactive
= (timings
->hactive
[0] | timings
->hactive
[1] << 8) + 1;
4094 unsigned hblank
= (timings
->hblank
[0] | timings
->hblank
[1] << 8) + 1;
4095 unsigned hsync
= (timings
->hsync
[0] | (timings
->hsync
[1] & 0x7f) << 8) + 1;
4096 unsigned hsync_width
= (timings
->hsw
[0] | timings
->hsw
[1] << 8) + 1;
4097 unsigned vactive
= (timings
->vactive
[0] | timings
->vactive
[1] << 8) + 1;
4098 unsigned vblank
= (timings
->vblank
[0] | timings
->vblank
[1] << 8) + 1;
4099 unsigned vsync
= (timings
->vsync
[0] | (timings
->vsync
[1] & 0x7f) << 8) + 1;
4100 unsigned vsync_width
= (timings
->vsw
[0] | timings
->vsw
[1] << 8) + 1;
4101 bool hsync_positive
= (timings
->hsync
[1] >> 7) & 0x1;
4102 bool vsync_positive
= (timings
->vsync
[1] >> 7) & 0x1;
4103 mode
= drm_mode_create(dev
);
4107 mode
->clock
= pixel_clock
* 10;
4108 mode
->hdisplay
= hactive
;
4109 mode
->hsync_start
= mode
->hdisplay
+ hsync
;
4110 mode
->hsync_end
= mode
->hsync_start
+ hsync_width
;
4111 mode
->htotal
= mode
->hdisplay
+ hblank
;
4113 mode
->vdisplay
= vactive
;
4114 mode
->vsync_start
= mode
->vdisplay
+ vsync
;
4115 mode
->vsync_end
= mode
->vsync_start
+ vsync_width
;
4116 mode
->vtotal
= mode
->vdisplay
+ vblank
;
4119 mode
->flags
|= hsync_positive
? DRM_MODE_FLAG_PHSYNC
: DRM_MODE_FLAG_NHSYNC
;
4120 mode
->flags
|= vsync_positive
? DRM_MODE_FLAG_PVSYNC
: DRM_MODE_FLAG_NVSYNC
;
4121 mode
->type
= DRM_MODE_TYPE_DRIVER
;
4123 if (timings
->flags
& 0x80)
4124 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4125 mode
->vrefresh
= drm_mode_vrefresh(mode
);
4126 drm_mode_set_name(mode
);
4131 static int add_displayid_detailed_1_modes(struct drm_connector
*connector
,
4132 struct displayid_block
*block
)
4134 struct displayid_detailed_timing_block
*det
= (struct displayid_detailed_timing_block
*)block
;
4137 struct drm_display_mode
*newmode
;
4139 /* blocks must be multiple of 20 bytes length */
4140 if (block
->num_bytes
% 20)
4143 num_timings
= block
->num_bytes
/ 20;
4144 for (i
= 0; i
< num_timings
; i
++) {
4145 struct displayid_detailed_timings_1
*timings
= &det
->timings
[i
];
4147 newmode
= drm_mode_displayid_detailed(connector
->dev
, timings
);
4151 drm_mode_probed_add(connector
, newmode
);
4157 static int add_displayid_detailed_modes(struct drm_connector
*connector
,
4163 int length
= EDID_LENGTH
;
4164 struct displayid_block
*block
;
4167 displayid
= drm_find_displayid_extension(edid
);
4171 ret
= validate_displayid(displayid
, length
, idx
);
4175 idx
+= sizeof(struct displayid_hdr
);
4176 while (block
= (struct displayid_block
*)&displayid
[idx
],
4177 idx
+ sizeof(struct displayid_block
) <= length
&&
4178 idx
+ sizeof(struct displayid_block
) + block
->num_bytes
<= length
&&
4179 block
->num_bytes
> 0) {
4180 idx
+= block
->num_bytes
+ sizeof(struct displayid_block
);
4181 switch (block
->tag
) {
4182 case DATA_BLOCK_TYPE_1_DETAILED_TIMING
:
4183 num_modes
+= add_displayid_detailed_1_modes(connector
, block
);
4191 * drm_add_edid_modes - add modes from EDID data, if available
4192 * @connector: connector we're probing
4195 * Add the specified modes to the connector's mode list. Also fills out the
4196 * &drm_display_info structure in @connector with any information which can be
4197 * derived from the edid.
4199 * Return: The number of modes added or 0 if we couldn't find any.
4201 int drm_add_edid_modes(struct drm_connector
*connector
, struct edid
*edid
)
4209 if (!drm_edid_is_valid(edid
)) {
4210 dev_warn(connector
->dev
->dev
, "%s: EDID invalid.\n",
4215 quirks
= edid_get_quirks(edid
);
4218 * EDID spec says modes should be preferred in this order:
4219 * - preferred detailed mode
4220 * - other detailed modes from base block
4221 * - detailed modes from extension blocks
4222 * - CVT 3-byte code modes
4223 * - standard timing codes
4224 * - established timing codes
4225 * - modes inferred from GTF or CVT range information
4227 * We get this pretty much right.
4229 * XXX order for additional mode types in extension blocks?
4231 num_modes
+= add_detailed_modes(connector
, edid
, quirks
);
4232 num_modes
+= add_cvt_modes(connector
, edid
);
4233 num_modes
+= add_standard_modes(connector
, edid
);
4234 num_modes
+= add_established_modes(connector
, edid
);
4235 num_modes
+= add_cea_modes(connector
, edid
);
4236 num_modes
+= add_alternate_cea_modes(connector
, edid
);
4237 num_modes
+= add_displayid_detailed_modes(connector
, edid
);
4238 if (edid
->features
& DRM_EDID_FEATURE_DEFAULT_GTF
)
4239 num_modes
+= add_inferred_modes(connector
, edid
);
4241 if (quirks
& (EDID_QUIRK_PREFER_LARGE_60
| EDID_QUIRK_PREFER_LARGE_75
))
4242 edid_fixup_preferred(connector
, quirks
);
4244 drm_add_display_info(connector
, edid
);
4246 if (quirks
& EDID_QUIRK_FORCE_6BPC
)
4247 connector
->display_info
.bpc
= 6;
4249 if (quirks
& EDID_QUIRK_FORCE_8BPC
)
4250 connector
->display_info
.bpc
= 8;
4252 if (quirks
& EDID_QUIRK_FORCE_10BPC
)
4253 connector
->display_info
.bpc
= 10;
4255 if (quirks
& EDID_QUIRK_FORCE_12BPC
)
4256 connector
->display_info
.bpc
= 12;
4260 EXPORT_SYMBOL(drm_add_edid_modes
);
4263 * drm_add_modes_noedid - add modes for the connectors without EDID
4264 * @connector: connector we're probing
4265 * @hdisplay: the horizontal display limit
4266 * @vdisplay: the vertical display limit
4268 * Add the specified modes to the connector's mode list. Only when the
4269 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4271 * Return: The number of modes added or 0 if we couldn't find any.
4273 int drm_add_modes_noedid(struct drm_connector
*connector
,
4274 int hdisplay
, int vdisplay
)
4276 int i
, count
, num_modes
= 0;
4277 struct drm_display_mode
*mode
;
4278 struct drm_device
*dev
= connector
->dev
;
4280 count
= ARRAY_SIZE(drm_dmt_modes
);
4286 for (i
= 0; i
< count
; i
++) {
4287 const struct drm_display_mode
*ptr
= &drm_dmt_modes
[i
];
4288 if (hdisplay
&& vdisplay
) {
4290 * Only when two are valid, they will be used to check
4291 * whether the mode should be added to the mode list of
4294 if (ptr
->hdisplay
> hdisplay
||
4295 ptr
->vdisplay
> vdisplay
)
4298 if (drm_mode_vrefresh(ptr
) > 61)
4300 mode
= drm_mode_duplicate(dev
, ptr
);
4302 drm_mode_probed_add(connector
, mode
);
4308 EXPORT_SYMBOL(drm_add_modes_noedid
);
4311 * drm_set_preferred_mode - Sets the preferred mode of a connector
4312 * @connector: connector whose mode list should be processed
4313 * @hpref: horizontal resolution of preferred mode
4314 * @vpref: vertical resolution of preferred mode
4316 * Marks a mode as preferred if it matches the resolution specified by @hpref
4319 void drm_set_preferred_mode(struct drm_connector
*connector
,
4320 int hpref
, int vpref
)
4322 struct drm_display_mode
*mode
;
4324 list_for_each_entry(mode
, &connector
->probed_modes
, head
) {
4325 if (mode
->hdisplay
== hpref
&&
4326 mode
->vdisplay
== vpref
)
4327 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4330 EXPORT_SYMBOL(drm_set_preferred_mode
);
4333 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4334 * data from a DRM display mode
4335 * @frame: HDMI AVI infoframe
4336 * @mode: DRM display mode
4338 * Return: 0 on success or a negative error code on failure.
4341 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe
*frame
,
4342 const struct drm_display_mode
*mode
)
4346 if (!frame
|| !mode
)
4349 err
= hdmi_avi_infoframe_init(frame
);
4353 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
4354 frame
->pixel_repeat
= 1;
4356 frame
->video_code
= drm_match_cea_mode(mode
);
4358 frame
->picture_aspect
= HDMI_PICTURE_ASPECT_NONE
;
4361 * Populate picture aspect ratio from either
4362 * user input (if specified) or from the CEA mode list.
4364 if (mode
->picture_aspect_ratio
== HDMI_PICTURE_ASPECT_4_3
||
4365 mode
->picture_aspect_ratio
== HDMI_PICTURE_ASPECT_16_9
)
4366 frame
->picture_aspect
= mode
->picture_aspect_ratio
;
4367 else if (frame
->video_code
> 0)
4368 frame
->picture_aspect
= drm_get_cea_aspect_ratio(
4371 frame
->active_aspect
= HDMI_ACTIVE_ASPECT_PICTURE
;
4372 frame
->scan_mode
= HDMI_SCAN_MODE_UNDERSCAN
;
4376 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode
);
4379 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4380 * quantization range information
4381 * @frame: HDMI AVI infoframe
4382 * @mode: DRM display mode
4383 * @rgb_quant_range: RGB quantization range (Q)
4384 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4387 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe
*frame
,
4388 const struct drm_display_mode
*mode
,
4389 enum hdmi_quantization_range rgb_quant_range
,
4390 bool rgb_quant_range_selectable
)
4394 * "A Source shall not send a non-zero Q value that does not correspond
4395 * to the default RGB Quantization Range for the transmitted Picture
4396 * unless the Sink indicates support for the Q bit in a Video
4397 * Capabilities Data Block."
4399 * HDMI 2.0 recommends sending non-zero Q when it does match the
4400 * default RGB quantization range for the mode, even when QS=0.
4402 if (rgb_quant_range_selectable
||
4403 rgb_quant_range
== drm_default_rgb_quant_range(mode
))
4404 frame
->quantization_range
= rgb_quant_range
;
4406 frame
->quantization_range
= HDMI_QUANTIZATION_RANGE_DEFAULT
;
4410 * "When transmitting any RGB colorimetry, the Source should set the
4411 * YQ-field to match the RGB Quantization Range being transmitted
4412 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4413 * set YQ=1) and the Sink shall ignore the YQ-field."
4415 if (rgb_quant_range
== HDMI_QUANTIZATION_RANGE_LIMITED
)
4416 frame
->ycc_quantization_range
=
4417 HDMI_YCC_QUANTIZATION_RANGE_LIMITED
;
4419 frame
->ycc_quantization_range
=
4420 HDMI_YCC_QUANTIZATION_RANGE_FULL
;
4422 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range
);
4424 static enum hdmi_3d_structure
4425 s3d_structure_from_display_mode(const struct drm_display_mode
*mode
)
4427 u32 layout
= mode
->flags
& DRM_MODE_FLAG_3D_MASK
;
4430 case DRM_MODE_FLAG_3D_FRAME_PACKING
:
4431 return HDMI_3D_STRUCTURE_FRAME_PACKING
;
4432 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE
:
4433 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE
;
4434 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE
:
4435 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE
;
4436 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL
:
4437 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL
;
4438 case DRM_MODE_FLAG_3D_L_DEPTH
:
4439 return HDMI_3D_STRUCTURE_L_DEPTH
;
4440 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH
:
4441 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH
;
4442 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
:
4443 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM
;
4444 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
:
4445 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF
;
4447 return HDMI_3D_STRUCTURE_INVALID
;
4452 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4453 * data from a DRM display mode
4454 * @frame: HDMI vendor infoframe
4455 * @mode: DRM display mode
4457 * Note that there's is a need to send HDMI vendor infoframes only when using a
4458 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4459 * function will return -EINVAL, error that can be safely ignored.
4461 * Return: 0 on success or a negative error code on failure.
4464 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe
*frame
,
4465 const struct drm_display_mode
*mode
)
4471 if (!frame
|| !mode
)
4474 vic
= drm_match_hdmi_mode(mode
);
4475 s3d_flags
= mode
->flags
& DRM_MODE_FLAG_3D_MASK
;
4477 if (!vic
&& !s3d_flags
)
4480 if (vic
&& s3d_flags
)
4483 err
= hdmi_vendor_infoframe_init(frame
);
4490 frame
->s3d_struct
= s3d_structure_from_display_mode(mode
);
4494 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode
);
4496 static int drm_parse_tiled_block(struct drm_connector
*connector
,
4497 struct displayid_block
*block
)
4499 struct displayid_tiled_block
*tile
= (struct displayid_tiled_block
*)block
;
4501 u8 tile_v_loc
, tile_h_loc
;
4502 u8 num_v_tile
, num_h_tile
;
4503 struct drm_tile_group
*tg
;
4505 w
= tile
->tile_size
[0] | tile
->tile_size
[1] << 8;
4506 h
= tile
->tile_size
[2] | tile
->tile_size
[3] << 8;
4508 num_v_tile
= (tile
->topo
[0] & 0xf) | (tile
->topo
[2] & 0x30);
4509 num_h_tile
= (tile
->topo
[0] >> 4) | ((tile
->topo
[2] >> 2) & 0x30);
4510 tile_v_loc
= (tile
->topo
[1] & 0xf) | ((tile
->topo
[2] & 0x3) << 4);
4511 tile_h_loc
= (tile
->topo
[1] >> 4) | (((tile
->topo
[2] >> 2) & 0x3) << 4);
4513 connector
->has_tile
= true;
4514 if (tile
->tile_cap
& 0x80)
4515 connector
->tile_is_single_monitor
= true;
4517 connector
->num_h_tile
= num_h_tile
+ 1;
4518 connector
->num_v_tile
= num_v_tile
+ 1;
4519 connector
->tile_h_loc
= tile_h_loc
;
4520 connector
->tile_v_loc
= tile_v_loc
;
4521 connector
->tile_h_size
= w
+ 1;
4522 connector
->tile_v_size
= h
+ 1;
4524 DRM_DEBUG_KMS("tile cap 0x%x\n", tile
->tile_cap
);
4525 DRM_DEBUG_KMS("tile_size %d x %d\n", w
+ 1, h
+ 1);
4526 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4527 num_h_tile
+ 1, num_v_tile
+ 1, tile_h_loc
, tile_v_loc
);
4528 DRM_DEBUG_KMS("vend %c%c%c\n", tile
->topology_id
[0], tile
->topology_id
[1], tile
->topology_id
[2]);
4530 tg
= drm_mode_get_tile_group(connector
->dev
, tile
->topology_id
);
4532 tg
= drm_mode_create_tile_group(connector
->dev
, tile
->topology_id
);
4537 if (connector
->tile_group
!= tg
) {
4538 /* if we haven't got a pointer,
4539 take the reference, drop ref to old tile group */
4540 if (connector
->tile_group
) {
4541 drm_mode_put_tile_group(connector
->dev
, connector
->tile_group
);
4543 connector
->tile_group
= tg
;
4545 /* if same tile group, then release the ref we just took. */
4546 drm_mode_put_tile_group(connector
->dev
, tg
);
4550 static int drm_parse_display_id(struct drm_connector
*connector
,
4551 u8
*displayid
, int length
,
4552 bool is_edid_extension
)
4554 /* if this is an EDID extension the first byte will be 0x70 */
4556 struct displayid_block
*block
;
4559 if (is_edid_extension
)
4562 ret
= validate_displayid(displayid
, length
, idx
);
4566 idx
+= sizeof(struct displayid_hdr
);
4567 while (block
= (struct displayid_block
*)&displayid
[idx
],
4568 idx
+ sizeof(struct displayid_block
) <= length
&&
4569 idx
+ sizeof(struct displayid_block
) + block
->num_bytes
<= length
&&
4570 block
->num_bytes
> 0) {
4571 idx
+= block
->num_bytes
+ sizeof(struct displayid_block
);
4572 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4573 block
->tag
, block
->rev
, block
->num_bytes
);
4575 switch (block
->tag
) {
4576 case DATA_BLOCK_TILED_DISPLAY
:
4577 ret
= drm_parse_tiled_block(connector
, block
);
4581 case DATA_BLOCK_TYPE_1_DETAILED_TIMING
:
4582 /* handled in mode gathering code. */
4585 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block
->tag
);
4592 static void drm_get_displayid(struct drm_connector
*connector
,
4595 void *displayid
= NULL
;
4597 connector
->has_tile
= false;
4598 displayid
= drm_find_displayid_extension(edid
);
4600 /* drop reference to any tile group we had */
4604 ret
= drm_parse_display_id(connector
, displayid
, EDID_LENGTH
, true);
4607 if (!connector
->has_tile
)
4611 if (connector
->tile_group
) {
4612 drm_mode_put_tile_group(connector
->dev
, connector
->tile_group
);
4613 connector
->tile_group
= NULL
;