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Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / drm_edid.c
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
36 #include <drm/drmP.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
41
42 #include "drm_crtc_internal.h"
43
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
47
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
51
52 /*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
77 /* Force 8bpc */
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
79 /* Force 12bpc */
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
81 /* Force 6bpc */
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
83
84 struct detailed_mode_closure {
85 struct drm_connector *connector;
86 struct edid *edid;
87 bool preferred;
88 u32 quirks;
89 int modes;
90 };
91
92 #define LEVEL_DMT 0
93 #define LEVEL_GTF 1
94 #define LEVEL_GTF2 2
95 #define LEVEL_CVT 3
96
97 static const struct edid_quirk {
98 char vendor[4];
99 int product_id;
100 u32 quirks;
101 } edid_quirk_list[] = {
102 /* Acer AL1706 */
103 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
104 /* Acer F51 */
105 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
106 /* Unknown Acer */
107 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
108
109 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
110 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
111
112 /* Belinea 10 15 55 */
113 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
114 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
115
116 /* Envision Peripherals, Inc. EN-7100e */
117 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
118 /* Envision EN2028 */
119 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
120
121 /* Funai Electronics PM36B */
122 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
123 EDID_QUIRK_DETAILED_IN_CM },
124
125 /* LG Philips LCD LP154W01-A5 */
126 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
127 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
128
129 /* Philips 107p5 CRT */
130 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
131
132 /* Proview AY765C */
133 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
134
135 /* Samsung SyncMaster 205BW. Note: irony */
136 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
137 /* Samsung SyncMaster 22[5-6]BW */
138 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
139 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
140
141 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
142 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
143
144 /* ViewSonic VA2026w */
145 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
146
147 /* Medion MD 30217 PG */
148 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
149
150 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
151 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
152
153 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
154 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
155 };
156
157 /*
158 * Autogenerated from the DMT spec.
159 * This table is copied from xfree86/modes/xf86EdidModes.c.
160 */
161 static const struct drm_display_mode drm_dmt_modes[] = {
162 /* 0x01 - 640x350@85Hz */
163 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
164 736, 832, 0, 350, 382, 385, 445, 0,
165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
166 /* 0x02 - 640x400@85Hz */
167 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
168 736, 832, 0, 400, 401, 404, 445, 0,
169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
170 /* 0x03 - 720x400@85Hz */
171 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
172 828, 936, 0, 400, 401, 404, 446, 0,
173 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
174 /* 0x04 - 640x480@60Hz */
175 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
176 752, 800, 0, 480, 490, 492, 525, 0,
177 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
178 /* 0x05 - 640x480@72Hz */
179 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
180 704, 832, 0, 480, 489, 492, 520, 0,
181 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
182 /* 0x06 - 640x480@75Hz */
183 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
184 720, 840, 0, 480, 481, 484, 500, 0,
185 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
186 /* 0x07 - 640x480@85Hz */
187 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
188 752, 832, 0, 480, 481, 484, 509, 0,
189 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
190 /* 0x08 - 800x600@56Hz */
191 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
192 896, 1024, 0, 600, 601, 603, 625, 0,
193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
194 /* 0x09 - 800x600@60Hz */
195 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
196 968, 1056, 0, 600, 601, 605, 628, 0,
197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
198 /* 0x0a - 800x600@72Hz */
199 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
200 976, 1040, 0, 600, 637, 643, 666, 0,
201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
202 /* 0x0b - 800x600@75Hz */
203 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
204 896, 1056, 0, 600, 601, 604, 625, 0,
205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
206 /* 0x0c - 800x600@85Hz */
207 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
208 896, 1048, 0, 600, 601, 604, 631, 0,
209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
210 /* 0x0d - 800x600@120Hz RB */
211 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
212 880, 960, 0, 600, 603, 607, 636, 0,
213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
214 /* 0x0e - 848x480@60Hz */
215 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
216 976, 1088, 0, 480, 486, 494, 517, 0,
217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
218 /* 0x0f - 1024x768@43Hz, interlace */
219 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
220 1208, 1264, 0, 768, 768, 776, 817, 0,
221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
222 DRM_MODE_FLAG_INTERLACE) },
223 /* 0x10 - 1024x768@60Hz */
224 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
225 1184, 1344, 0, 768, 771, 777, 806, 0,
226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
227 /* 0x11 - 1024x768@70Hz */
228 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
229 1184, 1328, 0, 768, 771, 777, 806, 0,
230 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
231 /* 0x12 - 1024x768@75Hz */
232 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
233 1136, 1312, 0, 768, 769, 772, 800, 0,
234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
235 /* 0x13 - 1024x768@85Hz */
236 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
237 1168, 1376, 0, 768, 769, 772, 808, 0,
238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
239 /* 0x14 - 1024x768@120Hz RB */
240 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
241 1104, 1184, 0, 768, 771, 775, 813, 0,
242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
243 /* 0x15 - 1152x864@75Hz */
244 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
245 1344, 1600, 0, 864, 865, 868, 900, 0,
246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
247 /* 0x55 - 1280x720@60Hz */
248 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
249 1430, 1650, 0, 720, 725, 730, 750, 0,
250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
251 /* 0x16 - 1280x768@60Hz RB */
252 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
253 1360, 1440, 0, 768, 771, 778, 790, 0,
254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
255 /* 0x17 - 1280x768@60Hz */
256 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
257 1472, 1664, 0, 768, 771, 778, 798, 0,
258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x18 - 1280x768@75Hz */
260 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
261 1488, 1696, 0, 768, 771, 778, 805, 0,
262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
263 /* 0x19 - 1280x768@85Hz */
264 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
265 1496, 1712, 0, 768, 771, 778, 809, 0,
266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
267 /* 0x1a - 1280x768@120Hz RB */
268 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
269 1360, 1440, 0, 768, 771, 778, 813, 0,
270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
271 /* 0x1b - 1280x800@60Hz RB */
272 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
273 1360, 1440, 0, 800, 803, 809, 823, 0,
274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
275 /* 0x1c - 1280x800@60Hz */
276 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
277 1480, 1680, 0, 800, 803, 809, 831, 0,
278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
279 /* 0x1d - 1280x800@75Hz */
280 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
281 1488, 1696, 0, 800, 803, 809, 838, 0,
282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
283 /* 0x1e - 1280x800@85Hz */
284 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
285 1496, 1712, 0, 800, 803, 809, 843, 0,
286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
287 /* 0x1f - 1280x800@120Hz RB */
288 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
289 1360, 1440, 0, 800, 803, 809, 847, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
291 /* 0x20 - 1280x960@60Hz */
292 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
293 1488, 1800, 0, 960, 961, 964, 1000, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
295 /* 0x21 - 1280x960@85Hz */
296 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
297 1504, 1728, 0, 960, 961, 964, 1011, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
299 /* 0x22 - 1280x960@120Hz RB */
300 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
301 1360, 1440, 0, 960, 963, 967, 1017, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
303 /* 0x23 - 1280x1024@60Hz */
304 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
305 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
307 /* 0x24 - 1280x1024@75Hz */
308 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
309 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
311 /* 0x25 - 1280x1024@85Hz */
312 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
313 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x26 - 1280x1024@120Hz RB */
316 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
317 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
319 /* 0x27 - 1360x768@60Hz */
320 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
321 1536, 1792, 0, 768, 771, 777, 795, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
323 /* 0x28 - 1360x768@120Hz RB */
324 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
325 1440, 1520, 0, 768, 771, 776, 813, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
327 /* 0x51 - 1366x768@60Hz */
328 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
329 1579, 1792, 0, 768, 771, 774, 798, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
331 /* 0x56 - 1366x768@60Hz */
332 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
333 1436, 1500, 0, 768, 769, 772, 800, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x29 - 1400x1050@60Hz RB */
336 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
337 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
339 /* 0x2a - 1400x1050@60Hz */
340 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
341 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x2b - 1400x1050@75Hz */
344 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
345 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
347 /* 0x2c - 1400x1050@85Hz */
348 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
349 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
350 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
351 /* 0x2d - 1400x1050@120Hz RB */
352 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
353 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
355 /* 0x2e - 1440x900@60Hz RB */
356 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
357 1520, 1600, 0, 900, 903, 909, 926, 0,
358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
359 /* 0x2f - 1440x900@60Hz */
360 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
361 1672, 1904, 0, 900, 903, 909, 934, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x30 - 1440x900@75Hz */
364 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
365 1688, 1936, 0, 900, 903, 909, 942, 0,
366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x31 - 1440x900@85Hz */
368 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
369 1696, 1952, 0, 900, 903, 909, 948, 0,
370 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x32 - 1440x900@120Hz RB */
372 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
373 1520, 1600, 0, 900, 903, 909, 953, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
375 /* 0x53 - 1600x900@60Hz */
376 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
377 1704, 1800, 0, 900, 901, 904, 1000, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
379 /* 0x33 - 1600x1200@60Hz */
380 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
381 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
383 /* 0x34 - 1600x1200@65Hz */
384 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
385 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x35 - 1600x1200@70Hz */
388 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
389 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x36 - 1600x1200@75Hz */
392 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
393 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
395 /* 0x37 - 1600x1200@85Hz */
396 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
397 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
399 /* 0x38 - 1600x1200@120Hz RB */
400 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
401 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
403 /* 0x39 - 1680x1050@60Hz RB */
404 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
405 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
407 /* 0x3a - 1680x1050@60Hz */
408 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
409 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x3b - 1680x1050@75Hz */
412 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
413 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
415 /* 0x3c - 1680x1050@85Hz */
416 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
417 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x3d - 1680x1050@120Hz RB */
420 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
421 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
423 /* 0x3e - 1792x1344@60Hz */
424 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
425 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x3f - 1792x1344@75Hz */
428 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
429 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
431 /* 0x40 - 1792x1344@120Hz RB */
432 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
433 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 0x41 - 1856x1392@60Hz */
436 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
437 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 0x42 - 1856x1392@75Hz */
440 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
441 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 0x43 - 1856x1392@120Hz RB */
444 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
445 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
447 /* 0x52 - 1920x1080@60Hz */
448 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
449 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
451 /* 0x44 - 1920x1200@60Hz RB */
452 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
453 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
455 /* 0x45 - 1920x1200@60Hz */
456 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
457 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x46 - 1920x1200@75Hz */
460 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
461 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x47 - 1920x1200@85Hz */
464 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
465 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
466 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x48 - 1920x1200@120Hz RB */
468 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
469 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
471 /* 0x49 - 1920x1440@60Hz */
472 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
473 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x4a - 1920x1440@75Hz */
476 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
477 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 0x4b - 1920x1440@120Hz RB */
480 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
481 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
483 /* 0x54 - 2048x1152@60Hz */
484 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
485 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x4c - 2560x1600@60Hz RB */
488 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
489 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
491 /* 0x4d - 2560x1600@60Hz */
492 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
493 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x4e - 2560x1600@75Hz */
496 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
497 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
499 /* 0x4f - 2560x1600@85Hz */
500 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
501 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
503 /* 0x50 - 2560x1600@120Hz RB */
504 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
505 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
507 /* 0x57 - 4096x2160@60Hz RB */
508 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
509 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
511 /* 0x58 - 4096x2160@59.94Hz RB */
512 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
513 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
515 };
516
517 /*
518 * These more or less come from the DMT spec. The 720x400 modes are
519 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
520 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
521 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
522 * mode.
523 *
524 * The DMT modes have been fact-checked; the rest are mild guesses.
525 */
526 static const struct drm_display_mode edid_est_modes[] = {
527 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
528 968, 1056, 0, 600, 601, 605, 628, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
530 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
531 896, 1024, 0, 600, 601, 603, 625, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
533 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
534 720, 840, 0, 480, 481, 484, 500, 0,
535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
536 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
537 704, 832, 0, 480, 489, 492, 520, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
539 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
540 768, 864, 0, 480, 483, 486, 525, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
542 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
543 752, 800, 0, 480, 490, 492, 525, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
545 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
546 846, 900, 0, 400, 421, 423, 449, 0,
547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
548 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
549 846, 900, 0, 400, 412, 414, 449, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
551 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
552 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
554 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
555 1136, 1312, 0, 768, 769, 772, 800, 0,
556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
557 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
558 1184, 1328, 0, 768, 771, 777, 806, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
560 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
561 1184, 1344, 0, 768, 771, 777, 806, 0,
562 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
563 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
564 1208, 1264, 0, 768, 768, 776, 817, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
566 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
567 928, 1152, 0, 624, 625, 628, 667, 0,
568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
569 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
570 896, 1056, 0, 600, 601, 604, 625, 0,
571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
572 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
573 976, 1040, 0, 600, 637, 643, 666, 0,
574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
575 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
576 1344, 1600, 0, 864, 865, 868, 900, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
578 };
579
580 struct minimode {
581 short w;
582 short h;
583 short r;
584 short rb;
585 };
586
587 static const struct minimode est3_modes[] = {
588 /* byte 6 */
589 { 640, 350, 85, 0 },
590 { 640, 400, 85, 0 },
591 { 720, 400, 85, 0 },
592 { 640, 480, 85, 0 },
593 { 848, 480, 60, 0 },
594 { 800, 600, 85, 0 },
595 { 1024, 768, 85, 0 },
596 { 1152, 864, 75, 0 },
597 /* byte 7 */
598 { 1280, 768, 60, 1 },
599 { 1280, 768, 60, 0 },
600 { 1280, 768, 75, 0 },
601 { 1280, 768, 85, 0 },
602 { 1280, 960, 60, 0 },
603 { 1280, 960, 85, 0 },
604 { 1280, 1024, 60, 0 },
605 { 1280, 1024, 85, 0 },
606 /* byte 8 */
607 { 1360, 768, 60, 0 },
608 { 1440, 900, 60, 1 },
609 { 1440, 900, 60, 0 },
610 { 1440, 900, 75, 0 },
611 { 1440, 900, 85, 0 },
612 { 1400, 1050, 60, 1 },
613 { 1400, 1050, 60, 0 },
614 { 1400, 1050, 75, 0 },
615 /* byte 9 */
616 { 1400, 1050, 85, 0 },
617 { 1680, 1050, 60, 1 },
618 { 1680, 1050, 60, 0 },
619 { 1680, 1050, 75, 0 },
620 { 1680, 1050, 85, 0 },
621 { 1600, 1200, 60, 0 },
622 { 1600, 1200, 65, 0 },
623 { 1600, 1200, 70, 0 },
624 /* byte 10 */
625 { 1600, 1200, 75, 0 },
626 { 1600, 1200, 85, 0 },
627 { 1792, 1344, 60, 0 },
628 { 1792, 1344, 75, 0 },
629 { 1856, 1392, 60, 0 },
630 { 1856, 1392, 75, 0 },
631 { 1920, 1200, 60, 1 },
632 { 1920, 1200, 60, 0 },
633 /* byte 11 */
634 { 1920, 1200, 75, 0 },
635 { 1920, 1200, 85, 0 },
636 { 1920, 1440, 60, 0 },
637 { 1920, 1440, 75, 0 },
638 };
639
640 static const struct minimode extra_modes[] = {
641 { 1024, 576, 60, 0 },
642 { 1366, 768, 60, 0 },
643 { 1600, 900, 60, 0 },
644 { 1680, 945, 60, 0 },
645 { 1920, 1080, 60, 0 },
646 { 2048, 1152, 60, 0 },
647 { 2048, 1536, 60, 0 },
648 };
649
650 /*
651 * Probably taken from CEA-861 spec.
652 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
653 *
654 * Index using the VIC.
655 */
656 static const struct drm_display_mode edid_cea_modes[] = {
657 /* 0 - dummy, VICs start at 1 */
658 { },
659 /* 1 - 640x480@60Hz */
660 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
661 752, 800, 0, 480, 490, 492, 525, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
663 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
664 /* 2 - 720x480@60Hz */
665 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
666 798, 858, 0, 480, 489, 495, 525, 0,
667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
669 /* 3 - 720x480@60Hz */
670 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
671 798, 858, 0, 480, 489, 495, 525, 0,
672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
674 /* 4 - 1280x720@60Hz */
675 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
676 1430, 1650, 0, 720, 725, 730, 750, 0,
677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
678 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
679 /* 5 - 1920x1080i@60Hz */
680 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
681 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
683 DRM_MODE_FLAG_INTERLACE),
684 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
685 /* 6 - 720(1440)x480i@60Hz */
686 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
687 801, 858, 0, 480, 488, 494, 525, 0,
688 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
689 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
691 /* 7 - 720(1440)x480i@60Hz */
692 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
693 801, 858, 0, 480, 488, 494, 525, 0,
694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
695 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
696 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
697 /* 8 - 720(1440)x240@60Hz */
698 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
699 801, 858, 0, 240, 244, 247, 262, 0,
700 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
701 DRM_MODE_FLAG_DBLCLK),
702 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
703 /* 9 - 720(1440)x240@60Hz */
704 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
705 801, 858, 0, 240, 244, 247, 262, 0,
706 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
707 DRM_MODE_FLAG_DBLCLK),
708 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
709 /* 10 - 2880x480i@60Hz */
710 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
711 3204, 3432, 0, 480, 488, 494, 525, 0,
712 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
713 DRM_MODE_FLAG_INTERLACE),
714 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
715 /* 11 - 2880x480i@60Hz */
716 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
717 3204, 3432, 0, 480, 488, 494, 525, 0,
718 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
719 DRM_MODE_FLAG_INTERLACE),
720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
721 /* 12 - 2880x240@60Hz */
722 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
723 3204, 3432, 0, 240, 244, 247, 262, 0,
724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
726 /* 13 - 2880x240@60Hz */
727 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
728 3204, 3432, 0, 240, 244, 247, 262, 0,
729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
731 /* 14 - 1440x480@60Hz */
732 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
733 1596, 1716, 0, 480, 489, 495, 525, 0,
734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
736 /* 15 - 1440x480@60Hz */
737 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
738 1596, 1716, 0, 480, 489, 495, 525, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741 /* 16 - 1920x1080@60Hz */
742 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
743 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
746 /* 17 - 720x576@50Hz */
747 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
748 796, 864, 0, 576, 581, 586, 625, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
751 /* 18 - 720x576@50Hz */
752 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
753 796, 864, 0, 576, 581, 586, 625, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
755 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 19 - 1280x720@50Hz */
757 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
758 1760, 1980, 0, 720, 725, 730, 750, 0,
759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
760 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 20 - 1920x1080i@50Hz */
762 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
763 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
765 DRM_MODE_FLAG_INTERLACE),
766 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
767 /* 21 - 720(1440)x576i@50Hz */
768 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
769 795, 864, 0, 576, 580, 586, 625, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
773 /* 22 - 720(1440)x576i@50Hz */
774 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
775 795, 864, 0, 576, 580, 586, 625, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
777 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
778 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
779 /* 23 - 720(1440)x288@50Hz */
780 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
781 795, 864, 0, 288, 290, 293, 312, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
783 DRM_MODE_FLAG_DBLCLK),
784 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785 /* 24 - 720(1440)x288@50Hz */
786 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
787 795, 864, 0, 288, 290, 293, 312, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_DBLCLK),
790 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 25 - 2880x576i@50Hz */
792 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
793 3180, 3456, 0, 576, 580, 586, 625, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
795 DRM_MODE_FLAG_INTERLACE),
796 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
797 /* 26 - 2880x576i@50Hz */
798 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
799 3180, 3456, 0, 576, 580, 586, 625, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
801 DRM_MODE_FLAG_INTERLACE),
802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
803 /* 27 - 2880x288@50Hz */
804 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
805 3180, 3456, 0, 288, 290, 293, 312, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
808 /* 28 - 2880x288@50Hz */
809 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
810 3180, 3456, 0, 288, 290, 293, 312, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
813 /* 29 - 1440x576@50Hz */
814 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
815 1592, 1728, 0, 576, 581, 586, 625, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
818 /* 30 - 1440x576@50Hz */
819 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
820 1592, 1728, 0, 576, 581, 586, 625, 0,
821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 31 - 1920x1080@50Hz */
824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
825 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828 /* 32 - 1920x1080@24Hz */
829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
830 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
832 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 33 - 1920x1080@25Hz */
834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
835 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
837 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 34 - 1920x1080@30Hz */
839 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
840 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
842 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 35 - 2880x480@60Hz */
844 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
845 3192, 3432, 0, 480, 489, 495, 525, 0,
846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
847 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
848 /* 36 - 2880x480@60Hz */
849 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
850 3192, 3432, 0, 480, 489, 495, 525, 0,
851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
852 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
853 /* 37 - 2880x576@50Hz */
854 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
855 3184, 3456, 0, 576, 581, 586, 625, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
857 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
858 /* 38 - 2880x576@50Hz */
859 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
860 3184, 3456, 0, 576, 581, 586, 625, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 39 - 1920x1080i@50Hz */
864 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
865 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
867 DRM_MODE_FLAG_INTERLACE),
868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
869 /* 40 - 1920x1080i@100Hz */
870 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
871 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
873 DRM_MODE_FLAG_INTERLACE),
874 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
875 /* 41 - 1280x720@100Hz */
876 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
877 1760, 1980, 0, 720, 725, 730, 750, 0,
878 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
880 /* 42 - 720x576@100Hz */
881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
882 796, 864, 0, 576, 581, 586, 625, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
885 /* 43 - 720x576@100Hz */
886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
887 796, 864, 0, 576, 581, 586, 625, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890 /* 44 - 720(1440)x576i@100Hz */
891 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
892 795, 864, 0, 576, 580, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
894 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
895 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
896 /* 45 - 720(1440)x576i@100Hz */
897 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
898 795, 864, 0, 576, 580, 586, 625, 0,
899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
900 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
901 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902 /* 46 - 1920x1080i@120Hz */
903 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
904 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
906 DRM_MODE_FLAG_INTERLACE),
907 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
908 /* 47 - 1280x720@120Hz */
909 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
910 1430, 1650, 0, 720, 725, 730, 750, 0,
911 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 48 - 720x480@120Hz */
914 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
915 798, 858, 0, 480, 489, 495, 525, 0,
916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
918 /* 49 - 720x480@120Hz */
919 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
920 798, 858, 0, 480, 489, 495, 525, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
922 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 50 - 720(1440)x480i@120Hz */
924 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
925 801, 858, 0, 480, 488, 494, 525, 0,
926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
927 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
928 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
929 /* 51 - 720(1440)x480i@120Hz */
930 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
931 801, 858, 0, 480, 488, 494, 525, 0,
932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
933 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
934 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 52 - 720x576@200Hz */
936 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
937 796, 864, 0, 576, 581, 586, 625, 0,
938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
939 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
940 /* 53 - 720x576@200Hz */
941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
942 796, 864, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
944 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 54 - 720(1440)x576i@200Hz */
946 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
947 795, 864, 0, 576, 580, 586, 625, 0,
948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
949 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
950 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
951 /* 55 - 720(1440)x576i@200Hz */
952 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
953 795, 864, 0, 576, 580, 586, 625, 0,
954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
955 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
956 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
957 /* 56 - 720x480@240Hz */
958 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
959 798, 858, 0, 480, 489, 495, 525, 0,
960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
961 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
962 /* 57 - 720x480@240Hz */
963 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
964 798, 858, 0, 480, 489, 495, 525, 0,
965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
966 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967 /* 58 - 720(1440)x480i@240Hz */
968 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
969 801, 858, 0, 480, 488, 494, 525, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
971 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
972 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
973 /* 59 - 720(1440)x480i@240Hz */
974 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
975 801, 858, 0, 480, 488, 494, 525, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
977 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
978 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
979 /* 60 - 1280x720@24Hz */
980 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
981 3080, 3300, 0, 720, 725, 730, 750, 0,
982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
983 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 61 - 1280x720@25Hz */
985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
986 3740, 3960, 0, 720, 725, 730, 750, 0,
987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
988 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
989 /* 62 - 1280x720@30Hz */
990 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
991 3080, 3300, 0, 720, 725, 730, 750, 0,
992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
993 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
994 /* 63 - 1920x1080@120Hz */
995 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
996 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
998 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 64 - 1920x1080@100Hz */
1000 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1001 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 };
1005
1006 /*
1007 * HDMI 1.4 4k modes. Index using the VIC.
1008 */
1009 static const struct drm_display_mode edid_4k_modes[] = {
1010 /* 0 - dummy, VICs start at 1 */
1011 { },
1012 /* 1 - 3840x2160@30Hz */
1013 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1014 3840, 4016, 4104, 4400, 0,
1015 2160, 2168, 2178, 2250, 0,
1016 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1017 .vrefresh = 30, },
1018 /* 2 - 3840x2160@25Hz */
1019 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1020 3840, 4896, 4984, 5280, 0,
1021 2160, 2168, 2178, 2250, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 25, },
1024 /* 3 - 3840x2160@24Hz */
1025 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1026 3840, 5116, 5204, 5500, 0,
1027 2160, 2168, 2178, 2250, 0,
1028 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1029 .vrefresh = 24, },
1030 /* 4 - 4096x2160@24Hz (SMPTE) */
1031 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1032 4096, 5116, 5204, 5500, 0,
1033 2160, 2168, 2178, 2250, 0,
1034 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1035 .vrefresh = 24, },
1036 };
1037
1038 /*** DDC fetch and block validation ***/
1039
1040 static const u8 edid_header[] = {
1041 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1042 };
1043
1044 /**
1045 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1046 * @raw_edid: pointer to raw base EDID block
1047 *
1048 * Sanity check the header of the base EDID block.
1049 *
1050 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1051 */
1052 int drm_edid_header_is_valid(const u8 *raw_edid)
1053 {
1054 int i, score = 0;
1055
1056 for (i = 0; i < sizeof(edid_header); i++)
1057 if (raw_edid[i] == edid_header[i])
1058 score++;
1059
1060 return score;
1061 }
1062 EXPORT_SYMBOL(drm_edid_header_is_valid);
1063
1064 static int edid_fixup __read_mostly = 6;
1065 module_param_named(edid_fixup, edid_fixup, int, 0400);
1066 MODULE_PARM_DESC(edid_fixup,
1067 "Minimum number of valid EDID header bytes (0-8, default 6)");
1068
1069 static void drm_get_displayid(struct drm_connector *connector,
1070 struct edid *edid);
1071
1072 static int drm_edid_block_checksum(const u8 *raw_edid)
1073 {
1074 int i;
1075 u8 csum = 0;
1076 for (i = 0; i < EDID_LENGTH; i++)
1077 csum += raw_edid[i];
1078
1079 return csum;
1080 }
1081
1082 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1083 {
1084 if (memchr_inv(in_edid, 0, length))
1085 return false;
1086
1087 return true;
1088 }
1089
1090 /**
1091 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1092 * @raw_edid: pointer to raw EDID block
1093 * @block: type of block to validate (0 for base, extension otherwise)
1094 * @print_bad_edid: if true, dump bad EDID blocks to the console
1095 * @edid_corrupt: if true, the header or checksum is invalid
1096 *
1097 * Validate a base or extension EDID block and optionally dump bad blocks to
1098 * the console.
1099 *
1100 * Return: True if the block is valid, false otherwise.
1101 */
1102 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1103 bool *edid_corrupt)
1104 {
1105 u8 csum;
1106 struct edid *edid = (struct edid *)raw_edid;
1107
1108 if (WARN_ON(!raw_edid))
1109 return false;
1110
1111 if (edid_fixup > 8 || edid_fixup < 0)
1112 edid_fixup = 6;
1113
1114 if (block == 0) {
1115 int score = drm_edid_header_is_valid(raw_edid);
1116 if (score == 8) {
1117 if (edid_corrupt)
1118 *edid_corrupt = false;
1119 } else if (score >= edid_fixup) {
1120 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1121 * The corrupt flag needs to be set here otherwise, the
1122 * fix-up code here will correct the problem, the
1123 * checksum is correct and the test fails
1124 */
1125 if (edid_corrupt)
1126 *edid_corrupt = true;
1127 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1128 memcpy(raw_edid, edid_header, sizeof(edid_header));
1129 } else {
1130 if (edid_corrupt)
1131 *edid_corrupt = true;
1132 goto bad;
1133 }
1134 }
1135
1136 csum = drm_edid_block_checksum(raw_edid);
1137 if (csum) {
1138 if (edid_corrupt)
1139 *edid_corrupt = true;
1140
1141 /* allow CEA to slide through, switches mangle this */
1142 if (raw_edid[0] == CEA_EXT) {
1143 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1144 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1145 } else {
1146 if (print_bad_edid)
1147 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1148
1149 goto bad;
1150 }
1151 }
1152
1153 /* per-block-type checks */
1154 switch (raw_edid[0]) {
1155 case 0: /* base */
1156 if (edid->version != 1) {
1157 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1158 goto bad;
1159 }
1160
1161 if (edid->revision > 4)
1162 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1163 break;
1164
1165 default:
1166 break;
1167 }
1168
1169 return true;
1170
1171 bad:
1172 if (print_bad_edid) {
1173 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1174 pr_notice("EDID block is all zeroes\n");
1175 } else {
1176 pr_notice("Raw EDID:\n");
1177 print_hex_dump(KERN_NOTICE,
1178 " \t", DUMP_PREFIX_NONE, 16, 1,
1179 raw_edid, EDID_LENGTH, false);
1180 }
1181 }
1182 return false;
1183 }
1184 EXPORT_SYMBOL(drm_edid_block_valid);
1185
1186 /**
1187 * drm_edid_is_valid - sanity check EDID data
1188 * @edid: EDID data
1189 *
1190 * Sanity-check an entire EDID record (including extensions)
1191 *
1192 * Return: True if the EDID data is valid, false otherwise.
1193 */
1194 bool drm_edid_is_valid(struct edid *edid)
1195 {
1196 int i;
1197 u8 *raw = (u8 *)edid;
1198
1199 if (!edid)
1200 return false;
1201
1202 for (i = 0; i <= edid->extensions; i++)
1203 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1204 return false;
1205
1206 return true;
1207 }
1208 EXPORT_SYMBOL(drm_edid_is_valid);
1209
1210 #define DDC_SEGMENT_ADDR 0x30
1211 /**
1212 * drm_do_probe_ddc_edid() - get EDID information via I2C
1213 * @data: I2C device adapter
1214 * @buf: EDID data buffer to be filled
1215 * @block: 128 byte EDID block to start fetching from
1216 * @len: EDID data buffer length to fetch
1217 *
1218 * Try to fetch EDID information by calling I2C driver functions.
1219 *
1220 * Return: 0 on success or -1 on failure.
1221 */
1222 static int
1223 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1224 {
1225 struct i2c_adapter *adapter = data;
1226 unsigned char start = block * EDID_LENGTH;
1227 unsigned char segment = block >> 1;
1228 unsigned char xfers = segment ? 3 : 2;
1229 int ret, retries = 5;
1230
1231 /*
1232 * The core I2C driver will automatically retry the transfer if the
1233 * adapter reports EAGAIN. However, we find that bit-banging transfers
1234 * are susceptible to errors under a heavily loaded machine and
1235 * generate spurious NAKs and timeouts. Retrying the transfer
1236 * of the individual block a few times seems to overcome this.
1237 */
1238 do {
1239 struct i2c_msg msgs[] = {
1240 {
1241 .addr = DDC_SEGMENT_ADDR,
1242 .flags = 0,
1243 .len = 1,
1244 .buf = &segment,
1245 }, {
1246 .addr = DDC_ADDR,
1247 .flags = 0,
1248 .len = 1,
1249 .buf = &start,
1250 }, {
1251 .addr = DDC_ADDR,
1252 .flags = I2C_M_RD,
1253 .len = len,
1254 .buf = buf,
1255 }
1256 };
1257
1258 /*
1259 * Avoid sending the segment addr to not upset non-compliant
1260 * DDC monitors.
1261 */
1262 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1263
1264 if (ret == -ENXIO) {
1265 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1266 adapter->name);
1267 break;
1268 }
1269 } while (ret != xfers && --retries);
1270
1271 return ret == xfers ? 0 : -1;
1272 }
1273
1274 static void connector_bad_edid(struct drm_connector *connector,
1275 u8 *edid, int num_blocks)
1276 {
1277 int i;
1278
1279 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1280 return;
1281
1282 dev_warn(connector->dev->dev,
1283 "%s: EDID is invalid:\n",
1284 connector->name);
1285 for (i = 0; i < num_blocks; i++) {
1286 u8 *block = edid + i * EDID_LENGTH;
1287 char prefix[20];
1288
1289 if (drm_edid_is_zero(block, EDID_LENGTH))
1290 sprintf(prefix, "\t[%02x] ZERO ", i);
1291 else if (!drm_edid_block_valid(block, i, false, NULL))
1292 sprintf(prefix, "\t[%02x] BAD ", i);
1293 else
1294 sprintf(prefix, "\t[%02x] GOOD ", i);
1295
1296 print_hex_dump(KERN_WARNING,
1297 prefix, DUMP_PREFIX_NONE, 16, 1,
1298 block, EDID_LENGTH, false);
1299 }
1300 }
1301
1302 /**
1303 * drm_do_get_edid - get EDID data using a custom EDID block read function
1304 * @connector: connector we're probing
1305 * @get_edid_block: EDID block read function
1306 * @data: private data passed to the block read function
1307 *
1308 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1309 * exposes a different interface to read EDID blocks this function can be used
1310 * to get EDID data using a custom block read function.
1311 *
1312 * As in the general case the DDC bus is accessible by the kernel at the I2C
1313 * level, drivers must make all reasonable efforts to expose it as an I2C
1314 * adapter and use drm_get_edid() instead of abusing this function.
1315 *
1316 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1317 */
1318 struct edid *drm_do_get_edid(struct drm_connector *connector,
1319 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1320 size_t len),
1321 void *data)
1322 {
1323 int i, j = 0, valid_extensions = 0;
1324 u8 *edid, *new;
1325
1326 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1327 return NULL;
1328
1329 /* base block fetch */
1330 for (i = 0; i < 4; i++) {
1331 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1332 goto out;
1333 if (drm_edid_block_valid(edid, 0, false,
1334 &connector->edid_corrupt))
1335 break;
1336 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1337 connector->null_edid_counter++;
1338 goto carp;
1339 }
1340 }
1341 if (i == 4)
1342 goto carp;
1343
1344 /* if there's no extensions, we're done */
1345 valid_extensions = edid[0x7e];
1346 if (valid_extensions == 0)
1347 return (struct edid *)edid;
1348
1349 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1350 if (!new)
1351 goto out;
1352 edid = new;
1353
1354 for (j = 1; j <= edid[0x7e]; j++) {
1355 u8 *block = edid + j * EDID_LENGTH;
1356
1357 for (i = 0; i < 4; i++) {
1358 if (get_edid_block(data, block, j, EDID_LENGTH))
1359 goto out;
1360 if (drm_edid_block_valid(block, j, false, NULL))
1361 break;
1362 }
1363
1364 if (i == 4)
1365 valid_extensions--;
1366 }
1367
1368 if (valid_extensions != edid[0x7e]) {
1369 u8 *base;
1370
1371 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1372
1373 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1374 edid[0x7e] = valid_extensions;
1375
1376 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1377 if (!new)
1378 goto out;
1379
1380 base = new;
1381 for (i = 0; i <= edid[0x7e]; i++) {
1382 u8 *block = edid + i * EDID_LENGTH;
1383
1384 if (!drm_edid_block_valid(block, i, false, NULL))
1385 continue;
1386
1387 memcpy(base, block, EDID_LENGTH);
1388 base += EDID_LENGTH;
1389 }
1390
1391 kfree(edid);
1392 edid = new;
1393 }
1394
1395 return (struct edid *)edid;
1396
1397 carp:
1398 connector_bad_edid(connector, edid, 1);
1399 out:
1400 kfree(edid);
1401 return NULL;
1402 }
1403 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1404
1405 /**
1406 * drm_probe_ddc() - probe DDC presence
1407 * @adapter: I2C adapter to probe
1408 *
1409 * Return: True on success, false on failure.
1410 */
1411 bool
1412 drm_probe_ddc(struct i2c_adapter *adapter)
1413 {
1414 unsigned char out;
1415
1416 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1417 }
1418 EXPORT_SYMBOL(drm_probe_ddc);
1419
1420 /**
1421 * drm_get_edid - get EDID data, if available
1422 * @connector: connector we're probing
1423 * @adapter: I2C adapter to use for DDC
1424 *
1425 * Poke the given I2C channel to grab EDID data if possible. If found,
1426 * attach it to the connector.
1427 *
1428 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1429 */
1430 struct edid *drm_get_edid(struct drm_connector *connector,
1431 struct i2c_adapter *adapter)
1432 {
1433 struct edid *edid;
1434
1435 if (connector->force == DRM_FORCE_OFF)
1436 return NULL;
1437
1438 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1439 return NULL;
1440
1441 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1442 if (edid)
1443 drm_get_displayid(connector, edid);
1444 return edid;
1445 }
1446 EXPORT_SYMBOL(drm_get_edid);
1447
1448 /**
1449 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1450 * @connector: connector we're probing
1451 * @adapter: I2C adapter to use for DDC
1452 *
1453 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1454 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1455 * switch DDC to the GPU which is retrieving EDID.
1456 *
1457 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1458 */
1459 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1460 struct i2c_adapter *adapter)
1461 {
1462 struct pci_dev *pdev = connector->dev->pdev;
1463 struct edid *edid;
1464
1465 vga_switcheroo_lock_ddc(pdev);
1466 edid = drm_get_edid(connector, adapter);
1467 vga_switcheroo_unlock_ddc(pdev);
1468
1469 return edid;
1470 }
1471 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1472
1473 /**
1474 * drm_edid_duplicate - duplicate an EDID and the extensions
1475 * @edid: EDID to duplicate
1476 *
1477 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1478 */
1479 struct edid *drm_edid_duplicate(const struct edid *edid)
1480 {
1481 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1482 }
1483 EXPORT_SYMBOL(drm_edid_duplicate);
1484
1485 /*** EDID parsing ***/
1486
1487 /**
1488 * edid_vendor - match a string against EDID's obfuscated vendor field
1489 * @edid: EDID to match
1490 * @vendor: vendor string
1491 *
1492 * Returns true if @vendor is in @edid, false otherwise
1493 */
1494 static bool edid_vendor(struct edid *edid, const char *vendor)
1495 {
1496 char edid_vendor[3];
1497
1498 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1499 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1500 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1501 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1502
1503 return !strncmp(edid_vendor, vendor, 3);
1504 }
1505
1506 /**
1507 * edid_get_quirks - return quirk flags for a given EDID
1508 * @edid: EDID to process
1509 *
1510 * This tells subsequent routines what fixes they need to apply.
1511 */
1512 static u32 edid_get_quirks(struct edid *edid)
1513 {
1514 const struct edid_quirk *quirk;
1515 int i;
1516
1517 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1518 quirk = &edid_quirk_list[i];
1519
1520 if (edid_vendor(edid, quirk->vendor) &&
1521 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1522 return quirk->quirks;
1523 }
1524
1525 return 0;
1526 }
1527
1528 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1529 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1530
1531 /**
1532 * edid_fixup_preferred - set preferred modes based on quirk list
1533 * @connector: has mode list to fix up
1534 * @quirks: quirks list
1535 *
1536 * Walk the mode list for @connector, clearing the preferred status
1537 * on existing modes and setting it anew for the right mode ala @quirks.
1538 */
1539 static void edid_fixup_preferred(struct drm_connector *connector,
1540 u32 quirks)
1541 {
1542 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1543 int target_refresh = 0;
1544 int cur_vrefresh, preferred_vrefresh;
1545
1546 if (list_empty(&connector->probed_modes))
1547 return;
1548
1549 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1550 target_refresh = 60;
1551 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1552 target_refresh = 75;
1553
1554 preferred_mode = list_first_entry(&connector->probed_modes,
1555 struct drm_display_mode, head);
1556
1557 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1558 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1559
1560 if (cur_mode == preferred_mode)
1561 continue;
1562
1563 /* Largest mode is preferred */
1564 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1565 preferred_mode = cur_mode;
1566
1567 cur_vrefresh = cur_mode->vrefresh ?
1568 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1569 preferred_vrefresh = preferred_mode->vrefresh ?
1570 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1571 /* At a given size, try to get closest to target refresh */
1572 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1573 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1574 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1575 preferred_mode = cur_mode;
1576 }
1577 }
1578
1579 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1580 }
1581
1582 static bool
1583 mode_is_rb(const struct drm_display_mode *mode)
1584 {
1585 return (mode->htotal - mode->hdisplay == 160) &&
1586 (mode->hsync_end - mode->hdisplay == 80) &&
1587 (mode->hsync_end - mode->hsync_start == 32) &&
1588 (mode->vsync_start - mode->vdisplay == 3);
1589 }
1590
1591 /*
1592 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1593 * @dev: Device to duplicate against
1594 * @hsize: Mode width
1595 * @vsize: Mode height
1596 * @fresh: Mode refresh rate
1597 * @rb: Mode reduced-blanking-ness
1598 *
1599 * Walk the DMT mode list looking for a match for the given parameters.
1600 *
1601 * Return: A newly allocated copy of the mode, or NULL if not found.
1602 */
1603 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1604 int hsize, int vsize, int fresh,
1605 bool rb)
1606 {
1607 int i;
1608
1609 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1610 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1611 if (hsize != ptr->hdisplay)
1612 continue;
1613 if (vsize != ptr->vdisplay)
1614 continue;
1615 if (fresh != drm_mode_vrefresh(ptr))
1616 continue;
1617 if (rb != mode_is_rb(ptr))
1618 continue;
1619
1620 return drm_mode_duplicate(dev, ptr);
1621 }
1622
1623 return NULL;
1624 }
1625 EXPORT_SYMBOL(drm_mode_find_dmt);
1626
1627 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1628
1629 static void
1630 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1631 {
1632 int i, n = 0;
1633 u8 d = ext[0x02];
1634 u8 *det_base = ext + d;
1635
1636 n = (127 - d) / 18;
1637 for (i = 0; i < n; i++)
1638 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1639 }
1640
1641 static void
1642 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1643 {
1644 unsigned int i, n = min((int)ext[0x02], 6);
1645 u8 *det_base = ext + 5;
1646
1647 if (ext[0x01] != 1)
1648 return; /* unknown version */
1649
1650 for (i = 0; i < n; i++)
1651 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1652 }
1653
1654 static void
1655 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1656 {
1657 int i;
1658 struct edid *edid = (struct edid *)raw_edid;
1659
1660 if (edid == NULL)
1661 return;
1662
1663 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1664 cb(&(edid->detailed_timings[i]), closure);
1665
1666 for (i = 1; i <= raw_edid[0x7e]; i++) {
1667 u8 *ext = raw_edid + (i * EDID_LENGTH);
1668 switch (*ext) {
1669 case CEA_EXT:
1670 cea_for_each_detailed_block(ext, cb, closure);
1671 break;
1672 case VTB_EXT:
1673 vtb_for_each_detailed_block(ext, cb, closure);
1674 break;
1675 default:
1676 break;
1677 }
1678 }
1679 }
1680
1681 static void
1682 is_rb(struct detailed_timing *t, void *data)
1683 {
1684 u8 *r = (u8 *)t;
1685 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1686 if (r[15] & 0x10)
1687 *(bool *)data = true;
1688 }
1689
1690 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1691 static bool
1692 drm_monitor_supports_rb(struct edid *edid)
1693 {
1694 if (edid->revision >= 4) {
1695 bool ret = false;
1696 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1697 return ret;
1698 }
1699
1700 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1701 }
1702
1703 static void
1704 find_gtf2(struct detailed_timing *t, void *data)
1705 {
1706 u8 *r = (u8 *)t;
1707 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1708 *(u8 **)data = r;
1709 }
1710
1711 /* Secondary GTF curve kicks in above some break frequency */
1712 static int
1713 drm_gtf2_hbreak(struct edid *edid)
1714 {
1715 u8 *r = NULL;
1716 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1717 return r ? (r[12] * 2) : 0;
1718 }
1719
1720 static int
1721 drm_gtf2_2c(struct edid *edid)
1722 {
1723 u8 *r = NULL;
1724 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1725 return r ? r[13] : 0;
1726 }
1727
1728 static int
1729 drm_gtf2_m(struct edid *edid)
1730 {
1731 u8 *r = NULL;
1732 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1733 return r ? (r[15] << 8) + r[14] : 0;
1734 }
1735
1736 static int
1737 drm_gtf2_k(struct edid *edid)
1738 {
1739 u8 *r = NULL;
1740 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1741 return r ? r[16] : 0;
1742 }
1743
1744 static int
1745 drm_gtf2_2j(struct edid *edid)
1746 {
1747 u8 *r = NULL;
1748 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1749 return r ? r[17] : 0;
1750 }
1751
1752 /**
1753 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1754 * @edid: EDID block to scan
1755 */
1756 static int standard_timing_level(struct edid *edid)
1757 {
1758 if (edid->revision >= 2) {
1759 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1760 return LEVEL_CVT;
1761 if (drm_gtf2_hbreak(edid))
1762 return LEVEL_GTF2;
1763 return LEVEL_GTF;
1764 }
1765 return LEVEL_DMT;
1766 }
1767
1768 /*
1769 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1770 * monitors fill with ascii space (0x20) instead.
1771 */
1772 static int
1773 bad_std_timing(u8 a, u8 b)
1774 {
1775 return (a == 0x00 && b == 0x00) ||
1776 (a == 0x01 && b == 0x01) ||
1777 (a == 0x20 && b == 0x20);
1778 }
1779
1780 /**
1781 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1782 * @connector: connector of for the EDID block
1783 * @edid: EDID block to scan
1784 * @t: standard timing params
1785 *
1786 * Take the standard timing params (in this case width, aspect, and refresh)
1787 * and convert them into a real mode using CVT/GTF/DMT.
1788 */
1789 static struct drm_display_mode *
1790 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1791 struct std_timing *t)
1792 {
1793 struct drm_device *dev = connector->dev;
1794 struct drm_display_mode *m, *mode = NULL;
1795 int hsize, vsize;
1796 int vrefresh_rate;
1797 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1798 >> EDID_TIMING_ASPECT_SHIFT;
1799 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1800 >> EDID_TIMING_VFREQ_SHIFT;
1801 int timing_level = standard_timing_level(edid);
1802
1803 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1804 return NULL;
1805
1806 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1807 hsize = t->hsize * 8 + 248;
1808 /* vrefresh_rate = vfreq + 60 */
1809 vrefresh_rate = vfreq + 60;
1810 /* the vdisplay is calculated based on the aspect ratio */
1811 if (aspect_ratio == 0) {
1812 if (edid->revision < 3)
1813 vsize = hsize;
1814 else
1815 vsize = (hsize * 10) / 16;
1816 } else if (aspect_ratio == 1)
1817 vsize = (hsize * 3) / 4;
1818 else if (aspect_ratio == 2)
1819 vsize = (hsize * 4) / 5;
1820 else
1821 vsize = (hsize * 9) / 16;
1822
1823 /* HDTV hack, part 1 */
1824 if (vrefresh_rate == 60 &&
1825 ((hsize == 1360 && vsize == 765) ||
1826 (hsize == 1368 && vsize == 769))) {
1827 hsize = 1366;
1828 vsize = 768;
1829 }
1830
1831 /*
1832 * If this connector already has a mode for this size and refresh
1833 * rate (because it came from detailed or CVT info), use that
1834 * instead. This way we don't have to guess at interlace or
1835 * reduced blanking.
1836 */
1837 list_for_each_entry(m, &connector->probed_modes, head)
1838 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1839 drm_mode_vrefresh(m) == vrefresh_rate)
1840 return NULL;
1841
1842 /* HDTV hack, part 2 */
1843 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1844 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1845 false);
1846 mode->hdisplay = 1366;
1847 mode->hsync_start = mode->hsync_start - 1;
1848 mode->hsync_end = mode->hsync_end - 1;
1849 return mode;
1850 }
1851
1852 /* check whether it can be found in default mode table */
1853 if (drm_monitor_supports_rb(edid)) {
1854 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1855 true);
1856 if (mode)
1857 return mode;
1858 }
1859 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1860 if (mode)
1861 return mode;
1862
1863 /* okay, generate it */
1864 switch (timing_level) {
1865 case LEVEL_DMT:
1866 break;
1867 case LEVEL_GTF:
1868 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1869 break;
1870 case LEVEL_GTF2:
1871 /*
1872 * This is potentially wrong if there's ever a monitor with
1873 * more than one ranges section, each claiming a different
1874 * secondary GTF curve. Please don't do that.
1875 */
1876 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1877 if (!mode)
1878 return NULL;
1879 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1880 drm_mode_destroy(dev, mode);
1881 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1882 vrefresh_rate, 0, 0,
1883 drm_gtf2_m(edid),
1884 drm_gtf2_2c(edid),
1885 drm_gtf2_k(edid),
1886 drm_gtf2_2j(edid));
1887 }
1888 break;
1889 case LEVEL_CVT:
1890 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1891 false);
1892 break;
1893 }
1894 return mode;
1895 }
1896
1897 /*
1898 * EDID is delightfully ambiguous about how interlaced modes are to be
1899 * encoded. Our internal representation is of frame height, but some
1900 * HDTV detailed timings are encoded as field height.
1901 *
1902 * The format list here is from CEA, in frame size. Technically we
1903 * should be checking refresh rate too. Whatever.
1904 */
1905 static void
1906 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1907 struct detailed_pixel_timing *pt)
1908 {
1909 int i;
1910 static const struct {
1911 int w, h;
1912 } cea_interlaced[] = {
1913 { 1920, 1080 },
1914 { 720, 480 },
1915 { 1440, 480 },
1916 { 2880, 480 },
1917 { 720, 576 },
1918 { 1440, 576 },
1919 { 2880, 576 },
1920 };
1921
1922 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1923 return;
1924
1925 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1926 if ((mode->hdisplay == cea_interlaced[i].w) &&
1927 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1928 mode->vdisplay *= 2;
1929 mode->vsync_start *= 2;
1930 mode->vsync_end *= 2;
1931 mode->vtotal *= 2;
1932 mode->vtotal |= 1;
1933 }
1934 }
1935
1936 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1937 }
1938
1939 /**
1940 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1941 * @dev: DRM device (needed to create new mode)
1942 * @edid: EDID block
1943 * @timing: EDID detailed timing info
1944 * @quirks: quirks to apply
1945 *
1946 * An EDID detailed timing block contains enough info for us to create and
1947 * return a new struct drm_display_mode.
1948 */
1949 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1950 struct edid *edid,
1951 struct detailed_timing *timing,
1952 u32 quirks)
1953 {
1954 struct drm_display_mode *mode;
1955 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
1956 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1957 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1958 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1959 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
1960 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1961 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1962 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
1963 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1964
1965 /* ignore tiny modes */
1966 if (hactive < 64 || vactive < 64)
1967 return NULL;
1968
1969 if (pt->misc & DRM_EDID_PT_STEREO) {
1970 DRM_DEBUG_KMS("stereo mode not supported\n");
1971 return NULL;
1972 }
1973 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
1974 DRM_DEBUG_KMS("composite sync not supported\n");
1975 }
1976
1977 /* it is incorrect if hsync/vsync width is zero */
1978 if (!hsync_pulse_width || !vsync_pulse_width) {
1979 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1980 "Wrong Hsync/Vsync pulse width\n");
1981 return NULL;
1982 }
1983
1984 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1985 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1986 if (!mode)
1987 return NULL;
1988
1989 goto set_size;
1990 }
1991
1992 mode = drm_mode_create(dev);
1993 if (!mode)
1994 return NULL;
1995
1996 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
1997 timing->pixel_clock = cpu_to_le16(1088);
1998
1999 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2000
2001 mode->hdisplay = hactive;
2002 mode->hsync_start = mode->hdisplay + hsync_offset;
2003 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2004 mode->htotal = mode->hdisplay + hblank;
2005
2006 mode->vdisplay = vactive;
2007 mode->vsync_start = mode->vdisplay + vsync_offset;
2008 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2009 mode->vtotal = mode->vdisplay + vblank;
2010
2011 /* Some EDIDs have bogus h/vtotal values */
2012 if (mode->hsync_end > mode->htotal)
2013 mode->htotal = mode->hsync_end + 1;
2014 if (mode->vsync_end > mode->vtotal)
2015 mode->vtotal = mode->vsync_end + 1;
2016
2017 drm_mode_do_interlace_quirk(mode, pt);
2018
2019 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2020 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2021 }
2022
2023 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2024 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2025 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2026 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2027
2028 set_size:
2029 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2030 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2031
2032 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2033 mode->width_mm *= 10;
2034 mode->height_mm *= 10;
2035 }
2036
2037 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2038 mode->width_mm = edid->width_cm * 10;
2039 mode->height_mm = edid->height_cm * 10;
2040 }
2041
2042 mode->type = DRM_MODE_TYPE_DRIVER;
2043 mode->vrefresh = drm_mode_vrefresh(mode);
2044 drm_mode_set_name(mode);
2045
2046 return mode;
2047 }
2048
2049 static bool
2050 mode_in_hsync_range(const struct drm_display_mode *mode,
2051 struct edid *edid, u8 *t)
2052 {
2053 int hsync, hmin, hmax;
2054
2055 hmin = t[7];
2056 if (edid->revision >= 4)
2057 hmin += ((t[4] & 0x04) ? 255 : 0);
2058 hmax = t[8];
2059 if (edid->revision >= 4)
2060 hmax += ((t[4] & 0x08) ? 255 : 0);
2061 hsync = drm_mode_hsync(mode);
2062
2063 return (hsync <= hmax && hsync >= hmin);
2064 }
2065
2066 static bool
2067 mode_in_vsync_range(const struct drm_display_mode *mode,
2068 struct edid *edid, u8 *t)
2069 {
2070 int vsync, vmin, vmax;
2071
2072 vmin = t[5];
2073 if (edid->revision >= 4)
2074 vmin += ((t[4] & 0x01) ? 255 : 0);
2075 vmax = t[6];
2076 if (edid->revision >= 4)
2077 vmax += ((t[4] & 0x02) ? 255 : 0);
2078 vsync = drm_mode_vrefresh(mode);
2079
2080 return (vsync <= vmax && vsync >= vmin);
2081 }
2082
2083 static u32
2084 range_pixel_clock(struct edid *edid, u8 *t)
2085 {
2086 /* unspecified */
2087 if (t[9] == 0 || t[9] == 255)
2088 return 0;
2089
2090 /* 1.4 with CVT support gives us real precision, yay */
2091 if (edid->revision >= 4 && t[10] == 0x04)
2092 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2093
2094 /* 1.3 is pathetic, so fuzz up a bit */
2095 return t[9] * 10000 + 5001;
2096 }
2097
2098 static bool
2099 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2100 struct detailed_timing *timing)
2101 {
2102 u32 max_clock;
2103 u8 *t = (u8 *)timing;
2104
2105 if (!mode_in_hsync_range(mode, edid, t))
2106 return false;
2107
2108 if (!mode_in_vsync_range(mode, edid, t))
2109 return false;
2110
2111 if ((max_clock = range_pixel_clock(edid, t)))
2112 if (mode->clock > max_clock)
2113 return false;
2114
2115 /* 1.4 max horizontal check */
2116 if (edid->revision >= 4 && t[10] == 0x04)
2117 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2118 return false;
2119
2120 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2121 return false;
2122
2123 return true;
2124 }
2125
2126 static bool valid_inferred_mode(const struct drm_connector *connector,
2127 const struct drm_display_mode *mode)
2128 {
2129 const struct drm_display_mode *m;
2130 bool ok = false;
2131
2132 list_for_each_entry(m, &connector->probed_modes, head) {
2133 if (mode->hdisplay == m->hdisplay &&
2134 mode->vdisplay == m->vdisplay &&
2135 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2136 return false; /* duplicated */
2137 if (mode->hdisplay <= m->hdisplay &&
2138 mode->vdisplay <= m->vdisplay)
2139 ok = true;
2140 }
2141 return ok;
2142 }
2143
2144 static int
2145 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2146 struct detailed_timing *timing)
2147 {
2148 int i, modes = 0;
2149 struct drm_display_mode *newmode;
2150 struct drm_device *dev = connector->dev;
2151
2152 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2153 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2154 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2155 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2156 if (newmode) {
2157 drm_mode_probed_add(connector, newmode);
2158 modes++;
2159 }
2160 }
2161 }
2162
2163 return modes;
2164 }
2165
2166 /* fix up 1366x768 mode from 1368x768;
2167 * GFT/CVT can't express 1366 width which isn't dividable by 8
2168 */
2169 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2170 {
2171 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2172 mode->hdisplay = 1366;
2173 mode->hsync_start--;
2174 mode->hsync_end--;
2175 drm_mode_set_name(mode);
2176 }
2177 }
2178
2179 static int
2180 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2181 struct detailed_timing *timing)
2182 {
2183 int i, modes = 0;
2184 struct drm_display_mode *newmode;
2185 struct drm_device *dev = connector->dev;
2186
2187 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2188 const struct minimode *m = &extra_modes[i];
2189 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2190 if (!newmode)
2191 return modes;
2192
2193 drm_mode_fixup_1366x768(newmode);
2194 if (!mode_in_range(newmode, edid, timing) ||
2195 !valid_inferred_mode(connector, newmode)) {
2196 drm_mode_destroy(dev, newmode);
2197 continue;
2198 }
2199
2200 drm_mode_probed_add(connector, newmode);
2201 modes++;
2202 }
2203
2204 return modes;
2205 }
2206
2207 static int
2208 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2209 struct detailed_timing *timing)
2210 {
2211 int i, modes = 0;
2212 struct drm_display_mode *newmode;
2213 struct drm_device *dev = connector->dev;
2214 bool rb = drm_monitor_supports_rb(edid);
2215
2216 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2217 const struct minimode *m = &extra_modes[i];
2218 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2219 if (!newmode)
2220 return modes;
2221
2222 drm_mode_fixup_1366x768(newmode);
2223 if (!mode_in_range(newmode, edid, timing) ||
2224 !valid_inferred_mode(connector, newmode)) {
2225 drm_mode_destroy(dev, newmode);
2226 continue;
2227 }
2228
2229 drm_mode_probed_add(connector, newmode);
2230 modes++;
2231 }
2232
2233 return modes;
2234 }
2235
2236 static void
2237 do_inferred_modes(struct detailed_timing *timing, void *c)
2238 {
2239 struct detailed_mode_closure *closure = c;
2240 struct detailed_non_pixel *data = &timing->data.other_data;
2241 struct detailed_data_monitor_range *range = &data->data.range;
2242
2243 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2244 return;
2245
2246 closure->modes += drm_dmt_modes_for_range(closure->connector,
2247 closure->edid,
2248 timing);
2249
2250 if (!version_greater(closure->edid, 1, 1))
2251 return; /* GTF not defined yet */
2252
2253 switch (range->flags) {
2254 case 0x02: /* secondary gtf, XXX could do more */
2255 case 0x00: /* default gtf */
2256 closure->modes += drm_gtf_modes_for_range(closure->connector,
2257 closure->edid,
2258 timing);
2259 break;
2260 case 0x04: /* cvt, only in 1.4+ */
2261 if (!version_greater(closure->edid, 1, 3))
2262 break;
2263
2264 closure->modes += drm_cvt_modes_for_range(closure->connector,
2265 closure->edid,
2266 timing);
2267 break;
2268 case 0x01: /* just the ranges, no formula */
2269 default:
2270 break;
2271 }
2272 }
2273
2274 static int
2275 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2276 {
2277 struct detailed_mode_closure closure = {
2278 .connector = connector,
2279 .edid = edid,
2280 };
2281
2282 if (version_greater(edid, 1, 0))
2283 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2284 &closure);
2285
2286 return closure.modes;
2287 }
2288
2289 static int
2290 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2291 {
2292 int i, j, m, modes = 0;
2293 struct drm_display_mode *mode;
2294 u8 *est = ((u8 *)timing) + 6;
2295
2296 for (i = 0; i < 6; i++) {
2297 for (j = 7; j >= 0; j--) {
2298 m = (i * 8) + (7 - j);
2299 if (m >= ARRAY_SIZE(est3_modes))
2300 break;
2301 if (est[i] & (1 << j)) {
2302 mode = drm_mode_find_dmt(connector->dev,
2303 est3_modes[m].w,
2304 est3_modes[m].h,
2305 est3_modes[m].r,
2306 est3_modes[m].rb);
2307 if (mode) {
2308 drm_mode_probed_add(connector, mode);
2309 modes++;
2310 }
2311 }
2312 }
2313 }
2314
2315 return modes;
2316 }
2317
2318 static void
2319 do_established_modes(struct detailed_timing *timing, void *c)
2320 {
2321 struct detailed_mode_closure *closure = c;
2322 struct detailed_non_pixel *data = &timing->data.other_data;
2323
2324 if (data->type == EDID_DETAIL_EST_TIMINGS)
2325 closure->modes += drm_est3_modes(closure->connector, timing);
2326 }
2327
2328 /**
2329 * add_established_modes - get est. modes from EDID and add them
2330 * @connector: connector to add mode(s) to
2331 * @edid: EDID block to scan
2332 *
2333 * Each EDID block contains a bitmap of the supported "established modes" list
2334 * (defined above). Tease them out and add them to the global modes list.
2335 */
2336 static int
2337 add_established_modes(struct drm_connector *connector, struct edid *edid)
2338 {
2339 struct drm_device *dev = connector->dev;
2340 unsigned long est_bits = edid->established_timings.t1 |
2341 (edid->established_timings.t2 << 8) |
2342 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2343 int i, modes = 0;
2344 struct detailed_mode_closure closure = {
2345 .connector = connector,
2346 .edid = edid,
2347 };
2348
2349 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2350 if (est_bits & (1<<i)) {
2351 struct drm_display_mode *newmode;
2352 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2353 if (newmode) {
2354 drm_mode_probed_add(connector, newmode);
2355 modes++;
2356 }
2357 }
2358 }
2359
2360 if (version_greater(edid, 1, 0))
2361 drm_for_each_detailed_block((u8 *)edid,
2362 do_established_modes, &closure);
2363
2364 return modes + closure.modes;
2365 }
2366
2367 static void
2368 do_standard_modes(struct detailed_timing *timing, void *c)
2369 {
2370 struct detailed_mode_closure *closure = c;
2371 struct detailed_non_pixel *data = &timing->data.other_data;
2372 struct drm_connector *connector = closure->connector;
2373 struct edid *edid = closure->edid;
2374
2375 if (data->type == EDID_DETAIL_STD_MODES) {
2376 int i;
2377 for (i = 0; i < 6; i++) {
2378 struct std_timing *std;
2379 struct drm_display_mode *newmode;
2380
2381 std = &data->data.timings[i];
2382 newmode = drm_mode_std(connector, edid, std);
2383 if (newmode) {
2384 drm_mode_probed_add(connector, newmode);
2385 closure->modes++;
2386 }
2387 }
2388 }
2389 }
2390
2391 /**
2392 * add_standard_modes - get std. modes from EDID and add them
2393 * @connector: connector to add mode(s) to
2394 * @edid: EDID block to scan
2395 *
2396 * Standard modes can be calculated using the appropriate standard (DMT,
2397 * GTF or CVT. Grab them from @edid and add them to the list.
2398 */
2399 static int
2400 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2401 {
2402 int i, modes = 0;
2403 struct detailed_mode_closure closure = {
2404 .connector = connector,
2405 .edid = edid,
2406 };
2407
2408 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2409 struct drm_display_mode *newmode;
2410
2411 newmode = drm_mode_std(connector, edid,
2412 &edid->standard_timings[i]);
2413 if (newmode) {
2414 drm_mode_probed_add(connector, newmode);
2415 modes++;
2416 }
2417 }
2418
2419 if (version_greater(edid, 1, 0))
2420 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2421 &closure);
2422
2423 /* XXX should also look for standard codes in VTB blocks */
2424
2425 return modes + closure.modes;
2426 }
2427
2428 static int drm_cvt_modes(struct drm_connector *connector,
2429 struct detailed_timing *timing)
2430 {
2431 int i, j, modes = 0;
2432 struct drm_display_mode *newmode;
2433 struct drm_device *dev = connector->dev;
2434 struct cvt_timing *cvt;
2435 const int rates[] = { 60, 85, 75, 60, 50 };
2436 const u8 empty[3] = { 0, 0, 0 };
2437
2438 for (i = 0; i < 4; i++) {
2439 int uninitialized_var(width), height;
2440 cvt = &(timing->data.other_data.data.cvt[i]);
2441
2442 if (!memcmp(cvt->code, empty, 3))
2443 continue;
2444
2445 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2446 switch (cvt->code[1] & 0x0c) {
2447 case 0x00:
2448 width = height * 4 / 3;
2449 break;
2450 case 0x04:
2451 width = height * 16 / 9;
2452 break;
2453 case 0x08:
2454 width = height * 16 / 10;
2455 break;
2456 case 0x0c:
2457 width = height * 15 / 9;
2458 break;
2459 }
2460
2461 for (j = 1; j < 5; j++) {
2462 if (cvt->code[2] & (1 << j)) {
2463 newmode = drm_cvt_mode(dev, width, height,
2464 rates[j], j == 0,
2465 false, false);
2466 if (newmode) {
2467 drm_mode_probed_add(connector, newmode);
2468 modes++;
2469 }
2470 }
2471 }
2472 }
2473
2474 return modes;
2475 }
2476
2477 static void
2478 do_cvt_mode(struct detailed_timing *timing, void *c)
2479 {
2480 struct detailed_mode_closure *closure = c;
2481 struct detailed_non_pixel *data = &timing->data.other_data;
2482
2483 if (data->type == EDID_DETAIL_CVT_3BYTE)
2484 closure->modes += drm_cvt_modes(closure->connector, timing);
2485 }
2486
2487 static int
2488 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2489 {
2490 struct detailed_mode_closure closure = {
2491 .connector = connector,
2492 .edid = edid,
2493 };
2494
2495 if (version_greater(edid, 1, 2))
2496 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2497
2498 /* XXX should also look for CVT codes in VTB blocks */
2499
2500 return closure.modes;
2501 }
2502
2503 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2504
2505 static void
2506 do_detailed_mode(struct detailed_timing *timing, void *c)
2507 {
2508 struct detailed_mode_closure *closure = c;
2509 struct drm_display_mode *newmode;
2510
2511 if (timing->pixel_clock) {
2512 newmode = drm_mode_detailed(closure->connector->dev,
2513 closure->edid, timing,
2514 closure->quirks);
2515 if (!newmode)
2516 return;
2517
2518 if (closure->preferred)
2519 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2520
2521 /*
2522 * Detailed modes are limited to 10kHz pixel clock resolution,
2523 * so fix up anything that looks like CEA/HDMI mode, but the clock
2524 * is just slightly off.
2525 */
2526 fixup_detailed_cea_mode_clock(newmode);
2527
2528 drm_mode_probed_add(closure->connector, newmode);
2529 closure->modes++;
2530 closure->preferred = 0;
2531 }
2532 }
2533
2534 /*
2535 * add_detailed_modes - Add modes from detailed timings
2536 * @connector: attached connector
2537 * @edid: EDID block to scan
2538 * @quirks: quirks to apply
2539 */
2540 static int
2541 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2542 u32 quirks)
2543 {
2544 struct detailed_mode_closure closure = {
2545 .connector = connector,
2546 .edid = edid,
2547 .preferred = 1,
2548 .quirks = quirks,
2549 };
2550
2551 if (closure.preferred && !version_greater(edid, 1, 3))
2552 closure.preferred =
2553 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2554
2555 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2556
2557 return closure.modes;
2558 }
2559
2560 #define AUDIO_BLOCK 0x01
2561 #define VIDEO_BLOCK 0x02
2562 #define VENDOR_BLOCK 0x03
2563 #define SPEAKER_BLOCK 0x04
2564 #define VIDEO_CAPABILITY_BLOCK 0x07
2565 #define EDID_BASIC_AUDIO (1 << 6)
2566 #define EDID_CEA_YCRCB444 (1 << 5)
2567 #define EDID_CEA_YCRCB422 (1 << 4)
2568 #define EDID_CEA_VCDB_QS (1 << 6)
2569
2570 /*
2571 * Search EDID for CEA extension block.
2572 */
2573 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2574 {
2575 u8 *edid_ext = NULL;
2576 int i;
2577
2578 /* No EDID or EDID extensions */
2579 if (edid == NULL || edid->extensions == 0)
2580 return NULL;
2581
2582 /* Find CEA extension */
2583 for (i = 0; i < edid->extensions; i++) {
2584 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2585 if (edid_ext[0] == ext_id)
2586 break;
2587 }
2588
2589 if (i == edid->extensions)
2590 return NULL;
2591
2592 return edid_ext;
2593 }
2594
2595 static u8 *drm_find_cea_extension(struct edid *edid)
2596 {
2597 return drm_find_edid_extension(edid, CEA_EXT);
2598 }
2599
2600 static u8 *drm_find_displayid_extension(struct edid *edid)
2601 {
2602 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2603 }
2604
2605 /*
2606 * Calculate the alternate clock for the CEA mode
2607 * (60Hz vs. 59.94Hz etc.)
2608 */
2609 static unsigned int
2610 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2611 {
2612 unsigned int clock = cea_mode->clock;
2613
2614 if (cea_mode->vrefresh % 6 != 0)
2615 return clock;
2616
2617 /*
2618 * edid_cea_modes contains the 59.94Hz
2619 * variant for 240 and 480 line modes,
2620 * and the 60Hz variant otherwise.
2621 */
2622 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2623 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2624 else
2625 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2626
2627 return clock;
2628 }
2629
2630 static bool
2631 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2632 {
2633 /*
2634 * For certain VICs the spec allows the vertical
2635 * front porch to vary by one or two lines.
2636 *
2637 * cea_modes[] stores the variant with the shortest
2638 * vertical front porch. We can adjust the mode to
2639 * get the other variants by simply increasing the
2640 * vertical front porch length.
2641 */
2642 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2643 edid_cea_modes[9].vtotal != 262 ||
2644 edid_cea_modes[12].vtotal != 262 ||
2645 edid_cea_modes[13].vtotal != 262 ||
2646 edid_cea_modes[23].vtotal != 312 ||
2647 edid_cea_modes[24].vtotal != 312 ||
2648 edid_cea_modes[27].vtotal != 312 ||
2649 edid_cea_modes[28].vtotal != 312);
2650
2651 if (((vic == 8 || vic == 9 ||
2652 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2653 ((vic == 23 || vic == 24 ||
2654 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2655 mode->vsync_start++;
2656 mode->vsync_end++;
2657 mode->vtotal++;
2658
2659 return true;
2660 }
2661
2662 return false;
2663 }
2664
2665 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2666 unsigned int clock_tolerance)
2667 {
2668 u8 vic;
2669
2670 if (!to_match->clock)
2671 return 0;
2672
2673 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2674 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2675 unsigned int clock1, clock2;
2676
2677 /* Check both 60Hz and 59.94Hz */
2678 clock1 = cea_mode.clock;
2679 clock2 = cea_mode_alternate_clock(&cea_mode);
2680
2681 if (abs(to_match->clock - clock1) > clock_tolerance &&
2682 abs(to_match->clock - clock2) > clock_tolerance)
2683 continue;
2684
2685 do {
2686 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2687 return vic;
2688 } while (cea_mode_alternate_timings(vic, &cea_mode));
2689 }
2690
2691 return 0;
2692 }
2693
2694 /**
2695 * drm_match_cea_mode - look for a CEA mode matching given mode
2696 * @to_match: display mode
2697 *
2698 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2699 * mode.
2700 */
2701 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2702 {
2703 u8 vic;
2704
2705 if (!to_match->clock)
2706 return 0;
2707
2708 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2709 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2710 unsigned int clock1, clock2;
2711
2712 /* Check both 60Hz and 59.94Hz */
2713 clock1 = cea_mode.clock;
2714 clock2 = cea_mode_alternate_clock(&cea_mode);
2715
2716 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2717 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2718 continue;
2719
2720 do {
2721 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2722 return vic;
2723 } while (cea_mode_alternate_timings(vic, &cea_mode));
2724 }
2725
2726 return 0;
2727 }
2728 EXPORT_SYMBOL(drm_match_cea_mode);
2729
2730 static bool drm_valid_cea_vic(u8 vic)
2731 {
2732 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2733 }
2734
2735 /**
2736 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2737 * the input VIC from the CEA mode list
2738 * @video_code: ID given to each of the CEA modes
2739 *
2740 * Returns picture aspect ratio
2741 */
2742 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2743 {
2744 return edid_cea_modes[video_code].picture_aspect_ratio;
2745 }
2746 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2747
2748 /*
2749 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2750 * specific block).
2751 *
2752 * It's almost like cea_mode_alternate_clock(), we just need to add an
2753 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2754 * one.
2755 */
2756 static unsigned int
2757 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2758 {
2759 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2760 return hdmi_mode->clock;
2761
2762 return cea_mode_alternate_clock(hdmi_mode);
2763 }
2764
2765 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2766 unsigned int clock_tolerance)
2767 {
2768 u8 vic;
2769
2770 if (!to_match->clock)
2771 return 0;
2772
2773 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2774 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2775 unsigned int clock1, clock2;
2776
2777 /* Make sure to also match alternate clocks */
2778 clock1 = hdmi_mode->clock;
2779 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2780
2781 if (abs(to_match->clock - clock1) > clock_tolerance &&
2782 abs(to_match->clock - clock2) > clock_tolerance)
2783 continue;
2784
2785 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2786 return vic;
2787 }
2788
2789 return 0;
2790 }
2791
2792 /*
2793 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2794 * @to_match: display mode
2795 *
2796 * An HDMI mode is one defined in the HDMI vendor specific block.
2797 *
2798 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2799 */
2800 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2801 {
2802 u8 vic;
2803
2804 if (!to_match->clock)
2805 return 0;
2806
2807 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2808 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2809 unsigned int clock1, clock2;
2810
2811 /* Make sure to also match alternate clocks */
2812 clock1 = hdmi_mode->clock;
2813 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2814
2815 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2816 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2817 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2818 return vic;
2819 }
2820 return 0;
2821 }
2822
2823 static bool drm_valid_hdmi_vic(u8 vic)
2824 {
2825 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2826 }
2827
2828 static int
2829 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2830 {
2831 struct drm_device *dev = connector->dev;
2832 struct drm_display_mode *mode, *tmp;
2833 LIST_HEAD(list);
2834 int modes = 0;
2835
2836 /* Don't add CEA modes if the CEA extension block is missing */
2837 if (!drm_find_cea_extension(edid))
2838 return 0;
2839
2840 /*
2841 * Go through all probed modes and create a new mode
2842 * with the alternate clock for certain CEA modes.
2843 */
2844 list_for_each_entry(mode, &connector->probed_modes, head) {
2845 const struct drm_display_mode *cea_mode = NULL;
2846 struct drm_display_mode *newmode;
2847 u8 vic = drm_match_cea_mode(mode);
2848 unsigned int clock1, clock2;
2849
2850 if (drm_valid_cea_vic(vic)) {
2851 cea_mode = &edid_cea_modes[vic];
2852 clock2 = cea_mode_alternate_clock(cea_mode);
2853 } else {
2854 vic = drm_match_hdmi_mode(mode);
2855 if (drm_valid_hdmi_vic(vic)) {
2856 cea_mode = &edid_4k_modes[vic];
2857 clock2 = hdmi_mode_alternate_clock(cea_mode);
2858 }
2859 }
2860
2861 if (!cea_mode)
2862 continue;
2863
2864 clock1 = cea_mode->clock;
2865
2866 if (clock1 == clock2)
2867 continue;
2868
2869 if (mode->clock != clock1 && mode->clock != clock2)
2870 continue;
2871
2872 newmode = drm_mode_duplicate(dev, cea_mode);
2873 if (!newmode)
2874 continue;
2875
2876 /* Carry over the stereo flags */
2877 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2878
2879 /*
2880 * The current mode could be either variant. Make
2881 * sure to pick the "other" clock for the new mode.
2882 */
2883 if (mode->clock != clock1)
2884 newmode->clock = clock1;
2885 else
2886 newmode->clock = clock2;
2887
2888 list_add_tail(&newmode->head, &list);
2889 }
2890
2891 list_for_each_entry_safe(mode, tmp, &list, head) {
2892 list_del(&mode->head);
2893 drm_mode_probed_add(connector, mode);
2894 modes++;
2895 }
2896
2897 return modes;
2898 }
2899
2900 static struct drm_display_mode *
2901 drm_display_mode_from_vic_index(struct drm_connector *connector,
2902 const u8 *video_db, u8 video_len,
2903 u8 video_index)
2904 {
2905 struct drm_device *dev = connector->dev;
2906 struct drm_display_mode *newmode;
2907 u8 vic;
2908
2909 if (video_db == NULL || video_index >= video_len)
2910 return NULL;
2911
2912 /* CEA modes are numbered 1..127 */
2913 vic = (video_db[video_index] & 127);
2914 if (!drm_valid_cea_vic(vic))
2915 return NULL;
2916
2917 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
2918 if (!newmode)
2919 return NULL;
2920
2921 newmode->vrefresh = 0;
2922
2923 return newmode;
2924 }
2925
2926 static int
2927 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2928 {
2929 int i, modes = 0;
2930
2931 for (i = 0; i < len; i++) {
2932 struct drm_display_mode *mode;
2933 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2934 if (mode) {
2935 drm_mode_probed_add(connector, mode);
2936 modes++;
2937 }
2938 }
2939
2940 return modes;
2941 }
2942
2943 struct stereo_mandatory_mode {
2944 int width, height, vrefresh;
2945 unsigned int flags;
2946 };
2947
2948 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2949 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2950 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2951 { 1920, 1080, 50,
2952 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2953 { 1920, 1080, 60,
2954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2955 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2956 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2957 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2958 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2959 };
2960
2961 static bool
2962 stereo_match_mandatory(const struct drm_display_mode *mode,
2963 const struct stereo_mandatory_mode *stereo_mode)
2964 {
2965 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2966
2967 return mode->hdisplay == stereo_mode->width &&
2968 mode->vdisplay == stereo_mode->height &&
2969 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2970 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2971 }
2972
2973 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2974 {
2975 struct drm_device *dev = connector->dev;
2976 const struct drm_display_mode *mode;
2977 struct list_head stereo_modes;
2978 int modes = 0, i;
2979
2980 INIT_LIST_HEAD(&stereo_modes);
2981
2982 list_for_each_entry(mode, &connector->probed_modes, head) {
2983 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2984 const struct stereo_mandatory_mode *mandatory;
2985 struct drm_display_mode *new_mode;
2986
2987 if (!stereo_match_mandatory(mode,
2988 &stereo_mandatory_modes[i]))
2989 continue;
2990
2991 mandatory = &stereo_mandatory_modes[i];
2992 new_mode = drm_mode_duplicate(dev, mode);
2993 if (!new_mode)
2994 continue;
2995
2996 new_mode->flags |= mandatory->flags;
2997 list_add_tail(&new_mode->head, &stereo_modes);
2998 modes++;
2999 }
3000 }
3001
3002 list_splice_tail(&stereo_modes, &connector->probed_modes);
3003
3004 return modes;
3005 }
3006
3007 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3008 {
3009 struct drm_device *dev = connector->dev;
3010 struct drm_display_mode *newmode;
3011
3012 if (!drm_valid_hdmi_vic(vic)) {
3013 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3014 return 0;
3015 }
3016
3017 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3018 if (!newmode)
3019 return 0;
3020
3021 drm_mode_probed_add(connector, newmode);
3022
3023 return 1;
3024 }
3025
3026 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3027 const u8 *video_db, u8 video_len, u8 video_index)
3028 {
3029 struct drm_display_mode *newmode;
3030 int modes = 0;
3031
3032 if (structure & (1 << 0)) {
3033 newmode = drm_display_mode_from_vic_index(connector, video_db,
3034 video_len,
3035 video_index);
3036 if (newmode) {
3037 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3038 drm_mode_probed_add(connector, newmode);
3039 modes++;
3040 }
3041 }
3042 if (structure & (1 << 6)) {
3043 newmode = drm_display_mode_from_vic_index(connector, video_db,
3044 video_len,
3045 video_index);
3046 if (newmode) {
3047 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3048 drm_mode_probed_add(connector, newmode);
3049 modes++;
3050 }
3051 }
3052 if (structure & (1 << 8)) {
3053 newmode = drm_display_mode_from_vic_index(connector, video_db,
3054 video_len,
3055 video_index);
3056 if (newmode) {
3057 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3058 drm_mode_probed_add(connector, newmode);
3059 modes++;
3060 }
3061 }
3062
3063 return modes;
3064 }
3065
3066 /*
3067 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3068 * @connector: connector corresponding to the HDMI sink
3069 * @db: start of the CEA vendor specific block
3070 * @len: length of the CEA block payload, ie. one can access up to db[len]
3071 *
3072 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3073 * also adds the stereo 3d modes when applicable.
3074 */
3075 static int
3076 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3077 const u8 *video_db, u8 video_len)
3078 {
3079 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3080 u8 vic_len, hdmi_3d_len = 0;
3081 u16 mask;
3082 u16 structure_all;
3083
3084 if (len < 8)
3085 goto out;
3086
3087 /* no HDMI_Video_Present */
3088 if (!(db[8] & (1 << 5)))
3089 goto out;
3090
3091 /* Latency_Fields_Present */
3092 if (db[8] & (1 << 7))
3093 offset += 2;
3094
3095 /* I_Latency_Fields_Present */
3096 if (db[8] & (1 << 6))
3097 offset += 2;
3098
3099 /* the declared length is not long enough for the 2 first bytes
3100 * of additional video format capabilities */
3101 if (len < (8 + offset + 2))
3102 goto out;
3103
3104 /* 3D_Present */
3105 offset++;
3106 if (db[8 + offset] & (1 << 7)) {
3107 modes += add_hdmi_mandatory_stereo_modes(connector);
3108
3109 /* 3D_Multi_present */
3110 multi_present = (db[8 + offset] & 0x60) >> 5;
3111 }
3112
3113 offset++;
3114 vic_len = db[8 + offset] >> 5;
3115 hdmi_3d_len = db[8 + offset] & 0x1f;
3116
3117 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3118 u8 vic;
3119
3120 vic = db[9 + offset + i];
3121 modes += add_hdmi_mode(connector, vic);
3122 }
3123 offset += 1 + vic_len;
3124
3125 if (multi_present == 1)
3126 multi_len = 2;
3127 else if (multi_present == 2)
3128 multi_len = 4;
3129 else
3130 multi_len = 0;
3131
3132 if (len < (8 + offset + hdmi_3d_len - 1))
3133 goto out;
3134
3135 if (hdmi_3d_len < multi_len)
3136 goto out;
3137
3138 if (multi_present == 1 || multi_present == 2) {
3139 /* 3D_Structure_ALL */
3140 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3141
3142 /* check if 3D_MASK is present */
3143 if (multi_present == 2)
3144 mask = (db[10 + offset] << 8) | db[11 + offset];
3145 else
3146 mask = 0xffff;
3147
3148 for (i = 0; i < 16; i++) {
3149 if (mask & (1 << i))
3150 modes += add_3d_struct_modes(connector,
3151 structure_all,
3152 video_db,
3153 video_len, i);
3154 }
3155 }
3156
3157 offset += multi_len;
3158
3159 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3160 int vic_index;
3161 struct drm_display_mode *newmode = NULL;
3162 unsigned int newflag = 0;
3163 bool detail_present;
3164
3165 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3166
3167 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3168 break;
3169
3170 /* 2D_VIC_order_X */
3171 vic_index = db[8 + offset + i] >> 4;
3172
3173 /* 3D_Structure_X */
3174 switch (db[8 + offset + i] & 0x0f) {
3175 case 0:
3176 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3177 break;
3178 case 6:
3179 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3180 break;
3181 case 8:
3182 /* 3D_Detail_X */
3183 if ((db[9 + offset + i] >> 4) == 1)
3184 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3185 break;
3186 }
3187
3188 if (newflag != 0) {
3189 newmode = drm_display_mode_from_vic_index(connector,
3190 video_db,
3191 video_len,
3192 vic_index);
3193
3194 if (newmode) {
3195 newmode->flags |= newflag;
3196 drm_mode_probed_add(connector, newmode);
3197 modes++;
3198 }
3199 }
3200
3201 if (detail_present)
3202 i++;
3203 }
3204
3205 out:
3206 return modes;
3207 }
3208
3209 static int
3210 cea_db_payload_len(const u8 *db)
3211 {
3212 return db[0] & 0x1f;
3213 }
3214
3215 static int
3216 cea_db_tag(const u8 *db)
3217 {
3218 return db[0] >> 5;
3219 }
3220
3221 static int
3222 cea_revision(const u8 *cea)
3223 {
3224 return cea[1];
3225 }
3226
3227 static int
3228 cea_db_offsets(const u8 *cea, int *start, int *end)
3229 {
3230 /* Data block offset in CEA extension block */
3231 *start = 4;
3232 *end = cea[2];
3233 if (*end == 0)
3234 *end = 127;
3235 if (*end < 4 || *end > 127)
3236 return -ERANGE;
3237 return 0;
3238 }
3239
3240 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3241 {
3242 int hdmi_id;
3243
3244 if (cea_db_tag(db) != VENDOR_BLOCK)
3245 return false;
3246
3247 if (cea_db_payload_len(db) < 5)
3248 return false;
3249
3250 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3251
3252 return hdmi_id == HDMI_IEEE_OUI;
3253 }
3254
3255 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3256 {
3257 unsigned int oui;
3258
3259 if (cea_db_tag(db) != VENDOR_BLOCK)
3260 return false;
3261
3262 if (cea_db_payload_len(db) < 7)
3263 return false;
3264
3265 oui = db[3] << 16 | db[2] << 8 | db[1];
3266
3267 return oui == HDMI_FORUM_IEEE_OUI;
3268 }
3269
3270 #define for_each_cea_db(cea, i, start, end) \
3271 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3272
3273 static int
3274 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3275 {
3276 const u8 *cea = drm_find_cea_extension(edid);
3277 const u8 *db, *hdmi = NULL, *video = NULL;
3278 u8 dbl, hdmi_len, video_len = 0;
3279 int modes = 0;
3280
3281 if (cea && cea_revision(cea) >= 3) {
3282 int i, start, end;
3283
3284 if (cea_db_offsets(cea, &start, &end))
3285 return 0;
3286
3287 for_each_cea_db(cea, i, start, end) {
3288 db = &cea[i];
3289 dbl = cea_db_payload_len(db);
3290
3291 if (cea_db_tag(db) == VIDEO_BLOCK) {
3292 video = db + 1;
3293 video_len = dbl;
3294 modes += do_cea_modes(connector, video, dbl);
3295 }
3296 else if (cea_db_is_hdmi_vsdb(db)) {
3297 hdmi = db;
3298 hdmi_len = dbl;
3299 }
3300 }
3301 }
3302
3303 /*
3304 * We parse the HDMI VSDB after having added the cea modes as we will
3305 * be patching their flags when the sink supports stereo 3D.
3306 */
3307 if (hdmi)
3308 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3309 video_len);
3310
3311 return modes;
3312 }
3313
3314 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3315 {
3316 const struct drm_display_mode *cea_mode;
3317 int clock1, clock2, clock;
3318 u8 vic;
3319 const char *type;
3320
3321 /*
3322 * allow 5kHz clock difference either way to account for
3323 * the 10kHz clock resolution limit of detailed timings.
3324 */
3325 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3326 if (drm_valid_cea_vic(vic)) {
3327 type = "CEA";
3328 cea_mode = &edid_cea_modes[vic];
3329 clock1 = cea_mode->clock;
3330 clock2 = cea_mode_alternate_clock(cea_mode);
3331 } else {
3332 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3333 if (drm_valid_hdmi_vic(vic)) {
3334 type = "HDMI";
3335 cea_mode = &edid_4k_modes[vic];
3336 clock1 = cea_mode->clock;
3337 clock2 = hdmi_mode_alternate_clock(cea_mode);
3338 } else {
3339 return;
3340 }
3341 }
3342
3343 /* pick whichever is closest */
3344 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3345 clock = clock1;
3346 else
3347 clock = clock2;
3348
3349 if (mode->clock == clock)
3350 return;
3351
3352 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3353 type, vic, mode->clock, clock);
3354 mode->clock = clock;
3355 }
3356
3357 static void
3358 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3359 {
3360 u8 len = cea_db_payload_len(db);
3361
3362 if (len >= 6)
3363 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3364 if (len >= 8) {
3365 connector->latency_present[0] = db[8] >> 7;
3366 connector->latency_present[1] = (db[8] >> 6) & 1;
3367 }
3368 if (len >= 9)
3369 connector->video_latency[0] = db[9];
3370 if (len >= 10)
3371 connector->audio_latency[0] = db[10];
3372 if (len >= 11)
3373 connector->video_latency[1] = db[11];
3374 if (len >= 12)
3375 connector->audio_latency[1] = db[12];
3376
3377 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3378 "video latency %d %d, "
3379 "audio latency %d %d\n",
3380 connector->latency_present[0],
3381 connector->latency_present[1],
3382 connector->video_latency[0],
3383 connector->video_latency[1],
3384 connector->audio_latency[0],
3385 connector->audio_latency[1]);
3386 }
3387
3388 static void
3389 monitor_name(struct detailed_timing *t, void *data)
3390 {
3391 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3392 *(u8 **)data = t->data.other_data.data.str.str;
3393 }
3394
3395 static int get_monitor_name(struct edid *edid, char name[13])
3396 {
3397 char *edid_name = NULL;
3398 int mnl;
3399
3400 if (!edid || !name)
3401 return 0;
3402
3403 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3404 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3405 if (edid_name[mnl] == 0x0a)
3406 break;
3407
3408 name[mnl] = edid_name[mnl];
3409 }
3410
3411 return mnl;
3412 }
3413
3414 /**
3415 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3416 * @edid: monitor EDID information
3417 * @name: pointer to a character array to hold the name of the monitor
3418 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3419 *
3420 */
3421 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3422 {
3423 int name_length;
3424 char buf[13];
3425
3426 if (bufsize <= 0)
3427 return;
3428
3429 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3430 memcpy(name, buf, name_length);
3431 name[name_length] = '\0';
3432 }
3433 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3434
3435 /**
3436 * drm_edid_to_eld - build ELD from EDID
3437 * @connector: connector corresponding to the HDMI/DP sink
3438 * @edid: EDID to parse
3439 *
3440 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3441 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3442 * fill in.
3443 */
3444 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3445 {
3446 uint8_t *eld = connector->eld;
3447 u8 *cea;
3448 u8 *db;
3449 int total_sad_count = 0;
3450 int mnl;
3451 int dbl;
3452
3453 memset(eld, 0, sizeof(connector->eld));
3454
3455 connector->latency_present[0] = false;
3456 connector->latency_present[1] = false;
3457 connector->video_latency[0] = 0;
3458 connector->audio_latency[0] = 0;
3459 connector->video_latency[1] = 0;
3460 connector->audio_latency[1] = 0;
3461
3462 if (!edid)
3463 return;
3464
3465 cea = drm_find_cea_extension(edid);
3466 if (!cea) {
3467 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3468 return;
3469 }
3470
3471 mnl = get_monitor_name(edid, eld + 20);
3472
3473 eld[4] = (cea[1] << 5) | mnl;
3474 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3475
3476 eld[0] = 2 << 3; /* ELD version: 2 */
3477
3478 eld[16] = edid->mfg_id[0];
3479 eld[17] = edid->mfg_id[1];
3480 eld[18] = edid->prod_code[0];
3481 eld[19] = edid->prod_code[1];
3482
3483 if (cea_revision(cea) >= 3) {
3484 int i, start, end;
3485
3486 if (cea_db_offsets(cea, &start, &end)) {
3487 start = 0;
3488 end = 0;
3489 }
3490
3491 for_each_cea_db(cea, i, start, end) {
3492 db = &cea[i];
3493 dbl = cea_db_payload_len(db);
3494
3495 switch (cea_db_tag(db)) {
3496 int sad_count;
3497
3498 case AUDIO_BLOCK:
3499 /* Audio Data Block, contains SADs */
3500 sad_count = min(dbl / 3, 15 - total_sad_count);
3501 if (sad_count >= 1)
3502 memcpy(eld + 20 + mnl + total_sad_count * 3,
3503 &db[1], sad_count * 3);
3504 total_sad_count += sad_count;
3505 break;
3506 case SPEAKER_BLOCK:
3507 /* Speaker Allocation Data Block */
3508 if (dbl >= 1)
3509 eld[7] = db[1];
3510 break;
3511 case VENDOR_BLOCK:
3512 /* HDMI Vendor-Specific Data Block */
3513 if (cea_db_is_hdmi_vsdb(db))
3514 drm_parse_hdmi_vsdb_audio(connector, db);
3515 break;
3516 default:
3517 break;
3518 }
3519 }
3520 }
3521 eld[5] |= total_sad_count << 4;
3522
3523 eld[DRM_ELD_BASELINE_ELD_LEN] =
3524 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3525
3526 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3527 drm_eld_size(eld), total_sad_count);
3528 }
3529 EXPORT_SYMBOL(drm_edid_to_eld);
3530
3531 /**
3532 * drm_edid_to_sad - extracts SADs from EDID
3533 * @edid: EDID to parse
3534 * @sads: pointer that will be set to the extracted SADs
3535 *
3536 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3537 *
3538 * Note: The returned pointer needs to be freed using kfree().
3539 *
3540 * Return: The number of found SADs or negative number on error.
3541 */
3542 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3543 {
3544 int count = 0;
3545 int i, start, end, dbl;
3546 u8 *cea;
3547
3548 cea = drm_find_cea_extension(edid);
3549 if (!cea) {
3550 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3551 return -ENOENT;
3552 }
3553
3554 if (cea_revision(cea) < 3) {
3555 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3556 return -ENOTSUPP;
3557 }
3558
3559 if (cea_db_offsets(cea, &start, &end)) {
3560 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3561 return -EPROTO;
3562 }
3563
3564 for_each_cea_db(cea, i, start, end) {
3565 u8 *db = &cea[i];
3566
3567 if (cea_db_tag(db) == AUDIO_BLOCK) {
3568 int j;
3569 dbl = cea_db_payload_len(db);
3570
3571 count = dbl / 3; /* SAD is 3B */
3572 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3573 if (!*sads)
3574 return -ENOMEM;
3575 for (j = 0; j < count; j++) {
3576 u8 *sad = &db[1 + j * 3];
3577
3578 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3579 (*sads)[j].channels = sad[0] & 0x7;
3580 (*sads)[j].freq = sad[1] & 0x7F;
3581 (*sads)[j].byte2 = sad[2];
3582 }
3583 break;
3584 }
3585 }
3586
3587 return count;
3588 }
3589 EXPORT_SYMBOL(drm_edid_to_sad);
3590
3591 /**
3592 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3593 * @edid: EDID to parse
3594 * @sadb: pointer to the speaker block
3595 *
3596 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3597 *
3598 * Note: The returned pointer needs to be freed using kfree().
3599 *
3600 * Return: The number of found Speaker Allocation Blocks or negative number on
3601 * error.
3602 */
3603 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3604 {
3605 int count = 0;
3606 int i, start, end, dbl;
3607 const u8 *cea;
3608
3609 cea = drm_find_cea_extension(edid);
3610 if (!cea) {
3611 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3612 return -ENOENT;
3613 }
3614
3615 if (cea_revision(cea) < 3) {
3616 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3617 return -ENOTSUPP;
3618 }
3619
3620 if (cea_db_offsets(cea, &start, &end)) {
3621 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3622 return -EPROTO;
3623 }
3624
3625 for_each_cea_db(cea, i, start, end) {
3626 const u8 *db = &cea[i];
3627
3628 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3629 dbl = cea_db_payload_len(db);
3630
3631 /* Speaker Allocation Data Block */
3632 if (dbl == 3) {
3633 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3634 if (!*sadb)
3635 return -ENOMEM;
3636 count = dbl;
3637 break;
3638 }
3639 }
3640 }
3641
3642 return count;
3643 }
3644 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3645
3646 /**
3647 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3648 * @connector: connector associated with the HDMI/DP sink
3649 * @mode: the display mode
3650 *
3651 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3652 * the sink doesn't support audio or video.
3653 */
3654 int drm_av_sync_delay(struct drm_connector *connector,
3655 const struct drm_display_mode *mode)
3656 {
3657 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3658 int a, v;
3659
3660 if (!connector->latency_present[0])
3661 return 0;
3662 if (!connector->latency_present[1])
3663 i = 0;
3664
3665 a = connector->audio_latency[i];
3666 v = connector->video_latency[i];
3667
3668 /*
3669 * HDMI/DP sink doesn't support audio or video?
3670 */
3671 if (a == 255 || v == 255)
3672 return 0;
3673
3674 /*
3675 * Convert raw EDID values to millisecond.
3676 * Treat unknown latency as 0ms.
3677 */
3678 if (a)
3679 a = min(2 * (a - 1), 500);
3680 if (v)
3681 v = min(2 * (v - 1), 500);
3682
3683 return max(v - a, 0);
3684 }
3685 EXPORT_SYMBOL(drm_av_sync_delay);
3686
3687 /**
3688 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3689 * @edid: monitor EDID information
3690 *
3691 * Parse the CEA extension according to CEA-861-B.
3692 *
3693 * Return: True if the monitor is HDMI, false if not or unknown.
3694 */
3695 bool drm_detect_hdmi_monitor(struct edid *edid)
3696 {
3697 u8 *edid_ext;
3698 int i;
3699 int start_offset, end_offset;
3700
3701 edid_ext = drm_find_cea_extension(edid);
3702 if (!edid_ext)
3703 return false;
3704
3705 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3706 return false;
3707
3708 /*
3709 * Because HDMI identifier is in Vendor Specific Block,
3710 * search it from all data blocks of CEA extension.
3711 */
3712 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3713 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3714 return true;
3715 }
3716
3717 return false;
3718 }
3719 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3720
3721 /**
3722 * drm_detect_monitor_audio - check monitor audio capability
3723 * @edid: EDID block to scan
3724 *
3725 * Monitor should have CEA extension block.
3726 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3727 * audio' only. If there is any audio extension block and supported
3728 * audio format, assume at least 'basic audio' support, even if 'basic
3729 * audio' is not defined in EDID.
3730 *
3731 * Return: True if the monitor supports audio, false otherwise.
3732 */
3733 bool drm_detect_monitor_audio(struct edid *edid)
3734 {
3735 u8 *edid_ext;
3736 int i, j;
3737 bool has_audio = false;
3738 int start_offset, end_offset;
3739
3740 edid_ext = drm_find_cea_extension(edid);
3741 if (!edid_ext)
3742 goto end;
3743
3744 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3745
3746 if (has_audio) {
3747 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3748 goto end;
3749 }
3750
3751 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3752 goto end;
3753
3754 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3755 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3756 has_audio = true;
3757 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3758 DRM_DEBUG_KMS("CEA audio format %d\n",
3759 (edid_ext[i + j] >> 3) & 0xf);
3760 goto end;
3761 }
3762 }
3763 end:
3764 return has_audio;
3765 }
3766 EXPORT_SYMBOL(drm_detect_monitor_audio);
3767
3768 /**
3769 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3770 * @edid: EDID block to scan
3771 *
3772 * Check whether the monitor reports the RGB quantization range selection
3773 * as supported. The AVI infoframe can then be used to inform the monitor
3774 * which quantization range (full or limited) is used.
3775 *
3776 * Return: True if the RGB quantization range is selectable, false otherwise.
3777 */
3778 bool drm_rgb_quant_range_selectable(struct edid *edid)
3779 {
3780 u8 *edid_ext;
3781 int i, start, end;
3782
3783 edid_ext = drm_find_cea_extension(edid);
3784 if (!edid_ext)
3785 return false;
3786
3787 if (cea_db_offsets(edid_ext, &start, &end))
3788 return false;
3789
3790 for_each_cea_db(edid_ext, i, start, end) {
3791 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3792 cea_db_payload_len(&edid_ext[i]) == 2) {
3793 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3794 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3795 }
3796 }
3797
3798 return false;
3799 }
3800 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3801
3802 /**
3803 * drm_default_rgb_quant_range - default RGB quantization range
3804 * @mode: display mode
3805 *
3806 * Determine the default RGB quantization range for the mode,
3807 * as specified in CEA-861.
3808 *
3809 * Return: The default RGB quantization range for the mode
3810 */
3811 enum hdmi_quantization_range
3812 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
3813 {
3814 /* All CEA modes other than VIC 1 use limited quantization range. */
3815 return drm_match_cea_mode(mode) > 1 ?
3816 HDMI_QUANTIZATION_RANGE_LIMITED :
3817 HDMI_QUANTIZATION_RANGE_FULL;
3818 }
3819 EXPORT_SYMBOL(drm_default_rgb_quant_range);
3820
3821 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
3822 const u8 *hf_vsdb)
3823 {
3824 struct drm_display_info *display = &connector->display_info;
3825 struct drm_hdmi_info *hdmi = &display->hdmi;
3826
3827 if (hf_vsdb[6] & 0x80) {
3828 hdmi->scdc.supported = true;
3829 if (hf_vsdb[6] & 0x40)
3830 hdmi->scdc.read_request = true;
3831 }
3832
3833 /*
3834 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
3835 * And as per the spec, three factors confirm this:
3836 * * Availability of a HF-VSDB block in EDID (check)
3837 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
3838 * * SCDC support available (let's check)
3839 * Lets check it out.
3840 */
3841
3842 if (hf_vsdb[5]) {
3843 /* max clock is 5000 KHz times block value */
3844 u32 max_tmds_clock = hf_vsdb[5] * 5000;
3845 struct drm_scdc *scdc = &hdmi->scdc;
3846
3847 if (max_tmds_clock > 340000) {
3848 display->max_tmds_clock = max_tmds_clock;
3849 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
3850 display->max_tmds_clock);
3851 }
3852
3853 if (scdc->supported) {
3854 scdc->scrambling.supported = true;
3855
3856 /* Few sinks support scrambling for cloks < 340M */
3857 if ((hf_vsdb[6] & 0x8))
3858 scdc->scrambling.low_rates = true;
3859 }
3860 }
3861 }
3862
3863 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
3864 const u8 *hdmi)
3865 {
3866 struct drm_display_info *info = &connector->display_info;
3867 unsigned int dc_bpc = 0;
3868
3869 /* HDMI supports at least 8 bpc */
3870 info->bpc = 8;
3871
3872 if (cea_db_payload_len(hdmi) < 6)
3873 return;
3874
3875 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3876 dc_bpc = 10;
3877 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3878 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3879 connector->name);
3880 }
3881
3882 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3883 dc_bpc = 12;
3884 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3885 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3886 connector->name);
3887 }
3888
3889 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3890 dc_bpc = 16;
3891 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3892 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3893 connector->name);
3894 }
3895
3896 if (dc_bpc == 0) {
3897 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3898 connector->name);
3899 return;
3900 }
3901
3902 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3903 connector->name, dc_bpc);
3904 info->bpc = dc_bpc;
3905
3906 /*
3907 * Deep color support mandates RGB444 support for all video
3908 * modes and forbids YCRCB422 support for all video modes per
3909 * HDMI 1.3 spec.
3910 */
3911 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3912
3913 /* YCRCB444 is optional according to spec. */
3914 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3915 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3916 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3917 connector->name);
3918 }
3919
3920 /*
3921 * Spec says that if any deep color mode is supported at all,
3922 * then deep color 36 bit must be supported.
3923 */
3924 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3925 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3926 connector->name);
3927 }
3928 }
3929
3930 static void
3931 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
3932 {
3933 struct drm_display_info *info = &connector->display_info;
3934 u8 len = cea_db_payload_len(db);
3935
3936 if (len >= 6)
3937 info->dvi_dual = db[6] & 1;
3938 if (len >= 7)
3939 info->max_tmds_clock = db[7] * 5000;
3940
3941 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3942 "max TMDS clock %d kHz\n",
3943 info->dvi_dual,
3944 info->max_tmds_clock);
3945
3946 drm_parse_hdmi_deep_color_info(connector, db);
3947 }
3948
3949 static void drm_parse_cea_ext(struct drm_connector *connector,
3950 struct edid *edid)
3951 {
3952 struct drm_display_info *info = &connector->display_info;
3953 const u8 *edid_ext;
3954 int i, start, end;
3955
3956 edid_ext = drm_find_cea_extension(edid);
3957 if (!edid_ext)
3958 return;
3959
3960 info->cea_rev = edid_ext[1];
3961
3962 /* The existence of a CEA block should imply RGB support */
3963 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3964 if (edid_ext[3] & EDID_CEA_YCRCB444)
3965 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3966 if (edid_ext[3] & EDID_CEA_YCRCB422)
3967 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3968
3969 if (cea_db_offsets(edid_ext, &start, &end))
3970 return;
3971
3972 for_each_cea_db(edid_ext, i, start, end) {
3973 const u8 *db = &edid_ext[i];
3974
3975 if (cea_db_is_hdmi_vsdb(db))
3976 drm_parse_hdmi_vsdb_video(connector, db);
3977 if (cea_db_is_hdmi_forum_vsdb(db))
3978 drm_parse_hdmi_forum_vsdb(connector, db);
3979 }
3980 }
3981
3982 static void drm_add_display_info(struct drm_connector *connector,
3983 struct edid *edid)
3984 {
3985 struct drm_display_info *info = &connector->display_info;
3986
3987 info->width_mm = edid->width_cm * 10;
3988 info->height_mm = edid->height_cm * 10;
3989
3990 /* driver figures it out in this case */
3991 info->bpc = 0;
3992 info->color_formats = 0;
3993 info->cea_rev = 0;
3994 info->max_tmds_clock = 0;
3995 info->dvi_dual = false;
3996
3997 if (edid->revision < 3)
3998 return;
3999
4000 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4001 return;
4002
4003 drm_parse_cea_ext(connector, edid);
4004
4005 /*
4006 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4007 *
4008 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4009 * tells us to assume 8 bpc color depth if the EDID doesn't have
4010 * extensions which tell otherwise.
4011 */
4012 if ((info->bpc == 0) && (edid->revision < 4) &&
4013 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4014 info->bpc = 8;
4015 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4016 connector->name, info->bpc);
4017 }
4018
4019 /* Only defined for 1.4 with digital displays */
4020 if (edid->revision < 4)
4021 return;
4022
4023 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4024 case DRM_EDID_DIGITAL_DEPTH_6:
4025 info->bpc = 6;
4026 break;
4027 case DRM_EDID_DIGITAL_DEPTH_8:
4028 info->bpc = 8;
4029 break;
4030 case DRM_EDID_DIGITAL_DEPTH_10:
4031 info->bpc = 10;
4032 break;
4033 case DRM_EDID_DIGITAL_DEPTH_12:
4034 info->bpc = 12;
4035 break;
4036 case DRM_EDID_DIGITAL_DEPTH_14:
4037 info->bpc = 14;
4038 break;
4039 case DRM_EDID_DIGITAL_DEPTH_16:
4040 info->bpc = 16;
4041 break;
4042 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4043 default:
4044 info->bpc = 0;
4045 break;
4046 }
4047
4048 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4049 connector->name, info->bpc);
4050
4051 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4052 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4053 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4054 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4055 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4056 }
4057
4058 static int validate_displayid(u8 *displayid, int length, int idx)
4059 {
4060 int i;
4061 u8 csum = 0;
4062 struct displayid_hdr *base;
4063
4064 base = (struct displayid_hdr *)&displayid[idx];
4065
4066 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4067 base->rev, base->bytes, base->prod_id, base->ext_count);
4068
4069 if (base->bytes + 5 > length - idx)
4070 return -EINVAL;
4071 for (i = idx; i <= base->bytes + 5; i++) {
4072 csum += displayid[i];
4073 }
4074 if (csum) {
4075 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4076 return -EINVAL;
4077 }
4078 return 0;
4079 }
4080
4081 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4082 struct displayid_detailed_timings_1 *timings)
4083 {
4084 struct drm_display_mode *mode;
4085 unsigned pixel_clock = (timings->pixel_clock[0] |
4086 (timings->pixel_clock[1] << 8) |
4087 (timings->pixel_clock[2] << 16));
4088 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4089 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4090 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4091 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4092 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4093 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4094 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4095 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4096 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4097 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4098 mode = drm_mode_create(dev);
4099 if (!mode)
4100 return NULL;
4101
4102 mode->clock = pixel_clock * 10;
4103 mode->hdisplay = hactive;
4104 mode->hsync_start = mode->hdisplay + hsync;
4105 mode->hsync_end = mode->hsync_start + hsync_width;
4106 mode->htotal = mode->hdisplay + hblank;
4107
4108 mode->vdisplay = vactive;
4109 mode->vsync_start = mode->vdisplay + vsync;
4110 mode->vsync_end = mode->vsync_start + vsync_width;
4111 mode->vtotal = mode->vdisplay + vblank;
4112
4113 mode->flags = 0;
4114 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4115 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4116 mode->type = DRM_MODE_TYPE_DRIVER;
4117
4118 if (timings->flags & 0x80)
4119 mode->type |= DRM_MODE_TYPE_PREFERRED;
4120 mode->vrefresh = drm_mode_vrefresh(mode);
4121 drm_mode_set_name(mode);
4122
4123 return mode;
4124 }
4125
4126 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4127 struct displayid_block *block)
4128 {
4129 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4130 int i;
4131 int num_timings;
4132 struct drm_display_mode *newmode;
4133 int num_modes = 0;
4134 /* blocks must be multiple of 20 bytes length */
4135 if (block->num_bytes % 20)
4136 return 0;
4137
4138 num_timings = block->num_bytes / 20;
4139 for (i = 0; i < num_timings; i++) {
4140 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4141
4142 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4143 if (!newmode)
4144 continue;
4145
4146 drm_mode_probed_add(connector, newmode);
4147 num_modes++;
4148 }
4149 return num_modes;
4150 }
4151
4152 static int add_displayid_detailed_modes(struct drm_connector *connector,
4153 struct edid *edid)
4154 {
4155 u8 *displayid;
4156 int ret;
4157 int idx = 1;
4158 int length = EDID_LENGTH;
4159 struct displayid_block *block;
4160 int num_modes = 0;
4161
4162 displayid = drm_find_displayid_extension(edid);
4163 if (!displayid)
4164 return 0;
4165
4166 ret = validate_displayid(displayid, length, idx);
4167 if (ret)
4168 return 0;
4169
4170 idx += sizeof(struct displayid_hdr);
4171 while (block = (struct displayid_block *)&displayid[idx],
4172 idx + sizeof(struct displayid_block) <= length &&
4173 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4174 block->num_bytes > 0) {
4175 idx += block->num_bytes + sizeof(struct displayid_block);
4176 switch (block->tag) {
4177 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4178 num_modes += add_displayid_detailed_1_modes(connector, block);
4179 break;
4180 }
4181 }
4182 return num_modes;
4183 }
4184
4185 /**
4186 * drm_add_edid_modes - add modes from EDID data, if available
4187 * @connector: connector we're probing
4188 * @edid: EDID data
4189 *
4190 * Add the specified modes to the connector's mode list. Also fills out the
4191 * &drm_display_info structure in @connector with any information which can be
4192 * derived from the edid.
4193 *
4194 * Return: The number of modes added or 0 if we couldn't find any.
4195 */
4196 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4197 {
4198 int num_modes = 0;
4199 u32 quirks;
4200
4201 if (edid == NULL) {
4202 return 0;
4203 }
4204 if (!drm_edid_is_valid(edid)) {
4205 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4206 connector->name);
4207 return 0;
4208 }
4209
4210 quirks = edid_get_quirks(edid);
4211
4212 /*
4213 * EDID spec says modes should be preferred in this order:
4214 * - preferred detailed mode
4215 * - other detailed modes from base block
4216 * - detailed modes from extension blocks
4217 * - CVT 3-byte code modes
4218 * - standard timing codes
4219 * - established timing codes
4220 * - modes inferred from GTF or CVT range information
4221 *
4222 * We get this pretty much right.
4223 *
4224 * XXX order for additional mode types in extension blocks?
4225 */
4226 num_modes += add_detailed_modes(connector, edid, quirks);
4227 num_modes += add_cvt_modes(connector, edid);
4228 num_modes += add_standard_modes(connector, edid);
4229 num_modes += add_established_modes(connector, edid);
4230 num_modes += add_cea_modes(connector, edid);
4231 num_modes += add_alternate_cea_modes(connector, edid);
4232 num_modes += add_displayid_detailed_modes(connector, edid);
4233 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4234 num_modes += add_inferred_modes(connector, edid);
4235
4236 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4237 edid_fixup_preferred(connector, quirks);
4238
4239 drm_add_display_info(connector, edid);
4240
4241 if (quirks & EDID_QUIRK_FORCE_6BPC)
4242 connector->display_info.bpc = 6;
4243
4244 if (quirks & EDID_QUIRK_FORCE_8BPC)
4245 connector->display_info.bpc = 8;
4246
4247 if (quirks & EDID_QUIRK_FORCE_12BPC)
4248 connector->display_info.bpc = 12;
4249
4250 return num_modes;
4251 }
4252 EXPORT_SYMBOL(drm_add_edid_modes);
4253
4254 /**
4255 * drm_add_modes_noedid - add modes for the connectors without EDID
4256 * @connector: connector we're probing
4257 * @hdisplay: the horizontal display limit
4258 * @vdisplay: the vertical display limit
4259 *
4260 * Add the specified modes to the connector's mode list. Only when the
4261 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4262 *
4263 * Return: The number of modes added or 0 if we couldn't find any.
4264 */
4265 int drm_add_modes_noedid(struct drm_connector *connector,
4266 int hdisplay, int vdisplay)
4267 {
4268 int i, count, num_modes = 0;
4269 struct drm_display_mode *mode;
4270 struct drm_device *dev = connector->dev;
4271
4272 count = ARRAY_SIZE(drm_dmt_modes);
4273 if (hdisplay < 0)
4274 hdisplay = 0;
4275 if (vdisplay < 0)
4276 vdisplay = 0;
4277
4278 for (i = 0; i < count; i++) {
4279 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4280 if (hdisplay && vdisplay) {
4281 /*
4282 * Only when two are valid, they will be used to check
4283 * whether the mode should be added to the mode list of
4284 * the connector.
4285 */
4286 if (ptr->hdisplay > hdisplay ||
4287 ptr->vdisplay > vdisplay)
4288 continue;
4289 }
4290 if (drm_mode_vrefresh(ptr) > 61)
4291 continue;
4292 mode = drm_mode_duplicate(dev, ptr);
4293 if (mode) {
4294 drm_mode_probed_add(connector, mode);
4295 num_modes++;
4296 }
4297 }
4298 return num_modes;
4299 }
4300 EXPORT_SYMBOL(drm_add_modes_noedid);
4301
4302 /**
4303 * drm_set_preferred_mode - Sets the preferred mode of a connector
4304 * @connector: connector whose mode list should be processed
4305 * @hpref: horizontal resolution of preferred mode
4306 * @vpref: vertical resolution of preferred mode
4307 *
4308 * Marks a mode as preferred if it matches the resolution specified by @hpref
4309 * and @vpref.
4310 */
4311 void drm_set_preferred_mode(struct drm_connector *connector,
4312 int hpref, int vpref)
4313 {
4314 struct drm_display_mode *mode;
4315
4316 list_for_each_entry(mode, &connector->probed_modes, head) {
4317 if (mode->hdisplay == hpref &&
4318 mode->vdisplay == vpref)
4319 mode->type |= DRM_MODE_TYPE_PREFERRED;
4320 }
4321 }
4322 EXPORT_SYMBOL(drm_set_preferred_mode);
4323
4324 /**
4325 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4326 * data from a DRM display mode
4327 * @frame: HDMI AVI infoframe
4328 * @mode: DRM display mode
4329 *
4330 * Return: 0 on success or a negative error code on failure.
4331 */
4332 int
4333 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4334 const struct drm_display_mode *mode)
4335 {
4336 int err;
4337
4338 if (!frame || !mode)
4339 return -EINVAL;
4340
4341 err = hdmi_avi_infoframe_init(frame);
4342 if (err < 0)
4343 return err;
4344
4345 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4346 frame->pixel_repeat = 1;
4347
4348 frame->video_code = drm_match_cea_mode(mode);
4349
4350 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4351
4352 /*
4353 * Populate picture aspect ratio from either
4354 * user input (if specified) or from the CEA mode list.
4355 */
4356 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4357 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4358 frame->picture_aspect = mode->picture_aspect_ratio;
4359 else if (frame->video_code > 0)
4360 frame->picture_aspect = drm_get_cea_aspect_ratio(
4361 frame->video_code);
4362
4363 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4364 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4365
4366 return 0;
4367 }
4368 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4369
4370 /**
4371 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4372 * quantization range information
4373 * @frame: HDMI AVI infoframe
4374 * @mode: DRM display mode
4375 * @rgb_quant_range: RGB quantization range (Q)
4376 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4377 */
4378 void
4379 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4380 const struct drm_display_mode *mode,
4381 enum hdmi_quantization_range rgb_quant_range,
4382 bool rgb_quant_range_selectable)
4383 {
4384 /*
4385 * CEA-861:
4386 * "A Source shall not send a non-zero Q value that does not correspond
4387 * to the default RGB Quantization Range for the transmitted Picture
4388 * unless the Sink indicates support for the Q bit in a Video
4389 * Capabilities Data Block."
4390 *
4391 * HDMI 2.0 recommends sending non-zero Q when it does match the
4392 * default RGB quantization range for the mode, even when QS=0.
4393 */
4394 if (rgb_quant_range_selectable ||
4395 rgb_quant_range == drm_default_rgb_quant_range(mode))
4396 frame->quantization_range = rgb_quant_range;
4397 else
4398 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4399
4400 /*
4401 * CEA-861-F:
4402 * "When transmitting any RGB colorimetry, the Source should set the
4403 * YQ-field to match the RGB Quantization Range being transmitted
4404 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4405 * set YQ=1) and the Sink shall ignore the YQ-field."
4406 */
4407 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4408 frame->ycc_quantization_range =
4409 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4410 else
4411 frame->ycc_quantization_range =
4412 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4413 }
4414 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4415
4416 static enum hdmi_3d_structure
4417 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4418 {
4419 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4420
4421 switch (layout) {
4422 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4423 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4424 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4425 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4426 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4427 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4428 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4429 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4430 case DRM_MODE_FLAG_3D_L_DEPTH:
4431 return HDMI_3D_STRUCTURE_L_DEPTH;
4432 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4433 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4434 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4435 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4436 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4437 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4438 default:
4439 return HDMI_3D_STRUCTURE_INVALID;
4440 }
4441 }
4442
4443 /**
4444 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4445 * data from a DRM display mode
4446 * @frame: HDMI vendor infoframe
4447 * @mode: DRM display mode
4448 *
4449 * Note that there's is a need to send HDMI vendor infoframes only when using a
4450 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4451 * function will return -EINVAL, error that can be safely ignored.
4452 *
4453 * Return: 0 on success or a negative error code on failure.
4454 */
4455 int
4456 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4457 const struct drm_display_mode *mode)
4458 {
4459 int err;
4460 u32 s3d_flags;
4461 u8 vic;
4462
4463 if (!frame || !mode)
4464 return -EINVAL;
4465
4466 vic = drm_match_hdmi_mode(mode);
4467 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4468
4469 if (!vic && !s3d_flags)
4470 return -EINVAL;
4471
4472 if (vic && s3d_flags)
4473 return -EINVAL;
4474
4475 err = hdmi_vendor_infoframe_init(frame);
4476 if (err < 0)
4477 return err;
4478
4479 if (vic)
4480 frame->vic = vic;
4481 else
4482 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4483
4484 return 0;
4485 }
4486 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4487
4488 static int drm_parse_tiled_block(struct drm_connector *connector,
4489 struct displayid_block *block)
4490 {
4491 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4492 u16 w, h;
4493 u8 tile_v_loc, tile_h_loc;
4494 u8 num_v_tile, num_h_tile;
4495 struct drm_tile_group *tg;
4496
4497 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4498 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4499
4500 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4501 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4502 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4503 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4504
4505 connector->has_tile = true;
4506 if (tile->tile_cap & 0x80)
4507 connector->tile_is_single_monitor = true;
4508
4509 connector->num_h_tile = num_h_tile + 1;
4510 connector->num_v_tile = num_v_tile + 1;
4511 connector->tile_h_loc = tile_h_loc;
4512 connector->tile_v_loc = tile_v_loc;
4513 connector->tile_h_size = w + 1;
4514 connector->tile_v_size = h + 1;
4515
4516 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4517 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4518 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4519 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4520 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4521
4522 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4523 if (!tg) {
4524 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4525 }
4526 if (!tg)
4527 return -ENOMEM;
4528
4529 if (connector->tile_group != tg) {
4530 /* if we haven't got a pointer,
4531 take the reference, drop ref to old tile group */
4532 if (connector->tile_group) {
4533 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4534 }
4535 connector->tile_group = tg;
4536 } else
4537 /* if same tile group, then release the ref we just took. */
4538 drm_mode_put_tile_group(connector->dev, tg);
4539 return 0;
4540 }
4541
4542 static int drm_parse_display_id(struct drm_connector *connector,
4543 u8 *displayid, int length,
4544 bool is_edid_extension)
4545 {
4546 /* if this is an EDID extension the first byte will be 0x70 */
4547 int idx = 0;
4548 struct displayid_block *block;
4549 int ret;
4550
4551 if (is_edid_extension)
4552 idx = 1;
4553
4554 ret = validate_displayid(displayid, length, idx);
4555 if (ret)
4556 return ret;
4557
4558 idx += sizeof(struct displayid_hdr);
4559 while (block = (struct displayid_block *)&displayid[idx],
4560 idx + sizeof(struct displayid_block) <= length &&
4561 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4562 block->num_bytes > 0) {
4563 idx += block->num_bytes + sizeof(struct displayid_block);
4564 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4565 block->tag, block->rev, block->num_bytes);
4566
4567 switch (block->tag) {
4568 case DATA_BLOCK_TILED_DISPLAY:
4569 ret = drm_parse_tiled_block(connector, block);
4570 if (ret)
4571 return ret;
4572 break;
4573 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4574 /* handled in mode gathering code. */
4575 break;
4576 default:
4577 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
4578 break;
4579 }
4580 }
4581 return 0;
4582 }
4583
4584 static void drm_get_displayid(struct drm_connector *connector,
4585 struct edid *edid)
4586 {
4587 void *displayid = NULL;
4588 int ret;
4589 connector->has_tile = false;
4590 displayid = drm_find_displayid_extension(edid);
4591 if (!displayid) {
4592 /* drop reference to any tile group we had */
4593 goto out_drop_ref;
4594 }
4595
4596 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4597 if (ret < 0)
4598 goto out_drop_ref;
4599 if (!connector->has_tile)
4600 goto out_drop_ref;
4601 return;
4602 out_drop_ref:
4603 if (connector->tile_group) {
4604 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4605 connector->tile_group = NULL;
4606 }
4607 return;
4608 }
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