2 * Copyright (C) 2015 Etnaviv Project
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/component.h>
18 #include <linux/fence.h>
19 #include <linux/moduleparam.h>
20 #include <linux/of_device.h>
21 #include "etnaviv_dump.h"
22 #include "etnaviv_gpu.h"
23 #include "etnaviv_gem.h"
24 #include "etnaviv_mmu.h"
25 #include "etnaviv_iommu.h"
26 #include "etnaviv_iommu_v2.h"
27 #include "common.xml.h"
28 #include "state.xml.h"
29 #include "state_hi.xml.h"
30 #include "cmdstream.xml.h"
32 static const struct platform_device_id gpu_ids
[] = {
33 { .name
= "etnaviv-gpu,2d" },
37 static bool etnaviv_dump_core
= true;
38 module_param_named(dump_core
, etnaviv_dump_core
, bool, 0600);
44 int etnaviv_gpu_get_param(struct etnaviv_gpu
*gpu
, u32 param
, u64
*value
)
47 case ETNAVIV_PARAM_GPU_MODEL
:
48 *value
= gpu
->identity
.model
;
51 case ETNAVIV_PARAM_GPU_REVISION
:
52 *value
= gpu
->identity
.revision
;
55 case ETNAVIV_PARAM_GPU_FEATURES_0
:
56 *value
= gpu
->identity
.features
;
59 case ETNAVIV_PARAM_GPU_FEATURES_1
:
60 *value
= gpu
->identity
.minor_features0
;
63 case ETNAVIV_PARAM_GPU_FEATURES_2
:
64 *value
= gpu
->identity
.minor_features1
;
67 case ETNAVIV_PARAM_GPU_FEATURES_3
:
68 *value
= gpu
->identity
.minor_features2
;
71 case ETNAVIV_PARAM_GPU_FEATURES_4
:
72 *value
= gpu
->identity
.minor_features3
;
75 case ETNAVIV_PARAM_GPU_FEATURES_5
:
76 *value
= gpu
->identity
.minor_features4
;
79 case ETNAVIV_PARAM_GPU_FEATURES_6
:
80 *value
= gpu
->identity
.minor_features5
;
83 case ETNAVIV_PARAM_GPU_STREAM_COUNT
:
84 *value
= gpu
->identity
.stream_count
;
87 case ETNAVIV_PARAM_GPU_REGISTER_MAX
:
88 *value
= gpu
->identity
.register_max
;
91 case ETNAVIV_PARAM_GPU_THREAD_COUNT
:
92 *value
= gpu
->identity
.thread_count
;
95 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE
:
96 *value
= gpu
->identity
.vertex_cache_size
;
99 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT
:
100 *value
= gpu
->identity
.shader_core_count
;
103 case ETNAVIV_PARAM_GPU_PIXEL_PIPES
:
104 *value
= gpu
->identity
.pixel_pipes
;
107 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE
:
108 *value
= gpu
->identity
.vertex_output_buffer_size
;
111 case ETNAVIV_PARAM_GPU_BUFFER_SIZE
:
112 *value
= gpu
->identity
.buffer_size
;
115 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT
:
116 *value
= gpu
->identity
.instruction_count
;
119 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS
:
120 *value
= gpu
->identity
.num_constants
;
123 case ETNAVIV_PARAM_GPU_NUM_VARYINGS
:
124 *value
= gpu
->identity
.varyings_count
;
128 DBG("%s: invalid param: %u", dev_name(gpu
->dev
), param
);
136 #define etnaviv_is_model_rev(gpu, mod, rev) \
137 ((gpu)->identity.model == chipModel_##mod && \
138 (gpu)->identity.revision == rev)
139 #define etnaviv_field(val, field) \
140 (((val) & field##__MASK) >> field##__SHIFT)
142 static void etnaviv_hw_specs(struct etnaviv_gpu
*gpu
)
144 if (gpu
->identity
.minor_features0
&
145 chipMinorFeatures0_MORE_MINOR_FEATURES
) {
147 unsigned int streams
;
149 specs
[0] = gpu_read(gpu
, VIVS_HI_CHIP_SPECS
);
150 specs
[1] = gpu_read(gpu
, VIVS_HI_CHIP_SPECS_2
);
151 specs
[2] = gpu_read(gpu
, VIVS_HI_CHIP_SPECS_3
);
152 specs
[3] = gpu_read(gpu
, VIVS_HI_CHIP_SPECS_4
);
154 gpu
->identity
.stream_count
= etnaviv_field(specs
[0],
155 VIVS_HI_CHIP_SPECS_STREAM_COUNT
);
156 gpu
->identity
.register_max
= etnaviv_field(specs
[0],
157 VIVS_HI_CHIP_SPECS_REGISTER_MAX
);
158 gpu
->identity
.thread_count
= etnaviv_field(specs
[0],
159 VIVS_HI_CHIP_SPECS_THREAD_COUNT
);
160 gpu
->identity
.vertex_cache_size
= etnaviv_field(specs
[0],
161 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE
);
162 gpu
->identity
.shader_core_count
= etnaviv_field(specs
[0],
163 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT
);
164 gpu
->identity
.pixel_pipes
= etnaviv_field(specs
[0],
165 VIVS_HI_CHIP_SPECS_PIXEL_PIPES
);
166 gpu
->identity
.vertex_output_buffer_size
=
167 etnaviv_field(specs
[0],
168 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE
);
170 gpu
->identity
.buffer_size
= etnaviv_field(specs
[1],
171 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE
);
172 gpu
->identity
.instruction_count
= etnaviv_field(specs
[1],
173 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT
);
174 gpu
->identity
.num_constants
= etnaviv_field(specs
[1],
175 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS
);
177 gpu
->identity
.varyings_count
= etnaviv_field(specs
[2],
178 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT
);
180 /* This overrides the value from older register if non-zero */
181 streams
= etnaviv_field(specs
[3],
182 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT
);
184 gpu
->identity
.stream_count
= streams
;
187 /* Fill in the stream count if not specified */
188 if (gpu
->identity
.stream_count
== 0) {
189 if (gpu
->identity
.model
>= 0x1000)
190 gpu
->identity
.stream_count
= 4;
192 gpu
->identity
.stream_count
= 1;
195 /* Convert the register max value */
196 if (gpu
->identity
.register_max
)
197 gpu
->identity
.register_max
= 1 << gpu
->identity
.register_max
;
198 else if (gpu
->identity
.model
== chipModel_GC400
)
199 gpu
->identity
.register_max
= 32;
201 gpu
->identity
.register_max
= 64;
203 /* Convert thread count */
204 if (gpu
->identity
.thread_count
)
205 gpu
->identity
.thread_count
= 1 << gpu
->identity
.thread_count
;
206 else if (gpu
->identity
.model
== chipModel_GC400
)
207 gpu
->identity
.thread_count
= 64;
208 else if (gpu
->identity
.model
== chipModel_GC500
||
209 gpu
->identity
.model
== chipModel_GC530
)
210 gpu
->identity
.thread_count
= 128;
212 gpu
->identity
.thread_count
= 256;
214 if (gpu
->identity
.vertex_cache_size
== 0)
215 gpu
->identity
.vertex_cache_size
= 8;
217 if (gpu
->identity
.shader_core_count
== 0) {
218 if (gpu
->identity
.model
>= 0x1000)
219 gpu
->identity
.shader_core_count
= 2;
221 gpu
->identity
.shader_core_count
= 1;
224 if (gpu
->identity
.pixel_pipes
== 0)
225 gpu
->identity
.pixel_pipes
= 1;
227 /* Convert virtex buffer size */
228 if (gpu
->identity
.vertex_output_buffer_size
) {
229 gpu
->identity
.vertex_output_buffer_size
=
230 1 << gpu
->identity
.vertex_output_buffer_size
;
231 } else if (gpu
->identity
.model
== chipModel_GC400
) {
232 if (gpu
->identity
.revision
< 0x4000)
233 gpu
->identity
.vertex_output_buffer_size
= 512;
234 else if (gpu
->identity
.revision
< 0x4200)
235 gpu
->identity
.vertex_output_buffer_size
= 256;
237 gpu
->identity
.vertex_output_buffer_size
= 128;
239 gpu
->identity
.vertex_output_buffer_size
= 512;
242 switch (gpu
->identity
.instruction_count
) {
244 if (etnaviv_is_model_rev(gpu
, GC2000
, 0x5108) ||
245 gpu
->identity
.model
== chipModel_GC880
)
246 gpu
->identity
.instruction_count
= 512;
248 gpu
->identity
.instruction_count
= 256;
252 gpu
->identity
.instruction_count
= 1024;
256 gpu
->identity
.instruction_count
= 2048;
260 gpu
->identity
.instruction_count
= 256;
264 if (gpu
->identity
.num_constants
== 0)
265 gpu
->identity
.num_constants
= 168;
267 if (gpu
->identity
.varyings_count
== 0) {
268 if (gpu
->identity
.minor_features1
& chipMinorFeatures1_HALTI0
)
269 gpu
->identity
.varyings_count
= 12;
271 gpu
->identity
.varyings_count
= 8;
275 * For some cores, two varyings are consumed for position, so the
276 * maximum varying count needs to be reduced by one.
278 if (etnaviv_is_model_rev(gpu
, GC5000
, 0x5434) ||
279 etnaviv_is_model_rev(gpu
, GC4000
, 0x5222) ||
280 etnaviv_is_model_rev(gpu
, GC4000
, 0x5245) ||
281 etnaviv_is_model_rev(gpu
, GC4000
, 0x5208) ||
282 etnaviv_is_model_rev(gpu
, GC3000
, 0x5435) ||
283 etnaviv_is_model_rev(gpu
, GC2200
, 0x5244) ||
284 etnaviv_is_model_rev(gpu
, GC2100
, 0x5108) ||
285 etnaviv_is_model_rev(gpu
, GC2000
, 0x5108) ||
286 etnaviv_is_model_rev(gpu
, GC1500
, 0x5246) ||
287 etnaviv_is_model_rev(gpu
, GC880
, 0x5107) ||
288 etnaviv_is_model_rev(gpu
, GC880
, 0x5106))
289 gpu
->identity
.varyings_count
-= 1;
292 static void etnaviv_hw_identify(struct etnaviv_gpu
*gpu
)
296 chipIdentity
= gpu_read(gpu
, VIVS_HI_CHIP_IDENTITY
);
298 /* Special case for older graphic cores. */
299 if (etnaviv_field(chipIdentity
, VIVS_HI_CHIP_IDENTITY_FAMILY
) == 0x01) {
300 gpu
->identity
.model
= chipModel_GC500
;
301 gpu
->identity
.revision
= etnaviv_field(chipIdentity
,
302 VIVS_HI_CHIP_IDENTITY_REVISION
);
305 gpu
->identity
.model
= gpu_read(gpu
, VIVS_HI_CHIP_MODEL
);
306 gpu
->identity
.revision
= gpu_read(gpu
, VIVS_HI_CHIP_REV
);
309 * !!!! HACK ALERT !!!!
310 * Because people change device IDs without letting software
311 * know about it - here is the hack to make it all look the
312 * same. Only for GC400 family.
314 if ((gpu
->identity
.model
& 0xff00) == 0x0400 &&
315 gpu
->identity
.model
!= chipModel_GC420
) {
316 gpu
->identity
.model
= gpu
->identity
.model
& 0x0400;
319 /* Another special case */
320 if (etnaviv_is_model_rev(gpu
, GC300
, 0x2201)) {
321 u32 chipDate
= gpu_read(gpu
, VIVS_HI_CHIP_DATE
);
322 u32 chipTime
= gpu_read(gpu
, VIVS_HI_CHIP_TIME
);
324 if (chipDate
== 0x20080814 && chipTime
== 0x12051100) {
326 * This IP has an ECO; put the correct
329 gpu
->identity
.revision
= 0x1051;
334 dev_info(gpu
->dev
, "model: GC%x, revision: %x\n",
335 gpu
->identity
.model
, gpu
->identity
.revision
);
337 gpu
->identity
.features
= gpu_read(gpu
, VIVS_HI_CHIP_FEATURE
);
339 /* Disable fast clear on GC700. */
340 if (gpu
->identity
.model
== chipModel_GC700
)
341 gpu
->identity
.features
&= ~chipFeatures_FAST_CLEAR
;
343 if ((gpu
->identity
.model
== chipModel_GC500
&&
344 gpu
->identity
.revision
< 2) ||
345 (gpu
->identity
.model
== chipModel_GC300
&&
346 gpu
->identity
.revision
< 0x2000)) {
349 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
352 gpu
->identity
.minor_features0
= 0;
353 gpu
->identity
.minor_features1
= 0;
354 gpu
->identity
.minor_features2
= 0;
355 gpu
->identity
.minor_features3
= 0;
356 gpu
->identity
.minor_features4
= 0;
357 gpu
->identity
.minor_features5
= 0;
359 gpu
->identity
.minor_features0
=
360 gpu_read(gpu
, VIVS_HI_CHIP_MINOR_FEATURE_0
);
362 if (gpu
->identity
.minor_features0
&
363 chipMinorFeatures0_MORE_MINOR_FEATURES
) {
364 gpu
->identity
.minor_features1
=
365 gpu_read(gpu
, VIVS_HI_CHIP_MINOR_FEATURE_1
);
366 gpu
->identity
.minor_features2
=
367 gpu_read(gpu
, VIVS_HI_CHIP_MINOR_FEATURE_2
);
368 gpu
->identity
.minor_features3
=
369 gpu_read(gpu
, VIVS_HI_CHIP_MINOR_FEATURE_3
);
370 gpu
->identity
.minor_features4
=
371 gpu_read(gpu
, VIVS_HI_CHIP_MINOR_FEATURE_4
);
372 gpu
->identity
.minor_features5
=
373 gpu_read(gpu
, VIVS_HI_CHIP_MINOR_FEATURE_5
);
376 /* GC600 idle register reports zero bits where modules aren't present */
377 if (gpu
->identity
.model
== chipModel_GC600
) {
378 gpu
->idle_mask
= VIVS_HI_IDLE_STATE_TX
|
379 VIVS_HI_IDLE_STATE_RA
|
380 VIVS_HI_IDLE_STATE_SE
|
381 VIVS_HI_IDLE_STATE_PA
|
382 VIVS_HI_IDLE_STATE_SH
|
383 VIVS_HI_IDLE_STATE_PE
|
384 VIVS_HI_IDLE_STATE_DE
|
385 VIVS_HI_IDLE_STATE_FE
;
387 gpu
->idle_mask
= ~VIVS_HI_IDLE_STATE_AXI_LP
;
390 etnaviv_hw_specs(gpu
);
393 static void etnaviv_gpu_load_clock(struct etnaviv_gpu
*gpu
, u32 clock
)
395 gpu_write(gpu
, VIVS_HI_CLOCK_CONTROL
, clock
|
396 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD
);
397 gpu_write(gpu
, VIVS_HI_CLOCK_CONTROL
, clock
);
400 static int etnaviv_hw_reset(struct etnaviv_gpu
*gpu
)
403 unsigned long timeout
;
413 /* We hope that the GPU resets in under one second */
414 timeout
= jiffies
+ msecs_to_jiffies(1000);
416 while (time_is_after_jiffies(timeout
)) {
417 control
= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS
|
418 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
421 etnaviv_gpu_load_clock(gpu
, control
);
423 /* Wait for stable clock. Vivante's code waited for 1ms */
424 usleep_range(1000, 10000);
426 /* isolate the GPU. */
427 control
|= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU
;
428 gpu_write(gpu
, VIVS_HI_CLOCK_CONTROL
, control
);
430 /* set soft reset. */
431 control
|= VIVS_HI_CLOCK_CONTROL_SOFT_RESET
;
432 gpu_write(gpu
, VIVS_HI_CLOCK_CONTROL
, control
);
434 /* wait for reset. */
437 /* reset soft reset bit. */
438 control
&= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET
;
439 gpu_write(gpu
, VIVS_HI_CLOCK_CONTROL
, control
);
441 /* reset GPU isolation. */
442 control
&= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU
;
443 gpu_write(gpu
, VIVS_HI_CLOCK_CONTROL
, control
);
445 /* read idle register. */
446 idle
= gpu_read(gpu
, VIVS_HI_IDLE_STATE
);
448 /* try reseting again if FE it not idle */
449 if ((idle
& VIVS_HI_IDLE_STATE_FE
) == 0) {
450 dev_dbg(gpu
->dev
, "FE is not idle\n");
454 /* read reset register. */
455 control
= gpu_read(gpu
, VIVS_HI_CLOCK_CONTROL
);
457 /* is the GPU idle? */
458 if (((control
& VIVS_HI_CLOCK_CONTROL_IDLE_3D
) == 0) ||
459 ((control
& VIVS_HI_CLOCK_CONTROL_IDLE_2D
) == 0)) {
460 dev_dbg(gpu
->dev
, "GPU is not idle\n");
469 idle
= gpu_read(gpu
, VIVS_HI_IDLE_STATE
);
470 control
= gpu_read(gpu
, VIVS_HI_CLOCK_CONTROL
);
472 dev_err(gpu
->dev
, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
473 idle
& VIVS_HI_IDLE_STATE_FE
? "" : "not ",
474 control
& VIVS_HI_CLOCK_CONTROL_IDLE_3D
? "" : "not ",
475 control
& VIVS_HI_CLOCK_CONTROL_IDLE_2D
? "" : "not ");
480 /* We rely on the GPU running, so program the clock */
481 control
= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS
|
482 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
485 etnaviv_gpu_load_clock(gpu
, control
);
490 static void etnaviv_gpu_hw_init(struct etnaviv_gpu
*gpu
)
494 if ((etnaviv_is_model_rev(gpu
, GC320
, 0x5007) ||
495 etnaviv_is_model_rev(gpu
, GC320
, 0x5220)) &&
496 gpu_read(gpu
, VIVS_HI_CHIP_TIME
) != 0x2062400) {
499 mc_memory_debug
= gpu_read(gpu
, VIVS_MC_DEBUG_MEMORY
) & ~0xff;
501 if (gpu
->identity
.revision
== 0x5007)
502 mc_memory_debug
|= 0x0c;
504 mc_memory_debug
|= 0x08;
506 gpu_write(gpu
, VIVS_MC_DEBUG_MEMORY
, mc_memory_debug
);
510 * Update GPU AXI cache atttribute to "cacheable, no allocate".
511 * This is necessary to prevent the iMX6 SoC locking up.
513 gpu_write(gpu
, VIVS_HI_AXI_CONFIG
,
514 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
515 VIVS_HI_AXI_CONFIG_ARCACHE(2));
517 /* GC2000 rev 5108 needs a special bus config */
518 if (etnaviv_is_model_rev(gpu
, GC2000
, 0x5108)) {
519 u32 bus_config
= gpu_read(gpu
, VIVS_MC_BUS_CONFIG
);
520 bus_config
&= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK
|
521 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK
);
522 bus_config
|= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
523 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
524 gpu_write(gpu
, VIVS_MC_BUS_CONFIG
, bus_config
);
527 /* set base addresses */
528 gpu_write(gpu
, VIVS_MC_MEMORY_BASE_ADDR_RA
, gpu
->memory_base
);
529 gpu_write(gpu
, VIVS_MC_MEMORY_BASE_ADDR_FE
, gpu
->memory_base
);
530 gpu_write(gpu
, VIVS_MC_MEMORY_BASE_ADDR_TX
, gpu
->memory_base
);
531 gpu_write(gpu
, VIVS_MC_MEMORY_BASE_ADDR_PEZ
, gpu
->memory_base
);
532 gpu_write(gpu
, VIVS_MC_MEMORY_BASE_ADDR_PE
, gpu
->memory_base
);
534 /* setup the MMU page table pointers */
535 etnaviv_iommu_domain_restore(gpu
, gpu
->mmu
->domain
);
537 /* Start command processor */
538 prefetch
= etnaviv_buffer_init(gpu
);
540 gpu_write(gpu
, VIVS_HI_INTR_ENBL
, ~0U);
541 gpu_write(gpu
, VIVS_FE_COMMAND_ADDRESS
,
542 gpu
->buffer
->paddr
- gpu
->memory_base
);
543 gpu_write(gpu
, VIVS_FE_COMMAND_CONTROL
,
544 VIVS_FE_COMMAND_CONTROL_ENABLE
|
545 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch
));
548 int etnaviv_gpu_init(struct etnaviv_gpu
*gpu
)
551 struct iommu_domain
*iommu
;
552 enum etnaviv_iommu_version version
;
555 ret
= pm_runtime_get_sync(gpu
->dev
);
559 etnaviv_hw_identify(gpu
);
561 if (gpu
->identity
.model
== 0) {
562 dev_err(gpu
->dev
, "Unknown GPU model\n");
567 /* Exclude VG cores with FE2.0 */
568 if (gpu
->identity
.features
& chipFeatures_PIPE_VG
&&
569 gpu
->identity
.features
& chipFeatures_FE20
) {
570 dev_info(gpu
->dev
, "Ignoring GPU with VG and FE2.0\n");
575 ret
= etnaviv_hw_reset(gpu
);
579 /* Setup IOMMU.. eventually we will (I think) do this once per context
580 * and have separate page tables per context. For now, to keep things
581 * simple and to get something working, just use a single address space:
583 mmuv2
= gpu
->identity
.minor_features1
& chipMinorFeatures1_MMU_VERSION
;
584 dev_dbg(gpu
->dev
, "mmuv2: %d\n", mmuv2
);
587 iommu
= etnaviv_iommu_domain_alloc(gpu
);
588 version
= ETNAVIV_IOMMU_V1
;
590 iommu
= etnaviv_iommu_v2_domain_alloc(gpu
);
591 version
= ETNAVIV_IOMMU_V2
;
599 gpu
->mmu
= etnaviv_iommu_new(gpu
, iommu
, version
);
601 iommu_domain_free(iommu
);
607 gpu
->buffer
= etnaviv_gpu_cmdbuf_new(gpu
, PAGE_SIZE
, 0);
610 dev_err(gpu
->dev
, "could not create command buffer\n");
613 if (gpu
->buffer
->paddr
- gpu
->memory_base
> 0x80000000) {
616 "command buffer outside valid memory window\n");
620 /* Setup event management */
621 spin_lock_init(&gpu
->event_spinlock
);
622 init_completion(&gpu
->event_free
);
623 for (i
= 0; i
< ARRAY_SIZE(gpu
->event
); i
++) {
624 gpu
->event
[i
].used
= false;
625 complete(&gpu
->event_free
);
628 /* Now program the hardware */
629 mutex_lock(&gpu
->lock
);
630 etnaviv_gpu_hw_init(gpu
);
631 mutex_unlock(&gpu
->lock
);
633 pm_runtime_mark_last_busy(gpu
->dev
);
634 pm_runtime_put_autosuspend(gpu
->dev
);
639 etnaviv_gpu_cmdbuf_free(gpu
->buffer
);
642 etnaviv_iommu_destroy(gpu
->mmu
);
645 pm_runtime_mark_last_busy(gpu
->dev
);
646 pm_runtime_put_autosuspend(gpu
->dev
);
651 #ifdef CONFIG_DEBUG_FS
657 static void verify_dma(struct etnaviv_gpu
*gpu
, struct dma_debug
*debug
)
661 debug
->address
[0] = gpu_read(gpu
, VIVS_FE_DMA_ADDRESS
);
662 debug
->state
[0] = gpu_read(gpu
, VIVS_FE_DMA_DEBUG_STATE
);
664 for (i
= 0; i
< 500; i
++) {
665 debug
->address
[1] = gpu_read(gpu
, VIVS_FE_DMA_ADDRESS
);
666 debug
->state
[1] = gpu_read(gpu
, VIVS_FE_DMA_DEBUG_STATE
);
668 if (debug
->address
[0] != debug
->address
[1])
671 if (debug
->state
[0] != debug
->state
[1])
676 int etnaviv_gpu_debugfs(struct etnaviv_gpu
*gpu
, struct seq_file
*m
)
678 struct dma_debug debug
;
679 u32 dma_lo
, dma_hi
, axi
, idle
;
682 seq_printf(m
, "%s Status:\n", dev_name(gpu
->dev
));
684 ret
= pm_runtime_get_sync(gpu
->dev
);
688 dma_lo
= gpu_read(gpu
, VIVS_FE_DMA_LOW
);
689 dma_hi
= gpu_read(gpu
, VIVS_FE_DMA_HIGH
);
690 axi
= gpu_read(gpu
, VIVS_HI_AXI_STATUS
);
691 idle
= gpu_read(gpu
, VIVS_HI_IDLE_STATE
);
693 verify_dma(gpu
, &debug
);
695 seq_puts(m
, "\tfeatures\n");
696 seq_printf(m
, "\t minor_features0: 0x%08x\n",
697 gpu
->identity
.minor_features0
);
698 seq_printf(m
, "\t minor_features1: 0x%08x\n",
699 gpu
->identity
.minor_features1
);
700 seq_printf(m
, "\t minor_features2: 0x%08x\n",
701 gpu
->identity
.minor_features2
);
702 seq_printf(m
, "\t minor_features3: 0x%08x\n",
703 gpu
->identity
.minor_features3
);
704 seq_printf(m
, "\t minor_features4: 0x%08x\n",
705 gpu
->identity
.minor_features4
);
706 seq_printf(m
, "\t minor_features5: 0x%08x\n",
707 gpu
->identity
.minor_features5
);
709 seq_puts(m
, "\tspecs\n");
710 seq_printf(m
, "\t stream_count: %d\n",
711 gpu
->identity
.stream_count
);
712 seq_printf(m
, "\t register_max: %d\n",
713 gpu
->identity
.register_max
);
714 seq_printf(m
, "\t thread_count: %d\n",
715 gpu
->identity
.thread_count
);
716 seq_printf(m
, "\t vertex_cache_size: %d\n",
717 gpu
->identity
.vertex_cache_size
);
718 seq_printf(m
, "\t shader_core_count: %d\n",
719 gpu
->identity
.shader_core_count
);
720 seq_printf(m
, "\t pixel_pipes: %d\n",
721 gpu
->identity
.pixel_pipes
);
722 seq_printf(m
, "\t vertex_output_buffer_size: %d\n",
723 gpu
->identity
.vertex_output_buffer_size
);
724 seq_printf(m
, "\t buffer_size: %d\n",
725 gpu
->identity
.buffer_size
);
726 seq_printf(m
, "\t instruction_count: %d\n",
727 gpu
->identity
.instruction_count
);
728 seq_printf(m
, "\t num_constants: %d\n",
729 gpu
->identity
.num_constants
);
730 seq_printf(m
, "\t varyings_count: %d\n",
731 gpu
->identity
.varyings_count
);
733 seq_printf(m
, "\taxi: 0x%08x\n", axi
);
734 seq_printf(m
, "\tidle: 0x%08x\n", idle
);
735 idle
|= ~gpu
->idle_mask
& ~VIVS_HI_IDLE_STATE_AXI_LP
;
736 if ((idle
& VIVS_HI_IDLE_STATE_FE
) == 0)
737 seq_puts(m
, "\t FE is not idle\n");
738 if ((idle
& VIVS_HI_IDLE_STATE_DE
) == 0)
739 seq_puts(m
, "\t DE is not idle\n");
740 if ((idle
& VIVS_HI_IDLE_STATE_PE
) == 0)
741 seq_puts(m
, "\t PE is not idle\n");
742 if ((idle
& VIVS_HI_IDLE_STATE_SH
) == 0)
743 seq_puts(m
, "\t SH is not idle\n");
744 if ((idle
& VIVS_HI_IDLE_STATE_PA
) == 0)
745 seq_puts(m
, "\t PA is not idle\n");
746 if ((idle
& VIVS_HI_IDLE_STATE_SE
) == 0)
747 seq_puts(m
, "\t SE is not idle\n");
748 if ((idle
& VIVS_HI_IDLE_STATE_RA
) == 0)
749 seq_puts(m
, "\t RA is not idle\n");
750 if ((idle
& VIVS_HI_IDLE_STATE_TX
) == 0)
751 seq_puts(m
, "\t TX is not idle\n");
752 if ((idle
& VIVS_HI_IDLE_STATE_VG
) == 0)
753 seq_puts(m
, "\t VG is not idle\n");
754 if ((idle
& VIVS_HI_IDLE_STATE_IM
) == 0)
755 seq_puts(m
, "\t IM is not idle\n");
756 if ((idle
& VIVS_HI_IDLE_STATE_FP
) == 0)
757 seq_puts(m
, "\t FP is not idle\n");
758 if ((idle
& VIVS_HI_IDLE_STATE_TS
) == 0)
759 seq_puts(m
, "\t TS is not idle\n");
760 if (idle
& VIVS_HI_IDLE_STATE_AXI_LP
)
761 seq_puts(m
, "\t AXI low power mode\n");
763 if (gpu
->identity
.features
& chipFeatures_DEBUG_MODE
) {
764 u32 read0
= gpu_read(gpu
, VIVS_MC_DEBUG_READ0
);
765 u32 read1
= gpu_read(gpu
, VIVS_MC_DEBUG_READ1
);
766 u32 write
= gpu_read(gpu
, VIVS_MC_DEBUG_WRITE
);
768 seq_puts(m
, "\tMC\n");
769 seq_printf(m
, "\t read0: 0x%08x\n", read0
);
770 seq_printf(m
, "\t read1: 0x%08x\n", read1
);
771 seq_printf(m
, "\t write: 0x%08x\n", write
);
774 seq_puts(m
, "\tDMA ");
776 if (debug
.address
[0] == debug
.address
[1] &&
777 debug
.state
[0] == debug
.state
[1]) {
778 seq_puts(m
, "seems to be stuck\n");
779 } else if (debug
.address
[0] == debug
.address
[1]) {
780 seq_puts(m
, "adress is constant\n");
782 seq_puts(m
, "is runing\n");
785 seq_printf(m
, "\t address 0: 0x%08x\n", debug
.address
[0]);
786 seq_printf(m
, "\t address 1: 0x%08x\n", debug
.address
[1]);
787 seq_printf(m
, "\t state 0: 0x%08x\n", debug
.state
[0]);
788 seq_printf(m
, "\t state 1: 0x%08x\n", debug
.state
[1]);
789 seq_printf(m
, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
794 pm_runtime_mark_last_busy(gpu
->dev
);
795 pm_runtime_put_autosuspend(gpu
->dev
);
804 static int enable_clk(struct etnaviv_gpu
*gpu
)
807 clk_prepare_enable(gpu
->clk_core
);
809 clk_prepare_enable(gpu
->clk_shader
);
814 static int disable_clk(struct etnaviv_gpu
*gpu
)
817 clk_disable_unprepare(gpu
->clk_core
);
819 clk_disable_unprepare(gpu
->clk_shader
);
824 static int enable_axi(struct etnaviv_gpu
*gpu
)
827 clk_prepare_enable(gpu
->clk_bus
);
832 static int disable_axi(struct etnaviv_gpu
*gpu
)
835 clk_disable_unprepare(gpu
->clk_bus
);
841 * Hangcheck detection for locked gpu:
843 static void recover_worker(struct work_struct
*work
)
845 struct etnaviv_gpu
*gpu
= container_of(work
, struct etnaviv_gpu
,
850 dev_err(gpu
->dev
, "hangcheck recover!\n");
852 if (pm_runtime_get_sync(gpu
->dev
) < 0)
855 mutex_lock(&gpu
->lock
);
857 /* Only catch the first event, or when manually re-armed */
858 if (etnaviv_dump_core
) {
859 etnaviv_core_dump(gpu
);
860 etnaviv_dump_core
= false;
863 etnaviv_hw_reset(gpu
);
865 /* complete all events, the GPU won't do it after the reset */
866 spin_lock_irqsave(&gpu
->event_spinlock
, flags
);
867 for (i
= 0; i
< ARRAY_SIZE(gpu
->event
); i
++) {
868 if (!gpu
->event
[i
].used
)
870 fence_signal(gpu
->event
[i
].fence
);
871 gpu
->event
[i
].fence
= NULL
;
872 gpu
->event
[i
].used
= false;
873 complete(&gpu
->event_free
);
875 * Decrement the PM count for each stuck event. This is safe
876 * even in atomic context as we use ASYNC RPM here.
878 pm_runtime_put_autosuspend(gpu
->dev
);
880 spin_unlock_irqrestore(&gpu
->event_spinlock
, flags
);
881 gpu
->completed_fence
= gpu
->active_fence
;
883 etnaviv_gpu_hw_init(gpu
);
884 gpu
->switch_context
= true;
886 mutex_unlock(&gpu
->lock
);
887 pm_runtime_mark_last_busy(gpu
->dev
);
888 pm_runtime_put_autosuspend(gpu
->dev
);
890 /* Retire the buffer objects in a work */
891 etnaviv_queue_work(gpu
->drm
, &gpu
->retire_work
);
894 static void hangcheck_timer_reset(struct etnaviv_gpu
*gpu
)
896 DBG("%s", dev_name(gpu
->dev
));
897 mod_timer(&gpu
->hangcheck_timer
,
898 round_jiffies_up(jiffies
+ DRM_ETNAVIV_HANGCHECK_JIFFIES
));
901 static void hangcheck_handler(unsigned long data
)
903 struct etnaviv_gpu
*gpu
= (struct etnaviv_gpu
*)data
;
904 u32 fence
= gpu
->completed_fence
;
905 bool progress
= false;
907 if (fence
!= gpu
->hangcheck_fence
) {
908 gpu
->hangcheck_fence
= fence
;
913 u32 dma_addr
= gpu_read(gpu
, VIVS_FE_DMA_ADDRESS
);
914 int change
= dma_addr
- gpu
->hangcheck_dma_addr
;
916 if (change
< 0 || change
> 16) {
917 gpu
->hangcheck_dma_addr
= dma_addr
;
922 if (!progress
&& fence_after(gpu
->active_fence
, fence
)) {
923 dev_err(gpu
->dev
, "hangcheck detected gpu lockup!\n");
924 dev_err(gpu
->dev
, " completed fence: %u\n", fence
);
925 dev_err(gpu
->dev
, " active fence: %u\n",
927 etnaviv_queue_work(gpu
->drm
, &gpu
->recover_work
);
930 /* if still more pending work, reset the hangcheck timer: */
931 if (fence_after(gpu
->active_fence
, gpu
->hangcheck_fence
))
932 hangcheck_timer_reset(gpu
);
935 static void hangcheck_disable(struct etnaviv_gpu
*gpu
)
937 del_timer_sync(&gpu
->hangcheck_timer
);
938 cancel_work_sync(&gpu
->recover_work
);
941 /* fence object management */
942 struct etnaviv_fence
{
943 struct etnaviv_gpu
*gpu
;
947 static inline struct etnaviv_fence
*to_etnaviv_fence(struct fence
*fence
)
949 return container_of(fence
, struct etnaviv_fence
, base
);
952 static const char *etnaviv_fence_get_driver_name(struct fence
*fence
)
957 static const char *etnaviv_fence_get_timeline_name(struct fence
*fence
)
959 struct etnaviv_fence
*f
= to_etnaviv_fence(fence
);
961 return dev_name(f
->gpu
->dev
);
964 static bool etnaviv_fence_enable_signaling(struct fence
*fence
)
969 static bool etnaviv_fence_signaled(struct fence
*fence
)
971 struct etnaviv_fence
*f
= to_etnaviv_fence(fence
);
973 return fence_completed(f
->gpu
, f
->base
.seqno
);
976 static void etnaviv_fence_release(struct fence
*fence
)
978 struct etnaviv_fence
*f
= to_etnaviv_fence(fence
);
980 kfree_rcu(f
, base
.rcu
);
983 static const struct fence_ops etnaviv_fence_ops
= {
984 .get_driver_name
= etnaviv_fence_get_driver_name
,
985 .get_timeline_name
= etnaviv_fence_get_timeline_name
,
986 .enable_signaling
= etnaviv_fence_enable_signaling
,
987 .signaled
= etnaviv_fence_signaled
,
988 .wait
= fence_default_wait
,
989 .release
= etnaviv_fence_release
,
992 static struct fence
*etnaviv_gpu_fence_alloc(struct etnaviv_gpu
*gpu
)
994 struct etnaviv_fence
*f
;
996 f
= kzalloc(sizeof(*f
), GFP_KERNEL
);
1002 fence_init(&f
->base
, &etnaviv_fence_ops
, &gpu
->fence_spinlock
,
1003 gpu
->fence_context
, ++gpu
->next_fence
);
1008 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object
*etnaviv_obj
,
1009 unsigned int context
, bool exclusive
)
1011 struct reservation_object
*robj
= etnaviv_obj
->resv
;
1012 struct reservation_object_list
*fobj
;
1013 struct fence
*fence
;
1017 ret
= reservation_object_reserve_shared(robj
);
1023 * If we have any shared fences, then the exclusive fence
1024 * should be ignored as it will already have been signalled.
1026 fobj
= reservation_object_get_list(robj
);
1027 if (!fobj
|| fobj
->shared_count
== 0) {
1028 /* Wait on any existing exclusive fence which isn't our own */
1029 fence
= reservation_object_get_excl(robj
);
1030 if (fence
&& fence
->context
!= context
) {
1031 ret
= fence_wait(fence
, true);
1037 if (!exclusive
|| !fobj
)
1040 for (i
= 0; i
< fobj
->shared_count
; i
++) {
1041 fence
= rcu_dereference_protected(fobj
->shared
[i
],
1042 reservation_object_held(robj
));
1043 if (fence
->context
!= context
) {
1044 ret
= fence_wait(fence
, true);
1057 static unsigned int event_alloc(struct etnaviv_gpu
*gpu
)
1059 unsigned long ret
, flags
;
1060 unsigned int i
, event
= ~0U;
1062 ret
= wait_for_completion_timeout(&gpu
->event_free
,
1063 msecs_to_jiffies(10 * 10000));
1065 dev_err(gpu
->dev
, "wait_for_completion_timeout failed");
1067 spin_lock_irqsave(&gpu
->event_spinlock
, flags
);
1069 /* find first free event */
1070 for (i
= 0; i
< ARRAY_SIZE(gpu
->event
); i
++) {
1071 if (gpu
->event
[i
].used
== false) {
1072 gpu
->event
[i
].used
= true;
1078 spin_unlock_irqrestore(&gpu
->event_spinlock
, flags
);
1083 static void event_free(struct etnaviv_gpu
*gpu
, unsigned int event
)
1085 unsigned long flags
;
1087 spin_lock_irqsave(&gpu
->event_spinlock
, flags
);
1089 if (gpu
->event
[event
].used
== false) {
1090 dev_warn(gpu
->dev
, "event %u is already marked as free",
1092 spin_unlock_irqrestore(&gpu
->event_spinlock
, flags
);
1094 gpu
->event
[event
].used
= false;
1095 spin_unlock_irqrestore(&gpu
->event_spinlock
, flags
);
1097 complete(&gpu
->event_free
);
1102 * Cmdstream submission/retirement:
1105 struct etnaviv_cmdbuf
*etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu
*gpu
, u32 size
,
1108 struct etnaviv_cmdbuf
*cmdbuf
;
1109 size_t sz
= size_vstruct(nr_bos
, sizeof(cmdbuf
->bo
[0]),
1112 cmdbuf
= kzalloc(sz
, GFP_KERNEL
);
1116 cmdbuf
->vaddr
= dma_alloc_writecombine(gpu
->dev
, size
, &cmdbuf
->paddr
,
1118 if (!cmdbuf
->vaddr
) {
1124 cmdbuf
->size
= size
;
1129 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf
*cmdbuf
)
1131 dma_free_writecombine(cmdbuf
->gpu
->dev
, cmdbuf
->size
,
1132 cmdbuf
->vaddr
, cmdbuf
->paddr
);
1136 static void retire_worker(struct work_struct
*work
)
1138 struct etnaviv_gpu
*gpu
= container_of(work
, struct etnaviv_gpu
,
1140 u32 fence
= gpu
->completed_fence
;
1141 struct etnaviv_cmdbuf
*cmdbuf
, *tmp
;
1144 mutex_lock(&gpu
->lock
);
1145 list_for_each_entry_safe(cmdbuf
, tmp
, &gpu
->active_cmd_list
, node
) {
1146 if (!fence_is_signaled(cmdbuf
->fence
))
1149 list_del(&cmdbuf
->node
);
1150 fence_put(cmdbuf
->fence
);
1152 for (i
= 0; i
< cmdbuf
->nr_bos
; i
++) {
1153 struct etnaviv_gem_object
*etnaviv_obj
= cmdbuf
->bo
[i
];
1155 atomic_dec(&etnaviv_obj
->gpu_active
);
1156 /* drop the refcount taken in etnaviv_gpu_submit */
1157 etnaviv_gem_put_iova(gpu
, &etnaviv_obj
->base
);
1160 etnaviv_gpu_cmdbuf_free(cmdbuf
);
1163 gpu
->retired_fence
= fence
;
1165 mutex_unlock(&gpu
->lock
);
1167 wake_up_all(&gpu
->fence_event
);
1170 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu
*gpu
,
1171 u32 fence
, struct timespec
*timeout
)
1175 if (fence_after(fence
, gpu
->next_fence
)) {
1176 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1177 fence
, gpu
->next_fence
);
1182 /* No timeout was requested: just test for completion */
1183 ret
= fence_completed(gpu
, fence
) ? 0 : -EBUSY
;
1185 unsigned long remaining
= etnaviv_timeout_to_jiffies(timeout
);
1187 ret
= wait_event_interruptible_timeout(gpu
->fence_event
,
1188 fence_completed(gpu
, fence
),
1191 DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1192 fence
, gpu
->retired_fence
,
1193 gpu
->completed_fence
);
1195 } else if (ret
!= -ERESTARTSYS
) {
1204 * Wait for an object to become inactive. This, on it's own, is not race
1205 * free: the object is moved by the retire worker off the active list, and
1206 * then the iova is put. Moreover, the object could be re-submitted just
1207 * after we notice that it's become inactive.
1209 * Although the retirement happens under the gpu lock, we don't want to hold
1210 * that lock in this function while waiting.
1212 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu
*gpu
,
1213 struct etnaviv_gem_object
*etnaviv_obj
, struct timespec
*timeout
)
1215 unsigned long remaining
;
1219 return !is_active(etnaviv_obj
) ? 0 : -EBUSY
;
1221 remaining
= etnaviv_timeout_to_jiffies(timeout
);
1223 ret
= wait_event_interruptible_timeout(gpu
->fence_event
,
1224 !is_active(etnaviv_obj
),
1227 struct etnaviv_drm_private
*priv
= gpu
->drm
->dev_private
;
1229 /* Synchronise with the retire worker */
1230 flush_workqueue(priv
->wq
);
1232 } else if (ret
== -ERESTARTSYS
) {
1233 return -ERESTARTSYS
;
1239 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu
*gpu
)
1241 return pm_runtime_get_sync(gpu
->dev
);
1244 void etnaviv_gpu_pm_put(struct etnaviv_gpu
*gpu
)
1246 pm_runtime_mark_last_busy(gpu
->dev
);
1247 pm_runtime_put_autosuspend(gpu
->dev
);
1250 /* add bo's to gpu's ring, and kick gpu: */
1251 int etnaviv_gpu_submit(struct etnaviv_gpu
*gpu
,
1252 struct etnaviv_gem_submit
*submit
, struct etnaviv_cmdbuf
*cmdbuf
)
1254 struct fence
*fence
;
1255 unsigned int event
, i
;
1258 ret
= etnaviv_gpu_pm_get_sync(gpu
);
1262 mutex_lock(&gpu
->lock
);
1273 event
= event_alloc(gpu
);
1274 if (unlikely(event
== ~0U)) {
1275 DRM_ERROR("no free event\n");
1280 fence
= etnaviv_gpu_fence_alloc(gpu
);
1282 event_free(gpu
, event
);
1287 gpu
->event
[event
].fence
= fence
;
1288 submit
->fence
= fence
->seqno
;
1289 gpu
->active_fence
= submit
->fence
;
1291 if (gpu
->lastctx
!= cmdbuf
->ctx
) {
1292 gpu
->mmu
->need_flush
= true;
1293 gpu
->switch_context
= true;
1294 gpu
->lastctx
= cmdbuf
->ctx
;
1297 etnaviv_buffer_queue(gpu
, event
, cmdbuf
);
1299 cmdbuf
->fence
= fence
;
1300 list_add_tail(&cmdbuf
->node
, &gpu
->active_cmd_list
);
1302 /* We're committed to adding this command buffer, hold a PM reference */
1303 pm_runtime_get_noresume(gpu
->dev
);
1305 for (i
= 0; i
< submit
->nr_bos
; i
++) {
1306 struct etnaviv_gem_object
*etnaviv_obj
= submit
->bos
[i
].obj
;
1309 /* Each cmdbuf takes a refcount on the iova */
1310 etnaviv_gem_get_iova(gpu
, &etnaviv_obj
->base
, &iova
);
1311 cmdbuf
->bo
[i
] = etnaviv_obj
;
1312 atomic_inc(&etnaviv_obj
->gpu_active
);
1314 if (submit
->bos
[i
].flags
& ETNA_SUBMIT_BO_WRITE
)
1315 reservation_object_add_excl_fence(etnaviv_obj
->resv
,
1318 reservation_object_add_shared_fence(etnaviv_obj
->resv
,
1321 cmdbuf
->nr_bos
= submit
->nr_bos
;
1322 hangcheck_timer_reset(gpu
);
1326 mutex_unlock(&gpu
->lock
);
1328 etnaviv_gpu_pm_put(gpu
);
1336 static irqreturn_t
irq_handler(int irq
, void *data
)
1338 struct etnaviv_gpu
*gpu
= data
;
1339 irqreturn_t ret
= IRQ_NONE
;
1341 u32 intr
= gpu_read(gpu
, VIVS_HI_INTR_ACKNOWLEDGE
);
1346 pm_runtime_mark_last_busy(gpu
->dev
);
1348 dev_dbg(gpu
->dev
, "intr 0x%08x\n", intr
);
1350 if (intr
& VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR
) {
1351 dev_err(gpu
->dev
, "AXI bus error\n");
1352 intr
&= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR
;
1355 while ((event
= ffs(intr
)) != 0) {
1356 struct fence
*fence
;
1360 intr
&= ~(1 << event
);
1362 dev_dbg(gpu
->dev
, "event %u\n", event
);
1364 fence
= gpu
->event
[event
].fence
;
1365 gpu
->event
[event
].fence
= NULL
;
1366 fence_signal(fence
);
1369 * Events can be processed out of order. Eg,
1370 * - allocate and queue event 0
1371 * - allocate event 1
1372 * - event 0 completes, we process it
1373 * - allocate and queue event 0
1374 * - event 1 and event 0 complete
1375 * we can end up processing event 0 first, then 1.
1377 if (fence_after(fence
->seqno
, gpu
->completed_fence
))
1378 gpu
->completed_fence
= fence
->seqno
;
1380 event_free(gpu
, event
);
1383 * We need to balance the runtime PM count caused by
1384 * each submission. Upon submission, we increment
1385 * the runtime PM counter, and allocate one event.
1386 * So here, we put the runtime PM count for each
1389 pm_runtime_put_autosuspend(gpu
->dev
);
1392 /* Retire the buffer objects in a work */
1393 etnaviv_queue_work(gpu
->drm
, &gpu
->retire_work
);
1401 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu
*gpu
)
1405 ret
= enable_clk(gpu
);
1409 ret
= enable_axi(gpu
);
1418 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu
*gpu
)
1422 ret
= disable_axi(gpu
);
1426 ret
= disable_clk(gpu
);
1433 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu
*gpu
)
1436 unsigned long timeout
;
1438 /* Replace the last WAIT with END */
1439 etnaviv_buffer_end(gpu
);
1442 * We know that only the FE is busy here, this should
1443 * happen quickly (as the WAIT is only 200 cycles). If
1444 * we fail, just warn and continue.
1446 timeout
= jiffies
+ msecs_to_jiffies(100);
1448 u32 idle
= gpu_read(gpu
, VIVS_HI_IDLE_STATE
);
1450 if ((idle
& gpu
->idle_mask
) == gpu
->idle_mask
)
1453 if (time_is_before_jiffies(timeout
)) {
1455 "timed out waiting for idle: idle=0x%x\n",
1464 return etnaviv_gpu_clk_disable(gpu
);
1468 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu
*gpu
)
1473 ret
= mutex_lock_killable(&gpu
->lock
);
1477 clock
= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS
|
1478 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1480 etnaviv_gpu_load_clock(gpu
, clock
);
1481 etnaviv_gpu_hw_init(gpu
);
1483 gpu
->switch_context
= true;
1485 mutex_unlock(&gpu
->lock
);
1491 static int etnaviv_gpu_bind(struct device
*dev
, struct device
*master
,
1494 struct drm_device
*drm
= data
;
1495 struct etnaviv_drm_private
*priv
= drm
->dev_private
;
1496 struct etnaviv_gpu
*gpu
= dev_get_drvdata(dev
);
1500 ret
= pm_runtime_get_sync(gpu
->dev
);
1502 ret
= etnaviv_gpu_clk_enable(gpu
);
1508 gpu
->fence_context
= fence_context_alloc(1);
1509 spin_lock_init(&gpu
->fence_spinlock
);
1511 INIT_LIST_HEAD(&gpu
->active_cmd_list
);
1512 INIT_WORK(&gpu
->retire_work
, retire_worker
);
1513 INIT_WORK(&gpu
->recover_work
, recover_worker
);
1514 init_waitqueue_head(&gpu
->fence_event
);
1516 setup_timer(&gpu
->hangcheck_timer
, hangcheck_handler
,
1517 (unsigned long)gpu
);
1519 priv
->gpu
[priv
->num_gpus
++] = gpu
;
1521 pm_runtime_mark_last_busy(gpu
->dev
);
1522 pm_runtime_put_autosuspend(gpu
->dev
);
1527 static void etnaviv_gpu_unbind(struct device
*dev
, struct device
*master
,
1530 struct etnaviv_gpu
*gpu
= dev_get_drvdata(dev
);
1532 DBG("%s", dev_name(gpu
->dev
));
1534 hangcheck_disable(gpu
);
1537 pm_runtime_get_sync(gpu
->dev
);
1538 pm_runtime_put_sync_suspend(gpu
->dev
);
1540 etnaviv_gpu_hw_suspend(gpu
);
1544 etnaviv_gpu_cmdbuf_free(gpu
->buffer
);
1549 etnaviv_iommu_destroy(gpu
->mmu
);
1556 static const struct component_ops gpu_ops
= {
1557 .bind
= etnaviv_gpu_bind
,
1558 .unbind
= etnaviv_gpu_unbind
,
1561 static const struct of_device_id etnaviv_gpu_match
[] = {
1563 .compatible
= "vivante,gc"
1568 static int etnaviv_gpu_platform_probe(struct platform_device
*pdev
)
1570 struct device
*dev
= &pdev
->dev
;
1571 struct etnaviv_gpu
*gpu
;
1574 gpu
= devm_kzalloc(dev
, sizeof(*gpu
), GFP_KERNEL
);
1578 gpu
->dev
= &pdev
->dev
;
1579 mutex_init(&gpu
->lock
);
1582 * Set the GPU base address to the start of physical memory. This
1583 * ensures that if we have up to 2GB, the v1 MMU can address the
1584 * highest memory. This is important as command buffers may be
1585 * allocated outside of this limit.
1587 gpu
->memory_base
= PHYS_OFFSET
;
1589 /* Map registers: */
1590 gpu
->mmio
= etnaviv_ioremap(pdev
, NULL
, dev_name(gpu
->dev
));
1591 if (IS_ERR(gpu
->mmio
))
1592 return PTR_ERR(gpu
->mmio
);
1594 /* Get Interrupt: */
1595 gpu
->irq
= platform_get_irq(pdev
, 0);
1598 dev_err(dev
, "failed to get irq: %d\n", err
);
1602 err
= devm_request_irq(&pdev
->dev
, gpu
->irq
, irq_handler
, 0,
1603 dev_name(gpu
->dev
), gpu
);
1605 dev_err(dev
, "failed to request IRQ%u: %d\n", gpu
->irq
, err
);
1610 gpu
->clk_bus
= devm_clk_get(&pdev
->dev
, "bus");
1611 DBG("clk_bus: %p", gpu
->clk_bus
);
1612 if (IS_ERR(gpu
->clk_bus
))
1613 gpu
->clk_bus
= NULL
;
1615 gpu
->clk_core
= devm_clk_get(&pdev
->dev
, "core");
1616 DBG("clk_core: %p", gpu
->clk_core
);
1617 if (IS_ERR(gpu
->clk_core
))
1618 gpu
->clk_core
= NULL
;
1620 gpu
->clk_shader
= devm_clk_get(&pdev
->dev
, "shader");
1621 DBG("clk_shader: %p", gpu
->clk_shader
);
1622 if (IS_ERR(gpu
->clk_shader
))
1623 gpu
->clk_shader
= NULL
;
1625 /* TODO: figure out max mapped size */
1626 dev_set_drvdata(dev
, gpu
);
1629 * We treat the device as initially suspended. The runtime PM
1630 * autosuspend delay is rather arbitary: no measurements have
1631 * yet been performed to determine an appropriate value.
1633 pm_runtime_use_autosuspend(gpu
->dev
);
1634 pm_runtime_set_autosuspend_delay(gpu
->dev
, 200);
1635 pm_runtime_enable(gpu
->dev
);
1637 err
= component_add(&pdev
->dev
, &gpu_ops
);
1639 dev_err(&pdev
->dev
, "failed to register component: %d\n", err
);
1649 static int etnaviv_gpu_platform_remove(struct platform_device
*pdev
)
1651 component_del(&pdev
->dev
, &gpu_ops
);
1652 pm_runtime_disable(&pdev
->dev
);
1657 static int etnaviv_gpu_rpm_suspend(struct device
*dev
)
1659 struct etnaviv_gpu
*gpu
= dev_get_drvdata(dev
);
1662 /* If we have outstanding fences, we're not idle */
1663 if (gpu
->completed_fence
!= gpu
->active_fence
)
1666 /* Check whether the hardware (except FE) is idle */
1667 mask
= gpu
->idle_mask
& ~VIVS_HI_IDLE_STATE_FE
;
1668 idle
= gpu_read(gpu
, VIVS_HI_IDLE_STATE
) & mask
;
1672 return etnaviv_gpu_hw_suspend(gpu
);
1675 static int etnaviv_gpu_rpm_resume(struct device
*dev
)
1677 struct etnaviv_gpu
*gpu
= dev_get_drvdata(dev
);
1680 ret
= etnaviv_gpu_clk_enable(gpu
);
1684 /* Re-initialise the basic hardware state */
1685 if (gpu
->drm
&& gpu
->buffer
) {
1686 ret
= etnaviv_gpu_hw_resume(gpu
);
1688 etnaviv_gpu_clk_disable(gpu
);
1697 static const struct dev_pm_ops etnaviv_gpu_pm_ops
= {
1698 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend
, etnaviv_gpu_rpm_resume
,
1702 struct platform_driver etnaviv_gpu_driver
= {
1704 .name
= "etnaviv-gpu",
1705 .owner
= THIS_MODULE
,
1706 .pm
= &etnaviv_gpu_pm_ops
,
1707 .of_match_table
= etnaviv_gpu_match
,
1709 .probe
= etnaviv_gpu_platform_probe
,
1710 .remove
= etnaviv_gpu_platform_remove
,
1711 .id_table
= gpu_ids
,