2 * Copyright (C) 2015 Etnaviv Project
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #ifndef __ETNAVIV_GPU_H__
18 #define __ETNAVIV_GPU_H__
20 #include <linux/clk.h>
21 #include <linux/regulator/consumer.h>
23 #include "etnaviv_drv.h"
25 struct etnaviv_gem_submit
;
27 struct etnaviv_chip_identity
{
34 /* Supported feature fields. */
37 /* Supported minor feature fields. */
40 /* Supported minor feature 1 fields. */
43 /* Supported minor feature 2 fields. */
46 /* Supported minor feature 3 fields. */
49 /* Supported minor feature 4 fields. */
52 /* Supported minor feature 5 fields. */
55 /* Number of streams supported. */
58 /* Total number of temporary registers per thread. */
61 /* Maximum number of threads. */
64 /* Number of shader cores. */
65 u32 shader_core_count
;
67 /* Size of the vertex cache. */
68 u32 vertex_cache_size
;
70 /* Number of entries in the vertex output buffer. */
71 u32 vertex_output_buffer_size
;
73 /* Number of pixel pipes. */
76 /* Number of instructions. */
77 u32 instruction_count
;
79 /* Number of constants. */
85 /* Number of varyings */
89 struct etnaviv_event
{
94 struct etnaviv_cmdbuf
;
97 struct drm_device
*drm
;
100 struct etnaviv_chip_identity identity
;
101 struct etnaviv_file_private
*lastctx
;
105 struct etnaviv_cmdbuf
*buffer
;
107 /* bus base address of memory */
110 /* event management: */
111 struct etnaviv_event event
[30];
112 struct completion event_free
;
113 spinlock_t event_spinlock
;
115 /* list of currently in-flight command buffers */
116 struct list_head active_cmd_list
;
120 /* Fencing support */
125 wait_queue_head_t fence_event
;
126 unsigned int fence_context
;
127 spinlock_t fence_spinlock
;
129 /* worker for handling active-list retiring: */
130 struct work_struct retire_work
;
135 struct etnaviv_iommu
*mmu
;
139 struct clk
*clk_core
;
140 struct clk
*clk_shader
;
143 #define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */
144 #define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD)
145 struct timer_list hangcheck_timer
;
147 u32 hangcheck_dma_addr
;
148 struct work_struct recover_work
;
151 struct etnaviv_cmdbuf
{
152 /* device this cmdbuf is allocated for */
153 struct etnaviv_gpu
*gpu
;
154 /* user context key, must be unique between all active users */
155 struct etnaviv_file_private
*ctx
;
156 /* cmdbuf properties */
161 /* fence after which this buffer is to be disposed */
163 /* target exec state */
165 /* per GPU in-flight list */
166 struct list_head node
;
167 /* BOs attached to this command buffer */
169 struct etnaviv_gem_object
*bo
[0];
172 static inline void gpu_write(struct etnaviv_gpu
*gpu
, u32 reg
, u32 data
)
174 etnaviv_writel(data
, gpu
->mmio
+ reg
);
177 static inline u32
gpu_read(struct etnaviv_gpu
*gpu
, u32 reg
)
179 return etnaviv_readl(gpu
->mmio
+ reg
);
182 static inline bool fence_completed(struct etnaviv_gpu
*gpu
, u32 fence
)
184 return fence_after_eq(gpu
->completed_fence
, fence
);
187 static inline bool fence_retired(struct etnaviv_gpu
*gpu
, u32 fence
)
189 return fence_after_eq(gpu
->retired_fence
, fence
);
192 int etnaviv_gpu_get_param(struct etnaviv_gpu
*gpu
, u32 param
, u64
*value
);
194 int etnaviv_gpu_init(struct etnaviv_gpu
*gpu
);
196 #ifdef CONFIG_DEBUG_FS
197 int etnaviv_gpu_debugfs(struct etnaviv_gpu
*gpu
, struct seq_file
*m
);
200 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object
*etnaviv_obj
,
201 unsigned int context
, bool exclusive
);
203 void etnaviv_gpu_retire(struct etnaviv_gpu
*gpu
);
204 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu
*gpu
,
205 u32 fence
, struct timespec
*timeout
);
206 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu
*gpu
,
207 struct etnaviv_gem_object
*etnaviv_obj
, struct timespec
*timeout
);
208 int etnaviv_gpu_submit(struct etnaviv_gpu
*gpu
,
209 struct etnaviv_gem_submit
*submit
, struct etnaviv_cmdbuf
*cmdbuf
);
210 struct etnaviv_cmdbuf
*etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu
*gpu
,
211 u32 size
, size_t nr_bos
);
212 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf
*cmdbuf
);
213 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu
*gpu
);
214 void etnaviv_gpu_pm_put(struct etnaviv_gpu
*gpu
);
216 extern struct platform_driver etnaviv_gpu_driver
;
218 #endif /* __ETNAVIV_GPU_H__ */