drivers/gpu/drm/etnaviv/etnaviv_gpu.h

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __ETNAVIV_GPU_H__
  18 #define __ETNAVIV_GPU_H__
  19
  20 #include <linux/clk.h>
  21 #include <linux/regulator/consumer.h>
  22
  23 #include "etnaviv_drv.h"
  24
  25 struct etnaviv_gem_submit;
  26 struct etnaviv_vram_mapping;
  27
  28 struct etnaviv_chip_identity {
  29         /* Chip model. */
  30         u32 model;
  31
  32         /* Revision value.*/
  33         u32 revision;
  34
  35         /* Supported feature fields. */
  36         u32 features;
  37
  38         /* Supported minor feature fields. */
  39         u32 minor_features0;
  40
  41         /* Supported minor feature 1 fields. */
  42         u32 minor_features1;
  43
  44         /* Supported minor feature 2 fields. */
  45         u32 minor_features2;
  46
  47         /* Supported minor feature 3 fields. */
  48         u32 minor_features3;
  49
  50         /* Supported minor feature 4 fields. */
  51         u32 minor_features4;
  52
  53         /* Supported minor feature 5 fields. */
  54         u32 minor_features5;
  55
  56         /* Number of streams supported. */
  57         u32 stream_count;
  58
  59         /* Total number of temporary registers per thread. */
  60         u32 register_max;
  61
  62         /* Maximum number of threads. */
  63         u32 thread_count;
  64
  65         /* Number of shader cores. */
  66         u32 shader_core_count;
  67
  68         /* Size of the vertex cache. */
  69         u32 vertex_cache_size;
  70
  71         /* Number of entries in the vertex output buffer. */
  72         u32 vertex_output_buffer_size;
  73
  74         /* Number of pixel pipes. */
  75         u32 pixel_pipes;
  76
  77         /* Number of instructions. */
  78         u32 instruction_count;
  79
  80         /* Number of constants. */
  81         u32 num_constants;
  82
  83         /* Buffer size */
  84         u32 buffer_size;
  85
  86         /* Number of varyings */
  87         u8 varyings_count;
  88 };
  89
  90 struct etnaviv_event {
  91         bool used;
  92         struct dma_fence *fence;
  93 };
  94
  95 struct etnaviv_cmdbuf_suballoc;
  96 struct etnaviv_cmdbuf;
  97
  98 struct etnaviv_gpu {
  99         struct drm_device *drm;
 100         struct thermal_cooling_device *cooling;
 101         struct device *dev;
 102         struct mutex lock;
 103         struct etnaviv_chip_identity identity;
 104         struct etnaviv_file_private *lastctx;
 105         bool switch_context;
 106
 107         /* 'ring'-buffer: */
 108         struct etnaviv_cmdbuf *buffer;
 109         int exec_state;
 110
 111         /* bus base address of memory  */
 112         u32 memory_base;
 113
 114         /* event management: */
 115         struct etnaviv_event event[30];
 116         struct completion event_free;
 117         spinlock_t event_spinlock;
 118
 119         /* list of currently in-flight command buffers */
 120         struct list_head active_cmd_list;
 121
 122         u32 idle_mask;
 123
 124         /* Fencing support */
 125         u32 next_fence;
 126         u32 active_fence;
 127         u32 completed_fence;
 128         u32 retired_fence;
 129         wait_queue_head_t fence_event;
 130         u64 fence_context;
 131         spinlock_t fence_spinlock;
 132
 133         /* worker for handling active-list retiring: */
 134         struct work_struct retire_work;
 135
 136         void __iomem *mmio;
 137         int irq;
 138
 139         struct etnaviv_iommu *mmu;
 140         struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc;
 141
 142         /* Power Control: */
 143         struct clk *clk_bus;
 144         struct clk *clk_core;
 145         struct clk *clk_shader;
 146
 147         /* Hang Detction: */
 148 #define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */
 149 #define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD)
 150         struct timer_list hangcheck_timer;
 151         u32 hangcheck_fence;
 152         u32 hangcheck_dma_addr;
 153         struct work_struct recover_work;
 154         unsigned int freq_scale;
 155         unsigned long base_rate_core;
 156         unsigned long base_rate_shader;
 157 };
 158
 159 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
 160 {
 161         etnaviv_writel(data, gpu->mmio + reg);
 162 }
 163
 164 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
 165 {
 166         return etnaviv_readl(gpu->mmio + reg);
 167 }
 168
 169 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
 170 {
 171         return fence_after_eq(gpu->completed_fence, fence);
 172 }
 173
 174 static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence)
 175 {
 176         return fence_after_eq(gpu->retired_fence, fence);
 177 }
 178
 179 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
 180
 181 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
 182
 183 #ifdef CONFIG_DEBUG_FS
 184 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
 185 #endif
 186
 187 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
 188         unsigned int context, bool exclusive, bool implicit);
 189
 190 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
 191 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
 192         u32 fence, struct timespec *timeout);
 193 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
 194         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
 195 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
 196         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf);
 197 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
 198 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
 199 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
 200 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
 201
 202 extern struct platform_driver etnaviv_gpu_driver;
 203
 204 #endif /* __ETNAVIV_GPU_H__ */