drivers/gpu/drm/etnaviv/etnaviv_gpu.h

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __ETNAVIV_GPU_H__
  18 #define __ETNAVIV_GPU_H__
  19
  20 #include <linux/clk.h>
  21 #include <linux/regulator/consumer.h>
  22
  23 #include "etnaviv_drv.h"
  24
  25 struct etnaviv_gem_submit;
  26
  27 struct etnaviv_chip_identity {
  28         /* Chip model. */
  29         u32 model;
  30
  31         /* Revision value.*/
  32         u32 revision;
  33
  34         /* Supported feature fields. */
  35         u32 features;
  36
  37         /* Supported minor feature fields. */
  38         u32 minor_features0;
  39
  40         /* Supported minor feature 1 fields. */
  41         u32 minor_features1;
  42
  43         /* Supported minor feature 2 fields. */
  44         u32 minor_features2;
  45
  46         /* Supported minor feature 3 fields. */
  47         u32 minor_features3;
  48
  49         /* Supported minor feature 4 fields. */
  50         u32 minor_features4;
  51
  52         /* Supported minor feature 5 fields. */
  53         u32 minor_features5;
  54
  55         /* Number of streams supported. */
  56         u32 stream_count;
  57
  58         /* Total number of temporary registers per thread. */
  59         u32 register_max;
  60
  61         /* Maximum number of threads. */
  62         u32 thread_count;
  63
  64         /* Number of shader cores. */
  65         u32 shader_core_count;
  66
  67         /* Size of the vertex cache. */
  68         u32 vertex_cache_size;
  69
  70         /* Number of entries in the vertex output buffer. */
  71         u32 vertex_output_buffer_size;
  72
  73         /* Number of pixel pipes. */
  74         u32 pixel_pipes;
  75
  76         /* Number of instructions. */
  77         u32 instruction_count;
  78
  79         /* Number of constants. */
  80         u32 num_constants;
  81
  82         /* Buffer size */
  83         u32 buffer_size;
  84
  85         /* Number of varyings */
  86         u8 varyings_count;
  87 };
  88
  89 struct etnaviv_event {
  90         bool used;
  91         struct fence *fence;
  92 };
  93
  94 struct etnaviv_cmdbuf;
  95
  96 struct etnaviv_gpu {
  97         struct drm_device *drm;
  98         struct device *dev;
  99         struct mutex lock;
 100         struct etnaviv_chip_identity identity;
 101         struct etnaviv_file_private *lastctx;
 102         bool switch_context;
 103
 104         /* 'ring'-buffer: */
 105         struct etnaviv_cmdbuf *buffer;
 106
 107         /* bus base address of memory  */
 108         u32 memory_base;
 109
 110         /* event management: */
 111         struct etnaviv_event event[30];
 112         struct completion event_free;
 113         spinlock_t event_spinlock;
 114
 115         /* list of currently in-flight command buffers */
 116         struct list_head active_cmd_list;
 117
 118         u32 idle_mask;
 119
 120         /* Fencing support */
 121         u32 next_fence;
 122         u32 active_fence;
 123         u32 completed_fence;
 124         u32 retired_fence;
 125         wait_queue_head_t fence_event;
 126         unsigned int fence_context;
 127         spinlock_t fence_spinlock;
 128
 129         /* worker for handling active-list retiring: */
 130         struct work_struct retire_work;
 131
 132         void __iomem *mmio;
 133         int irq;
 134
 135         struct etnaviv_iommu *mmu;
 136
 137         /* Power Control: */
 138         struct clk *clk_bus;
 139         struct clk *clk_core;
 140         struct clk *clk_shader;
 141
 142         /* Hang Detction: */
 143 #define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */
 144 #define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD)
 145         struct timer_list hangcheck_timer;
 146         u32 hangcheck_fence;
 147         u32 hangcheck_dma_addr;
 148         struct work_struct recover_work;
 149 };
 150
 151 struct etnaviv_cmdbuf {
 152         /* device this cmdbuf is allocated for */
 153         struct etnaviv_gpu *gpu;
 154         /* user context key, must be unique between all active users */
 155         struct etnaviv_file_private *ctx;
 156         /* cmdbuf properties */
 157         void *vaddr;
 158         dma_addr_t paddr;
 159         u32 size;
 160         u32 user_size;
 161         /* fence after which this buffer is to be disposed */
 162         struct fence *fence;
 163         /* target exec state */
 164         u32 exec_state;
 165         /* per GPU in-flight list */
 166         struct list_head node;
 167         /* BOs attached to this command buffer */
 168         unsigned int nr_bos;
 169         struct etnaviv_gem_object *bo[0];
 170 };
 171
 172 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
 173 {
 174         etnaviv_writel(data, gpu->mmio + reg);
 175 }
 176
 177 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
 178 {
 179         return etnaviv_readl(gpu->mmio + reg);
 180 }
 181
 182 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
 183 {
 184         return fence_after_eq(gpu->completed_fence, fence);
 185 }
 186
 187 static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence)
 188 {
 189         return fence_after_eq(gpu->retired_fence, fence);
 190 }
 191
 192 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
 193
 194 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
 195
 196 #ifdef CONFIG_DEBUG_FS
 197 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
 198 #endif
 199
 200 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
 201         unsigned int context, bool exclusive);
 202
 203 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
 204 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
 205         u32 fence, struct timespec *timeout);
 206 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
 207         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
 208 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
 209         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf);
 210 struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu,
 211                                               u32 size, size_t nr_bos);
 212 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf);
 213 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
 214 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
 215
 216 extern struct platform_driver etnaviv_gpu_driver;
 217
 218 #endif /* __ETNAVIV_GPU_H__ */