1 /* drivers/gpu/drm/exynos5433_drm_decon.c
3 * Copyright (C) 2015 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Hyungwon Hwang <human.hwang@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundationr
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/of_device.h>
18 #include <linux/of_gpio.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
22 #include <video/exynos5433_decon.h>
24 #include "exynos_drm_drv.h"
25 #include "exynos_drm_crtc.h"
26 #include "exynos_drm_fb.h"
27 #include "exynos_drm_plane.h"
28 #include "exynos_drm_iommu.h"
30 #define DSD_CFG_MUX 0x1004
31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
34 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
36 #define IFTYPE_I80 (1 << 0)
37 #define I80_HW_TRG (1 << 1)
38 #define IFTYPE_HDMI (1 << 2)
40 static const char * const decon_clks_name
[] = {
50 enum decon_flag_bits
{
58 struct decon_context
{
60 struct drm_device
*drm_dev
;
61 struct exynos_drm_crtc
*crtc
;
62 struct exynos_drm_plane planes
[WINDOWS_NR
];
63 struct exynos_drm_plane_config configs
[WINDOWS_NR
];
65 struct regmap
*sysreg
;
66 struct clk
*clks
[ARRAY_SIZE(decon_clks_name
)];
69 unsigned long out_type
;
73 static const uint32_t decon_formats
[] = {
80 static const enum drm_plane_type decon_win_types
[WINDOWS_NR
] = {
81 DRM_PLANE_TYPE_PRIMARY
,
82 DRM_PLANE_TYPE_OVERLAY
,
83 DRM_PLANE_TYPE_CURSOR
,
86 static inline void decon_set_bits(struct decon_context
*ctx
, u32 reg
, u32 mask
,
89 val
= (val
& mask
) | (readl(ctx
->addr
+ reg
) & ~mask
);
90 writel(val
, ctx
->addr
+ reg
);
93 static int decon_enable_vblank(struct exynos_drm_crtc
*crtc
)
95 struct decon_context
*ctx
= crtc
->ctx
;
98 if (test_bit(BIT_SUSPENDED
, &ctx
->flags
))
101 if (!test_and_set_bit(BIT_IRQS_ENABLED
, &ctx
->flags
)) {
102 val
= VIDINTCON0_INTEN
;
103 if (ctx
->out_type
& IFTYPE_I80
)
104 val
|= VIDINTCON0_FRAMEDONE
;
106 val
|= VIDINTCON0_INTFRMEN
;
108 writel(val
, ctx
->addr
+ DECON_VIDINTCON0
);
114 static void decon_disable_vblank(struct exynos_drm_crtc
*crtc
)
116 struct decon_context
*ctx
= crtc
->ctx
;
118 if (test_bit(BIT_SUSPENDED
, &ctx
->flags
))
121 if (test_and_clear_bit(BIT_IRQS_ENABLED
, &ctx
->flags
))
122 writel(0, ctx
->addr
+ DECON_VIDINTCON0
);
125 static void decon_setup_trigger(struct decon_context
*ctx
)
127 if (!(ctx
->out_type
& (IFTYPE_I80
| I80_HW_TRG
)))
130 if (!(ctx
->out_type
& I80_HW_TRG
)) {
131 writel(TRIGCON_TE_AUTO_MASK
| TRIGCON_SWTRIGEN
132 | TRIGCON_TE_AUTO_MASK
| TRIGCON_SWTRIGEN
,
133 ctx
->addr
+ DECON_TRIGCON
);
137 writel(TRIGCON_TRIGEN_PER_F
| TRIGCON_TRIGEN_F
| TRIGCON_HWTRIGMASK
138 | TRIGCON_HWTRIGEN
, ctx
->addr
+ DECON_TRIGCON
);
140 if (regmap_update_bits(ctx
->sysreg
, DSD_CFG_MUX
,
141 DSD_CFG_MUX_TE_UNMASK_GLOBAL
, ~0))
142 DRM_ERROR("Cannot update sysreg.\n");
145 static void decon_commit(struct exynos_drm_crtc
*crtc
)
147 struct decon_context
*ctx
= crtc
->ctx
;
148 struct drm_display_mode
*m
= &crtc
->base
.mode
;
149 bool interlaced
= false;
152 if (test_bit(BIT_SUSPENDED
, &ctx
->flags
))
155 if (ctx
->out_type
& IFTYPE_HDMI
) {
156 m
->crtc_hsync_start
= m
->crtc_hdisplay
+ 10;
157 m
->crtc_hsync_end
= m
->crtc_htotal
- 92;
158 m
->crtc_vsync_start
= m
->crtc_vdisplay
+ 1;
159 m
->crtc_vsync_end
= m
->crtc_vsync_start
+ 1;
160 if (m
->flags
& DRM_MODE_FLAG_INTERLACE
)
164 decon_setup_trigger(ctx
);
166 /* lcd on and use command if */
169 val
|= VIDOUT_INTERLACE_EN_F
;
170 if (ctx
->out_type
& IFTYPE_I80
) {
171 val
|= VIDOUT_COMMAND_IF
;
173 val
|= VIDOUT_RGB_IF
;
176 writel(val
, ctx
->addr
+ DECON_VIDOUTCON0
);
179 val
= VIDTCON2_LINEVAL(m
->vdisplay
/ 2 - 1) |
180 VIDTCON2_HOZVAL(m
->hdisplay
- 1);
182 val
= VIDTCON2_LINEVAL(m
->vdisplay
- 1) |
183 VIDTCON2_HOZVAL(m
->hdisplay
- 1);
184 writel(val
, ctx
->addr
+ DECON_VIDTCON2
);
186 if (!(ctx
->out_type
& IFTYPE_I80
)) {
187 int vbp
= m
->crtc_vtotal
- m
->crtc_vsync_end
;
188 int vfp
= m
->crtc_vsync_start
- m
->crtc_vdisplay
;
192 val
= VIDTCON00_VBPD_F(vbp
- 1) | VIDTCON00_VFPD_F(vfp
- 1);
193 writel(val
, ctx
->addr
+ DECON_VIDTCON00
);
195 val
= VIDTCON01_VSPW_F(
196 m
->crtc_vsync_end
- m
->crtc_vsync_start
- 1);
197 writel(val
, ctx
->addr
+ DECON_VIDTCON01
);
199 val
= VIDTCON10_HBPD_F(
200 m
->crtc_htotal
- m
->crtc_hsync_end
- 1) |
202 m
->crtc_hsync_start
- m
->crtc_hdisplay
- 1);
203 writel(val
, ctx
->addr
+ DECON_VIDTCON10
);
205 val
= VIDTCON11_HSPW_F(
206 m
->crtc_hsync_end
- m
->crtc_hsync_start
- 1);
207 writel(val
, ctx
->addr
+ DECON_VIDTCON11
);
210 /* enable output and display signal */
211 decon_set_bits(ctx
, DECON_VIDCON0
, VIDCON0_ENVID
| VIDCON0_ENVID_F
, ~0);
213 decon_set_bits(ctx
, DECON_UPDATE
, STANDALONE_UPDATE_F
, ~0);
216 static void decon_win_set_pixfmt(struct decon_context
*ctx
, unsigned int win
,
217 struct drm_framebuffer
*fb
)
221 val
= readl(ctx
->addr
+ DECON_WINCONx(win
));
222 val
&= ~WINCONx_BPPMODE_MASK
;
224 switch (fb
->format
->format
) {
225 case DRM_FORMAT_XRGB1555
:
226 val
|= WINCONx_BPPMODE_16BPP_I1555
;
227 val
|= WINCONx_HAWSWP_F
;
228 val
|= WINCONx_BURSTLEN_16WORD
;
230 case DRM_FORMAT_RGB565
:
231 val
|= WINCONx_BPPMODE_16BPP_565
;
232 val
|= WINCONx_HAWSWP_F
;
233 val
|= WINCONx_BURSTLEN_16WORD
;
235 case DRM_FORMAT_XRGB8888
:
236 val
|= WINCONx_BPPMODE_24BPP_888
;
237 val
|= WINCONx_WSWP_F
;
238 val
|= WINCONx_BURSTLEN_16WORD
;
240 case DRM_FORMAT_ARGB8888
:
241 val
|= WINCONx_BPPMODE_32BPP_A8888
;
242 val
|= WINCONx_WSWP_F
| WINCONx_BLD_PIX_F
| WINCONx_ALPHA_SEL_F
;
243 val
|= WINCONx_BURSTLEN_16WORD
;
246 DRM_ERROR("Proper pixel format is not set\n");
250 DRM_DEBUG_KMS("bpp = %u\n", fb
->format
->cpp
[0] * 8);
253 * In case of exynos, setting dma-burst to 16Word causes permanent
254 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
255 * switching which is based on plane size is not recommended as
256 * plane size varies a lot towards the end of the screen and rapid
257 * movement causes unstable DMA which results into iommu crash/tear.
260 if (fb
->width
< MIN_FB_WIDTH_FOR_16WORD_BURST
) {
261 val
&= ~WINCONx_BURSTLEN_MASK
;
262 val
|= WINCONx_BURSTLEN_8WORD
;
265 writel(val
, ctx
->addr
+ DECON_WINCONx(win
));
268 static void decon_shadow_protect_win(struct decon_context
*ctx
, int win
,
271 decon_set_bits(ctx
, DECON_SHADOWCON
, SHADOWCON_Wx_PROTECT(win
),
275 static void decon_atomic_begin(struct exynos_drm_crtc
*crtc
)
277 struct decon_context
*ctx
= crtc
->ctx
;
280 if (test_bit(BIT_SUSPENDED
, &ctx
->flags
))
283 for (i
= ctx
->first_win
; i
< WINDOWS_NR
; i
++)
284 decon_shadow_protect_win(ctx
, i
, true);
287 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
288 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
289 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
291 static void decon_update_plane(struct exynos_drm_crtc
*crtc
,
292 struct exynos_drm_plane
*plane
)
294 struct exynos_drm_plane_state
*state
=
295 to_exynos_plane_state(plane
->base
.state
);
296 struct decon_context
*ctx
= crtc
->ctx
;
297 struct drm_framebuffer
*fb
= state
->base
.fb
;
298 unsigned int win
= plane
->index
;
299 unsigned int bpp
= fb
->format
->cpp
[0];
300 unsigned int pitch
= fb
->pitches
[0];
301 dma_addr_t dma_addr
= exynos_drm_fb_dma_addr(fb
, 0);
304 if (test_bit(BIT_SUSPENDED
, &ctx
->flags
))
307 if (crtc
->base
.mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
308 val
= COORDINATE_X(state
->crtc
.x
) |
309 COORDINATE_Y(state
->crtc
.y
/ 2);
310 writel(val
, ctx
->addr
+ DECON_VIDOSDxA(win
));
312 val
= COORDINATE_X(state
->crtc
.x
+ state
->crtc
.w
- 1) |
313 COORDINATE_Y((state
->crtc
.y
+ state
->crtc
.h
) / 2 - 1);
314 writel(val
, ctx
->addr
+ DECON_VIDOSDxB(win
));
316 val
= COORDINATE_X(state
->crtc
.x
) | COORDINATE_Y(state
->crtc
.y
);
317 writel(val
, ctx
->addr
+ DECON_VIDOSDxA(win
));
319 val
= COORDINATE_X(state
->crtc
.x
+ state
->crtc
.w
- 1) |
320 COORDINATE_Y(state
->crtc
.y
+ state
->crtc
.h
- 1);
321 writel(val
, ctx
->addr
+ DECON_VIDOSDxB(win
));
324 val
= VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
325 VIDOSD_Wx_ALPHA_B_F(0x0);
326 writel(val
, ctx
->addr
+ DECON_VIDOSDxC(win
));
328 val
= VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
329 VIDOSD_Wx_ALPHA_B_F(0x0);
330 writel(val
, ctx
->addr
+ DECON_VIDOSDxD(win
));
332 writel(dma_addr
, ctx
->addr
+ DECON_VIDW0xADD0B0(win
));
334 val
= dma_addr
+ pitch
* state
->src
.h
;
335 writel(val
, ctx
->addr
+ DECON_VIDW0xADD1B0(win
));
337 if (!(ctx
->out_type
& IFTYPE_HDMI
))
338 val
= BIT_VAL(pitch
- state
->crtc
.w
* bpp
, 27, 14)
339 | BIT_VAL(state
->crtc
.w
* bpp
, 13, 0);
341 val
= BIT_VAL(pitch
- state
->crtc
.w
* bpp
, 29, 15)
342 | BIT_VAL(state
->crtc
.w
* bpp
, 14, 0);
343 writel(val
, ctx
->addr
+ DECON_VIDW0xADD2(win
));
345 decon_win_set_pixfmt(ctx
, win
, fb
);
348 decon_set_bits(ctx
, DECON_WINCONx(win
), WINCONx_ENWIN_F
, ~0);
349 set_bit(BIT_REQUEST_UPDATE
, &ctx
->flags
);
352 static void decon_disable_plane(struct exynos_drm_crtc
*crtc
,
353 struct exynos_drm_plane
*plane
)
355 struct decon_context
*ctx
= crtc
->ctx
;
356 unsigned int win
= plane
->index
;
358 if (test_bit(BIT_SUSPENDED
, &ctx
->flags
))
361 decon_set_bits(ctx
, DECON_WINCONx(win
), WINCONx_ENWIN_F
, 0);
362 set_bit(BIT_REQUEST_UPDATE
, &ctx
->flags
);
365 static void decon_atomic_flush(struct exynos_drm_crtc
*crtc
)
367 struct decon_context
*ctx
= crtc
->ctx
;
370 if (test_bit(BIT_SUSPENDED
, &ctx
->flags
))
373 for (i
= ctx
->first_win
; i
< WINDOWS_NR
; i
++)
374 decon_shadow_protect_win(ctx
, i
, false);
376 if (test_and_clear_bit(BIT_REQUEST_UPDATE
, &ctx
->flags
))
377 decon_set_bits(ctx
, DECON_UPDATE
, STANDALONE_UPDATE_F
, ~0);
379 if (ctx
->out_type
& IFTYPE_I80
)
380 set_bit(BIT_WIN_UPDATED
, &ctx
->flags
);
383 static void decon_swreset(struct decon_context
*ctx
)
387 writel(0, ctx
->addr
+ DECON_VIDCON0
);
388 for (tries
= 2000; tries
; --tries
) {
389 if (~readl(ctx
->addr
+ DECON_VIDCON0
) & VIDCON0_STOP_STATUS
)
394 writel(VIDCON0_SWRESET
, ctx
->addr
+ DECON_VIDCON0
);
395 for (tries
= 2000; tries
; --tries
) {
396 if (~readl(ctx
->addr
+ DECON_VIDCON0
) & VIDCON0_SWRESET
)
401 WARN(tries
== 0, "failed to software reset DECON\n");
403 if (!(ctx
->out_type
& IFTYPE_HDMI
))
406 writel(VIDCON0_CLKVALUP
| VIDCON0_VLCKFREE
, ctx
->addr
+ DECON_VIDCON0
);
407 decon_set_bits(ctx
, DECON_CMU
,
408 CMU_CLKGAGE_MODE_SFR_F
| CMU_CLKGAGE_MODE_MEM_F
, ~0);
409 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE
, ctx
->addr
+ DECON_VIDCON1
);
410 writel(CRCCTRL_CRCEN
| CRCCTRL_CRCSTART_F
| CRCCTRL_CRCCLKEN
,
411 ctx
->addr
+ DECON_CRCCTRL
);
414 static void decon_enable(struct exynos_drm_crtc
*crtc
)
416 struct decon_context
*ctx
= crtc
->ctx
;
418 if (!test_and_clear_bit(BIT_SUSPENDED
, &ctx
->flags
))
421 pm_runtime_get_sync(ctx
->dev
);
423 exynos_drm_pipe_clk_enable(crtc
, true);
425 set_bit(BIT_CLKS_ENABLED
, &ctx
->flags
);
429 /* if vblank was enabled status, enable it again. */
430 if (test_and_clear_bit(BIT_IRQS_ENABLED
, &ctx
->flags
))
431 decon_enable_vblank(ctx
->crtc
);
433 decon_commit(ctx
->crtc
);
436 static void decon_disable(struct exynos_drm_crtc
*crtc
)
438 struct decon_context
*ctx
= crtc
->ctx
;
441 if (test_bit(BIT_SUSPENDED
, &ctx
->flags
))
445 * We need to make sure that all windows are disabled before we
446 * suspend that connector. Otherwise we might try to scan from
447 * a destroyed buffer later.
449 for (i
= ctx
->first_win
; i
< WINDOWS_NR
; i
++)
450 decon_disable_plane(crtc
, &ctx
->planes
[i
]);
454 clear_bit(BIT_CLKS_ENABLED
, &ctx
->flags
);
456 exynos_drm_pipe_clk_enable(crtc
, false);
458 pm_runtime_put_sync(ctx
->dev
);
460 set_bit(BIT_SUSPENDED
, &ctx
->flags
);
463 static void decon_te_irq_handler(struct exynos_drm_crtc
*crtc
)
465 struct decon_context
*ctx
= crtc
->ctx
;
467 if (!test_bit(BIT_CLKS_ENABLED
, &ctx
->flags
) ||
468 (ctx
->out_type
& I80_HW_TRG
))
471 if (test_and_clear_bit(BIT_WIN_UPDATED
, &ctx
->flags
))
472 decon_set_bits(ctx
, DECON_TRIGCON
, TRIGCON_SWTRIGCMD
, ~0);
475 static void decon_clear_channels(struct exynos_drm_crtc
*crtc
)
477 struct decon_context
*ctx
= crtc
->ctx
;
480 DRM_DEBUG_KMS("%s\n", __FILE__
);
482 for (i
= 0; i
< ARRAY_SIZE(decon_clks_name
); i
++) {
483 ret
= clk_prepare_enable(ctx
->clks
[i
]);
488 for (win
= 0; win
< WINDOWS_NR
; win
++) {
489 decon_shadow_protect_win(ctx
, win
, true);
490 decon_set_bits(ctx
, DECON_WINCONx(win
), WINCONx_ENWIN_F
, 0);
491 decon_shadow_protect_win(ctx
, win
, false);
494 decon_set_bits(ctx
, DECON_UPDATE
, STANDALONE_UPDATE_F
, ~0);
496 /* TODO: wait for possible vsync */
501 clk_disable_unprepare(ctx
->clks
[i
]);
504 static const struct exynos_drm_crtc_ops decon_crtc_ops
= {
505 .enable
= decon_enable
,
506 .disable
= decon_disable
,
507 .enable_vblank
= decon_enable_vblank
,
508 .disable_vblank
= decon_disable_vblank
,
509 .atomic_begin
= decon_atomic_begin
,
510 .update_plane
= decon_update_plane
,
511 .disable_plane
= decon_disable_plane
,
512 .atomic_flush
= decon_atomic_flush
,
513 .te_handler
= decon_te_irq_handler
,
516 static int decon_bind(struct device
*dev
, struct device
*master
, void *data
)
518 struct decon_context
*ctx
= dev_get_drvdata(dev
);
519 struct drm_device
*drm_dev
= data
;
520 struct exynos_drm_private
*priv
= drm_dev
->dev_private
;
521 struct exynos_drm_plane
*exynos_plane
;
522 enum exynos_drm_output_type out_type
;
526 ctx
->drm_dev
= drm_dev
;
527 ctx
->pipe
= priv
->pipe
++;
529 for (win
= ctx
->first_win
; win
< WINDOWS_NR
; win
++) {
530 int tmp
= (win
== ctx
->first_win
) ? 0 : win
;
532 ctx
->configs
[win
].pixel_formats
= decon_formats
;
533 ctx
->configs
[win
].num_pixel_formats
= ARRAY_SIZE(decon_formats
);
534 ctx
->configs
[win
].zpos
= win
;
535 ctx
->configs
[win
].type
= decon_win_types
[tmp
];
537 ret
= exynos_plane_init(drm_dev
, &ctx
->planes
[win
], win
,
538 1 << ctx
->pipe
, &ctx
->configs
[win
]);
543 exynos_plane
= &ctx
->planes
[ctx
->first_win
];
544 out_type
= (ctx
->out_type
& IFTYPE_HDMI
) ? EXYNOS_DISPLAY_TYPE_HDMI
545 : EXYNOS_DISPLAY_TYPE_LCD
;
546 ctx
->crtc
= exynos_drm_crtc_create(drm_dev
, &exynos_plane
->base
,
548 &decon_crtc_ops
, ctx
);
549 if (IS_ERR(ctx
->crtc
)) {
550 ret
= PTR_ERR(ctx
->crtc
);
554 decon_clear_channels(ctx
->crtc
);
556 ret
= drm_iommu_attach_device(drm_dev
, dev
);
566 static void decon_unbind(struct device
*dev
, struct device
*master
, void *data
)
568 struct decon_context
*ctx
= dev_get_drvdata(dev
);
570 decon_disable(ctx
->crtc
);
572 /* detach this sub driver from iommu mapping if supported. */
573 drm_iommu_detach_device(ctx
->drm_dev
, ctx
->dev
);
576 static const struct component_ops decon_component_ops
= {
578 .unbind
= decon_unbind
,
581 static irqreturn_t
decon_irq_handler(int irq
, void *dev_id
)
583 struct decon_context
*ctx
= dev_id
;
586 if (!test_bit(BIT_CLKS_ENABLED
, &ctx
->flags
))
589 val
= readl(ctx
->addr
+ DECON_VIDINTCON1
);
590 val
&= VIDINTCON1_INTFRMDONEPEND
| VIDINTCON1_INTFRMPEND
;
593 writel(val
, ctx
->addr
+ DECON_VIDINTCON1
);
594 if (ctx
->out_type
& IFTYPE_HDMI
) {
595 val
= readl(ctx
->addr
+ DECON_VIDOUTCON0
);
596 val
&= VIDOUT_INTERLACE_EN_F
| VIDOUT_INTERLACE_FIELD_F
;
598 (VIDOUT_INTERLACE_EN_F
| VIDOUT_INTERLACE_FIELD_F
))
601 drm_crtc_handle_vblank(&ctx
->crtc
->base
);
609 static int exynos5433_decon_suspend(struct device
*dev
)
611 struct decon_context
*ctx
= dev_get_drvdata(dev
);
612 int i
= ARRAY_SIZE(decon_clks_name
);
615 clk_disable_unprepare(ctx
->clks
[i
]);
620 static int exynos5433_decon_resume(struct device
*dev
)
622 struct decon_context
*ctx
= dev_get_drvdata(dev
);
625 for (i
= 0; i
< ARRAY_SIZE(decon_clks_name
); i
++) {
626 ret
= clk_prepare_enable(ctx
->clks
[i
]);
635 clk_disable_unprepare(ctx
->clks
[i
]);
641 static const struct dev_pm_ops exynos5433_decon_pm_ops
= {
642 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend
, exynos5433_decon_resume
,
646 static const struct of_device_id exynos5433_decon_driver_dt_match
[] = {
648 .compatible
= "samsung,exynos5433-decon",
649 .data
= (void *)I80_HW_TRG
652 .compatible
= "samsung,exynos5433-decon-tv",
653 .data
= (void *)(I80_HW_TRG
| IFTYPE_HDMI
)
657 MODULE_DEVICE_TABLE(of
, exynos5433_decon_driver_dt_match
);
659 static int exynos5433_decon_probe(struct platform_device
*pdev
)
661 struct device
*dev
= &pdev
->dev
;
662 struct decon_context
*ctx
;
663 struct resource
*res
;
667 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
671 __set_bit(BIT_SUSPENDED
, &ctx
->flags
);
673 ctx
->out_type
= (unsigned long)of_device_get_match_data(dev
);
675 if (ctx
->out_type
& IFTYPE_HDMI
) {
677 } else if (of_get_child_by_name(dev
->of_node
, "i80-if-timings")) {
678 ctx
->out_type
|= IFTYPE_I80
;
681 if (ctx
->out_type
| I80_HW_TRG
) {
682 ctx
->sysreg
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
683 "samsung,disp-sysreg");
684 if (IS_ERR(ctx
->sysreg
)) {
685 dev_err(dev
, "failed to get system register\n");
686 return PTR_ERR(ctx
->sysreg
);
690 for (i
= 0; i
< ARRAY_SIZE(decon_clks_name
); i
++) {
693 clk
= devm_clk_get(ctx
->dev
, decon_clks_name
[i
]);
700 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
702 dev_err(dev
, "cannot find IO resource\n");
706 ctx
->addr
= devm_ioremap_resource(dev
, res
);
707 if (IS_ERR(ctx
->addr
)) {
708 dev_err(dev
, "ioremap failed\n");
709 return PTR_ERR(ctx
->addr
);
712 res
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
,
713 (ctx
->out_type
& IFTYPE_I80
) ? "lcd_sys" : "vsync");
715 dev_err(dev
, "cannot find IRQ resource\n");
719 ret
= devm_request_irq(dev
, res
->start
, decon_irq_handler
, 0,
722 dev_err(dev
, "lcd_sys irq request failed\n");
726 platform_set_drvdata(pdev
, ctx
);
728 pm_runtime_enable(dev
);
730 ret
= component_add(dev
, &decon_component_ops
);
732 goto err_disable_pm_runtime
;
736 err_disable_pm_runtime
:
737 pm_runtime_disable(dev
);
742 static int exynos5433_decon_remove(struct platform_device
*pdev
)
744 pm_runtime_disable(&pdev
->dev
);
746 component_del(&pdev
->dev
, &decon_component_ops
);
751 struct platform_driver exynos5433_decon_driver
= {
752 .probe
= exynos5433_decon_probe
,
753 .remove
= exynos5433_decon_remove
,
755 .name
= "exynos5433-decon",
756 .pm
= &exynos5433_decon_pm_ops
,
757 .of_match_table
= exynos5433_decon_driver_dt_match
,