1 /* drivers/gpu/drm/exynos5433_drm_decon.c
3 * Copyright (C) 2015 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Hyungwon Hwang <human.hwang@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundationr
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/iopoll.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/of_device.h>
19 #include <linux/of_gpio.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
23 #include <video/exynos5433_decon.h>
25 #include "exynos_drm_drv.h"
26 #include "exynos_drm_crtc.h"
27 #include "exynos_drm_fb.h"
28 #include "exynos_drm_plane.h"
29 #include "exynos_drm_iommu.h"
31 #define DSD_CFG_MUX 0x1004
32 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
35 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
37 #define I80_HW_TRG (1 << 0)
38 #define IFTYPE_HDMI (1 << 1)
40 static const char * const decon_clks_name
[] = {
50 struct decon_context
{
52 struct drm_device
*drm_dev
;
53 struct exynos_drm_crtc
*crtc
;
54 struct exynos_drm_plane planes
[WINDOWS_NR
];
55 struct exynos_drm_plane_config configs
[WINDOWS_NR
];
57 struct regmap
*sysreg
;
58 struct clk
*clks
[ARRAY_SIZE(decon_clks_name
)];
60 unsigned int irq_vsync
;
61 unsigned int irq_lcd_sys
;
63 unsigned long out_type
;
65 spinlock_t vblank_lock
;
69 static const uint32_t decon_formats
[] = {
76 static const enum drm_plane_type decon_win_types
[WINDOWS_NR
] = {
77 DRM_PLANE_TYPE_PRIMARY
,
78 DRM_PLANE_TYPE_OVERLAY
,
79 DRM_PLANE_TYPE_CURSOR
,
82 static inline void decon_set_bits(struct decon_context
*ctx
, u32 reg
, u32 mask
,
85 val
= (val
& mask
) | (readl(ctx
->addr
+ reg
) & ~mask
);
86 writel(val
, ctx
->addr
+ reg
);
89 static int decon_enable_vblank(struct exynos_drm_crtc
*crtc
)
91 struct decon_context
*ctx
= crtc
->ctx
;
94 val
= VIDINTCON0_INTEN
;
96 val
|= VIDINTCON0_FRAMEDONE
;
98 val
|= VIDINTCON0_INTFRMEN
| VIDINTCON0_FRAMESEL_FP
;
100 writel(val
, ctx
->addr
+ DECON_VIDINTCON0
);
102 enable_irq(ctx
->irq
);
103 if (!(ctx
->out_type
& I80_HW_TRG
))
104 enable_irq(ctx
->te_irq
);
109 static void decon_disable_vblank(struct exynos_drm_crtc
*crtc
)
111 struct decon_context
*ctx
= crtc
->ctx
;
113 if (!(ctx
->out_type
& I80_HW_TRG
))
114 disable_irq_nosync(ctx
->te_irq
);
115 disable_irq_nosync(ctx
->irq
);
117 writel(0, ctx
->addr
+ DECON_VIDINTCON0
);
120 /* return number of starts/ends of frame transmissions since reset */
121 static u32
decon_get_frame_count(struct decon_context
*ctx
, bool end
)
123 u32 frm
, pfrm
, status
, cnt
= 2;
125 /* To get consistent result repeat read until frame id is stable.
126 * Usually the loop will be executed once, in rare cases when the loop
127 * is executed at frame change time 2nd pass will be needed.
129 frm
= readl(ctx
->addr
+ DECON_CRFMID
);
131 status
= readl(ctx
->addr
+ DECON_VIDCON1
);
133 frm
= readl(ctx
->addr
+ DECON_CRFMID
);
134 } while (frm
!= pfrm
&& --cnt
);
136 /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
137 * of RGB, it should be taken into account.
142 switch (status
& (VIDCON1_VSTATUS_MASK
| VIDCON1_I80_ACTIVE
)) {
143 case VIDCON1_VSTATUS_VS
:
144 if (!(ctx
->crtc
->i80_mode
))
147 case VIDCON1_VSTATUS_BP
:
150 case VIDCON1_I80_ACTIVE
:
151 case VIDCON1_VSTATUS_AC
:
162 static u32
decon_get_vblank_counter(struct exynos_drm_crtc
*crtc
)
164 struct decon_context
*ctx
= crtc
->ctx
;
166 return decon_get_frame_count(ctx
, false);
169 static void decon_setup_trigger(struct decon_context
*ctx
)
171 if (!ctx
->crtc
->i80_mode
&& !(ctx
->out_type
& I80_HW_TRG
))
174 if (!(ctx
->out_type
& I80_HW_TRG
)) {
175 writel(TRIGCON_TRIGEN_PER_F
| TRIGCON_TRIGEN_F
|
176 TRIGCON_TE_AUTO_MASK
| TRIGCON_SWTRIGEN
,
177 ctx
->addr
+ DECON_TRIGCON
);
181 writel(TRIGCON_TRIGEN_PER_F
| TRIGCON_TRIGEN_F
| TRIGCON_HWTRIGMASK
182 | TRIGCON_HWTRIGEN
, ctx
->addr
+ DECON_TRIGCON
);
184 if (regmap_update_bits(ctx
->sysreg
, DSD_CFG_MUX
,
185 DSD_CFG_MUX_TE_UNMASK_GLOBAL
, ~0))
186 DRM_ERROR("Cannot update sysreg.\n");
189 static void decon_commit(struct exynos_drm_crtc
*crtc
)
191 struct decon_context
*ctx
= crtc
->ctx
;
192 struct drm_display_mode
*m
= &crtc
->base
.mode
;
193 bool interlaced
= false;
196 if (ctx
->out_type
& IFTYPE_HDMI
) {
197 m
->crtc_hsync_start
= m
->crtc_hdisplay
+ 10;
198 m
->crtc_hsync_end
= m
->crtc_htotal
- 92;
199 m
->crtc_vsync_start
= m
->crtc_vdisplay
+ 1;
200 m
->crtc_vsync_end
= m
->crtc_vsync_start
+ 1;
201 if (m
->flags
& DRM_MODE_FLAG_INTERLACE
)
205 decon_setup_trigger(ctx
);
207 /* lcd on and use command if */
210 val
|= VIDOUT_INTERLACE_EN_F
;
211 if (crtc
->i80_mode
) {
212 val
|= VIDOUT_COMMAND_IF
;
214 val
|= VIDOUT_RGB_IF
;
217 writel(val
, ctx
->addr
+ DECON_VIDOUTCON0
);
220 val
= VIDTCON2_LINEVAL(m
->vdisplay
/ 2 - 1) |
221 VIDTCON2_HOZVAL(m
->hdisplay
- 1);
223 val
= VIDTCON2_LINEVAL(m
->vdisplay
- 1) |
224 VIDTCON2_HOZVAL(m
->hdisplay
- 1);
225 writel(val
, ctx
->addr
+ DECON_VIDTCON2
);
227 if (!crtc
->i80_mode
) {
228 int vbp
= m
->crtc_vtotal
- m
->crtc_vsync_end
;
229 int vfp
= m
->crtc_vsync_start
- m
->crtc_vdisplay
;
233 val
= VIDTCON00_VBPD_F(vbp
- 1) | VIDTCON00_VFPD_F(vfp
- 1);
234 writel(val
, ctx
->addr
+ DECON_VIDTCON00
);
236 val
= VIDTCON01_VSPW_F(
237 m
->crtc_vsync_end
- m
->crtc_vsync_start
- 1);
238 writel(val
, ctx
->addr
+ DECON_VIDTCON01
);
240 val
= VIDTCON10_HBPD_F(
241 m
->crtc_htotal
- m
->crtc_hsync_end
- 1) |
243 m
->crtc_hsync_start
- m
->crtc_hdisplay
- 1);
244 writel(val
, ctx
->addr
+ DECON_VIDTCON10
);
246 val
= VIDTCON11_HSPW_F(
247 m
->crtc_hsync_end
- m
->crtc_hsync_start
- 1);
248 writel(val
, ctx
->addr
+ DECON_VIDTCON11
);
251 /* enable output and display signal */
252 decon_set_bits(ctx
, DECON_VIDCON0
, VIDCON0_ENVID
| VIDCON0_ENVID_F
, ~0);
254 decon_set_bits(ctx
, DECON_UPDATE
, STANDALONE_UPDATE_F
, ~0);
257 static void decon_win_set_pixfmt(struct decon_context
*ctx
, unsigned int win
,
258 struct drm_framebuffer
*fb
)
262 val
= readl(ctx
->addr
+ DECON_WINCONx(win
));
263 val
&= ~WINCONx_BPPMODE_MASK
;
265 switch (fb
->format
->format
) {
266 case DRM_FORMAT_XRGB1555
:
267 val
|= WINCONx_BPPMODE_16BPP_I1555
;
268 val
|= WINCONx_HAWSWP_F
;
269 val
|= WINCONx_BURSTLEN_16WORD
;
271 case DRM_FORMAT_RGB565
:
272 val
|= WINCONx_BPPMODE_16BPP_565
;
273 val
|= WINCONx_HAWSWP_F
;
274 val
|= WINCONx_BURSTLEN_16WORD
;
276 case DRM_FORMAT_XRGB8888
:
277 val
|= WINCONx_BPPMODE_24BPP_888
;
278 val
|= WINCONx_WSWP_F
;
279 val
|= WINCONx_BURSTLEN_16WORD
;
281 case DRM_FORMAT_ARGB8888
:
283 val
|= WINCONx_BPPMODE_32BPP_A8888
;
284 val
|= WINCONx_WSWP_F
| WINCONx_BLD_PIX_F
| WINCONx_ALPHA_SEL_F
;
285 val
|= WINCONx_BURSTLEN_16WORD
;
289 DRM_DEBUG_KMS("cpp = %u\n", fb
->format
->cpp
[0]);
292 * In case of exynos, setting dma-burst to 16Word causes permanent
293 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
294 * switching which is based on plane size is not recommended as
295 * plane size varies a lot towards the end of the screen and rapid
296 * movement causes unstable DMA which results into iommu crash/tear.
299 if (fb
->width
< MIN_FB_WIDTH_FOR_16WORD_BURST
) {
300 val
&= ~WINCONx_BURSTLEN_MASK
;
301 val
|= WINCONx_BURSTLEN_8WORD
;
304 writel(val
, ctx
->addr
+ DECON_WINCONx(win
));
307 static void decon_shadow_protect(struct decon_context
*ctx
, bool protect
)
309 decon_set_bits(ctx
, DECON_SHADOWCON
, SHADOWCON_PROTECT_MASK
,
313 static void decon_atomic_begin(struct exynos_drm_crtc
*crtc
)
315 struct decon_context
*ctx
= crtc
->ctx
;
317 decon_shadow_protect(ctx
, true);
320 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
321 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
322 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
324 static void decon_update_plane(struct exynos_drm_crtc
*crtc
,
325 struct exynos_drm_plane
*plane
)
327 struct exynos_drm_plane_state
*state
=
328 to_exynos_plane_state(plane
->base
.state
);
329 struct decon_context
*ctx
= crtc
->ctx
;
330 struct drm_framebuffer
*fb
= state
->base
.fb
;
331 unsigned int win
= plane
->index
;
332 unsigned int cpp
= fb
->format
->cpp
[0];
333 unsigned int pitch
= fb
->pitches
[0];
334 dma_addr_t dma_addr
= exynos_drm_fb_dma_addr(fb
, 0);
337 if (crtc
->base
.mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
338 val
= COORDINATE_X(state
->crtc
.x
) |
339 COORDINATE_Y(state
->crtc
.y
/ 2);
340 writel(val
, ctx
->addr
+ DECON_VIDOSDxA(win
));
342 val
= COORDINATE_X(state
->crtc
.x
+ state
->crtc
.w
- 1) |
343 COORDINATE_Y((state
->crtc
.y
+ state
->crtc
.h
) / 2 - 1);
344 writel(val
, ctx
->addr
+ DECON_VIDOSDxB(win
));
346 val
= COORDINATE_X(state
->crtc
.x
) | COORDINATE_Y(state
->crtc
.y
);
347 writel(val
, ctx
->addr
+ DECON_VIDOSDxA(win
));
349 val
= COORDINATE_X(state
->crtc
.x
+ state
->crtc
.w
- 1) |
350 COORDINATE_Y(state
->crtc
.y
+ state
->crtc
.h
- 1);
351 writel(val
, ctx
->addr
+ DECON_VIDOSDxB(win
));
354 val
= VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
355 VIDOSD_Wx_ALPHA_B_F(0x0);
356 writel(val
, ctx
->addr
+ DECON_VIDOSDxC(win
));
358 val
= VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
359 VIDOSD_Wx_ALPHA_B_F(0x0);
360 writel(val
, ctx
->addr
+ DECON_VIDOSDxD(win
));
362 writel(dma_addr
, ctx
->addr
+ DECON_VIDW0xADD0B0(win
));
364 val
= dma_addr
+ pitch
* state
->src
.h
;
365 writel(val
, ctx
->addr
+ DECON_VIDW0xADD1B0(win
));
367 if (!(ctx
->out_type
& IFTYPE_HDMI
))
368 val
= BIT_VAL(pitch
- state
->crtc
.w
* cpp
, 27, 14)
369 | BIT_VAL(state
->crtc
.w
* cpp
, 13, 0);
371 val
= BIT_VAL(pitch
- state
->crtc
.w
* cpp
, 29, 15)
372 | BIT_VAL(state
->crtc
.w
* cpp
, 14, 0);
373 writel(val
, ctx
->addr
+ DECON_VIDW0xADD2(win
));
375 decon_win_set_pixfmt(ctx
, win
, fb
);
378 decon_set_bits(ctx
, DECON_WINCONx(win
), WINCONx_ENWIN_F
, ~0);
381 static void decon_disable_plane(struct exynos_drm_crtc
*crtc
,
382 struct exynos_drm_plane
*plane
)
384 struct decon_context
*ctx
= crtc
->ctx
;
385 unsigned int win
= plane
->index
;
387 decon_set_bits(ctx
, DECON_WINCONx(win
), WINCONx_ENWIN_F
, 0);
390 static void decon_atomic_flush(struct exynos_drm_crtc
*crtc
)
392 struct decon_context
*ctx
= crtc
->ctx
;
395 spin_lock_irqsave(&ctx
->vblank_lock
, flags
);
397 decon_shadow_protect(ctx
, false);
399 decon_set_bits(ctx
, DECON_UPDATE
, STANDALONE_UPDATE_F
, ~0);
401 ctx
->frame_id
= decon_get_frame_count(ctx
, true);
403 exynos_crtc_handle_event(crtc
);
405 spin_unlock_irqrestore(&ctx
->vblank_lock
, flags
);
408 static void decon_swreset(struct decon_context
*ctx
)
414 writel(0, ctx
->addr
+ DECON_VIDCON0
);
415 readl_poll_timeout(ctx
->addr
+ DECON_VIDCON0
, val
,
416 ~val
& VIDCON0_STOP_STATUS
, 12, 20000);
418 writel(VIDCON0_SWRESET
, ctx
->addr
+ DECON_VIDCON0
);
419 ret
= readl_poll_timeout(ctx
->addr
+ DECON_VIDCON0
, val
,
420 ~val
& VIDCON0_SWRESET
, 12, 20000);
422 WARN(ret
< 0, "failed to software reset DECON\n");
424 spin_lock_irqsave(&ctx
->vblank_lock
, flags
);
426 spin_unlock_irqrestore(&ctx
->vblank_lock
, flags
);
428 if (!(ctx
->out_type
& IFTYPE_HDMI
))
431 writel(VIDCON0_CLKVALUP
| VIDCON0_VLCKFREE
, ctx
->addr
+ DECON_VIDCON0
);
432 decon_set_bits(ctx
, DECON_CMU
,
433 CMU_CLKGAGE_MODE_SFR_F
| CMU_CLKGAGE_MODE_MEM_F
, ~0);
434 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE
, ctx
->addr
+ DECON_VIDCON1
);
435 writel(CRCCTRL_CRCEN
| CRCCTRL_CRCSTART_F
| CRCCTRL_CRCCLKEN
,
436 ctx
->addr
+ DECON_CRCCTRL
);
439 static void decon_enable(struct exynos_drm_crtc
*crtc
)
441 struct decon_context
*ctx
= crtc
->ctx
;
443 pm_runtime_get_sync(ctx
->dev
);
445 exynos_drm_pipe_clk_enable(crtc
, true);
449 decon_commit(ctx
->crtc
);
452 static void decon_disable(struct exynos_drm_crtc
*crtc
)
454 struct decon_context
*ctx
= crtc
->ctx
;
457 if (!(ctx
->out_type
& I80_HW_TRG
))
458 synchronize_irq(ctx
->te_irq
);
459 synchronize_irq(ctx
->irq
);
462 * We need to make sure that all windows are disabled before we
463 * suspend that connector. Otherwise we might try to scan from
464 * a destroyed buffer later.
466 for (i
= ctx
->first_win
; i
< WINDOWS_NR
; i
++)
467 decon_disable_plane(crtc
, &ctx
->planes
[i
]);
471 exynos_drm_pipe_clk_enable(crtc
, false);
473 pm_runtime_put_sync(ctx
->dev
);
476 static irqreturn_t
decon_te_irq_handler(int irq
, void *dev_id
)
478 struct decon_context
*ctx
= dev_id
;
480 decon_set_bits(ctx
, DECON_TRIGCON
, TRIGCON_SWTRIGCMD
, ~0);
485 static void decon_clear_channels(struct exynos_drm_crtc
*crtc
)
487 struct decon_context
*ctx
= crtc
->ctx
;
490 DRM_DEBUG_KMS("%s\n", __FILE__
);
492 for (i
= 0; i
< ARRAY_SIZE(decon_clks_name
); i
++) {
493 ret
= clk_prepare_enable(ctx
->clks
[i
]);
498 decon_shadow_protect(ctx
, true);
499 for (win
= 0; win
< WINDOWS_NR
; win
++)
500 decon_set_bits(ctx
, DECON_WINCONx(win
), WINCONx_ENWIN_F
, 0);
501 decon_shadow_protect(ctx
, false);
503 decon_set_bits(ctx
, DECON_UPDATE
, STANDALONE_UPDATE_F
, ~0);
505 /* TODO: wait for possible vsync */
510 clk_disable_unprepare(ctx
->clks
[i
]);
513 static enum drm_mode_status
decon_mode_valid(struct exynos_drm_crtc
*crtc
,
514 const struct drm_display_mode
*mode
)
516 struct decon_context
*ctx
= crtc
->ctx
;
518 ctx
->irq
= crtc
->i80_mode
? ctx
->irq_lcd_sys
: ctx
->irq_vsync
;
523 dev_info(ctx
->dev
, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
524 crtc
->i80_mode
? "command" : "video");
529 static const struct exynos_drm_crtc_ops decon_crtc_ops
= {
530 .enable
= decon_enable
,
531 .disable
= decon_disable
,
532 .enable_vblank
= decon_enable_vblank
,
533 .disable_vblank
= decon_disable_vblank
,
534 .get_vblank_counter
= decon_get_vblank_counter
,
535 .atomic_begin
= decon_atomic_begin
,
536 .update_plane
= decon_update_plane
,
537 .disable_plane
= decon_disable_plane
,
538 .mode_valid
= decon_mode_valid
,
539 .atomic_flush
= decon_atomic_flush
,
542 static int decon_bind(struct device
*dev
, struct device
*master
, void *data
)
544 struct decon_context
*ctx
= dev_get_drvdata(dev
);
545 struct drm_device
*drm_dev
= data
;
546 struct exynos_drm_plane
*exynos_plane
;
547 enum exynos_drm_output_type out_type
;
551 ctx
->drm_dev
= drm_dev
;
552 drm_dev
->max_vblank_count
= 0xffffffff;
554 for (win
= ctx
->first_win
; win
< WINDOWS_NR
; win
++) {
555 int tmp
= (win
== ctx
->first_win
) ? 0 : win
;
557 ctx
->configs
[win
].pixel_formats
= decon_formats
;
558 ctx
->configs
[win
].num_pixel_formats
= ARRAY_SIZE(decon_formats
);
559 ctx
->configs
[win
].zpos
= win
;
560 ctx
->configs
[win
].type
= decon_win_types
[tmp
];
562 ret
= exynos_plane_init(drm_dev
, &ctx
->planes
[win
], win
,
568 exynos_plane
= &ctx
->planes
[ctx
->first_win
];
569 out_type
= (ctx
->out_type
& IFTYPE_HDMI
) ? EXYNOS_DISPLAY_TYPE_HDMI
570 : EXYNOS_DISPLAY_TYPE_LCD
;
571 ctx
->crtc
= exynos_drm_crtc_create(drm_dev
, &exynos_plane
->base
,
572 out_type
, &decon_crtc_ops
, ctx
);
573 if (IS_ERR(ctx
->crtc
))
574 return PTR_ERR(ctx
->crtc
);
576 decon_clear_channels(ctx
->crtc
);
578 return drm_iommu_attach_device(drm_dev
, dev
);
581 static void decon_unbind(struct device
*dev
, struct device
*master
, void *data
)
583 struct decon_context
*ctx
= dev_get_drvdata(dev
);
585 decon_disable(ctx
->crtc
);
587 /* detach this sub driver from iommu mapping if supported. */
588 drm_iommu_detach_device(ctx
->drm_dev
, ctx
->dev
);
591 static const struct component_ops decon_component_ops
= {
593 .unbind
= decon_unbind
,
596 static void decon_handle_vblank(struct decon_context
*ctx
)
600 spin_lock(&ctx
->vblank_lock
);
602 frm
= decon_get_frame_count(ctx
, true);
604 if (frm
!= ctx
->frame_id
) {
605 /* handle only if incremented, take care of wrap-around */
606 if ((s32
)(frm
- ctx
->frame_id
) > 0)
607 drm_crtc_handle_vblank(&ctx
->crtc
->base
);
611 spin_unlock(&ctx
->vblank_lock
);
614 static irqreturn_t
decon_irq_handler(int irq
, void *dev_id
)
616 struct decon_context
*ctx
= dev_id
;
619 val
= readl(ctx
->addr
+ DECON_VIDINTCON1
);
620 val
&= VIDINTCON1_INTFRMDONEPEND
| VIDINTCON1_INTFRMPEND
;
623 writel(val
, ctx
->addr
+ DECON_VIDINTCON1
);
624 if (ctx
->out_type
& IFTYPE_HDMI
) {
625 val
= readl(ctx
->addr
+ DECON_VIDOUTCON0
);
626 val
&= VIDOUT_INTERLACE_EN_F
| VIDOUT_INTERLACE_FIELD_F
;
628 (VIDOUT_INTERLACE_EN_F
| VIDOUT_INTERLACE_FIELD_F
))
631 decon_handle_vblank(ctx
);
638 static int exynos5433_decon_suspend(struct device
*dev
)
640 struct decon_context
*ctx
= dev_get_drvdata(dev
);
641 int i
= ARRAY_SIZE(decon_clks_name
);
644 clk_disable_unprepare(ctx
->clks
[i
]);
649 static int exynos5433_decon_resume(struct device
*dev
)
651 struct decon_context
*ctx
= dev_get_drvdata(dev
);
654 for (i
= 0; i
< ARRAY_SIZE(decon_clks_name
); i
++) {
655 ret
= clk_prepare_enable(ctx
->clks
[i
]);
664 clk_disable_unprepare(ctx
->clks
[i
]);
670 static const struct dev_pm_ops exynos5433_decon_pm_ops
= {
671 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend
, exynos5433_decon_resume
,
675 static const struct of_device_id exynos5433_decon_driver_dt_match
[] = {
677 .compatible
= "samsung,exynos5433-decon",
678 .data
= (void *)I80_HW_TRG
681 .compatible
= "samsung,exynos5433-decon-tv",
682 .data
= (void *)(I80_HW_TRG
| IFTYPE_HDMI
)
686 MODULE_DEVICE_TABLE(of
, exynos5433_decon_driver_dt_match
);
688 static int decon_conf_irq(struct decon_context
*ctx
, const char *name
,
689 irq_handler_t handler
, unsigned long int flags
)
691 struct platform_device
*pdev
= to_platform_device(ctx
->dev
);
692 int ret
, irq
= platform_get_irq_byname(pdev
, name
);
702 dev_err(ctx
->dev
, "IRQ %s get failed, %d\n", name
, irq
);
706 irq_set_status_flags(irq
, IRQ_NOAUTOEN
);
707 ret
= devm_request_irq(ctx
->dev
, irq
, handler
, flags
, "drm_decon", ctx
);
709 dev_err(ctx
->dev
, "IRQ %s request failed\n", name
);
716 static int exynos5433_decon_probe(struct platform_device
*pdev
)
718 struct device
*dev
= &pdev
->dev
;
719 struct decon_context
*ctx
;
720 struct resource
*res
;
724 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
729 ctx
->out_type
= (unsigned long)of_device_get_match_data(dev
);
730 spin_lock_init(&ctx
->vblank_lock
);
732 if (ctx
->out_type
& IFTYPE_HDMI
)
735 for (i
= 0; i
< ARRAY_SIZE(decon_clks_name
); i
++) {
738 clk
= devm_clk_get(ctx
->dev
, decon_clks_name
[i
]);
745 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
747 dev_err(dev
, "cannot find IO resource\n");
751 ctx
->addr
= devm_ioremap_resource(dev
, res
);
752 if (IS_ERR(ctx
->addr
)) {
753 dev_err(dev
, "ioremap failed\n");
754 return PTR_ERR(ctx
->addr
);
757 ret
= decon_conf_irq(ctx
, "vsync", decon_irq_handler
, 0);
760 ctx
->irq_vsync
= ret
;
762 ret
= decon_conf_irq(ctx
, "lcd_sys", decon_irq_handler
, 0);
765 ctx
->irq_lcd_sys
= ret
;
767 ret
= decon_conf_irq(ctx
, "te", decon_te_irq_handler
,
768 IRQF_TRIGGER_RISING
);
773 ctx
->out_type
&= ~I80_HW_TRG
;
776 if (ctx
->out_type
& I80_HW_TRG
) {
777 ctx
->sysreg
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
778 "samsung,disp-sysreg");
779 if (IS_ERR(ctx
->sysreg
)) {
780 dev_err(dev
, "failed to get system register\n");
781 return PTR_ERR(ctx
->sysreg
);
785 platform_set_drvdata(pdev
, ctx
);
787 pm_runtime_enable(dev
);
789 ret
= component_add(dev
, &decon_component_ops
);
791 goto err_disable_pm_runtime
;
795 err_disable_pm_runtime
:
796 pm_runtime_disable(dev
);
801 static int exynos5433_decon_remove(struct platform_device
*pdev
)
803 pm_runtime_disable(&pdev
->dev
);
805 component_del(&pdev
->dev
, &decon_component_ops
);
810 struct platform_driver exynos5433_decon_driver
= {
811 .probe
= exynos5433_decon_probe
,
812 .remove
= exynos5433_decon_remove
,
814 .name
= "exynos5433-decon",
815 .pm
= &exynos5433_decon_pm_ops
,
816 .of_match_table
= exynos5433_decon_driver_dt_match
,