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drm/exynos/ipp: replace work_struct casting with better constructs
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / exynos / exynos_drm_fimc.c
1 /*
2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
3 * Authors:
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/regmap.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/of.h>
21 #include <linux/spinlock.h>
22
23 #include <drm/drmP.h>
24 #include <drm/exynos_drm.h>
25 #include "regs-fimc.h"
26 #include "exynos_drm_drv.h"
27 #include "exynos_drm_ipp.h"
28 #include "exynos_drm_fimc.h"
29
30 /*
31 * FIMC stands for Fully Interactive Mobile Camera and
32 * supports image scaler/rotator and input/output DMA operations.
33 * input DMA reads image data from the memory.
34 * output DMA writes image data to memory.
35 * FIMC supports image rotation and image effect functions.
36 *
37 * M2M operation : supports crop/scale/rotation/csc so on.
38 * Memory ----> FIMC H/W ----> Memory.
39 * Writeback operation : supports cloned screen with FIMD.
40 * FIMD ----> FIMC H/W ----> Memory.
41 * Output operation : supports direct display using local path.
42 * Memory ----> FIMC H/W ----> FIMD.
43 */
44
45 /*
46 * TODO
47 * 1. check suspend/resume api if needed.
48 * 2. need to check use case platform_device_id.
49 * 3. check src/dst size with, height.
50 * 4. added check_prepare api for right register.
51 * 5. need to add supported list in prop_list.
52 * 6. check prescaler/scaler optimization.
53 */
54
55 #define FIMC_MAX_DEVS 4
56 #define FIMC_MAX_SRC 2
57 #define FIMC_MAX_DST 32
58 #define FIMC_SHFACTOR 10
59 #define FIMC_BUF_STOP 1
60 #define FIMC_BUF_START 2
61 #define FIMC_WIDTH_ITU_709 1280
62 #define FIMC_REFRESH_MAX 60
63 #define FIMC_REFRESH_MIN 12
64 #define FIMC_CROP_MAX 8192
65 #define FIMC_CROP_MIN 32
66 #define FIMC_SCALE_MAX 4224
67 #define FIMC_SCALE_MIN 32
68
69 #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev))
70 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
71 struct fimc_context, ippdrv);
72 enum fimc_wb {
73 FIMC_WB_NONE,
74 FIMC_WB_A,
75 FIMC_WB_B,
76 };
77
78 enum {
79 FIMC_CLK_LCLK,
80 FIMC_CLK_GATE,
81 FIMC_CLK_WB_A,
82 FIMC_CLK_WB_B,
83 FIMC_CLK_MUX,
84 FIMC_CLK_PARENT,
85 FIMC_CLKS_MAX
86 };
87
88 static const char * const fimc_clock_names[] = {
89 [FIMC_CLK_LCLK] = "sclk_fimc",
90 [FIMC_CLK_GATE] = "fimc",
91 [FIMC_CLK_WB_A] = "pxl_async0",
92 [FIMC_CLK_WB_B] = "pxl_async1",
93 [FIMC_CLK_MUX] = "mux",
94 [FIMC_CLK_PARENT] = "parent",
95 };
96
97 #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL
98
99 /*
100 * A structure of scaler.
101 *
102 * @range: narrow, wide.
103 * @bypass: unused scaler path.
104 * @up_h: horizontal scale up.
105 * @up_v: vertical scale up.
106 * @hratio: horizontal ratio.
107 * @vratio: vertical ratio.
108 */
109 struct fimc_scaler {
110 bool range;
111 bool bypass;
112 bool up_h;
113 bool up_v;
114 u32 hratio;
115 u32 vratio;
116 };
117
118 /*
119 * A structure of scaler capability.
120 *
121 * find user manual table 43-1.
122 * @in_hori: scaler input horizontal size.
123 * @bypass: scaler bypass mode.
124 * @dst_h_wo_rot: target horizontal size without output rotation.
125 * @dst_h_rot: target horizontal size with output rotation.
126 * @rl_w_wo_rot: real width without input rotation.
127 * @rl_h_rot: real height without output rotation.
128 */
129 struct fimc_capability {
130 /* scaler */
131 u32 in_hori;
132 u32 bypass;
133 /* output rotator */
134 u32 dst_h_wo_rot;
135 u32 dst_h_rot;
136 /* input rotator */
137 u32 rl_w_wo_rot;
138 u32 rl_h_rot;
139 };
140
141 /*
142 * A structure of fimc context.
143 *
144 * @ippdrv: prepare initialization using ippdrv.
145 * @regs_res: register resources.
146 * @regs: memory mapped io registers.
147 * @lock: locking of operations.
148 * @clocks: fimc clocks.
149 * @clk_frequency: LCLK clock frequency.
150 * @sysreg: handle to SYSREG block regmap.
151 * @sc: scaler infomations.
152 * @pol: porarity of writeback.
153 * @id: fimc id.
154 * @irq: irq number.
155 * @suspended: qos operations.
156 */
157 struct fimc_context {
158 struct exynos_drm_ippdrv ippdrv;
159 struct resource *regs_res;
160 void __iomem *regs;
161 spinlock_t lock;
162 struct clk *clocks[FIMC_CLKS_MAX];
163 u32 clk_frequency;
164 struct regmap *sysreg;
165 struct fimc_scaler sc;
166 struct exynos_drm_ipp_pol pol;
167 int id;
168 int irq;
169 bool suspended;
170 };
171
172 static u32 fimc_read(struct fimc_context *ctx, u32 reg)
173 {
174 return readl(ctx->regs + reg);
175 }
176
177 static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg)
178 {
179 writel(val, ctx->regs + reg);
180 }
181
182 static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits)
183 {
184 void __iomem *r = ctx->regs + reg;
185
186 writel(readl(r) | bits, r);
187 }
188
189 static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits)
190 {
191 void __iomem *r = ctx->regs + reg;
192
193 writel(readl(r) & ~bits, r);
194 }
195
196 static void fimc_sw_reset(struct fimc_context *ctx)
197 {
198 u32 cfg;
199
200 /* stop dma operation */
201 cfg = fimc_read(ctx, EXYNOS_CISTATUS);
202 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg))
203 fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
204
205 fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT);
206
207 /* disable image capture */
208 fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
209 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
210
211 /* s/w reset */
212 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
213
214 /* s/w reset complete */
215 fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
216
217 /* reset sequence */
218 fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
219 }
220
221 static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
222 {
223 return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK,
224 SYSREG_FIMD0WB_DEST_MASK,
225 ctx->id << SYSREG_FIMD0WB_DEST_SHIFT);
226 }
227
228 static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
229 {
230 u32 cfg;
231
232 DRM_DEBUG_KMS("wb[%d]\n", wb);
233
234 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
235 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
236 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
237 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
238 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
239 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
240 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
241
242 switch (wb) {
243 case FIMC_WB_A:
244 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
245 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
246 break;
247 case FIMC_WB_B:
248 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
249 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
250 break;
251 case FIMC_WB_NONE:
252 default:
253 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
254 EXYNOS_CIGCTRL_SELWRITEBACK_A |
255 EXYNOS_CIGCTRL_SELCAM_MIPI_A |
256 EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
257 break;
258 }
259
260 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
261 }
262
263 static void fimc_set_polarity(struct fimc_context *ctx,
264 struct exynos_drm_ipp_pol *pol)
265 {
266 u32 cfg;
267
268 DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n",
269 pol->inv_pclk, pol->inv_vsync);
270 DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n",
271 pol->inv_href, pol->inv_hsync);
272
273 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
274 cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC |
275 EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC);
276
277 if (pol->inv_pclk)
278 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK;
279 if (pol->inv_vsync)
280 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC;
281 if (pol->inv_href)
282 cfg |= EXYNOS_CIGCTRL_INVPOLHREF;
283 if (pol->inv_hsync)
284 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC;
285
286 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
287 }
288
289 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
290 {
291 u32 cfg;
292
293 DRM_DEBUG_KMS("enable[%d]\n", enable);
294
295 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
296 if (enable)
297 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
298 else
299 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
300
301 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
302 }
303
304 static void fimc_mask_irq(struct fimc_context *ctx, bool enable)
305 {
306 u32 cfg;
307
308 DRM_DEBUG_KMS("enable[%d]\n", enable);
309
310 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
311 if (enable) {
312 cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN;
313 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL;
314 } else
315 cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE;
316 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
317 }
318
319 static void fimc_clear_irq(struct fimc_context *ctx)
320 {
321 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR);
322 }
323
324 static bool fimc_check_ovf(struct fimc_context *ctx)
325 {
326 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
327 u32 status, flag;
328
329 status = fimc_read(ctx, EXYNOS_CISTATUS);
330 flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
331 EXYNOS_CISTATUS_OVFICR;
332
333 DRM_DEBUG_KMS("flag[0x%x]\n", flag);
334
335 if (status & flag) {
336 fimc_set_bits(ctx, EXYNOS_CIWDOFST,
337 EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
338 EXYNOS_CIWDOFST_CLROVFICR);
339 fimc_clear_bits(ctx, EXYNOS_CIWDOFST,
340 EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
341 EXYNOS_CIWDOFST_CLROVFICR);
342
343 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
344 ctx->id, status);
345 return true;
346 }
347
348 return false;
349 }
350
351 static bool fimc_check_frame_end(struct fimc_context *ctx)
352 {
353 u32 cfg;
354
355 cfg = fimc_read(ctx, EXYNOS_CISTATUS);
356
357 DRM_DEBUG_KMS("cfg[0x%x]\n", cfg);
358
359 if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
360 return false;
361
362 cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
363 fimc_write(ctx, cfg, EXYNOS_CISTATUS);
364
365 return true;
366 }
367
368 static int fimc_get_buf_id(struct fimc_context *ctx)
369 {
370 u32 cfg;
371 int frame_cnt, buf_id;
372
373 cfg = fimc_read(ctx, EXYNOS_CISTATUS2);
374 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
375
376 if (frame_cnt == 0)
377 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
378
379 DRM_DEBUG_KMS("present[%d]before[%d]\n",
380 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
381 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
382
383 if (frame_cnt == 0) {
384 DRM_ERROR("failed to get frame count.\n");
385 return -EIO;
386 }
387
388 buf_id = frame_cnt - 1;
389 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
390
391 return buf_id;
392 }
393
394 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
395 {
396 u32 cfg;
397
398 DRM_DEBUG_KMS("enable[%d]\n", enable);
399
400 cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
401 if (enable)
402 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
403 else
404 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
405
406 fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
407 }
408
409
410 static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
411 {
412 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
413 u32 cfg;
414
415 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
416
417 /* RGB */
418 cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
419 cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
420
421 switch (fmt) {
422 case DRM_FORMAT_RGB565:
423 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
424 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
425 return 0;
426 case DRM_FORMAT_RGB888:
427 case DRM_FORMAT_XRGB8888:
428 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
429 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
430 return 0;
431 default:
432 /* bypass */
433 break;
434 }
435
436 /* YUV */
437 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
438 cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
439 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
440 EXYNOS_MSCTRL_ORDER422_YCBYCR);
441
442 switch (fmt) {
443 case DRM_FORMAT_YUYV:
444 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
445 break;
446 case DRM_FORMAT_YVYU:
447 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
448 break;
449 case DRM_FORMAT_UYVY:
450 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
451 break;
452 case DRM_FORMAT_VYUY:
453 case DRM_FORMAT_YUV444:
454 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
455 break;
456 case DRM_FORMAT_NV21:
457 case DRM_FORMAT_NV61:
458 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
459 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
460 break;
461 case DRM_FORMAT_YUV422:
462 case DRM_FORMAT_YUV420:
463 case DRM_FORMAT_YVU420:
464 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
465 break;
466 case DRM_FORMAT_NV12:
467 case DRM_FORMAT_NV12MT:
468 case DRM_FORMAT_NV16:
469 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
470 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
471 break;
472 default:
473 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt);
474 return -EINVAL;
475 }
476
477 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
478
479 return 0;
480 }
481
482 static int fimc_src_set_fmt(struct device *dev, u32 fmt)
483 {
484 struct fimc_context *ctx = get_fimc_context(dev);
485 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
486 u32 cfg;
487
488 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
489
490 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
491 cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
492
493 switch (fmt) {
494 case DRM_FORMAT_RGB565:
495 case DRM_FORMAT_RGB888:
496 case DRM_FORMAT_XRGB8888:
497 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
498 break;
499 case DRM_FORMAT_YUV444:
500 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
501 break;
502 case DRM_FORMAT_YUYV:
503 case DRM_FORMAT_YVYU:
504 case DRM_FORMAT_UYVY:
505 case DRM_FORMAT_VYUY:
506 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
507 break;
508 case DRM_FORMAT_NV16:
509 case DRM_FORMAT_NV61:
510 case DRM_FORMAT_YUV422:
511 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
512 break;
513 case DRM_FORMAT_YUV420:
514 case DRM_FORMAT_YVU420:
515 case DRM_FORMAT_NV12:
516 case DRM_FORMAT_NV21:
517 case DRM_FORMAT_NV12MT:
518 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
519 break;
520 default:
521 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt);
522 return -EINVAL;
523 }
524
525 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
526
527 cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
528 cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
529
530 if (fmt == DRM_FORMAT_NV12MT)
531 cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32;
532 else
533 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
534
535 fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
536
537 return fimc_src_set_fmt_order(ctx, fmt);
538 }
539
540 static int fimc_src_set_transf(struct device *dev,
541 enum drm_exynos_degree degree,
542 enum drm_exynos_flip flip, bool *swap)
543 {
544 struct fimc_context *ctx = get_fimc_context(dev);
545 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
546 u32 cfg1, cfg2;
547
548 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
549
550 cfg1 = fimc_read(ctx, EXYNOS_MSCTRL);
551 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
552 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
553
554 cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT);
555 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
556
557 switch (degree) {
558 case EXYNOS_DRM_DEGREE_0:
559 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
560 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
561 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
562 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
563 break;
564 case EXYNOS_DRM_DEGREE_90:
565 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
566 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
567 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
568 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
569 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
570 break;
571 case EXYNOS_DRM_DEGREE_180:
572 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
573 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
574 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
575 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
576 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
577 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
578 break;
579 case EXYNOS_DRM_DEGREE_270:
580 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
581 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
582 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
583 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
584 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
585 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
586 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
587 break;
588 default:
589 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
590 return -EINVAL;
591 }
592
593 fimc_write(ctx, cfg1, EXYNOS_MSCTRL);
594 fimc_write(ctx, cfg2, EXYNOS_CITRGFMT);
595 *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
596
597 return 0;
598 }
599
600 static int fimc_set_window(struct fimc_context *ctx,
601 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
602 {
603 u32 cfg, h1, h2, v1, v2;
604
605 /* cropped image */
606 h1 = pos->x;
607 h2 = sz->hsize - pos->w - pos->x;
608 v1 = pos->y;
609 v2 = sz->vsize - pos->h - pos->y;
610
611 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
612 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
613 DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2);
614
615 /*
616 * set window offset 1, 2 size
617 * check figure 43-21 in user manual
618 */
619 cfg = fimc_read(ctx, EXYNOS_CIWDOFST);
620 cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
621 EXYNOS_CIWDOFST_WINVEROFST_MASK);
622 cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
623 EXYNOS_CIWDOFST_WINVEROFST(v1));
624 cfg |= EXYNOS_CIWDOFST_WINOFSEN;
625 fimc_write(ctx, cfg, EXYNOS_CIWDOFST);
626
627 cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
628 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
629 fimc_write(ctx, cfg, EXYNOS_CIWDOFST2);
630
631 return 0;
632 }
633
634 static int fimc_src_set_size(struct device *dev, int swap,
635 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
636 {
637 struct fimc_context *ctx = get_fimc_context(dev);
638 struct drm_exynos_pos img_pos = *pos;
639 struct drm_exynos_sz img_sz = *sz;
640 u32 cfg;
641
642 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
643 swap, sz->hsize, sz->vsize);
644
645 /* original size */
646 cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
647 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
648
649 fimc_write(ctx, cfg, EXYNOS_ORGISIZE);
650
651 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
652
653 if (swap) {
654 img_pos.w = pos->h;
655 img_pos.h = pos->w;
656 img_sz.hsize = sz->vsize;
657 img_sz.vsize = sz->hsize;
658 }
659
660 /* set input DMA image size */
661 cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE);
662 cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
663 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
664 cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
665 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
666 fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE);
667
668 /*
669 * set input FIFO image size
670 * for now, we support only ITU601 8 bit mode
671 */
672 cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
673 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
674 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
675 fimc_write(ctx, cfg, EXYNOS_CISRCFMT);
676
677 /* offset Y(RGB), Cb, Cr */
678 cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
679 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
680 fimc_write(ctx, cfg, EXYNOS_CIIYOFF);
681 cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
682 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
683 fimc_write(ctx, cfg, EXYNOS_CIICBOFF);
684 cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
685 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
686 fimc_write(ctx, cfg, EXYNOS_CIICROFF);
687
688 return fimc_set_window(ctx, &img_pos, &img_sz);
689 }
690
691 static int fimc_src_set_addr(struct device *dev,
692 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
693 enum drm_exynos_ipp_buf_type buf_type)
694 {
695 struct fimc_context *ctx = get_fimc_context(dev);
696 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
697 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
698 struct drm_exynos_ipp_property *property;
699 struct drm_exynos_ipp_config *config;
700
701 if (!c_node) {
702 DRM_ERROR("failed to get c_node.\n");
703 return -EINVAL;
704 }
705
706 property = &c_node->property;
707
708 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
709 property->prop_id, buf_id, buf_type);
710
711 if (buf_id > FIMC_MAX_SRC) {
712 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
713 return -ENOMEM;
714 }
715
716 /* address register set */
717 switch (buf_type) {
718 case IPP_BUF_ENQUEUE:
719 config = &property->config[EXYNOS_DRM_OPS_SRC];
720 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
721 EXYNOS_CIIYSA(buf_id));
722
723 if (config->fmt == DRM_FORMAT_YVU420) {
724 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
725 EXYNOS_CIICBSA(buf_id));
726 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
727 EXYNOS_CIICRSA(buf_id));
728 } else {
729 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
730 EXYNOS_CIICBSA(buf_id));
731 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
732 EXYNOS_CIICRSA(buf_id));
733 }
734 break;
735 case IPP_BUF_DEQUEUE:
736 fimc_write(ctx, 0x0, EXYNOS_CIIYSA(buf_id));
737 fimc_write(ctx, 0x0, EXYNOS_CIICBSA(buf_id));
738 fimc_write(ctx, 0x0, EXYNOS_CIICRSA(buf_id));
739 break;
740 default:
741 /* bypass */
742 break;
743 }
744
745 return 0;
746 }
747
748 static struct exynos_drm_ipp_ops fimc_src_ops = {
749 .set_fmt = fimc_src_set_fmt,
750 .set_transf = fimc_src_set_transf,
751 .set_size = fimc_src_set_size,
752 .set_addr = fimc_src_set_addr,
753 };
754
755 static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
756 {
757 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
758 u32 cfg;
759
760 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
761
762 /* RGB */
763 cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
764 cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
765
766 switch (fmt) {
767 case DRM_FORMAT_RGB565:
768 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
769 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
770 return 0;
771 case DRM_FORMAT_RGB888:
772 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
773 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
774 return 0;
775 case DRM_FORMAT_XRGB8888:
776 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
777 EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
778 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
779 break;
780 default:
781 /* bypass */
782 break;
783 }
784
785 /* YUV */
786 cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
787 cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
788 EXYNOS_CIOCTRL_ORDER422_MASK |
789 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
790
791 switch (fmt) {
792 case DRM_FORMAT_XRGB8888:
793 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
794 break;
795 case DRM_FORMAT_YUYV:
796 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
797 break;
798 case DRM_FORMAT_YVYU:
799 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
800 break;
801 case DRM_FORMAT_UYVY:
802 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
803 break;
804 case DRM_FORMAT_VYUY:
805 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
806 break;
807 case DRM_FORMAT_NV21:
808 case DRM_FORMAT_NV61:
809 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
810 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
811 break;
812 case DRM_FORMAT_YUV422:
813 case DRM_FORMAT_YUV420:
814 case DRM_FORMAT_YVU420:
815 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
816 break;
817 case DRM_FORMAT_NV12:
818 case DRM_FORMAT_NV12MT:
819 case DRM_FORMAT_NV16:
820 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
821 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
822 break;
823 default:
824 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
825 return -EINVAL;
826 }
827
828 fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
829
830 return 0;
831 }
832
833 static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
834 {
835 struct fimc_context *ctx = get_fimc_context(dev);
836 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
837 u32 cfg;
838
839 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
840
841 cfg = fimc_read(ctx, EXYNOS_CIEXTEN);
842
843 if (fmt == DRM_FORMAT_AYUV) {
844 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
845 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
846 } else {
847 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
848 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
849
850 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
851 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
852
853 switch (fmt) {
854 case DRM_FORMAT_RGB565:
855 case DRM_FORMAT_RGB888:
856 case DRM_FORMAT_XRGB8888:
857 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
858 break;
859 case DRM_FORMAT_YUYV:
860 case DRM_FORMAT_YVYU:
861 case DRM_FORMAT_UYVY:
862 case DRM_FORMAT_VYUY:
863 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
864 break;
865 case DRM_FORMAT_NV16:
866 case DRM_FORMAT_NV61:
867 case DRM_FORMAT_YUV422:
868 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
869 break;
870 case DRM_FORMAT_YUV420:
871 case DRM_FORMAT_YVU420:
872 case DRM_FORMAT_NV12:
873 case DRM_FORMAT_NV12MT:
874 case DRM_FORMAT_NV21:
875 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
876 break;
877 default:
878 dev_err(ippdrv->dev, "inavlid target format 0x%x.\n",
879 fmt);
880 return -EINVAL;
881 }
882
883 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
884 }
885
886 cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
887 cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
888
889 if (fmt == DRM_FORMAT_NV12MT)
890 cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32;
891 else
892 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
893
894 fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
895
896 return fimc_dst_set_fmt_order(ctx, fmt);
897 }
898
899 static int fimc_dst_set_transf(struct device *dev,
900 enum drm_exynos_degree degree,
901 enum drm_exynos_flip flip, bool *swap)
902 {
903 struct fimc_context *ctx = get_fimc_context(dev);
904 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
905 u32 cfg;
906
907 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
908
909 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
910 cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
911 cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
912
913 switch (degree) {
914 case EXYNOS_DRM_DEGREE_0:
915 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
916 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
917 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
918 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
919 break;
920 case EXYNOS_DRM_DEGREE_90:
921 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
922 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
923 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
924 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
925 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
926 break;
927 case EXYNOS_DRM_DEGREE_180:
928 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
929 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
930 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
931 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
932 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
933 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
934 break;
935 case EXYNOS_DRM_DEGREE_270:
936 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
937 EXYNOS_CITRGFMT_FLIP_X_MIRROR |
938 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
939 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
940 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
941 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
942 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
943 break;
944 default:
945 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
946 return -EINVAL;
947 }
948
949 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
950 *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
951
952 return 0;
953 }
954
955 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
956 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
957 {
958 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
959 u32 cfg, cfg_ext, shfactor;
960 u32 pre_dst_width, pre_dst_height;
961 u32 hfactor, vfactor;
962 int ret = 0;
963 u32 src_w, src_h, dst_w, dst_h;
964
965 cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT);
966 if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
967 src_w = src->h;
968 src_h = src->w;
969 } else {
970 src_w = src->w;
971 src_h = src->h;
972 }
973
974 if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
975 dst_w = dst->h;
976 dst_h = dst->w;
977 } else {
978 dst_w = dst->w;
979 dst_h = dst->h;
980 }
981
982 /* fimc_ippdrv_check_property assures that dividers are not null */
983 hfactor = fls(src_w / dst_w / 2);
984 if (hfactor > FIMC_SHFACTOR / 2) {
985 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
986 return -EINVAL;
987 }
988
989 vfactor = fls(src_h / dst_h / 2);
990 if (vfactor > FIMC_SHFACTOR / 2) {
991 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
992 return -EINVAL;
993 }
994
995 pre_dst_width = src_w >> hfactor;
996 pre_dst_height = src_h >> vfactor;
997 DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n",
998 pre_dst_width, pre_dst_height);
999 DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor);
1000
1001 sc->hratio = (src_w << 14) / (dst_w << hfactor);
1002 sc->vratio = (src_h << 14) / (dst_h << vfactor);
1003 sc->up_h = (dst_w >= src_w) ? true : false;
1004 sc->up_v = (dst_h >= src_h) ? true : false;
1005 DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
1006 sc->hratio, sc->vratio, sc->up_h, sc->up_v);
1007
1008 shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
1009 DRM_DEBUG_KMS("shfactor[%d]\n", shfactor);
1010
1011 cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
1012 EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) |
1013 EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor));
1014 fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO);
1015
1016 cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
1017 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
1018 fimc_write(ctx, cfg, EXYNOS_CISCPREDST);
1019
1020 return ret;
1021 }
1022
1023 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
1024 {
1025 u32 cfg, cfg_ext;
1026
1027 DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1028 sc->range, sc->bypass, sc->up_h, sc->up_v);
1029 DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n",
1030 sc->hratio, sc->vratio);
1031
1032 cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
1033 cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
1034 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
1035 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
1036 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
1037 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1038 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1039
1040 if (sc->range)
1041 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1042 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1043 if (sc->bypass)
1044 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1045 if (sc->up_h)
1046 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1047 if (sc->up_v)
1048 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1049
1050 cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1051 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1052 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
1053
1054 cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN);
1055 cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1056 cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1057 cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1058 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1059 fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN);
1060 }
1061
1062 static int fimc_dst_set_size(struct device *dev, int swap,
1063 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1064 {
1065 struct fimc_context *ctx = get_fimc_context(dev);
1066 struct drm_exynos_pos img_pos = *pos;
1067 struct drm_exynos_sz img_sz = *sz;
1068 u32 cfg;
1069
1070 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
1071 swap, sz->hsize, sz->vsize);
1072
1073 /* original size */
1074 cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1075 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1076
1077 fimc_write(ctx, cfg, EXYNOS_ORGOSIZE);
1078
1079 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
1080
1081 /* CSC ITU */
1082 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
1083 cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1084
1085 if (sz->hsize >= FIMC_WIDTH_ITU_709)
1086 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1087 else
1088 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1089
1090 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
1091
1092 if (swap) {
1093 img_pos.w = pos->h;
1094 img_pos.h = pos->w;
1095 img_sz.hsize = sz->vsize;
1096 img_sz.vsize = sz->hsize;
1097 }
1098
1099 /* target image size */
1100 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
1101 cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1102 EXYNOS_CITRGFMT_TARGETV_MASK);
1103 cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1104 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1105 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
1106
1107 /* target area */
1108 cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1109 fimc_write(ctx, cfg, EXYNOS_CITAREA);
1110
1111 /* offset Y(RGB), Cb, Cr */
1112 cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1113 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1114 fimc_write(ctx, cfg, EXYNOS_CIOYOFF);
1115 cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1116 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1117 fimc_write(ctx, cfg, EXYNOS_CIOCBOFF);
1118 cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1119 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1120 fimc_write(ctx, cfg, EXYNOS_CIOCROFF);
1121
1122 return 0;
1123 }
1124
1125 static int fimc_dst_get_buf_count(struct fimc_context *ctx)
1126 {
1127 u32 cfg, buf_num;
1128
1129 cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ);
1130
1131 buf_num = hweight32(cfg);
1132
1133 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
1134
1135 return buf_num;
1136 }
1137
1138 static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1139 enum drm_exynos_ipp_buf_type buf_type)
1140 {
1141 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1142 bool enable;
1143 u32 cfg;
1144 u32 mask = 0x00000001 << buf_id;
1145 int ret = 0;
1146 unsigned long flags;
1147
1148 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1149
1150 spin_lock_irqsave(&ctx->lock, flags);
1151
1152 /* mask register set */
1153 cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ);
1154
1155 switch (buf_type) {
1156 case IPP_BUF_ENQUEUE:
1157 enable = true;
1158 break;
1159 case IPP_BUF_DEQUEUE:
1160 enable = false;
1161 break;
1162 default:
1163 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1164 ret = -EINVAL;
1165 goto err_unlock;
1166 }
1167
1168 /* sequence id */
1169 cfg &= ~mask;
1170 cfg |= (enable << buf_id);
1171 fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ);
1172
1173 /* interrupt enable */
1174 if (buf_type == IPP_BUF_ENQUEUE &&
1175 fimc_dst_get_buf_count(ctx) >= FIMC_BUF_START)
1176 fimc_mask_irq(ctx, true);
1177
1178 /* interrupt disable */
1179 if (buf_type == IPP_BUF_DEQUEUE &&
1180 fimc_dst_get_buf_count(ctx) <= FIMC_BUF_STOP)
1181 fimc_mask_irq(ctx, false);
1182
1183 err_unlock:
1184 spin_unlock_irqrestore(&ctx->lock, flags);
1185 return ret;
1186 }
1187
1188 static int fimc_dst_set_addr(struct device *dev,
1189 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1190 enum drm_exynos_ipp_buf_type buf_type)
1191 {
1192 struct fimc_context *ctx = get_fimc_context(dev);
1193 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1194 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1195 struct drm_exynos_ipp_property *property;
1196 struct drm_exynos_ipp_config *config;
1197
1198 if (!c_node) {
1199 DRM_ERROR("failed to get c_node.\n");
1200 return -EINVAL;
1201 }
1202
1203 property = &c_node->property;
1204
1205 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1206 property->prop_id, buf_id, buf_type);
1207
1208 if (buf_id > FIMC_MAX_DST) {
1209 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1210 return -ENOMEM;
1211 }
1212
1213 /* address register set */
1214 switch (buf_type) {
1215 case IPP_BUF_ENQUEUE:
1216 config = &property->config[EXYNOS_DRM_OPS_DST];
1217
1218 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
1219 EXYNOS_CIOYSA(buf_id));
1220
1221 if (config->fmt == DRM_FORMAT_YVU420) {
1222 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1223 EXYNOS_CIOCBSA(buf_id));
1224 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1225 EXYNOS_CIOCRSA(buf_id));
1226 } else {
1227 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1228 EXYNOS_CIOCBSA(buf_id));
1229 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1230 EXYNOS_CIOCRSA(buf_id));
1231 }
1232 break;
1233 case IPP_BUF_DEQUEUE:
1234 fimc_write(ctx, 0x0, EXYNOS_CIOYSA(buf_id));
1235 fimc_write(ctx, 0x0, EXYNOS_CIOCBSA(buf_id));
1236 fimc_write(ctx, 0x0, EXYNOS_CIOCRSA(buf_id));
1237 break;
1238 default:
1239 /* bypass */
1240 break;
1241 }
1242
1243 return fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1244 }
1245
1246 static struct exynos_drm_ipp_ops fimc_dst_ops = {
1247 .set_fmt = fimc_dst_set_fmt,
1248 .set_transf = fimc_dst_set_transf,
1249 .set_size = fimc_dst_set_size,
1250 .set_addr = fimc_dst_set_addr,
1251 };
1252
1253 static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1254 {
1255 DRM_DEBUG_KMS("enable[%d]\n", enable);
1256
1257 if (enable) {
1258 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1259 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]);
1260 ctx->suspended = false;
1261 } else {
1262 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1263 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]);
1264 ctx->suspended = true;
1265 }
1266
1267 return 0;
1268 }
1269
1270 static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1271 {
1272 struct fimc_context *ctx = dev_id;
1273 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1274 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1275 struct drm_exynos_ipp_event_work *event_work =
1276 c_node->event_work;
1277 int buf_id;
1278
1279 DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id);
1280
1281 fimc_clear_irq(ctx);
1282 if (fimc_check_ovf(ctx))
1283 return IRQ_NONE;
1284
1285 if (!fimc_check_frame_end(ctx))
1286 return IRQ_NONE;
1287
1288 buf_id = fimc_get_buf_id(ctx);
1289 if (buf_id < 0)
1290 return IRQ_HANDLED;
1291
1292 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
1293
1294 if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) {
1295 DRM_ERROR("failed to dequeue.\n");
1296 return IRQ_HANDLED;
1297 }
1298
1299 event_work->ippdrv = ippdrv;
1300 event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1301 queue_work(ippdrv->event_workq, &event_work->work);
1302
1303 return IRQ_HANDLED;
1304 }
1305
1306 static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1307 {
1308 struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1309
1310 prop_list->version = 1;
1311 prop_list->writeback = 1;
1312 prop_list->refresh_min = FIMC_REFRESH_MIN;
1313 prop_list->refresh_max = FIMC_REFRESH_MAX;
1314 prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1315 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1316 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1317 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1318 (1 << EXYNOS_DRM_DEGREE_90) |
1319 (1 << EXYNOS_DRM_DEGREE_180) |
1320 (1 << EXYNOS_DRM_DEGREE_270);
1321 prop_list->csc = 1;
1322 prop_list->crop = 1;
1323 prop_list->crop_max.hsize = FIMC_CROP_MAX;
1324 prop_list->crop_max.vsize = FIMC_CROP_MAX;
1325 prop_list->crop_min.hsize = FIMC_CROP_MIN;
1326 prop_list->crop_min.vsize = FIMC_CROP_MIN;
1327 prop_list->scale = 1;
1328 prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1329 prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1330 prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1331 prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1332
1333 return 0;
1334 }
1335
1336 static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1337 {
1338 switch (flip) {
1339 case EXYNOS_DRM_FLIP_NONE:
1340 case EXYNOS_DRM_FLIP_VERTICAL:
1341 case EXYNOS_DRM_FLIP_HORIZONTAL:
1342 case EXYNOS_DRM_FLIP_BOTH:
1343 return true;
1344 default:
1345 DRM_DEBUG_KMS("invalid flip\n");
1346 return false;
1347 }
1348 }
1349
1350 static int fimc_ippdrv_check_property(struct device *dev,
1351 struct drm_exynos_ipp_property *property)
1352 {
1353 struct fimc_context *ctx = get_fimc_context(dev);
1354 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1355 struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1356 struct drm_exynos_ipp_config *config;
1357 struct drm_exynos_pos *pos;
1358 struct drm_exynos_sz *sz;
1359 bool swap;
1360 int i;
1361
1362 for_each_ipp_ops(i) {
1363 if ((i == EXYNOS_DRM_OPS_SRC) &&
1364 (property->cmd == IPP_CMD_WB))
1365 continue;
1366
1367 config = &property->config[i];
1368 pos = &config->pos;
1369 sz = &config->sz;
1370
1371 /* check for flip */
1372 if (!fimc_check_drm_flip(config->flip)) {
1373 DRM_ERROR("invalid flip.\n");
1374 goto err_property;
1375 }
1376
1377 /* check for degree */
1378 switch (config->degree) {
1379 case EXYNOS_DRM_DEGREE_90:
1380 case EXYNOS_DRM_DEGREE_270:
1381 swap = true;
1382 break;
1383 case EXYNOS_DRM_DEGREE_0:
1384 case EXYNOS_DRM_DEGREE_180:
1385 swap = false;
1386 break;
1387 default:
1388 DRM_ERROR("invalid degree.\n");
1389 goto err_property;
1390 }
1391
1392 /* check for buffer bound */
1393 if ((pos->x + pos->w > sz->hsize) ||
1394 (pos->y + pos->h > sz->vsize)) {
1395 DRM_ERROR("out of buf bound.\n");
1396 goto err_property;
1397 }
1398
1399 /* check for crop */
1400 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1401 if (swap) {
1402 if ((pos->h < pp->crop_min.hsize) ||
1403 (sz->vsize > pp->crop_max.hsize) ||
1404 (pos->w < pp->crop_min.vsize) ||
1405 (sz->hsize > pp->crop_max.vsize)) {
1406 DRM_ERROR("out of crop size.\n");
1407 goto err_property;
1408 }
1409 } else {
1410 if ((pos->w < pp->crop_min.hsize) ||
1411 (sz->hsize > pp->crop_max.hsize) ||
1412 (pos->h < pp->crop_min.vsize) ||
1413 (sz->vsize > pp->crop_max.vsize)) {
1414 DRM_ERROR("out of crop size.\n");
1415 goto err_property;
1416 }
1417 }
1418 }
1419
1420 /* check for scale */
1421 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1422 if (swap) {
1423 if ((pos->h < pp->scale_min.hsize) ||
1424 (sz->vsize > pp->scale_max.hsize) ||
1425 (pos->w < pp->scale_min.vsize) ||
1426 (sz->hsize > pp->scale_max.vsize)) {
1427 DRM_ERROR("out of scale size.\n");
1428 goto err_property;
1429 }
1430 } else {
1431 if ((pos->w < pp->scale_min.hsize) ||
1432 (sz->hsize > pp->scale_max.hsize) ||
1433 (pos->h < pp->scale_min.vsize) ||
1434 (sz->vsize > pp->scale_max.vsize)) {
1435 DRM_ERROR("out of scale size.\n");
1436 goto err_property;
1437 }
1438 }
1439 }
1440 }
1441
1442 return 0;
1443
1444 err_property:
1445 for_each_ipp_ops(i) {
1446 if ((i == EXYNOS_DRM_OPS_SRC) &&
1447 (property->cmd == IPP_CMD_WB))
1448 continue;
1449
1450 config = &property->config[i];
1451 pos = &config->pos;
1452 sz = &config->sz;
1453
1454 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1455 i ? "dst" : "src", config->flip, config->degree,
1456 pos->x, pos->y, pos->w, pos->h,
1457 sz->hsize, sz->vsize);
1458 }
1459
1460 return -EINVAL;
1461 }
1462
1463 static void fimc_clear_addr(struct fimc_context *ctx)
1464 {
1465 int i;
1466
1467 for (i = 0; i < FIMC_MAX_SRC; i++) {
1468 fimc_write(ctx, 0, EXYNOS_CIIYSA(i));
1469 fimc_write(ctx, 0, EXYNOS_CIICBSA(i));
1470 fimc_write(ctx, 0, EXYNOS_CIICRSA(i));
1471 }
1472
1473 for (i = 0; i < FIMC_MAX_DST; i++) {
1474 fimc_write(ctx, 0, EXYNOS_CIOYSA(i));
1475 fimc_write(ctx, 0, EXYNOS_CIOCBSA(i));
1476 fimc_write(ctx, 0, EXYNOS_CIOCRSA(i));
1477 }
1478 }
1479
1480 static int fimc_ippdrv_reset(struct device *dev)
1481 {
1482 struct fimc_context *ctx = get_fimc_context(dev);
1483
1484 /* reset h/w block */
1485 fimc_sw_reset(ctx);
1486
1487 /* reset scaler capability */
1488 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1489
1490 fimc_clear_addr(ctx);
1491
1492 return 0;
1493 }
1494
1495 static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1496 {
1497 struct fimc_context *ctx = get_fimc_context(dev);
1498 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1499 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1500 struct drm_exynos_ipp_property *property;
1501 struct drm_exynos_ipp_config *config;
1502 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1503 struct drm_exynos_ipp_set_wb set_wb;
1504 int ret, i;
1505 u32 cfg0, cfg1;
1506
1507 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1508
1509 if (!c_node) {
1510 DRM_ERROR("failed to get c_node.\n");
1511 return -EINVAL;
1512 }
1513
1514 property = &c_node->property;
1515
1516 fimc_mask_irq(ctx, true);
1517
1518 for_each_ipp_ops(i) {
1519 config = &property->config[i];
1520 img_pos[i] = config->pos;
1521 }
1522
1523 ret = fimc_set_prescaler(ctx, &ctx->sc,
1524 &img_pos[EXYNOS_DRM_OPS_SRC],
1525 &img_pos[EXYNOS_DRM_OPS_DST]);
1526 if (ret) {
1527 dev_err(dev, "failed to set precalser.\n");
1528 return ret;
1529 }
1530
1531 /* If set ture, we can save jpeg about screen */
1532 fimc_handle_jpeg(ctx, false);
1533 fimc_set_scaler(ctx, &ctx->sc);
1534 fimc_set_polarity(ctx, &ctx->pol);
1535
1536 switch (cmd) {
1537 case IPP_CMD_M2M:
1538 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1539 fimc_handle_lastend(ctx, false);
1540
1541 /* setup dma */
1542 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL);
1543 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1544 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1545 fimc_write(ctx, cfg0, EXYNOS_MSCTRL);
1546 break;
1547 case IPP_CMD_WB:
1548 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1549 fimc_handle_lastend(ctx, true);
1550
1551 /* setup FIMD */
1552 ret = fimc_set_camblk_fimd0_wb(ctx);
1553 if (ret < 0) {
1554 dev_err(dev, "camblk setup failed.\n");
1555 return ret;
1556 }
1557
1558 set_wb.enable = 1;
1559 set_wb.refresh = property->refresh_rate;
1560 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1561 break;
1562 case IPP_CMD_OUTPUT:
1563 default:
1564 ret = -EINVAL;
1565 dev_err(dev, "invalid operations.\n");
1566 return ret;
1567 }
1568
1569 /* Reset status */
1570 fimc_write(ctx, 0x0, EXYNOS_CISTATUS);
1571
1572 cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT);
1573 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1574 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1575
1576 /* Scaler */
1577 cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL);
1578 cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1579 cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1580 EXYNOS_CISCCTRL_SCALERSTART);
1581
1582 fimc_write(ctx, cfg1, EXYNOS_CISCCTRL);
1583
1584 /* Enable image capture*/
1585 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1586 fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT);
1587
1588 /* Disable frame end irq */
1589 fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1590
1591 fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK);
1592
1593 if (cmd == IPP_CMD_M2M) {
1594 fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
1595
1596 fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
1597 }
1598
1599 return 0;
1600 }
1601
1602 static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1603 {
1604 struct fimc_context *ctx = get_fimc_context(dev);
1605 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1606 u32 cfg;
1607
1608 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1609
1610 switch (cmd) {
1611 case IPP_CMD_M2M:
1612 /* Source clear */
1613 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
1614 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1615 cfg &= ~EXYNOS_MSCTRL_ENVID;
1616 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
1617 break;
1618 case IPP_CMD_WB:
1619 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1620 break;
1621 case IPP_CMD_OUTPUT:
1622 default:
1623 dev_err(dev, "invalid operations.\n");
1624 break;
1625 }
1626
1627 fimc_mask_irq(ctx, false);
1628
1629 /* reset sequence */
1630 fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
1631
1632 /* Scaler disable */
1633 fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART);
1634
1635 /* Disable image capture */
1636 fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
1637 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1638
1639 /* Enable frame end irq */
1640 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1641 }
1642
1643 static void fimc_put_clocks(struct fimc_context *ctx)
1644 {
1645 int i;
1646
1647 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1648 if (IS_ERR(ctx->clocks[i]))
1649 continue;
1650 clk_put(ctx->clocks[i]);
1651 ctx->clocks[i] = ERR_PTR(-EINVAL);
1652 }
1653 }
1654
1655 static int fimc_setup_clocks(struct fimc_context *ctx)
1656 {
1657 struct device *fimc_dev = ctx->ippdrv.dev;
1658 struct device *dev;
1659 int ret, i;
1660
1661 for (i = 0; i < FIMC_CLKS_MAX; i++)
1662 ctx->clocks[i] = ERR_PTR(-EINVAL);
1663
1664 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1665 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1666 dev = fimc_dev->parent;
1667 else
1668 dev = fimc_dev;
1669
1670 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1671 if (IS_ERR(ctx->clocks[i])) {
1672 if (i >= FIMC_CLK_MUX)
1673 break;
1674 ret = PTR_ERR(ctx->clocks[i]);
1675 dev_err(fimc_dev, "failed to get clock: %s\n",
1676 fimc_clock_names[i]);
1677 goto e_clk_free;
1678 }
1679 }
1680
1681 /* Optional FIMC LCLK parent clock setting */
1682 if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) {
1683 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX],
1684 ctx->clocks[FIMC_CLK_PARENT]);
1685 if (ret < 0) {
1686 dev_err(fimc_dev, "failed to set parent.\n");
1687 goto e_clk_free;
1688 }
1689 }
1690
1691 ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency);
1692 if (ret < 0)
1693 goto e_clk_free;
1694
1695 ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1696 if (!ret)
1697 return ret;
1698 e_clk_free:
1699 fimc_put_clocks(ctx);
1700 return ret;
1701 }
1702
1703 static int fimc_parse_dt(struct fimc_context *ctx)
1704 {
1705 struct device_node *node = ctx->ippdrv.dev->of_node;
1706
1707 /* Handle only devices that support the LCD Writeback data path */
1708 if (!of_property_read_bool(node, "samsung,lcd-wb"))
1709 return -ENODEV;
1710
1711 if (of_property_read_u32(node, "clock-frequency",
1712 &ctx->clk_frequency))
1713 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
1714
1715 ctx->id = of_alias_get_id(node, "fimc");
1716
1717 if (ctx->id < 0) {
1718 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n");
1719 return -EINVAL;
1720 }
1721
1722 return 0;
1723 }
1724
1725 static int fimc_probe(struct platform_device *pdev)
1726 {
1727 struct device *dev = &pdev->dev;
1728 struct fimc_context *ctx;
1729 struct resource *res;
1730 struct exynos_drm_ippdrv *ippdrv;
1731 int ret;
1732
1733 if (!dev->of_node) {
1734 dev_err(dev, "device tree node not found.\n");
1735 return -ENODEV;
1736 }
1737
1738 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1739 if (!ctx)
1740 return -ENOMEM;
1741
1742 ctx->ippdrv.dev = dev;
1743
1744 ret = fimc_parse_dt(ctx);
1745 if (ret < 0)
1746 return ret;
1747
1748 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1749 "samsung,sysreg");
1750 if (IS_ERR(ctx->sysreg)) {
1751 dev_err(dev, "syscon regmap lookup failed.\n");
1752 return PTR_ERR(ctx->sysreg);
1753 }
1754
1755 /* resource memory */
1756 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1757 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1758 if (IS_ERR(ctx->regs))
1759 return PTR_ERR(ctx->regs);
1760
1761 /* resource irq */
1762 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1763 if (!res) {
1764 dev_err(dev, "failed to request irq resource.\n");
1765 return -ENOENT;
1766 }
1767
1768 ctx->irq = res->start;
1769 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
1770 IRQF_ONESHOT, "drm_fimc", ctx);
1771 if (ret < 0) {
1772 dev_err(dev, "failed to request irq.\n");
1773 return ret;
1774 }
1775
1776 ret = fimc_setup_clocks(ctx);
1777 if (ret < 0)
1778 return ret;
1779
1780 ippdrv = &ctx->ippdrv;
1781 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1782 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1783 ippdrv->check_property = fimc_ippdrv_check_property;
1784 ippdrv->reset = fimc_ippdrv_reset;
1785 ippdrv->start = fimc_ippdrv_start;
1786 ippdrv->stop = fimc_ippdrv_stop;
1787 ret = fimc_init_prop_list(ippdrv);
1788 if (ret < 0) {
1789 dev_err(dev, "failed to init property list.\n");
1790 goto err_put_clk;
1791 }
1792
1793 DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1794
1795 spin_lock_init(&ctx->lock);
1796 platform_set_drvdata(pdev, ctx);
1797
1798 pm_runtime_set_active(dev);
1799 pm_runtime_enable(dev);
1800
1801 ret = exynos_drm_ippdrv_register(ippdrv);
1802 if (ret < 0) {
1803 dev_err(dev, "failed to register drm fimc device.\n");
1804 goto err_pm_dis;
1805 }
1806
1807 dev_info(dev, "drm fimc registered successfully.\n");
1808
1809 return 0;
1810
1811 err_pm_dis:
1812 pm_runtime_disable(dev);
1813 err_put_clk:
1814 fimc_put_clocks(ctx);
1815
1816 return ret;
1817 }
1818
1819 static int fimc_remove(struct platform_device *pdev)
1820 {
1821 struct device *dev = &pdev->dev;
1822 struct fimc_context *ctx = get_fimc_context(dev);
1823 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1824
1825 exynos_drm_ippdrv_unregister(ippdrv);
1826
1827 fimc_put_clocks(ctx);
1828 pm_runtime_set_suspended(dev);
1829 pm_runtime_disable(dev);
1830
1831 return 0;
1832 }
1833
1834 #ifdef CONFIG_PM_SLEEP
1835 static int fimc_suspend(struct device *dev)
1836 {
1837 struct fimc_context *ctx = get_fimc_context(dev);
1838
1839 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1840
1841 if (pm_runtime_suspended(dev))
1842 return 0;
1843
1844 return fimc_clk_ctrl(ctx, false);
1845 }
1846
1847 static int fimc_resume(struct device *dev)
1848 {
1849 struct fimc_context *ctx = get_fimc_context(dev);
1850
1851 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1852
1853 if (!pm_runtime_suspended(dev))
1854 return fimc_clk_ctrl(ctx, true);
1855
1856 return 0;
1857 }
1858 #endif
1859
1860 #ifdef CONFIG_PM_RUNTIME
1861 static int fimc_runtime_suspend(struct device *dev)
1862 {
1863 struct fimc_context *ctx = get_fimc_context(dev);
1864
1865 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1866
1867 return fimc_clk_ctrl(ctx, false);
1868 }
1869
1870 static int fimc_runtime_resume(struct device *dev)
1871 {
1872 struct fimc_context *ctx = get_fimc_context(dev);
1873
1874 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1875
1876 return fimc_clk_ctrl(ctx, true);
1877 }
1878 #endif
1879
1880 static const struct dev_pm_ops fimc_pm_ops = {
1881 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1882 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1883 };
1884
1885 static const struct of_device_id fimc_of_match[] = {
1886 { .compatible = "samsung,exynos4210-fimc" },
1887 { .compatible = "samsung,exynos4212-fimc" },
1888 { },
1889 };
1890 MODULE_DEVICE_TABLE(of, fimc_of_match);
1891
1892 struct platform_driver fimc_driver = {
1893 .probe = fimc_probe,
1894 .remove = fimc_remove,
1895 .driver = {
1896 .of_match_table = fimc_of_match,
1897 .name = "exynos-drm-fimc",
1898 .owner = THIS_MODULE,
1899 .pm = &fimc_pm_ops,
1900 },
1901 };
1902
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