3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fb.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_plane.h"
35 #include "exynos_drm_iommu.h"
38 * FIMD stands for Fully Interactive Mobile Display and
39 * as a display controller, it transfers contents drawn on memory
40 * to a LCD Panel through Display Interfaces such as RGB or
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
58 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
60 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
61 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
62 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
63 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
65 /* color key control register for hardware window 1 ~ 4. */
66 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
67 /* color key value register for hardware window 1 ~ 4. */
68 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
70 /* I80 trigger control register */
72 #define TRGMODE_ENABLE (1 << 0)
73 #define SWTRGCMD_ENABLE (1 << 1)
74 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
75 #define HWTRGEN_ENABLE (1 << 3)
76 #define HWTRGMASK_ENABLE (1 << 4)
77 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
78 #define HWTRIGEN_PER_ENABLE (1 << 31)
80 /* display mode change control register except exynos4 */
81 #define VIDOUT_CON 0x000
82 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
84 /* I80 interface control for main LDI register */
85 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
86 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
87 #define LCD_CS_SETUP(x) ((x) << 16)
88 #define LCD_WR_SETUP(x) ((x) << 12)
89 #define LCD_WR_ACTIVE(x) ((x) << 8)
90 #define LCD_WR_HOLD(x) ((x) << 4)
91 #define I80IFEN_ENABLE (1 << 0)
93 /* FIMD has totally five hardware windows. */
96 /* HW trigger flag on i80 panel. */
97 #define I80_HW_TRG (1 << 1)
99 struct fimd_driver_data
{
100 unsigned int timing_base
;
101 unsigned int lcdblk_offset
;
102 unsigned int lcdblk_vt_shift
;
103 unsigned int lcdblk_bypass_shift
;
104 unsigned int lcdblk_mic_bypass_shift
;
105 unsigned int trg_type
;
107 unsigned int has_shadowcon
:1;
108 unsigned int has_clksel
:1;
109 unsigned int has_limited_fmt
:1;
110 unsigned int has_vidoutcon
:1;
111 unsigned int has_vtsel
:1;
112 unsigned int has_mic_bypass
:1;
113 unsigned int has_dp_clk
:1;
114 unsigned int has_hw_trigger
:1;
115 unsigned int has_trigger_per_te
:1;
118 static struct fimd_driver_data s3c64xx_fimd_driver_data
= {
121 .has_limited_fmt
= 1,
124 static struct fimd_driver_data exynos3_fimd_driver_data
= {
125 .timing_base
= 0x20000,
126 .lcdblk_offset
= 0x210,
127 .lcdblk_bypass_shift
= 1,
132 static struct fimd_driver_data exynos4_fimd_driver_data
= {
134 .lcdblk_offset
= 0x210,
135 .lcdblk_vt_shift
= 10,
136 .lcdblk_bypass_shift
= 1,
141 static struct fimd_driver_data exynos5_fimd_driver_data
= {
142 .timing_base
= 0x20000,
143 .lcdblk_offset
= 0x214,
144 .lcdblk_vt_shift
= 24,
145 .lcdblk_bypass_shift
= 15,
152 static struct fimd_driver_data exynos5420_fimd_driver_data
= {
153 .timing_base
= 0x20000,
154 .lcdblk_offset
= 0x214,
155 .lcdblk_vt_shift
= 24,
156 .lcdblk_bypass_shift
= 15,
157 .lcdblk_mic_bypass_shift
= 11,
165 struct fimd_context
{
167 struct drm_device
*drm_dev
;
168 struct exynos_drm_crtc
*crtc
;
169 struct exynos_drm_plane planes
[WINDOWS_NR
];
170 struct exynos_drm_plane_config configs
[WINDOWS_NR
];
174 struct regmap
*sysreg
;
175 unsigned long irq_flags
;
183 wait_queue_head_t wait_vsync_queue
;
184 atomic_t wait_vsync_event
;
185 atomic_t win_updated
;
189 const struct fimd_driver_data
*driver_data
;
190 struct drm_encoder
*encoder
;
191 struct exynos_drm_clk dp_clk
;
194 static const struct of_device_id fimd_driver_dt_match
[] = {
195 { .compatible
= "samsung,s3c6400-fimd",
196 .data
= &s3c64xx_fimd_driver_data
},
197 { .compatible
= "samsung,exynos3250-fimd",
198 .data
= &exynos3_fimd_driver_data
},
199 { .compatible
= "samsung,exynos4210-fimd",
200 .data
= &exynos4_fimd_driver_data
},
201 { .compatible
= "samsung,exynos5250-fimd",
202 .data
= &exynos5_fimd_driver_data
},
203 { .compatible
= "samsung,exynos5420-fimd",
204 .data
= &exynos5420_fimd_driver_data
},
207 MODULE_DEVICE_TABLE(of
, fimd_driver_dt_match
);
209 static const enum drm_plane_type fimd_win_types
[WINDOWS_NR
] = {
210 DRM_PLANE_TYPE_PRIMARY
,
211 DRM_PLANE_TYPE_OVERLAY
,
212 DRM_PLANE_TYPE_OVERLAY
,
213 DRM_PLANE_TYPE_OVERLAY
,
214 DRM_PLANE_TYPE_CURSOR
,
217 static const uint32_t fimd_formats
[] = {
225 static int fimd_enable_vblank(struct exynos_drm_crtc
*crtc
)
227 struct fimd_context
*ctx
= crtc
->ctx
;
233 if (!test_and_set_bit(0, &ctx
->irq_flags
)) {
234 val
= readl(ctx
->regs
+ VIDINTCON0
);
236 val
|= VIDINTCON0_INT_ENABLE
;
239 val
|= VIDINTCON0_INT_I80IFDONE
;
240 val
|= VIDINTCON0_INT_SYSMAINCON
;
241 val
&= ~VIDINTCON0_INT_SYSSUBCON
;
243 val
|= VIDINTCON0_INT_FRAME
;
245 val
&= ~VIDINTCON0_FRAMESEL0_MASK
;
246 val
|= VIDINTCON0_FRAMESEL0_FRONTPORCH
;
247 val
&= ~VIDINTCON0_FRAMESEL1_MASK
;
248 val
|= VIDINTCON0_FRAMESEL1_NONE
;
251 writel(val
, ctx
->regs
+ VIDINTCON0
);
257 static void fimd_disable_vblank(struct exynos_drm_crtc
*crtc
)
259 struct fimd_context
*ctx
= crtc
->ctx
;
265 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
266 val
= readl(ctx
->regs
+ VIDINTCON0
);
268 val
&= ~VIDINTCON0_INT_ENABLE
;
271 val
&= ~VIDINTCON0_INT_I80IFDONE
;
272 val
&= ~VIDINTCON0_INT_SYSMAINCON
;
273 val
&= ~VIDINTCON0_INT_SYSSUBCON
;
275 val
&= ~VIDINTCON0_INT_FRAME
;
277 writel(val
, ctx
->regs
+ VIDINTCON0
);
281 static void fimd_wait_for_vblank(struct exynos_drm_crtc
*crtc
)
283 struct fimd_context
*ctx
= crtc
->ctx
;
288 atomic_set(&ctx
->wait_vsync_event
, 1);
291 * wait for FIMD to signal VSYNC interrupt or return after
292 * timeout which is set to 50ms (refresh rate of 20).
294 if (!wait_event_timeout(ctx
->wait_vsync_queue
,
295 !atomic_read(&ctx
->wait_vsync_event
),
297 DRM_DEBUG_KMS("vblank wait timed out.\n");
300 static void fimd_enable_video_output(struct fimd_context
*ctx
, unsigned int win
,
303 u32 val
= readl(ctx
->regs
+ WINCON(win
));
306 val
|= WINCONx_ENWIN
;
308 val
&= ~WINCONx_ENWIN
;
310 writel(val
, ctx
->regs
+ WINCON(win
));
313 static void fimd_enable_shadow_channel_path(struct fimd_context
*ctx
,
317 u32 val
= readl(ctx
->regs
+ SHADOWCON
);
320 val
|= SHADOWCON_CHx_ENABLE(win
);
322 val
&= ~SHADOWCON_CHx_ENABLE(win
);
324 writel(val
, ctx
->regs
+ SHADOWCON
);
327 static void fimd_clear_channels(struct exynos_drm_crtc
*crtc
)
329 struct fimd_context
*ctx
= crtc
->ctx
;
330 unsigned int win
, ch_enabled
= 0;
332 DRM_DEBUG_KMS("%s\n", __FILE__
);
334 /* Hardware is in unknown state, so ensure it gets enabled properly */
335 pm_runtime_get_sync(ctx
->dev
);
337 clk_prepare_enable(ctx
->bus_clk
);
338 clk_prepare_enable(ctx
->lcd_clk
);
340 /* Check if any channel is enabled. */
341 for (win
= 0; win
< WINDOWS_NR
; win
++) {
342 u32 val
= readl(ctx
->regs
+ WINCON(win
));
344 if (val
& WINCONx_ENWIN
) {
345 fimd_enable_video_output(ctx
, win
, false);
347 if (ctx
->driver_data
->has_shadowcon
)
348 fimd_enable_shadow_channel_path(ctx
, win
,
355 /* Wait for vsync, as disable channel takes effect at next vsync */
357 int pipe
= ctx
->pipe
;
359 /* ensure that vblank interrupt won't be reported to core */
360 ctx
->suspended
= false;
363 fimd_enable_vblank(ctx
->crtc
);
364 fimd_wait_for_vblank(ctx
->crtc
);
365 fimd_disable_vblank(ctx
->crtc
);
367 ctx
->suspended
= true;
371 clk_disable_unprepare(ctx
->lcd_clk
);
372 clk_disable_unprepare(ctx
->bus_clk
);
374 pm_runtime_put(ctx
->dev
);
378 static int fimd_atomic_check(struct exynos_drm_crtc
*crtc
,
379 struct drm_crtc_state
*state
)
381 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
382 struct fimd_context
*ctx
= crtc
->ctx
;
383 unsigned long ideal_clk
, lcd_rate
;
386 if (mode
->clock
== 0) {
387 DRM_INFO("Mode has zero clock value.\n");
391 ideal_clk
= mode
->clock
* 1000;
395 * The frame done interrupt should be occurred prior to the
401 lcd_rate
= clk_get_rate(ctx
->lcd_clk
);
402 if (2 * lcd_rate
< ideal_clk
) {
403 DRM_INFO("sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
404 lcd_rate
, ideal_clk
);
408 /* Find the clock divider value that gets us closest to ideal_clk */
409 clkdiv
= DIV_ROUND_CLOSEST(lcd_rate
, ideal_clk
);
410 if (clkdiv
>= 0x200) {
411 DRM_INFO("requested pixel clock(%lu) too low\n", ideal_clk
);
415 ctx
->clkdiv
= (clkdiv
< 0x100) ? clkdiv
: 0xff;
420 static void fimd_setup_trigger(struct fimd_context
*ctx
)
422 void __iomem
*timing_base
= ctx
->regs
+ ctx
->driver_data
->timing_base
;
423 u32 trg_type
= ctx
->driver_data
->trg_type
;
424 u32 val
= readl(timing_base
+ TRIGCON
);
426 val
&= ~(TRGMODE_ENABLE
);
428 if (trg_type
== I80_HW_TRG
) {
429 if (ctx
->driver_data
->has_hw_trigger
)
430 val
|= HWTRGEN_ENABLE
| HWTRGMASK_ENABLE
;
431 if (ctx
->driver_data
->has_trigger_per_te
)
432 val
|= HWTRIGEN_PER_ENABLE
;
434 val
|= TRGMODE_ENABLE
;
437 writel(val
, timing_base
+ TRIGCON
);
440 static void fimd_commit(struct exynos_drm_crtc
*crtc
)
442 struct fimd_context
*ctx
= crtc
->ctx
;
443 struct drm_display_mode
*mode
= &crtc
->base
.state
->adjusted_mode
;
444 const struct fimd_driver_data
*driver_data
= ctx
->driver_data
;
445 void *timing_base
= ctx
->regs
+ driver_data
->timing_base
;
451 /* nothing to do if we haven't set the mode yet */
452 if (mode
->htotal
== 0 || mode
->vtotal
== 0)
456 val
= ctx
->i80ifcon
| I80IFEN_ENABLE
;
457 writel(val
, timing_base
+ I80IFCONFAx(0));
459 /* disable auto frame rate */
460 writel(0, timing_base
+ I80IFCONFBx(0));
462 /* set video type selection to I80 interface */
463 if (driver_data
->has_vtsel
&& ctx
->sysreg
&&
464 regmap_update_bits(ctx
->sysreg
,
465 driver_data
->lcdblk_offset
,
466 0x3 << driver_data
->lcdblk_vt_shift
,
467 0x1 << driver_data
->lcdblk_vt_shift
)) {
468 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
472 int vsync_len
, vbpd
, vfpd
, hsync_len
, hbpd
, hfpd
;
475 /* setup polarity values */
476 vidcon1
= ctx
->vidcon1
;
477 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
478 vidcon1
|= VIDCON1_INV_VSYNC
;
479 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
480 vidcon1
|= VIDCON1_INV_HSYNC
;
481 writel(vidcon1
, ctx
->regs
+ driver_data
->timing_base
+ VIDCON1
);
483 /* setup vertical timing values. */
484 vsync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
485 vbpd
= mode
->crtc_vtotal
- mode
->crtc_vsync_end
;
486 vfpd
= mode
->crtc_vsync_start
- mode
->crtc_vdisplay
;
488 val
= VIDTCON0_VBPD(vbpd
- 1) |
489 VIDTCON0_VFPD(vfpd
- 1) |
490 VIDTCON0_VSPW(vsync_len
- 1);
491 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON0
);
493 /* setup horizontal timing values. */
494 hsync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
495 hbpd
= mode
->crtc_htotal
- mode
->crtc_hsync_end
;
496 hfpd
= mode
->crtc_hsync_start
- mode
->crtc_hdisplay
;
498 val
= VIDTCON1_HBPD(hbpd
- 1) |
499 VIDTCON1_HFPD(hfpd
- 1) |
500 VIDTCON1_HSPW(hsync_len
- 1);
501 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON1
);
504 if (driver_data
->has_vidoutcon
)
505 writel(ctx
->vidout_con
, timing_base
+ VIDOUT_CON
);
507 /* set bypass selection */
508 if (ctx
->sysreg
&& regmap_update_bits(ctx
->sysreg
,
509 driver_data
->lcdblk_offset
,
510 0x1 << driver_data
->lcdblk_bypass_shift
,
511 0x1 << driver_data
->lcdblk_bypass_shift
)) {
512 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
516 /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
517 * bit should be cleared.
519 if (driver_data
->has_mic_bypass
&& ctx
->sysreg
&&
520 regmap_update_bits(ctx
->sysreg
,
521 driver_data
->lcdblk_offset
,
522 0x1 << driver_data
->lcdblk_mic_bypass_shift
,
523 0x1 << driver_data
->lcdblk_mic_bypass_shift
)) {
524 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
528 /* setup horizontal and vertical display size. */
529 val
= VIDTCON2_LINEVAL(mode
->vdisplay
- 1) |
530 VIDTCON2_HOZVAL(mode
->hdisplay
- 1) |
531 VIDTCON2_LINEVAL_E(mode
->vdisplay
- 1) |
532 VIDTCON2_HOZVAL_E(mode
->hdisplay
- 1);
533 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON2
);
535 fimd_setup_trigger(ctx
);
538 * fields of register with prefix '_F' would be updated
539 * at vsync(same as dma start)
542 val
|= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
544 if (ctx
->driver_data
->has_clksel
)
545 val
|= VIDCON0_CLKSEL_LCD
;
548 val
|= VIDCON0_CLKVAL_F(ctx
->clkdiv
- 1) | VIDCON0_CLKDIR
;
550 writel(val
, ctx
->regs
+ VIDCON0
);
554 static void fimd_win_set_pixfmt(struct fimd_context
*ctx
, unsigned int win
,
555 uint32_t pixel_format
, int width
)
562 * In case of s3c64xx, window 0 doesn't support alpha channel.
563 * So the request format is ARGB8888 then change it to XRGB8888.
565 if (ctx
->driver_data
->has_limited_fmt
&& !win
) {
566 if (pixel_format
== DRM_FORMAT_ARGB8888
)
567 pixel_format
= DRM_FORMAT_XRGB8888
;
570 switch (pixel_format
) {
572 val
|= WINCON0_BPPMODE_8BPP_PALETTE
;
573 val
|= WINCONx_BURSTLEN_8WORD
;
574 val
|= WINCONx_BYTSWP
;
576 case DRM_FORMAT_XRGB1555
:
577 val
|= WINCON0_BPPMODE_16BPP_1555
;
578 val
|= WINCONx_HAWSWP
;
579 val
|= WINCONx_BURSTLEN_16WORD
;
581 case DRM_FORMAT_RGB565
:
582 val
|= WINCON0_BPPMODE_16BPP_565
;
583 val
|= WINCONx_HAWSWP
;
584 val
|= WINCONx_BURSTLEN_16WORD
;
586 case DRM_FORMAT_XRGB8888
:
587 val
|= WINCON0_BPPMODE_24BPP_888
;
589 val
|= WINCONx_BURSTLEN_16WORD
;
591 case DRM_FORMAT_ARGB8888
:
592 val
|= WINCON1_BPPMODE_25BPP_A1888
593 | WINCON1_BLD_PIX
| WINCON1_ALPHA_SEL
;
595 val
|= WINCONx_BURSTLEN_16WORD
;
598 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
600 val
|= WINCON0_BPPMODE_24BPP_888
;
602 val
|= WINCONx_BURSTLEN_16WORD
;
607 * Setting dma-burst to 16Word causes permanent tearing for very small
608 * buffers, e.g. cursor buffer. Burst Mode switching which based on
609 * plane size is not recommended as plane size varies alot towards the
610 * end of the screen and rapid movement causes unstable DMA, but it is
611 * still better to change dma-burst than displaying garbage.
614 if (width
< MIN_FB_WIDTH_FOR_16WORD_BURST
) {
615 val
&= ~WINCONx_BURSTLEN_MASK
;
616 val
|= WINCONx_BURSTLEN_4WORD
;
619 writel(val
, ctx
->regs
+ WINCON(win
));
621 /* hardware window 0 doesn't support alpha channel. */
624 val
= VIDISD14C_ALPHA0_R(0xf) |
625 VIDISD14C_ALPHA0_G(0xf) |
626 VIDISD14C_ALPHA0_B(0xf) |
627 VIDISD14C_ALPHA1_R(0xf) |
628 VIDISD14C_ALPHA1_G(0xf) |
629 VIDISD14C_ALPHA1_B(0xf);
631 writel(val
, ctx
->regs
+ VIDOSD_C(win
));
633 val
= VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
635 writel(val
, ctx
->regs
+ VIDWnALPHA0(win
));
636 writel(val
, ctx
->regs
+ VIDWnALPHA1(win
));
640 static void fimd_win_set_colkey(struct fimd_context
*ctx
, unsigned int win
)
642 unsigned int keycon0
= 0, keycon1
= 0;
644 keycon0
= ~(WxKEYCON0_KEYBL_EN
| WxKEYCON0_KEYEN_F
|
645 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
647 keycon1
= WxKEYCON1_COLVAL(0xffffffff);
649 writel(keycon0
, ctx
->regs
+ WKEYCON0_BASE(win
));
650 writel(keycon1
, ctx
->regs
+ WKEYCON1_BASE(win
));
654 * shadow_protect_win() - disable updating values from shadow registers at vsync
656 * @win: window to protect registers for
657 * @protect: 1 to protect (disable updates)
659 static void fimd_shadow_protect_win(struct fimd_context
*ctx
,
660 unsigned int win
, bool protect
)
665 * SHADOWCON/PRTCON register is used for enabling timing.
667 * for example, once only width value of a register is set,
668 * if the dma is started then fimd hardware could malfunction so
669 * with protect window setting, the register fields with prefix '_F'
670 * wouldn't be updated at vsync also but updated once unprotect window
674 if (ctx
->driver_data
->has_shadowcon
) {
676 bits
= SHADOWCON_WINx_PROTECT(win
);
679 bits
= PRTCON_PROTECT
;
682 val
= readl(ctx
->regs
+ reg
);
687 writel(val
, ctx
->regs
+ reg
);
690 static void fimd_atomic_begin(struct exynos_drm_crtc
*crtc
)
692 struct fimd_context
*ctx
= crtc
->ctx
;
698 for (i
= 0; i
< WINDOWS_NR
; i
++)
699 fimd_shadow_protect_win(ctx
, i
, true);
702 static void fimd_atomic_flush(struct exynos_drm_crtc
*crtc
)
704 struct fimd_context
*ctx
= crtc
->ctx
;
710 for (i
= 0; i
< WINDOWS_NR
; i
++)
711 fimd_shadow_protect_win(ctx
, i
, false);
713 exynos_crtc_handle_event(crtc
);
716 static void fimd_update_plane(struct exynos_drm_crtc
*crtc
,
717 struct exynos_drm_plane
*plane
)
719 struct exynos_drm_plane_state
*state
=
720 to_exynos_plane_state(plane
->base
.state
);
721 struct fimd_context
*ctx
= crtc
->ctx
;
722 struct drm_framebuffer
*fb
= state
->base
.fb
;
724 unsigned long val
, size
, offset
;
725 unsigned int last_x
, last_y
, buf_offsize
, line_size
;
726 unsigned int win
= plane
->index
;
727 unsigned int bpp
= fb
->format
->cpp
[0];
728 unsigned int pitch
= fb
->pitches
[0];
733 offset
= state
->src
.x
* bpp
;
734 offset
+= state
->src
.y
* pitch
;
736 /* buffer start address */
737 dma_addr
= exynos_drm_fb_dma_addr(fb
, 0) + offset
;
738 val
= (unsigned long)dma_addr
;
739 writel(val
, ctx
->regs
+ VIDWx_BUF_START(win
, 0));
741 /* buffer end address */
742 size
= pitch
* state
->crtc
.h
;
743 val
= (unsigned long)(dma_addr
+ size
);
744 writel(val
, ctx
->regs
+ VIDWx_BUF_END(win
, 0));
746 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
747 (unsigned long)dma_addr
, val
, size
);
748 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
749 state
->crtc
.w
, state
->crtc
.h
);
752 buf_offsize
= pitch
- (state
->crtc
.w
* bpp
);
753 line_size
= state
->crtc
.w
* bpp
;
754 val
= VIDW_BUF_SIZE_OFFSET(buf_offsize
) |
755 VIDW_BUF_SIZE_PAGEWIDTH(line_size
) |
756 VIDW_BUF_SIZE_OFFSET_E(buf_offsize
) |
757 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size
);
758 writel(val
, ctx
->regs
+ VIDWx_BUF_SIZE(win
, 0));
761 val
= VIDOSDxA_TOPLEFT_X(state
->crtc
.x
) |
762 VIDOSDxA_TOPLEFT_Y(state
->crtc
.y
) |
763 VIDOSDxA_TOPLEFT_X_E(state
->crtc
.x
) |
764 VIDOSDxA_TOPLEFT_Y_E(state
->crtc
.y
);
765 writel(val
, ctx
->regs
+ VIDOSD_A(win
));
767 last_x
= state
->crtc
.x
+ state
->crtc
.w
;
770 last_y
= state
->crtc
.y
+ state
->crtc
.h
;
774 val
= VIDOSDxB_BOTRIGHT_X(last_x
) | VIDOSDxB_BOTRIGHT_Y(last_y
) |
775 VIDOSDxB_BOTRIGHT_X_E(last_x
) | VIDOSDxB_BOTRIGHT_Y_E(last_y
);
777 writel(val
, ctx
->regs
+ VIDOSD_B(win
));
779 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
780 state
->crtc
.x
, state
->crtc
.y
, last_x
, last_y
);
783 if (win
!= 3 && win
!= 4) {
784 u32 offset
= VIDOSD_D(win
);
786 offset
= VIDOSD_C(win
);
787 val
= state
->crtc
.w
* state
->crtc
.h
;
788 writel(val
, ctx
->regs
+ offset
);
790 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val
);
793 fimd_win_set_pixfmt(ctx
, win
, fb
->format
->format
, state
->src
.w
);
795 /* hardware window 0 doesn't support color key. */
797 fimd_win_set_colkey(ctx
, win
);
799 fimd_enable_video_output(ctx
, win
, true);
801 if (ctx
->driver_data
->has_shadowcon
)
802 fimd_enable_shadow_channel_path(ctx
, win
, true);
805 atomic_set(&ctx
->win_updated
, 1);
808 static void fimd_disable_plane(struct exynos_drm_crtc
*crtc
,
809 struct exynos_drm_plane
*plane
)
811 struct fimd_context
*ctx
= crtc
->ctx
;
812 unsigned int win
= plane
->index
;
817 fimd_enable_video_output(ctx
, win
, false);
819 if (ctx
->driver_data
->has_shadowcon
)
820 fimd_enable_shadow_channel_path(ctx
, win
, false);
823 static void fimd_enable(struct exynos_drm_crtc
*crtc
)
825 struct fimd_context
*ctx
= crtc
->ctx
;
830 ctx
->suspended
= false;
832 pm_runtime_get_sync(ctx
->dev
);
834 /* if vblank was enabled status, enable it again. */
835 if (test_and_clear_bit(0, &ctx
->irq_flags
))
836 fimd_enable_vblank(ctx
->crtc
);
838 fimd_commit(ctx
->crtc
);
841 static void fimd_disable(struct exynos_drm_crtc
*crtc
)
843 struct fimd_context
*ctx
= crtc
->ctx
;
850 * We need to make sure that all windows are disabled before we
851 * suspend that connector. Otherwise we might try to scan from
852 * a destroyed buffer later.
854 for (i
= 0; i
< WINDOWS_NR
; i
++)
855 fimd_disable_plane(crtc
, &ctx
->planes
[i
]);
857 fimd_enable_vblank(crtc
);
858 fimd_wait_for_vblank(crtc
);
859 fimd_disable_vblank(crtc
);
861 writel(0, ctx
->regs
+ VIDCON0
);
863 pm_runtime_put_sync(ctx
->dev
);
864 ctx
->suspended
= true;
867 static void fimd_trigger(struct device
*dev
)
869 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
870 const struct fimd_driver_data
*driver_data
= ctx
->driver_data
;
871 void *timing_base
= ctx
->regs
+ driver_data
->timing_base
;
875 * Skips triggering if in triggering state, because multiple triggering
876 * requests can cause panel reset.
878 if (atomic_read(&ctx
->triggering
))
881 /* Enters triggering mode */
882 atomic_set(&ctx
->triggering
, 1);
884 reg
= readl(timing_base
+ TRIGCON
);
885 reg
|= (TRGMODE_ENABLE
| SWTRGCMD_ENABLE
);
886 writel(reg
, timing_base
+ TRIGCON
);
889 * Exits triggering mode if vblank is not enabled yet, because when the
890 * VIDINTCON0 register is not set, it can not exit from triggering mode.
892 if (!test_bit(0, &ctx
->irq_flags
))
893 atomic_set(&ctx
->triggering
, 0);
896 static void fimd_te_handler(struct exynos_drm_crtc
*crtc
)
898 struct fimd_context
*ctx
= crtc
->ctx
;
899 u32 trg_type
= ctx
->driver_data
->trg_type
;
901 /* Checks the crtc is detached already from encoder */
902 if (ctx
->pipe
< 0 || !ctx
->drm_dev
)
905 if (trg_type
== I80_HW_TRG
)
909 * If there is a page flip request, triggers and handles the page flip
910 * event so that current fb can be updated into panel GRAM.
912 if (atomic_add_unless(&ctx
->win_updated
, -1, 0))
913 fimd_trigger(ctx
->dev
);
916 /* Wakes up vsync event queue */
917 if (atomic_read(&ctx
->wait_vsync_event
)) {
918 atomic_set(&ctx
->wait_vsync_event
, 0);
919 wake_up(&ctx
->wait_vsync_queue
);
922 if (test_bit(0, &ctx
->irq_flags
))
923 drm_crtc_handle_vblank(&ctx
->crtc
->base
);
926 static void fimd_dp_clock_enable(struct exynos_drm_clk
*clk
, bool enable
)
928 struct fimd_context
*ctx
= container_of(clk
, struct fimd_context
,
930 u32 val
= enable
? DP_MIE_CLK_DP_ENABLE
: DP_MIE_CLK_DISABLE
;
931 writel(val
, ctx
->regs
+ DP_MIE_CLKCON
);
934 static const struct exynos_drm_crtc_ops fimd_crtc_ops
= {
935 .enable
= fimd_enable
,
936 .disable
= fimd_disable
,
937 .commit
= fimd_commit
,
938 .enable_vblank
= fimd_enable_vblank
,
939 .disable_vblank
= fimd_disable_vblank
,
940 .atomic_begin
= fimd_atomic_begin
,
941 .update_plane
= fimd_update_plane
,
942 .disable_plane
= fimd_disable_plane
,
943 .atomic_flush
= fimd_atomic_flush
,
944 .atomic_check
= fimd_atomic_check
,
945 .te_handler
= fimd_te_handler
,
948 static irqreturn_t
fimd_irq_handler(int irq
, void *dev_id
)
950 struct fimd_context
*ctx
= (struct fimd_context
*)dev_id
;
953 val
= readl(ctx
->regs
+ VIDINTCON1
);
955 clear_bit
= ctx
->i80_if
? VIDINTCON1_INT_I80
: VIDINTCON1_INT_FRAME
;
957 writel(clear_bit
, ctx
->regs
+ VIDINTCON1
);
959 /* check the crtc is detached already from encoder */
960 if (ctx
->pipe
< 0 || !ctx
->drm_dev
)
964 drm_crtc_handle_vblank(&ctx
->crtc
->base
);
967 /* Exits triggering mode */
968 atomic_set(&ctx
->triggering
, 0);
970 /* set wait vsync event to zero and wake up queue. */
971 if (atomic_read(&ctx
->wait_vsync_event
)) {
972 atomic_set(&ctx
->wait_vsync_event
, 0);
973 wake_up(&ctx
->wait_vsync_queue
);
981 static int fimd_bind(struct device
*dev
, struct device
*master
, void *data
)
983 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
984 struct drm_device
*drm_dev
= data
;
985 struct exynos_drm_private
*priv
= drm_dev
->dev_private
;
986 struct exynos_drm_plane
*exynos_plane
;
990 ctx
->drm_dev
= drm_dev
;
991 ctx
->pipe
= priv
->pipe
++;
993 for (i
= 0; i
< WINDOWS_NR
; i
++) {
994 ctx
->configs
[i
].pixel_formats
= fimd_formats
;
995 ctx
->configs
[i
].num_pixel_formats
= ARRAY_SIZE(fimd_formats
);
996 ctx
->configs
[i
].zpos
= i
;
997 ctx
->configs
[i
].type
= fimd_win_types
[i
];
998 ret
= exynos_plane_init(drm_dev
, &ctx
->planes
[i
], i
,
999 1 << ctx
->pipe
, &ctx
->configs
[i
]);
1004 exynos_plane
= &ctx
->planes
[DEFAULT_WIN
];
1005 ctx
->crtc
= exynos_drm_crtc_create(drm_dev
, &exynos_plane
->base
,
1006 ctx
->pipe
, EXYNOS_DISPLAY_TYPE_LCD
,
1007 &fimd_crtc_ops
, ctx
);
1008 if (IS_ERR(ctx
->crtc
))
1009 return PTR_ERR(ctx
->crtc
);
1011 if (ctx
->driver_data
->has_dp_clk
) {
1012 ctx
->dp_clk
.enable
= fimd_dp_clock_enable
;
1013 ctx
->crtc
->pipe_clk
= &ctx
->dp_clk
;
1017 exynos_dpi_bind(drm_dev
, ctx
->encoder
);
1019 if (is_drm_iommu_supported(drm_dev
))
1020 fimd_clear_channels(ctx
->crtc
);
1022 ret
= drm_iommu_attach_device(drm_dev
, dev
);
1029 static void fimd_unbind(struct device
*dev
, struct device
*master
,
1032 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1034 fimd_disable(ctx
->crtc
);
1036 drm_iommu_detach_device(ctx
->drm_dev
, ctx
->dev
);
1039 exynos_dpi_remove(ctx
->encoder
);
1042 static const struct component_ops fimd_component_ops
= {
1044 .unbind
= fimd_unbind
,
1047 static int fimd_probe(struct platform_device
*pdev
)
1049 struct device
*dev
= &pdev
->dev
;
1050 struct fimd_context
*ctx
;
1051 struct device_node
*i80_if_timings
;
1052 struct resource
*res
;
1058 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
1063 ctx
->suspended
= true;
1064 ctx
->driver_data
= of_device_get_match_data(dev
);
1066 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vden"))
1067 ctx
->vidcon1
|= VIDCON1_INV_VDEN
;
1068 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vclk"))
1069 ctx
->vidcon1
|= VIDCON1_INV_VCLK
;
1071 i80_if_timings
= of_get_child_by_name(dev
->of_node
, "i80-if-timings");
1072 if (i80_if_timings
) {
1077 if (ctx
->driver_data
->has_vidoutcon
)
1078 ctx
->vidout_con
|= VIDOUT_CON_F_I80_LDI0
;
1080 ctx
->vidcon0
|= VIDCON0_VIDOUT_I80_LDI0
;
1082 * The user manual describes that this "DSI_EN" bit is required
1083 * to enable I80 24-bit data interface.
1085 ctx
->vidcon0
|= VIDCON0_DSI_EN
;
1087 if (of_property_read_u32(i80_if_timings
, "cs-setup", &val
))
1089 ctx
->i80ifcon
= LCD_CS_SETUP(val
);
1090 if (of_property_read_u32(i80_if_timings
, "wr-setup", &val
))
1092 ctx
->i80ifcon
|= LCD_WR_SETUP(val
);
1093 if (of_property_read_u32(i80_if_timings
, "wr-active", &val
))
1095 ctx
->i80ifcon
|= LCD_WR_ACTIVE(val
);
1096 if (of_property_read_u32(i80_if_timings
, "wr-hold", &val
))
1098 ctx
->i80ifcon
|= LCD_WR_HOLD(val
);
1100 of_node_put(i80_if_timings
);
1102 ctx
->sysreg
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
1104 if (IS_ERR(ctx
->sysreg
)) {
1105 dev_warn(dev
, "failed to get system register.\n");
1109 ctx
->bus_clk
= devm_clk_get(dev
, "fimd");
1110 if (IS_ERR(ctx
->bus_clk
)) {
1111 dev_err(dev
, "failed to get bus clock\n");
1112 return PTR_ERR(ctx
->bus_clk
);
1115 ctx
->lcd_clk
= devm_clk_get(dev
, "sclk_fimd");
1116 if (IS_ERR(ctx
->lcd_clk
)) {
1117 dev_err(dev
, "failed to get lcd clock\n");
1118 return PTR_ERR(ctx
->lcd_clk
);
1121 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1123 ctx
->regs
= devm_ioremap_resource(dev
, res
);
1124 if (IS_ERR(ctx
->regs
))
1125 return PTR_ERR(ctx
->regs
);
1127 res
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
,
1128 ctx
->i80_if
? "lcd_sys" : "vsync");
1130 dev_err(dev
, "irq request failed.\n");
1134 ret
= devm_request_irq(dev
, res
->start
, fimd_irq_handler
,
1135 0, "drm_fimd", ctx
);
1137 dev_err(dev
, "irq request failed.\n");
1141 init_waitqueue_head(&ctx
->wait_vsync_queue
);
1142 atomic_set(&ctx
->wait_vsync_event
, 0);
1144 platform_set_drvdata(pdev
, ctx
);
1146 ctx
->encoder
= exynos_dpi_probe(dev
);
1147 if (IS_ERR(ctx
->encoder
))
1148 return PTR_ERR(ctx
->encoder
);
1150 pm_runtime_enable(dev
);
1152 ret
= component_add(dev
, &fimd_component_ops
);
1154 goto err_disable_pm_runtime
;
1158 err_disable_pm_runtime
:
1159 pm_runtime_disable(dev
);
1164 static int fimd_remove(struct platform_device
*pdev
)
1166 pm_runtime_disable(&pdev
->dev
);
1168 component_del(&pdev
->dev
, &fimd_component_ops
);
1174 static int exynos_fimd_suspend(struct device
*dev
)
1176 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1178 clk_disable_unprepare(ctx
->lcd_clk
);
1179 clk_disable_unprepare(ctx
->bus_clk
);
1184 static int exynos_fimd_resume(struct device
*dev
)
1186 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1189 ret
= clk_prepare_enable(ctx
->bus_clk
);
1191 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret
);
1195 ret
= clk_prepare_enable(ctx
->lcd_clk
);
1197 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret
);
1205 static const struct dev_pm_ops exynos_fimd_pm_ops
= {
1206 SET_RUNTIME_PM_OPS(exynos_fimd_suspend
, exynos_fimd_resume
, NULL
)
1209 struct platform_driver fimd_driver
= {
1210 .probe
= fimd_probe
,
1211 .remove
= fimd_remove
,
1213 .name
= "exynos4-fb",
1214 .owner
= THIS_MODULE
,
1215 .pm
= &exynos_fimd_pm_ops
,
1216 .of_match_table
= fimd_driver_dt_match
,