3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
23 #include <video/of_display_timing.h>
24 #include <video/of_videomode.h>
25 #include <video/samsung_fimd.h>
26 #include <drm/exynos_drm.h>
28 #include "exynos_drm_drv.h"
29 #include "exynos_drm_fbdev.h"
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_iommu.h"
34 * FIMD stands for Fully Interactive Mobile Display and
35 * as a display controller, it transfers contents drawn on memory
36 * to a LCD Panel through Display Interfaces such as RGB or
40 #define FIMD_DEFAULT_FRAMERATE 60
42 /* position control register for hardware window 0, 2 ~ 4.*/
43 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
44 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
46 * size control register for hardware windows 0 and alpha control register
47 * for hardware windows 1 ~ 4
49 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
50 /* size control register for hardware windows 1 ~ 2. */
51 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
53 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
54 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
55 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
57 /* color key control register for hardware window 1 ~ 4. */
58 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
59 /* color key value register for hardware window 1 ~ 4. */
60 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
62 /* FIMD has totally five hardware windows. */
65 #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev))
67 struct fimd_driver_data
{
68 unsigned int timing_base
;
70 unsigned int has_shadowcon
:1;
71 unsigned int has_clksel
:1;
72 unsigned int has_limited_fmt
:1;
75 static struct fimd_driver_data s3c64xx_fimd_driver_data
= {
81 static struct fimd_driver_data exynos4_fimd_driver_data
= {
86 static struct fimd_driver_data exynos5_fimd_driver_data
= {
87 .timing_base
= 0x20000,
91 struct fimd_win_data
{
92 unsigned int offset_x
;
93 unsigned int offset_y
;
94 unsigned int ovl_width
;
95 unsigned int ovl_height
;
96 unsigned int fb_width
;
97 unsigned int fb_height
;
99 unsigned int pixel_format
;
101 unsigned int buf_offsize
;
102 unsigned int line_size
; /* bytes */
107 struct fimd_context
{
109 struct drm_device
*drm_dev
;
113 struct drm_display_mode mode
;
114 struct fimd_win_data win_data
[WINDOWS_NR
];
115 unsigned int default_win
;
116 unsigned long irq_flags
;
120 wait_queue_head_t wait_vsync_queue
;
121 atomic_t wait_vsync_event
;
123 struct exynos_drm_panel_info panel
;
124 struct fimd_driver_data
*driver_data
;
127 static const struct of_device_id fimd_driver_dt_match
[] = {
128 { .compatible
= "samsung,s3c6400-fimd",
129 .data
= &s3c64xx_fimd_driver_data
},
130 { .compatible
= "samsung,exynos4210-fimd",
131 .data
= &exynos4_fimd_driver_data
},
132 { .compatible
= "samsung,exynos5250-fimd",
133 .data
= &exynos5_fimd_driver_data
},
137 static inline struct fimd_driver_data
*drm_fimd_get_driver_data(
138 struct platform_device
*pdev
)
140 const struct of_device_id
*of_id
=
141 of_match_device(fimd_driver_dt_match
, &pdev
->dev
);
143 return (struct fimd_driver_data
*)of_id
->data
;
146 static void fimd_wait_for_vblank(struct exynos_drm_manager
*mgr
)
148 struct fimd_context
*ctx
= mgr
->ctx
;
153 atomic_set(&ctx
->wait_vsync_event
, 1);
156 * wait for FIMD to signal VSYNC interrupt or return after
157 * timeout which is set to 50ms (refresh rate of 20).
159 if (!wait_event_timeout(ctx
->wait_vsync_queue
,
160 !atomic_read(&ctx
->wait_vsync_event
),
162 DRM_DEBUG_KMS("vblank wait timed out.\n");
166 static void fimd_clear_channel(struct exynos_drm_manager
*mgr
)
168 struct fimd_context
*ctx
= mgr
->ctx
;
169 int win
, ch_enabled
= 0;
171 DRM_DEBUG_KMS("%s\n", __FILE__
);
173 /* Check if any channel is enabled. */
174 for (win
= 0; win
< WINDOWS_NR
; win
++) {
175 u32 val
= readl(ctx
->regs
+ SHADOWCON
);
176 if (val
& SHADOWCON_CHx_ENABLE(win
)) {
177 val
&= ~SHADOWCON_CHx_ENABLE(win
);
178 writel(val
, ctx
->regs
+ SHADOWCON
);
183 /* Wait for vsync, as disable channel takes effect at next vsync */
185 fimd_wait_for_vblank(mgr
);
188 static int fimd_mgr_initialize(struct exynos_drm_manager
*mgr
,
189 struct drm_device
*drm_dev
, int pipe
)
191 struct fimd_context
*ctx
= mgr
->ctx
;
193 ctx
->drm_dev
= drm_dev
;
197 * enable drm irq mode.
198 * - with irq_enabled = true, we can use the vblank feature.
200 * P.S. note that we wouldn't use drm irq handler but
201 * just specific driver own one instead because
202 * drm framework supports only one irq handler.
204 drm_dev
->irq_enabled
= true;
207 * with vblank_disable_allowed = true, vblank interrupt will be disabled
208 * by drm timer once a current process gives up ownership of
209 * vblank event.(after drm_vblank_put function is called)
211 drm_dev
->vblank_disable_allowed
= true;
213 /* attach this sub driver to iommu mapping if supported. */
214 if (is_drm_iommu_supported(ctx
->drm_dev
)) {
216 * If any channel is already active, iommu will throw
217 * a PAGE FAULT when enabled. So clear any channel if enabled.
219 fimd_clear_channel(mgr
);
220 drm_iommu_attach_device(ctx
->drm_dev
, ctx
->dev
);
226 static void fimd_mgr_remove(struct exynos_drm_manager
*mgr
)
228 struct fimd_context
*ctx
= mgr
->ctx
;
230 /* detach this sub driver from iommu mapping if supported. */
231 if (is_drm_iommu_supported(ctx
->drm_dev
))
232 drm_iommu_detach_device(ctx
->drm_dev
, ctx
->dev
);
235 static u32
fimd_calc_clkdiv(struct fimd_context
*ctx
,
236 const struct drm_display_mode
*mode
)
238 unsigned long ideal_clk
= mode
->htotal
* mode
->vtotal
* mode
->vrefresh
;
241 /* Find the clock divider value that gets us closest to ideal_clk */
242 clkdiv
= DIV_ROUND_UP(clk_get_rate(ctx
->lcd_clk
), ideal_clk
);
244 return (clkdiv
< 0x100) ? clkdiv
: 0xff;
247 static bool fimd_mode_fixup(struct exynos_drm_manager
*mgr
,
248 const struct drm_display_mode
*mode
,
249 struct drm_display_mode
*adjusted_mode
)
251 if (adjusted_mode
->vrefresh
== 0)
252 adjusted_mode
->vrefresh
= FIMD_DEFAULT_FRAMERATE
;
257 static void fimd_mode_set(struct exynos_drm_manager
*mgr
,
258 const struct drm_display_mode
*in_mode
)
260 struct fimd_context
*ctx
= mgr
->ctx
;
262 drm_mode_copy(&ctx
->mode
, in_mode
);
265 static void fimd_commit(struct exynos_drm_manager
*mgr
)
267 struct fimd_context
*ctx
= mgr
->ctx
;
268 struct drm_display_mode
*mode
= &ctx
->mode
;
269 struct fimd_driver_data
*driver_data
;
270 u32 val
, clkdiv
, vidcon1
;
271 int vsync_len
, vbpd
, vfpd
, hsync_len
, hbpd
, hfpd
;
273 driver_data
= ctx
->driver_data
;
277 /* nothing to do if we haven't set the mode yet */
278 if (mode
->htotal
== 0 || mode
->vtotal
== 0)
281 /* setup polarity values */
282 vidcon1
= ctx
->vidcon1
;
283 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
284 vidcon1
|= VIDCON1_INV_VSYNC
;
285 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
286 vidcon1
|= VIDCON1_INV_HSYNC
;
287 writel(vidcon1
, ctx
->regs
+ driver_data
->timing_base
+ VIDCON1
);
289 /* setup vertical timing values. */
290 vsync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
291 vbpd
= mode
->crtc_vtotal
- mode
->crtc_vsync_end
;
292 vfpd
= mode
->crtc_vsync_start
- mode
->crtc_vdisplay
;
294 val
= VIDTCON0_VBPD(vbpd
- 1) |
295 VIDTCON0_VFPD(vfpd
- 1) |
296 VIDTCON0_VSPW(vsync_len
- 1);
297 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON0
);
299 /* setup horizontal timing values. */
300 hsync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
301 hbpd
= mode
->crtc_htotal
- mode
->crtc_hsync_end
;
302 hfpd
= mode
->crtc_hsync_start
- mode
->crtc_hdisplay
;
304 val
= VIDTCON1_HBPD(hbpd
- 1) |
305 VIDTCON1_HFPD(hfpd
- 1) |
306 VIDTCON1_HSPW(hsync_len
- 1);
307 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON1
);
309 /* setup horizontal and vertical display size. */
310 val
= VIDTCON2_LINEVAL(mode
->vdisplay
- 1) |
311 VIDTCON2_HOZVAL(mode
->hdisplay
- 1) |
312 VIDTCON2_LINEVAL_E(mode
->vdisplay
- 1) |
313 VIDTCON2_HOZVAL_E(mode
->hdisplay
- 1);
314 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON2
);
317 * fields of register with prefix '_F' would be updated
318 * at vsync(same as dma start)
320 val
= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
322 if (ctx
->driver_data
->has_clksel
)
323 val
|= VIDCON0_CLKSEL_LCD
;
325 clkdiv
= fimd_calc_clkdiv(ctx
, mode
);
327 val
|= VIDCON0_CLKVAL_F(clkdiv
- 1) | VIDCON0_CLKDIR
;
329 writel(val
, ctx
->regs
+ VIDCON0
);
332 static int fimd_enable_vblank(struct exynos_drm_manager
*mgr
)
334 struct fimd_context
*ctx
= mgr
->ctx
;
340 if (!test_and_set_bit(0, &ctx
->irq_flags
)) {
341 val
= readl(ctx
->regs
+ VIDINTCON0
);
343 val
|= VIDINTCON0_INT_ENABLE
;
344 val
|= VIDINTCON0_INT_FRAME
;
346 val
&= ~VIDINTCON0_FRAMESEL0_MASK
;
347 val
|= VIDINTCON0_FRAMESEL0_VSYNC
;
348 val
&= ~VIDINTCON0_FRAMESEL1_MASK
;
349 val
|= VIDINTCON0_FRAMESEL1_NONE
;
351 writel(val
, ctx
->regs
+ VIDINTCON0
);
357 static void fimd_disable_vblank(struct exynos_drm_manager
*mgr
)
359 struct fimd_context
*ctx
= mgr
->ctx
;
365 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
366 val
= readl(ctx
->regs
+ VIDINTCON0
);
368 val
&= ~VIDINTCON0_INT_FRAME
;
369 val
&= ~VIDINTCON0_INT_ENABLE
;
371 writel(val
, ctx
->regs
+ VIDINTCON0
);
375 static void fimd_win_mode_set(struct exynos_drm_manager
*mgr
,
376 struct exynos_drm_overlay
*overlay
)
378 struct fimd_context
*ctx
= mgr
->ctx
;
379 struct fimd_win_data
*win_data
;
381 unsigned long offset
;
384 DRM_ERROR("overlay is NULL\n");
389 if (win
== DEFAULT_ZPOS
)
390 win
= ctx
->default_win
;
392 if (win
< 0 || win
>= WINDOWS_NR
)
395 offset
= overlay
->fb_x
* (overlay
->bpp
>> 3);
396 offset
+= overlay
->fb_y
* overlay
->pitch
;
398 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset
, overlay
->pitch
);
400 win_data
= &ctx
->win_data
[win
];
402 win_data
->offset_x
= overlay
->crtc_x
;
403 win_data
->offset_y
= overlay
->crtc_y
;
404 win_data
->ovl_width
= overlay
->crtc_width
;
405 win_data
->ovl_height
= overlay
->crtc_height
;
406 win_data
->fb_width
= overlay
->fb_width
;
407 win_data
->fb_height
= overlay
->fb_height
;
408 win_data
->dma_addr
= overlay
->dma_addr
[0] + offset
;
409 win_data
->bpp
= overlay
->bpp
;
410 win_data
->pixel_format
= overlay
->pixel_format
;
411 win_data
->buf_offsize
= (overlay
->fb_width
- overlay
->crtc_width
) *
413 win_data
->line_size
= overlay
->crtc_width
* (overlay
->bpp
>> 3);
415 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
416 win_data
->offset_x
, win_data
->offset_y
);
417 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
418 win_data
->ovl_width
, win_data
->ovl_height
);
419 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data
->dma_addr
);
420 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
421 overlay
->fb_width
, overlay
->crtc_width
);
424 static void fimd_win_set_pixfmt(struct fimd_context
*ctx
, unsigned int win
)
426 struct fimd_win_data
*win_data
= &ctx
->win_data
[win
];
432 * In case of s3c64xx, window 0 doesn't support alpha channel.
433 * So the request format is ARGB8888 then change it to XRGB8888.
435 if (ctx
->driver_data
->has_limited_fmt
&& !win
) {
436 if (win_data
->pixel_format
== DRM_FORMAT_ARGB8888
)
437 win_data
->pixel_format
= DRM_FORMAT_XRGB8888
;
440 switch (win_data
->pixel_format
) {
442 val
|= WINCON0_BPPMODE_8BPP_PALETTE
;
443 val
|= WINCONx_BURSTLEN_8WORD
;
444 val
|= WINCONx_BYTSWP
;
446 case DRM_FORMAT_XRGB1555
:
447 val
|= WINCON0_BPPMODE_16BPP_1555
;
448 val
|= WINCONx_HAWSWP
;
449 val
|= WINCONx_BURSTLEN_16WORD
;
451 case DRM_FORMAT_RGB565
:
452 val
|= WINCON0_BPPMODE_16BPP_565
;
453 val
|= WINCONx_HAWSWP
;
454 val
|= WINCONx_BURSTLEN_16WORD
;
456 case DRM_FORMAT_XRGB8888
:
457 val
|= WINCON0_BPPMODE_24BPP_888
;
459 val
|= WINCONx_BURSTLEN_16WORD
;
461 case DRM_FORMAT_ARGB8888
:
462 val
|= WINCON1_BPPMODE_25BPP_A1888
463 | WINCON1_BLD_PIX
| WINCON1_ALPHA_SEL
;
465 val
|= WINCONx_BURSTLEN_16WORD
;
468 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
470 val
|= WINCON0_BPPMODE_24BPP_888
;
472 val
|= WINCONx_BURSTLEN_16WORD
;
476 DRM_DEBUG_KMS("bpp = %d\n", win_data
->bpp
);
478 writel(val
, ctx
->regs
+ WINCON(win
));
481 static void fimd_win_set_colkey(struct fimd_context
*ctx
, unsigned int win
)
483 unsigned int keycon0
= 0, keycon1
= 0;
485 keycon0
= ~(WxKEYCON0_KEYBL_EN
| WxKEYCON0_KEYEN_F
|
486 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
488 keycon1
= WxKEYCON1_COLVAL(0xffffffff);
490 writel(keycon0
, ctx
->regs
+ WKEYCON0_BASE(win
));
491 writel(keycon1
, ctx
->regs
+ WKEYCON1_BASE(win
));
495 * shadow_protect_win() - disable updating values from shadow registers at vsync
497 * @win: window to protect registers for
498 * @protect: 1 to protect (disable updates)
500 static void fimd_shadow_protect_win(struct fimd_context
*ctx
,
501 int win
, bool protect
)
505 if (ctx
->driver_data
->has_shadowcon
) {
507 bits
= SHADOWCON_WINx_PROTECT(win
);
510 bits
= PRTCON_PROTECT
;
513 val
= readl(ctx
->regs
+ reg
);
518 writel(val
, ctx
->regs
+ reg
);
521 static void fimd_win_commit(struct exynos_drm_manager
*mgr
, int zpos
)
523 struct fimd_context
*ctx
= mgr
->ctx
;
524 struct fimd_win_data
*win_data
;
526 unsigned long val
, alpha
, size
;
533 if (win
== DEFAULT_ZPOS
)
534 win
= ctx
->default_win
;
536 if (win
< 0 || win
>= WINDOWS_NR
)
539 win_data
= &ctx
->win_data
[win
];
541 /* If suspended, enable this on resume */
542 if (ctx
->suspended
) {
543 win_data
->resume
= true;
548 * SHADOWCON/PRTCON register is used for enabling timing.
550 * for example, once only width value of a register is set,
551 * if the dma is started then fimd hardware could malfunction so
552 * with protect window setting, the register fields with prefix '_F'
553 * wouldn't be updated at vsync also but updated once unprotect window
557 /* protect windows */
558 fimd_shadow_protect_win(ctx
, win
, true);
560 /* buffer start address */
561 val
= (unsigned long)win_data
->dma_addr
;
562 writel(val
, ctx
->regs
+ VIDWx_BUF_START(win
, 0));
564 /* buffer end address */
565 size
= win_data
->fb_width
* win_data
->ovl_height
* (win_data
->bpp
>> 3);
566 val
= (unsigned long)(win_data
->dma_addr
+ size
);
567 writel(val
, ctx
->regs
+ VIDWx_BUF_END(win
, 0));
569 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
570 (unsigned long)win_data
->dma_addr
, val
, size
);
571 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
572 win_data
->ovl_width
, win_data
->ovl_height
);
575 val
= VIDW_BUF_SIZE_OFFSET(win_data
->buf_offsize
) |
576 VIDW_BUF_SIZE_PAGEWIDTH(win_data
->line_size
) |
577 VIDW_BUF_SIZE_OFFSET_E(win_data
->buf_offsize
) |
578 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data
->line_size
);
579 writel(val
, ctx
->regs
+ VIDWx_BUF_SIZE(win
, 0));
582 val
= VIDOSDxA_TOPLEFT_X(win_data
->offset_x
) |
583 VIDOSDxA_TOPLEFT_Y(win_data
->offset_y
) |
584 VIDOSDxA_TOPLEFT_X_E(win_data
->offset_x
) |
585 VIDOSDxA_TOPLEFT_Y_E(win_data
->offset_y
);
586 writel(val
, ctx
->regs
+ VIDOSD_A(win
));
588 last_x
= win_data
->offset_x
+ win_data
->ovl_width
;
591 last_y
= win_data
->offset_y
+ win_data
->ovl_height
;
595 val
= VIDOSDxB_BOTRIGHT_X(last_x
) | VIDOSDxB_BOTRIGHT_Y(last_y
) |
596 VIDOSDxB_BOTRIGHT_X_E(last_x
) | VIDOSDxB_BOTRIGHT_Y_E(last_y
);
598 writel(val
, ctx
->regs
+ VIDOSD_B(win
));
600 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
601 win_data
->offset_x
, win_data
->offset_y
, last_x
, last_y
);
603 /* hardware window 0 doesn't support alpha channel. */
606 alpha
= VIDISD14C_ALPHA1_R(0xf) |
607 VIDISD14C_ALPHA1_G(0xf) |
608 VIDISD14C_ALPHA1_B(0xf);
610 writel(alpha
, ctx
->regs
+ VIDOSD_C(win
));
614 if (win
!= 3 && win
!= 4) {
615 u32 offset
= VIDOSD_D(win
);
617 offset
= VIDOSD_C(win
);
618 val
= win_data
->ovl_width
* win_data
->ovl_height
;
619 writel(val
, ctx
->regs
+ offset
);
621 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val
);
624 fimd_win_set_pixfmt(ctx
, win
);
626 /* hardware window 0 doesn't support color key. */
628 fimd_win_set_colkey(ctx
, win
);
631 val
= readl(ctx
->regs
+ WINCON(win
));
632 val
|= WINCONx_ENWIN
;
633 writel(val
, ctx
->regs
+ WINCON(win
));
635 /* Enable DMA channel and unprotect windows */
636 fimd_shadow_protect_win(ctx
, win
, false);
638 if (ctx
->driver_data
->has_shadowcon
) {
639 val
= readl(ctx
->regs
+ SHADOWCON
);
640 val
|= SHADOWCON_CHx_ENABLE(win
);
641 writel(val
, ctx
->regs
+ SHADOWCON
);
644 win_data
->enabled
= true;
647 static void fimd_win_disable(struct exynos_drm_manager
*mgr
, int zpos
)
649 struct fimd_context
*ctx
= mgr
->ctx
;
650 struct fimd_win_data
*win_data
;
654 if (win
== DEFAULT_ZPOS
)
655 win
= ctx
->default_win
;
657 if (win
< 0 || win
>= WINDOWS_NR
)
660 win_data
= &ctx
->win_data
[win
];
662 if (ctx
->suspended
) {
663 /* do not resume this window*/
664 win_data
->resume
= false;
668 /* protect windows */
669 fimd_shadow_protect_win(ctx
, win
, true);
672 val
= readl(ctx
->regs
+ WINCON(win
));
673 val
&= ~WINCONx_ENWIN
;
674 writel(val
, ctx
->regs
+ WINCON(win
));
676 /* unprotect windows */
677 if (ctx
->driver_data
->has_shadowcon
) {
678 val
= readl(ctx
->regs
+ SHADOWCON
);
679 val
&= ~SHADOWCON_CHx_ENABLE(win
);
680 writel(val
, ctx
->regs
+ SHADOWCON
);
683 fimd_shadow_protect_win(ctx
, win
, false);
685 win_data
->enabled
= false;
688 static void fimd_clear_win(struct fimd_context
*ctx
, int win
)
690 writel(0, ctx
->regs
+ WINCON(win
));
691 writel(0, ctx
->regs
+ VIDOSD_A(win
));
692 writel(0, ctx
->regs
+ VIDOSD_B(win
));
693 writel(0, ctx
->regs
+ VIDOSD_C(win
));
695 if (win
== 1 || win
== 2)
696 writel(0, ctx
->regs
+ VIDOSD_D(win
));
698 fimd_shadow_protect_win(ctx
, win
, false);
701 static void fimd_window_suspend(struct exynos_drm_manager
*mgr
)
703 struct fimd_context
*ctx
= mgr
->ctx
;
704 struct fimd_win_data
*win_data
;
707 for (i
= 0; i
< WINDOWS_NR
; i
++) {
708 win_data
= &ctx
->win_data
[i
];
709 win_data
->resume
= win_data
->enabled
;
710 if (win_data
->enabled
)
711 fimd_win_disable(mgr
, i
);
713 fimd_wait_for_vblank(mgr
);
716 static void fimd_window_resume(struct exynos_drm_manager
*mgr
)
718 struct fimd_context
*ctx
= mgr
->ctx
;
719 struct fimd_win_data
*win_data
;
722 for (i
= 0; i
< WINDOWS_NR
; i
++) {
723 win_data
= &ctx
->win_data
[i
];
724 win_data
->enabled
= win_data
->resume
;
725 win_data
->resume
= false;
729 static void fimd_apply(struct exynos_drm_manager
*mgr
)
731 struct fimd_context
*ctx
= mgr
->ctx
;
732 struct fimd_win_data
*win_data
;
735 for (i
= 0; i
< WINDOWS_NR
; i
++) {
736 win_data
= &ctx
->win_data
[i
];
737 if (win_data
->enabled
)
738 fimd_win_commit(mgr
, i
);
744 static int fimd_poweron(struct exynos_drm_manager
*mgr
)
746 struct fimd_context
*ctx
= mgr
->ctx
;
752 ctx
->suspended
= false;
754 pm_runtime_get_sync(ctx
->dev
);
756 ret
= clk_prepare_enable(ctx
->bus_clk
);
758 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret
);
762 ret
= clk_prepare_enable(ctx
->lcd_clk
);
764 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret
);
768 /* if vblank was enabled status, enable it again. */
769 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
770 ret
= fimd_enable_vblank(mgr
);
772 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret
);
773 goto enable_vblank_err
;
777 fimd_window_resume(mgr
);
784 clk_disable_unprepare(ctx
->lcd_clk
);
786 clk_disable_unprepare(ctx
->bus_clk
);
788 ctx
->suspended
= true;
792 static int fimd_poweroff(struct exynos_drm_manager
*mgr
)
794 struct fimd_context
*ctx
= mgr
->ctx
;
800 * We need to make sure that all windows are disabled before we
801 * suspend that connector. Otherwise we might try to scan from
802 * a destroyed buffer later.
804 fimd_window_suspend(mgr
);
806 clk_disable_unprepare(ctx
->lcd_clk
);
807 clk_disable_unprepare(ctx
->bus_clk
);
809 pm_runtime_put_sync(ctx
->dev
);
811 ctx
->suspended
= true;
815 static void fimd_dpms(struct exynos_drm_manager
*mgr
, int mode
)
817 DRM_DEBUG_KMS("%s, %d\n", __FILE__
, mode
);
820 case DRM_MODE_DPMS_ON
:
823 case DRM_MODE_DPMS_STANDBY
:
824 case DRM_MODE_DPMS_SUSPEND
:
825 case DRM_MODE_DPMS_OFF
:
829 DRM_DEBUG_KMS("unspecified mode %d\n", mode
);
834 static struct exynos_drm_manager_ops fimd_manager_ops
= {
835 .initialize
= fimd_mgr_initialize
,
836 .remove
= fimd_mgr_remove
,
838 .mode_fixup
= fimd_mode_fixup
,
839 .mode_set
= fimd_mode_set
,
840 .commit
= fimd_commit
,
841 .enable_vblank
= fimd_enable_vblank
,
842 .disable_vblank
= fimd_disable_vblank
,
843 .wait_for_vblank
= fimd_wait_for_vblank
,
844 .win_mode_set
= fimd_win_mode_set
,
845 .win_commit
= fimd_win_commit
,
846 .win_disable
= fimd_win_disable
,
849 static struct exynos_drm_manager fimd_manager
= {
850 .type
= EXYNOS_DISPLAY_TYPE_LCD
,
851 .ops
= &fimd_manager_ops
,
854 static irqreturn_t
fimd_irq_handler(int irq
, void *dev_id
)
856 struct fimd_context
*ctx
= (struct fimd_context
*)dev_id
;
859 val
= readl(ctx
->regs
+ VIDINTCON1
);
861 if (val
& VIDINTCON1_INT_FRAME
)
862 /* VSYNC interrupt */
863 writel(VIDINTCON1_INT_FRAME
, ctx
->regs
+ VIDINTCON1
);
865 /* check the crtc is detached already from encoder */
866 if (ctx
->pipe
< 0 || !ctx
->drm_dev
)
869 drm_handle_vblank(ctx
->drm_dev
, ctx
->pipe
);
870 exynos_drm_crtc_finish_pageflip(ctx
->drm_dev
, ctx
->pipe
);
872 /* set wait vsync event to zero and wake up queue. */
873 if (atomic_read(&ctx
->wait_vsync_event
)) {
874 atomic_set(&ctx
->wait_vsync_event
, 0);
875 wake_up(&ctx
->wait_vsync_queue
);
881 static int fimd_probe(struct platform_device
*pdev
)
883 struct device
*dev
= &pdev
->dev
;
884 struct fimd_context
*ctx
;
885 struct resource
*res
;
892 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
897 ctx
->suspended
= true;
899 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vden"))
900 ctx
->vidcon1
|= VIDCON1_INV_VDEN
;
901 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vclk"))
902 ctx
->vidcon1
|= VIDCON1_INV_VCLK
;
904 ctx
->bus_clk
= devm_clk_get(dev
, "fimd");
905 if (IS_ERR(ctx
->bus_clk
)) {
906 dev_err(dev
, "failed to get bus clock\n");
907 return PTR_ERR(ctx
->bus_clk
);
910 ctx
->lcd_clk
= devm_clk_get(dev
, "sclk_fimd");
911 if (IS_ERR(ctx
->lcd_clk
)) {
912 dev_err(dev
, "failed to get lcd clock\n");
913 return PTR_ERR(ctx
->lcd_clk
);
916 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
918 ctx
->regs
= devm_ioremap_resource(dev
, res
);
919 if (IS_ERR(ctx
->regs
))
920 return PTR_ERR(ctx
->regs
);
922 res
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
, "vsync");
924 dev_err(dev
, "irq request failed.\n");
928 ret
= devm_request_irq(dev
, res
->start
, fimd_irq_handler
,
931 dev_err(dev
, "irq request failed.\n");
935 ctx
->driver_data
= drm_fimd_get_driver_data(pdev
);
936 init_waitqueue_head(&ctx
->wait_vsync_queue
);
937 atomic_set(&ctx
->wait_vsync_event
, 0);
939 platform_set_drvdata(pdev
, &fimd_manager
);
941 fimd_manager
.ctx
= ctx
;
942 exynos_drm_manager_register(&fimd_manager
);
944 exynos_dpi_probe(ctx
->dev
);
946 pm_runtime_enable(dev
);
948 for (win
= 0; win
< WINDOWS_NR
; win
++)
949 fimd_clear_win(ctx
, win
);
954 static int fimd_remove(struct platform_device
*pdev
)
956 struct exynos_drm_manager
*mgr
= platform_get_drvdata(pdev
);
958 exynos_dpi_remove(&pdev
->dev
);
960 exynos_drm_manager_unregister(&fimd_manager
);
962 fimd_dpms(mgr
, DRM_MODE_DPMS_OFF
);
964 pm_runtime_disable(&pdev
->dev
);
969 struct platform_driver fimd_driver
= {
971 .remove
= fimd_remove
,
973 .name
= "exynos4-fb",
974 .owner
= THIS_MODULE
,
975 .of_match_table
= fimd_driver_dt_match
,