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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fb.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_plane.h"
35 #include "exynos_drm_iommu.h"
36
37 /*
38 * FIMD stands for Fully Interactive Mobile Display and
39 * as a display controller, it transfers contents drawn on memory
40 * to a LCD Panel through Display Interfaces such as RGB or
41 * CPU Interface.
42 */
43
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
45
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
49 /*
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
52 */
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
56
57 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
58 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
59
60 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
61 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
62 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
63 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
64
65 /* color key control register for hardware window 1 ~ 4. */
66 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
67 /* color key value register for hardware window 1 ~ 4. */
68 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
69
70 /* I80 trigger control register */
71 #define TRIGCON 0x1A4
72 #define TRGMODE_ENABLE (1 << 0)
73 #define SWTRGCMD_ENABLE (1 << 1)
74 /* Exynos3250, 3472, 4415, 5260 5410, 5420 and 5422 only supported. */
75 #define HWTRGEN_ENABLE (1 << 3)
76 #define HWTRGMASK_ENABLE (1 << 4)
77 /* Exynos3250, 3472, 4415, 5260, 5420 and 5422 only supported. */
78 #define HWTRIGEN_PER_ENABLE (1 << 31)
79
80 /* display mode change control register except exynos4 */
81 #define VIDOUT_CON 0x000
82 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
83
84 /* I80 interface control for main LDI register */
85 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
86 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
87 #define LCD_CS_SETUP(x) ((x) << 16)
88 #define LCD_WR_SETUP(x) ((x) << 12)
89 #define LCD_WR_ACTIVE(x) ((x) << 8)
90 #define LCD_WR_HOLD(x) ((x) << 4)
91 #define I80IFEN_ENABLE (1 << 0)
92
93 /* FIMD has totally five hardware windows. */
94 #define WINDOWS_NR 5
95
96 /* HW trigger flag on i80 panel. */
97 #define I80_HW_TRG (1 << 1)
98
99 struct fimd_driver_data {
100 unsigned int timing_base;
101 unsigned int lcdblk_offset;
102 unsigned int lcdblk_vt_shift;
103 unsigned int lcdblk_bypass_shift;
104 unsigned int lcdblk_mic_bypass_shift;
105 unsigned int trg_type;
106
107 unsigned int has_shadowcon:1;
108 unsigned int has_clksel:1;
109 unsigned int has_limited_fmt:1;
110 unsigned int has_vidoutcon:1;
111 unsigned int has_vtsel:1;
112 unsigned int has_mic_bypass:1;
113 unsigned int has_dp_clk:1;
114 unsigned int has_hw_trigger:1;
115 unsigned int has_trigger_per_te:1;
116 };
117
118 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
119 .timing_base = 0x0,
120 .has_clksel = 1,
121 .has_limited_fmt = 1,
122 };
123
124 static struct fimd_driver_data exynos3_fimd_driver_data = {
125 .timing_base = 0x20000,
126 .lcdblk_offset = 0x210,
127 .lcdblk_bypass_shift = 1,
128 .has_shadowcon = 1,
129 .has_vidoutcon = 1,
130 };
131
132 static struct fimd_driver_data exynos4_fimd_driver_data = {
133 .timing_base = 0x0,
134 .lcdblk_offset = 0x210,
135 .lcdblk_vt_shift = 10,
136 .lcdblk_bypass_shift = 1,
137 .has_shadowcon = 1,
138 .has_vtsel = 1,
139 };
140
141 static struct fimd_driver_data exynos4415_fimd_driver_data = {
142 .timing_base = 0x20000,
143 .lcdblk_offset = 0x210,
144 .lcdblk_vt_shift = 10,
145 .lcdblk_bypass_shift = 1,
146 .trg_type = I80_HW_TRG,
147 .has_shadowcon = 1,
148 .has_vidoutcon = 1,
149 .has_vtsel = 1,
150 .has_trigger_per_te = 1,
151 };
152
153 static struct fimd_driver_data exynos5_fimd_driver_data = {
154 .timing_base = 0x20000,
155 .lcdblk_offset = 0x214,
156 .lcdblk_vt_shift = 24,
157 .lcdblk_bypass_shift = 15,
158 .has_shadowcon = 1,
159 .has_vidoutcon = 1,
160 .has_vtsel = 1,
161 .has_dp_clk = 1,
162 };
163
164 static struct fimd_driver_data exynos5420_fimd_driver_data = {
165 .timing_base = 0x20000,
166 .lcdblk_offset = 0x214,
167 .lcdblk_vt_shift = 24,
168 .lcdblk_bypass_shift = 15,
169 .lcdblk_mic_bypass_shift = 11,
170 .has_shadowcon = 1,
171 .has_vidoutcon = 1,
172 .has_vtsel = 1,
173 .has_mic_bypass = 1,
174 .has_dp_clk = 1,
175 };
176
177 struct fimd_context {
178 struct device *dev;
179 struct drm_device *drm_dev;
180 struct exynos_drm_crtc *crtc;
181 struct exynos_drm_plane planes[WINDOWS_NR];
182 struct exynos_drm_plane_config configs[WINDOWS_NR];
183 struct clk *bus_clk;
184 struct clk *lcd_clk;
185 void __iomem *regs;
186 struct regmap *sysreg;
187 unsigned long irq_flags;
188 u32 vidcon0;
189 u32 vidcon1;
190 u32 vidout_con;
191 u32 i80ifcon;
192 bool i80_if;
193 bool suspended;
194 int pipe;
195 wait_queue_head_t wait_vsync_queue;
196 atomic_t wait_vsync_event;
197 atomic_t win_updated;
198 atomic_t triggering;
199 u32 clkdiv;
200
201 const struct fimd_driver_data *driver_data;
202 struct drm_encoder *encoder;
203 struct exynos_drm_clk dp_clk;
204 };
205
206 static const struct of_device_id fimd_driver_dt_match[] = {
207 { .compatible = "samsung,s3c6400-fimd",
208 .data = &s3c64xx_fimd_driver_data },
209 { .compatible = "samsung,exynos3250-fimd",
210 .data = &exynos3_fimd_driver_data },
211 { .compatible = "samsung,exynos4210-fimd",
212 .data = &exynos4_fimd_driver_data },
213 { .compatible = "samsung,exynos4415-fimd",
214 .data = &exynos4415_fimd_driver_data },
215 { .compatible = "samsung,exynos5250-fimd",
216 .data = &exynos5_fimd_driver_data },
217 { .compatible = "samsung,exynos5420-fimd",
218 .data = &exynos5420_fimd_driver_data },
219 {},
220 };
221 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
222
223 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
224 DRM_PLANE_TYPE_PRIMARY,
225 DRM_PLANE_TYPE_OVERLAY,
226 DRM_PLANE_TYPE_OVERLAY,
227 DRM_PLANE_TYPE_OVERLAY,
228 DRM_PLANE_TYPE_CURSOR,
229 };
230
231 static const uint32_t fimd_formats[] = {
232 DRM_FORMAT_C8,
233 DRM_FORMAT_XRGB1555,
234 DRM_FORMAT_RGB565,
235 DRM_FORMAT_XRGB8888,
236 DRM_FORMAT_ARGB8888,
237 };
238
239 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
240 {
241 struct fimd_context *ctx = crtc->ctx;
242 u32 val;
243
244 if (ctx->suspended)
245 return -EPERM;
246
247 if (!test_and_set_bit(0, &ctx->irq_flags)) {
248 val = readl(ctx->regs + VIDINTCON0);
249
250 val |= VIDINTCON0_INT_ENABLE;
251
252 if (ctx->i80_if) {
253 val |= VIDINTCON0_INT_I80IFDONE;
254 val |= VIDINTCON0_INT_SYSMAINCON;
255 val &= ~VIDINTCON0_INT_SYSSUBCON;
256 } else {
257 val |= VIDINTCON0_INT_FRAME;
258
259 val &= ~VIDINTCON0_FRAMESEL0_MASK;
260 val |= VIDINTCON0_FRAMESEL0_VSYNC;
261 val &= ~VIDINTCON0_FRAMESEL1_MASK;
262 val |= VIDINTCON0_FRAMESEL1_NONE;
263 }
264
265 writel(val, ctx->regs + VIDINTCON0);
266 }
267
268 return 0;
269 }
270
271 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
272 {
273 struct fimd_context *ctx = crtc->ctx;
274 u32 val;
275
276 if (ctx->suspended)
277 return;
278
279 if (test_and_clear_bit(0, &ctx->irq_flags)) {
280 val = readl(ctx->regs + VIDINTCON0);
281
282 val &= ~VIDINTCON0_INT_ENABLE;
283
284 if (ctx->i80_if) {
285 val &= ~VIDINTCON0_INT_I80IFDONE;
286 val &= ~VIDINTCON0_INT_SYSMAINCON;
287 val &= ~VIDINTCON0_INT_SYSSUBCON;
288 } else
289 val &= ~VIDINTCON0_INT_FRAME;
290
291 writel(val, ctx->regs + VIDINTCON0);
292 }
293 }
294
295 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
296 {
297 struct fimd_context *ctx = crtc->ctx;
298
299 if (ctx->suspended)
300 return;
301
302 atomic_set(&ctx->wait_vsync_event, 1);
303
304 /*
305 * wait for FIMD to signal VSYNC interrupt or return after
306 * timeout which is set to 50ms (refresh rate of 20).
307 */
308 if (!wait_event_timeout(ctx->wait_vsync_queue,
309 !atomic_read(&ctx->wait_vsync_event),
310 HZ/20))
311 DRM_DEBUG_KMS("vblank wait timed out.\n");
312 }
313
314 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
315 bool enable)
316 {
317 u32 val = readl(ctx->regs + WINCON(win));
318
319 if (enable)
320 val |= WINCONx_ENWIN;
321 else
322 val &= ~WINCONx_ENWIN;
323
324 writel(val, ctx->regs + WINCON(win));
325 }
326
327 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
328 unsigned int win,
329 bool enable)
330 {
331 u32 val = readl(ctx->regs + SHADOWCON);
332
333 if (enable)
334 val |= SHADOWCON_CHx_ENABLE(win);
335 else
336 val &= ~SHADOWCON_CHx_ENABLE(win);
337
338 writel(val, ctx->regs + SHADOWCON);
339 }
340
341 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
342 {
343 struct fimd_context *ctx = crtc->ctx;
344 unsigned int win, ch_enabled = 0;
345
346 DRM_DEBUG_KMS("%s\n", __FILE__);
347
348 /* Hardware is in unknown state, so ensure it gets enabled properly */
349 pm_runtime_get_sync(ctx->dev);
350
351 clk_prepare_enable(ctx->bus_clk);
352 clk_prepare_enable(ctx->lcd_clk);
353
354 /* Check if any channel is enabled. */
355 for (win = 0; win < WINDOWS_NR; win++) {
356 u32 val = readl(ctx->regs + WINCON(win));
357
358 if (val & WINCONx_ENWIN) {
359 fimd_enable_video_output(ctx, win, false);
360
361 if (ctx->driver_data->has_shadowcon)
362 fimd_enable_shadow_channel_path(ctx, win,
363 false);
364
365 ch_enabled = 1;
366 }
367 }
368
369 /* Wait for vsync, as disable channel takes effect at next vsync */
370 if (ch_enabled) {
371 int pipe = ctx->pipe;
372
373 /* ensure that vblank interrupt won't be reported to core */
374 ctx->suspended = false;
375 ctx->pipe = -1;
376
377 fimd_enable_vblank(ctx->crtc);
378 fimd_wait_for_vblank(ctx->crtc);
379 fimd_disable_vblank(ctx->crtc);
380
381 ctx->suspended = true;
382 ctx->pipe = pipe;
383 }
384
385 clk_disable_unprepare(ctx->lcd_clk);
386 clk_disable_unprepare(ctx->bus_clk);
387
388 pm_runtime_put(ctx->dev);
389 }
390
391
392 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
393 struct drm_crtc_state *state)
394 {
395 struct drm_display_mode *mode = &state->adjusted_mode;
396 struct fimd_context *ctx = crtc->ctx;
397 unsigned long ideal_clk, lcd_rate;
398 u32 clkdiv;
399
400 if (mode->clock == 0) {
401 DRM_INFO("Mode has zero clock value.\n");
402 return -EINVAL;
403 }
404
405 ideal_clk = mode->clock * 1000;
406
407 if (ctx->i80_if) {
408 /*
409 * The frame done interrupt should be occurred prior to the
410 * next TE signal.
411 */
412 ideal_clk *= 2;
413 }
414
415 lcd_rate = clk_get_rate(ctx->lcd_clk);
416 if (2 * lcd_rate < ideal_clk) {
417 DRM_INFO("sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
418 lcd_rate, ideal_clk);
419 return -EINVAL;
420 }
421
422 /* Find the clock divider value that gets us closest to ideal_clk */
423 clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
424 if (clkdiv >= 0x200) {
425 DRM_INFO("requested pixel clock(%lu) too low\n", ideal_clk);
426 return -EINVAL;
427 }
428
429 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
430
431 return 0;
432 }
433
434 static void fimd_setup_trigger(struct fimd_context *ctx)
435 {
436 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
437 u32 trg_type = ctx->driver_data->trg_type;
438 u32 val = readl(timing_base + TRIGCON);
439
440 val &= ~(TRGMODE_ENABLE);
441
442 if (trg_type == I80_HW_TRG) {
443 if (ctx->driver_data->has_hw_trigger)
444 val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
445 if (ctx->driver_data->has_trigger_per_te)
446 val |= HWTRIGEN_PER_ENABLE;
447 } else {
448 val |= TRGMODE_ENABLE;
449 }
450
451 writel(val, timing_base + TRIGCON);
452 }
453
454 static void fimd_commit(struct exynos_drm_crtc *crtc)
455 {
456 struct fimd_context *ctx = crtc->ctx;
457 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
458 const struct fimd_driver_data *driver_data = ctx->driver_data;
459 void *timing_base = ctx->regs + driver_data->timing_base;
460 u32 val;
461
462 if (ctx->suspended)
463 return;
464
465 /* nothing to do if we haven't set the mode yet */
466 if (mode->htotal == 0 || mode->vtotal == 0)
467 return;
468
469 if (ctx->i80_if) {
470 val = ctx->i80ifcon | I80IFEN_ENABLE;
471 writel(val, timing_base + I80IFCONFAx(0));
472
473 /* disable auto frame rate */
474 writel(0, timing_base + I80IFCONFBx(0));
475
476 /* set video type selection to I80 interface */
477 if (driver_data->has_vtsel && ctx->sysreg &&
478 regmap_update_bits(ctx->sysreg,
479 driver_data->lcdblk_offset,
480 0x3 << driver_data->lcdblk_vt_shift,
481 0x1 << driver_data->lcdblk_vt_shift)) {
482 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
483 return;
484 }
485 } else {
486 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
487 u32 vidcon1;
488
489 /* setup polarity values */
490 vidcon1 = ctx->vidcon1;
491 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
492 vidcon1 |= VIDCON1_INV_VSYNC;
493 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
494 vidcon1 |= VIDCON1_INV_HSYNC;
495 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
496
497 /* setup vertical timing values. */
498 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
499 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
500 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
501
502 val = VIDTCON0_VBPD(vbpd - 1) |
503 VIDTCON0_VFPD(vfpd - 1) |
504 VIDTCON0_VSPW(vsync_len - 1);
505 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
506
507 /* setup horizontal timing values. */
508 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
509 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
510 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
511
512 val = VIDTCON1_HBPD(hbpd - 1) |
513 VIDTCON1_HFPD(hfpd - 1) |
514 VIDTCON1_HSPW(hsync_len - 1);
515 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
516 }
517
518 if (driver_data->has_vidoutcon)
519 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
520
521 /* set bypass selection */
522 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
523 driver_data->lcdblk_offset,
524 0x1 << driver_data->lcdblk_bypass_shift,
525 0x1 << driver_data->lcdblk_bypass_shift)) {
526 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
527 return;
528 }
529
530 /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
531 * bit should be cleared.
532 */
533 if (driver_data->has_mic_bypass && ctx->sysreg &&
534 regmap_update_bits(ctx->sysreg,
535 driver_data->lcdblk_offset,
536 0x1 << driver_data->lcdblk_mic_bypass_shift,
537 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
538 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
539 return;
540 }
541
542 /* setup horizontal and vertical display size. */
543 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
544 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
545 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
546 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
547 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
548
549 fimd_setup_trigger(ctx);
550
551 /*
552 * fields of register with prefix '_F' would be updated
553 * at vsync(same as dma start)
554 */
555 val = ctx->vidcon0;
556 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
557
558 if (ctx->driver_data->has_clksel)
559 val |= VIDCON0_CLKSEL_LCD;
560
561 if (ctx->clkdiv > 1)
562 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
563
564 writel(val, ctx->regs + VIDCON0);
565 }
566
567
568 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
569 uint32_t pixel_format, int width)
570 {
571 unsigned long val;
572
573 val = WINCONx_ENWIN;
574
575 /*
576 * In case of s3c64xx, window 0 doesn't support alpha channel.
577 * So the request format is ARGB8888 then change it to XRGB8888.
578 */
579 if (ctx->driver_data->has_limited_fmt && !win) {
580 if (pixel_format == DRM_FORMAT_ARGB8888)
581 pixel_format = DRM_FORMAT_XRGB8888;
582 }
583
584 switch (pixel_format) {
585 case DRM_FORMAT_C8:
586 val |= WINCON0_BPPMODE_8BPP_PALETTE;
587 val |= WINCONx_BURSTLEN_8WORD;
588 val |= WINCONx_BYTSWP;
589 break;
590 case DRM_FORMAT_XRGB1555:
591 val |= WINCON0_BPPMODE_16BPP_1555;
592 val |= WINCONx_HAWSWP;
593 val |= WINCONx_BURSTLEN_16WORD;
594 break;
595 case DRM_FORMAT_RGB565:
596 val |= WINCON0_BPPMODE_16BPP_565;
597 val |= WINCONx_HAWSWP;
598 val |= WINCONx_BURSTLEN_16WORD;
599 break;
600 case DRM_FORMAT_XRGB8888:
601 val |= WINCON0_BPPMODE_24BPP_888;
602 val |= WINCONx_WSWP;
603 val |= WINCONx_BURSTLEN_16WORD;
604 break;
605 case DRM_FORMAT_ARGB8888:
606 val |= WINCON1_BPPMODE_25BPP_A1888
607 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
608 val |= WINCONx_WSWP;
609 val |= WINCONx_BURSTLEN_16WORD;
610 break;
611 default:
612 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
613
614 val |= WINCON0_BPPMODE_24BPP_888;
615 val |= WINCONx_WSWP;
616 val |= WINCONx_BURSTLEN_16WORD;
617 break;
618 }
619
620 /*
621 * Setting dma-burst to 16Word causes permanent tearing for very small
622 * buffers, e.g. cursor buffer. Burst Mode switching which based on
623 * plane size is not recommended as plane size varies alot towards the
624 * end of the screen and rapid movement causes unstable DMA, but it is
625 * still better to change dma-burst than displaying garbage.
626 */
627
628 if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
629 val &= ~WINCONx_BURSTLEN_MASK;
630 val |= WINCONx_BURSTLEN_4WORD;
631 }
632
633 writel(val, ctx->regs + WINCON(win));
634
635 /* hardware window 0 doesn't support alpha channel. */
636 if (win != 0) {
637 /* OSD alpha */
638 val = VIDISD14C_ALPHA0_R(0xf) |
639 VIDISD14C_ALPHA0_G(0xf) |
640 VIDISD14C_ALPHA0_B(0xf) |
641 VIDISD14C_ALPHA1_R(0xf) |
642 VIDISD14C_ALPHA1_G(0xf) |
643 VIDISD14C_ALPHA1_B(0xf);
644
645 writel(val, ctx->regs + VIDOSD_C(win));
646
647 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
648 VIDW_ALPHA_G(0xf);
649 writel(val, ctx->regs + VIDWnALPHA0(win));
650 writel(val, ctx->regs + VIDWnALPHA1(win));
651 }
652 }
653
654 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
655 {
656 unsigned int keycon0 = 0, keycon1 = 0;
657
658 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
659 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
660
661 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
662
663 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
664 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
665 }
666
667 /**
668 * shadow_protect_win() - disable updating values from shadow registers at vsync
669 *
670 * @win: window to protect registers for
671 * @protect: 1 to protect (disable updates)
672 */
673 static void fimd_shadow_protect_win(struct fimd_context *ctx,
674 unsigned int win, bool protect)
675 {
676 u32 reg, bits, val;
677
678 /*
679 * SHADOWCON/PRTCON register is used for enabling timing.
680 *
681 * for example, once only width value of a register is set,
682 * if the dma is started then fimd hardware could malfunction so
683 * with protect window setting, the register fields with prefix '_F'
684 * wouldn't be updated at vsync also but updated once unprotect window
685 * is set.
686 */
687
688 if (ctx->driver_data->has_shadowcon) {
689 reg = SHADOWCON;
690 bits = SHADOWCON_WINx_PROTECT(win);
691 } else {
692 reg = PRTCON;
693 bits = PRTCON_PROTECT;
694 }
695
696 val = readl(ctx->regs + reg);
697 if (protect)
698 val |= bits;
699 else
700 val &= ~bits;
701 writel(val, ctx->regs + reg);
702 }
703
704 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
705 {
706 struct fimd_context *ctx = crtc->ctx;
707 int i;
708
709 if (ctx->suspended)
710 return;
711
712 for (i = 0; i < WINDOWS_NR; i++)
713 fimd_shadow_protect_win(ctx, i, true);
714 }
715
716 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
717 {
718 struct fimd_context *ctx = crtc->ctx;
719 int i;
720
721 if (ctx->suspended)
722 return;
723
724 for (i = 0; i < WINDOWS_NR; i++)
725 fimd_shadow_protect_win(ctx, i, false);
726 }
727
728 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
729 struct exynos_drm_plane *plane)
730 {
731 struct exynos_drm_plane_state *state =
732 to_exynos_plane_state(plane->base.state);
733 struct fimd_context *ctx = crtc->ctx;
734 struct drm_framebuffer *fb = state->base.fb;
735 dma_addr_t dma_addr;
736 unsigned long val, size, offset;
737 unsigned int last_x, last_y, buf_offsize, line_size;
738 unsigned int win = plane->index;
739 unsigned int bpp = fb->format->cpp[0];
740 unsigned int pitch = fb->pitches[0];
741
742 if (ctx->suspended)
743 return;
744
745 offset = state->src.x * bpp;
746 offset += state->src.y * pitch;
747
748 /* buffer start address */
749 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
750 val = (unsigned long)dma_addr;
751 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
752
753 /* buffer end address */
754 size = pitch * state->crtc.h;
755 val = (unsigned long)(dma_addr + size);
756 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
757
758 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
759 (unsigned long)dma_addr, val, size);
760 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
761 state->crtc.w, state->crtc.h);
762
763 /* buffer size */
764 buf_offsize = pitch - (state->crtc.w * bpp);
765 line_size = state->crtc.w * bpp;
766 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
767 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
768 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
769 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
770 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
771
772 /* OSD position */
773 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
774 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
775 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
776 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
777 writel(val, ctx->regs + VIDOSD_A(win));
778
779 last_x = state->crtc.x + state->crtc.w;
780 if (last_x)
781 last_x--;
782 last_y = state->crtc.y + state->crtc.h;
783 if (last_y)
784 last_y--;
785
786 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
787 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
788
789 writel(val, ctx->regs + VIDOSD_B(win));
790
791 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
792 state->crtc.x, state->crtc.y, last_x, last_y);
793
794 /* OSD size */
795 if (win != 3 && win != 4) {
796 u32 offset = VIDOSD_D(win);
797 if (win == 0)
798 offset = VIDOSD_C(win);
799 val = state->crtc.w * state->crtc.h;
800 writel(val, ctx->regs + offset);
801
802 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
803 }
804
805 fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w);
806
807 /* hardware window 0 doesn't support color key. */
808 if (win != 0)
809 fimd_win_set_colkey(ctx, win);
810
811 fimd_enable_video_output(ctx, win, true);
812
813 if (ctx->driver_data->has_shadowcon)
814 fimd_enable_shadow_channel_path(ctx, win, true);
815
816 if (ctx->i80_if)
817 atomic_set(&ctx->win_updated, 1);
818 }
819
820 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
821 struct exynos_drm_plane *plane)
822 {
823 struct fimd_context *ctx = crtc->ctx;
824 unsigned int win = plane->index;
825
826 if (ctx->suspended)
827 return;
828
829 fimd_enable_video_output(ctx, win, false);
830
831 if (ctx->driver_data->has_shadowcon)
832 fimd_enable_shadow_channel_path(ctx, win, false);
833 }
834
835 static void fimd_enable(struct exynos_drm_crtc *crtc)
836 {
837 struct fimd_context *ctx = crtc->ctx;
838
839 if (!ctx->suspended)
840 return;
841
842 ctx->suspended = false;
843
844 pm_runtime_get_sync(ctx->dev);
845
846 /* if vblank was enabled status, enable it again. */
847 if (test_and_clear_bit(0, &ctx->irq_flags))
848 fimd_enable_vblank(ctx->crtc);
849
850 fimd_commit(ctx->crtc);
851 }
852
853 static void fimd_disable(struct exynos_drm_crtc *crtc)
854 {
855 struct fimd_context *ctx = crtc->ctx;
856 int i;
857
858 if (ctx->suspended)
859 return;
860
861 /*
862 * We need to make sure that all windows are disabled before we
863 * suspend that connector. Otherwise we might try to scan from
864 * a destroyed buffer later.
865 */
866 for (i = 0; i < WINDOWS_NR; i++)
867 fimd_disable_plane(crtc, &ctx->planes[i]);
868
869 fimd_enable_vblank(crtc);
870 fimd_wait_for_vblank(crtc);
871 fimd_disable_vblank(crtc);
872
873 writel(0, ctx->regs + VIDCON0);
874
875 pm_runtime_put_sync(ctx->dev);
876 ctx->suspended = true;
877 }
878
879 static void fimd_trigger(struct device *dev)
880 {
881 struct fimd_context *ctx = dev_get_drvdata(dev);
882 const struct fimd_driver_data *driver_data = ctx->driver_data;
883 void *timing_base = ctx->regs + driver_data->timing_base;
884 u32 reg;
885
886 /*
887 * Skips triggering if in triggering state, because multiple triggering
888 * requests can cause panel reset.
889 */
890 if (atomic_read(&ctx->triggering))
891 return;
892
893 /* Enters triggering mode */
894 atomic_set(&ctx->triggering, 1);
895
896 reg = readl(timing_base + TRIGCON);
897 reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
898 writel(reg, timing_base + TRIGCON);
899
900 /*
901 * Exits triggering mode if vblank is not enabled yet, because when the
902 * VIDINTCON0 register is not set, it can not exit from triggering mode.
903 */
904 if (!test_bit(0, &ctx->irq_flags))
905 atomic_set(&ctx->triggering, 0);
906 }
907
908 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
909 {
910 struct fimd_context *ctx = crtc->ctx;
911 u32 trg_type = ctx->driver_data->trg_type;
912
913 /* Checks the crtc is detached already from encoder */
914 if (ctx->pipe < 0 || !ctx->drm_dev)
915 return;
916
917 if (trg_type == I80_HW_TRG)
918 goto out;
919
920 /*
921 * If there is a page flip request, triggers and handles the page flip
922 * event so that current fb can be updated into panel GRAM.
923 */
924 if (atomic_add_unless(&ctx->win_updated, -1, 0))
925 fimd_trigger(ctx->dev);
926
927 out:
928 /* Wakes up vsync event queue */
929 if (atomic_read(&ctx->wait_vsync_event)) {
930 atomic_set(&ctx->wait_vsync_event, 0);
931 wake_up(&ctx->wait_vsync_queue);
932 }
933
934 if (test_bit(0, &ctx->irq_flags))
935 drm_crtc_handle_vblank(&ctx->crtc->base);
936 }
937
938 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
939 {
940 struct fimd_context *ctx = container_of(clk, struct fimd_context,
941 dp_clk);
942 u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
943 writel(val, ctx->regs + DP_MIE_CLKCON);
944 }
945
946 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
947 .enable = fimd_enable,
948 .disable = fimd_disable,
949 .commit = fimd_commit,
950 .enable_vblank = fimd_enable_vblank,
951 .disable_vblank = fimd_disable_vblank,
952 .atomic_begin = fimd_atomic_begin,
953 .update_plane = fimd_update_plane,
954 .disable_plane = fimd_disable_plane,
955 .atomic_flush = fimd_atomic_flush,
956 .atomic_check = fimd_atomic_check,
957 .te_handler = fimd_te_handler,
958 };
959
960 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
961 {
962 struct fimd_context *ctx = (struct fimd_context *)dev_id;
963 u32 val, clear_bit;
964
965 val = readl(ctx->regs + VIDINTCON1);
966
967 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
968 if (val & clear_bit)
969 writel(clear_bit, ctx->regs + VIDINTCON1);
970
971 /* check the crtc is detached already from encoder */
972 if (ctx->pipe < 0 || !ctx->drm_dev)
973 goto out;
974
975 if (!ctx->i80_if)
976 drm_crtc_handle_vblank(&ctx->crtc->base);
977
978 if (ctx->i80_if) {
979 /* Exits triggering mode */
980 atomic_set(&ctx->triggering, 0);
981 } else {
982 /* set wait vsync event to zero and wake up queue. */
983 if (atomic_read(&ctx->wait_vsync_event)) {
984 atomic_set(&ctx->wait_vsync_event, 0);
985 wake_up(&ctx->wait_vsync_queue);
986 }
987 }
988
989 out:
990 return IRQ_HANDLED;
991 }
992
993 static int fimd_bind(struct device *dev, struct device *master, void *data)
994 {
995 struct fimd_context *ctx = dev_get_drvdata(dev);
996 struct drm_device *drm_dev = data;
997 struct exynos_drm_private *priv = drm_dev->dev_private;
998 struct exynos_drm_plane *exynos_plane;
999 unsigned int i;
1000 int ret;
1001
1002 ctx->drm_dev = drm_dev;
1003 ctx->pipe = priv->pipe++;
1004
1005 for (i = 0; i < WINDOWS_NR; i++) {
1006 ctx->configs[i].pixel_formats = fimd_formats;
1007 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
1008 ctx->configs[i].zpos = i;
1009 ctx->configs[i].type = fimd_win_types[i];
1010 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1011 1 << ctx->pipe, &ctx->configs[i]);
1012 if (ret)
1013 return ret;
1014 }
1015
1016 exynos_plane = &ctx->planes[DEFAULT_WIN];
1017 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1018 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
1019 &fimd_crtc_ops, ctx);
1020 if (IS_ERR(ctx->crtc))
1021 return PTR_ERR(ctx->crtc);
1022
1023 if (ctx->driver_data->has_dp_clk) {
1024 ctx->dp_clk.enable = fimd_dp_clock_enable;
1025 ctx->crtc->pipe_clk = &ctx->dp_clk;
1026 }
1027
1028 if (ctx->encoder)
1029 exynos_dpi_bind(drm_dev, ctx->encoder);
1030
1031 if (is_drm_iommu_supported(drm_dev))
1032 fimd_clear_channels(ctx->crtc);
1033
1034 ret = drm_iommu_attach_device(drm_dev, dev);
1035 if (ret)
1036 priv->pipe--;
1037
1038 return ret;
1039 }
1040
1041 static void fimd_unbind(struct device *dev, struct device *master,
1042 void *data)
1043 {
1044 struct fimd_context *ctx = dev_get_drvdata(dev);
1045
1046 fimd_disable(ctx->crtc);
1047
1048 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
1049
1050 if (ctx->encoder)
1051 exynos_dpi_remove(ctx->encoder);
1052 }
1053
1054 static const struct component_ops fimd_component_ops = {
1055 .bind = fimd_bind,
1056 .unbind = fimd_unbind,
1057 };
1058
1059 static int fimd_probe(struct platform_device *pdev)
1060 {
1061 struct device *dev = &pdev->dev;
1062 struct fimd_context *ctx;
1063 struct device_node *i80_if_timings;
1064 struct resource *res;
1065 int ret;
1066
1067 if (!dev->of_node)
1068 return -ENODEV;
1069
1070 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1071 if (!ctx)
1072 return -ENOMEM;
1073
1074 ctx->dev = dev;
1075 ctx->suspended = true;
1076 ctx->driver_data = of_device_get_match_data(dev);
1077
1078 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1079 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1080 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1081 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1082
1083 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1084 if (i80_if_timings) {
1085 u32 val;
1086
1087 ctx->i80_if = true;
1088
1089 if (ctx->driver_data->has_vidoutcon)
1090 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1091 else
1092 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1093 /*
1094 * The user manual describes that this "DSI_EN" bit is required
1095 * to enable I80 24-bit data interface.
1096 */
1097 ctx->vidcon0 |= VIDCON0_DSI_EN;
1098
1099 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1100 val = 0;
1101 ctx->i80ifcon = LCD_CS_SETUP(val);
1102 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1103 val = 0;
1104 ctx->i80ifcon |= LCD_WR_SETUP(val);
1105 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1106 val = 1;
1107 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1108 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1109 val = 0;
1110 ctx->i80ifcon |= LCD_WR_HOLD(val);
1111 }
1112 of_node_put(i80_if_timings);
1113
1114 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1115 "samsung,sysreg");
1116 if (IS_ERR(ctx->sysreg)) {
1117 dev_warn(dev, "failed to get system register.\n");
1118 ctx->sysreg = NULL;
1119 }
1120
1121 ctx->bus_clk = devm_clk_get(dev, "fimd");
1122 if (IS_ERR(ctx->bus_clk)) {
1123 dev_err(dev, "failed to get bus clock\n");
1124 return PTR_ERR(ctx->bus_clk);
1125 }
1126
1127 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1128 if (IS_ERR(ctx->lcd_clk)) {
1129 dev_err(dev, "failed to get lcd clock\n");
1130 return PTR_ERR(ctx->lcd_clk);
1131 }
1132
1133 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1134
1135 ctx->regs = devm_ioremap_resource(dev, res);
1136 if (IS_ERR(ctx->regs))
1137 return PTR_ERR(ctx->regs);
1138
1139 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1140 ctx->i80_if ? "lcd_sys" : "vsync");
1141 if (!res) {
1142 dev_err(dev, "irq request failed.\n");
1143 return -ENXIO;
1144 }
1145
1146 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1147 0, "drm_fimd", ctx);
1148 if (ret) {
1149 dev_err(dev, "irq request failed.\n");
1150 return ret;
1151 }
1152
1153 init_waitqueue_head(&ctx->wait_vsync_queue);
1154 atomic_set(&ctx->wait_vsync_event, 0);
1155
1156 platform_set_drvdata(pdev, ctx);
1157
1158 ctx->encoder = exynos_dpi_probe(dev);
1159 if (IS_ERR(ctx->encoder))
1160 return PTR_ERR(ctx->encoder);
1161
1162 pm_runtime_enable(dev);
1163
1164 ret = component_add(dev, &fimd_component_ops);
1165 if (ret)
1166 goto err_disable_pm_runtime;
1167
1168 return ret;
1169
1170 err_disable_pm_runtime:
1171 pm_runtime_disable(dev);
1172
1173 return ret;
1174 }
1175
1176 static int fimd_remove(struct platform_device *pdev)
1177 {
1178 pm_runtime_disable(&pdev->dev);
1179
1180 component_del(&pdev->dev, &fimd_component_ops);
1181
1182 return 0;
1183 }
1184
1185 #ifdef CONFIG_PM
1186 static int exynos_fimd_suspend(struct device *dev)
1187 {
1188 struct fimd_context *ctx = dev_get_drvdata(dev);
1189
1190 clk_disable_unprepare(ctx->lcd_clk);
1191 clk_disable_unprepare(ctx->bus_clk);
1192
1193 return 0;
1194 }
1195
1196 static int exynos_fimd_resume(struct device *dev)
1197 {
1198 struct fimd_context *ctx = dev_get_drvdata(dev);
1199 int ret;
1200
1201 ret = clk_prepare_enable(ctx->bus_clk);
1202 if (ret < 0) {
1203 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1204 return ret;
1205 }
1206
1207 ret = clk_prepare_enable(ctx->lcd_clk);
1208 if (ret < 0) {
1209 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1210 return ret;
1211 }
1212
1213 return 0;
1214 }
1215 #endif
1216
1217 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1218 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1219 };
1220
1221 struct platform_driver fimd_driver = {
1222 .probe = fimd_probe,
1223 .remove = fimd_remove,
1224 .driver = {
1225 .name = "exynos4-fb",
1226 .owner = THIS_MODULE,
1227 .pm = &exynos_fimd_pm_ops,
1228 .of_match_table = fimd_driver_dt_match,
1229 },
1230 };
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