1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 Samsung Electronics Co.Ltd
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 * Inki Dae <inki.dae@samsung.com>
11 #include <linux/kernel.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
15 #include <linux/of_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/component.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
21 #include <video/of_display_timing.h>
22 #include <video/of_videomode.h>
23 #include <video/samsung_fimd.h>
24 #include <drm/exynos_drm.h>
26 #include "exynos_drm_drv.h"
27 #include "exynos_drm_fb.h"
28 #include "exynos_drm_crtc.h"
29 #include "exynos_drm_plane.h"
32 * FIMD stands for Fully Interactive Mobile Display and
33 * as a display controller, it transfers contents drawn on memory
34 * to a LCD Panel through Display Interfaces such as RGB or
38 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
40 /* position control register for hardware window 0, 2 ~ 4.*/
41 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
42 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
44 * size control register for hardware windows 0 and alpha control register
45 * for hardware windows 1 ~ 4
47 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
48 /* size control register for hardware windows 1 ~ 2. */
49 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
51 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
52 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
54 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
55 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
56 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
57 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
59 /* color key control register for hardware window 1 ~ 4. */
60 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
61 /* color key value register for hardware window 1 ~ 4. */
62 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
64 /* I80 trigger control register */
66 #define TRGMODE_ENABLE (1 << 0)
67 #define SWTRGCMD_ENABLE (1 << 1)
68 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
69 #define HWTRGEN_ENABLE (1 << 3)
70 #define HWTRGMASK_ENABLE (1 << 4)
71 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
72 #define HWTRIGEN_PER_ENABLE (1 << 31)
74 /* display mode change control register except exynos4 */
75 #define VIDOUT_CON 0x000
76 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
78 /* I80 interface control for main LDI register */
79 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
80 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
81 #define LCD_CS_SETUP(x) ((x) << 16)
82 #define LCD_WR_SETUP(x) ((x) << 12)
83 #define LCD_WR_ACTIVE(x) ((x) << 8)
84 #define LCD_WR_HOLD(x) ((x) << 4)
85 #define I80IFEN_ENABLE (1 << 0)
87 /* FIMD has totally five hardware windows. */
90 /* HW trigger flag on i80 panel. */
91 #define I80_HW_TRG (1 << 1)
93 struct fimd_driver_data
{
94 unsigned int timing_base
;
95 unsigned int lcdblk_offset
;
96 unsigned int lcdblk_vt_shift
;
97 unsigned int lcdblk_bypass_shift
;
98 unsigned int lcdblk_mic_bypass_shift
;
99 unsigned int trg_type
;
101 unsigned int has_shadowcon
:1;
102 unsigned int has_clksel
:1;
103 unsigned int has_limited_fmt
:1;
104 unsigned int has_vidoutcon
:1;
105 unsigned int has_vtsel
:1;
106 unsigned int has_mic_bypass
:1;
107 unsigned int has_dp_clk
:1;
108 unsigned int has_hw_trigger
:1;
109 unsigned int has_trigger_per_te
:1;
112 static struct fimd_driver_data s3c64xx_fimd_driver_data
= {
115 .has_limited_fmt
= 1,
118 static struct fimd_driver_data s5pv210_fimd_driver_data
= {
124 static struct fimd_driver_data exynos3_fimd_driver_data
= {
125 .timing_base
= 0x20000,
126 .lcdblk_offset
= 0x210,
127 .lcdblk_bypass_shift
= 1,
132 static struct fimd_driver_data exynos4_fimd_driver_data
= {
134 .lcdblk_offset
= 0x210,
135 .lcdblk_vt_shift
= 10,
136 .lcdblk_bypass_shift
= 1,
141 static struct fimd_driver_data exynos5_fimd_driver_data
= {
142 .timing_base
= 0x20000,
143 .lcdblk_offset
= 0x214,
144 .lcdblk_vt_shift
= 24,
145 .lcdblk_bypass_shift
= 15,
152 static struct fimd_driver_data exynos5420_fimd_driver_data
= {
153 .timing_base
= 0x20000,
154 .lcdblk_offset
= 0x214,
155 .lcdblk_vt_shift
= 24,
156 .lcdblk_bypass_shift
= 15,
157 .lcdblk_mic_bypass_shift
= 11,
165 struct fimd_context
{
167 struct drm_device
*drm_dev
;
168 struct exynos_drm_crtc
*crtc
;
169 struct exynos_drm_plane planes
[WINDOWS_NR
];
170 struct exynos_drm_plane_config configs
[WINDOWS_NR
];
174 struct regmap
*sysreg
;
175 unsigned long irq_flags
;
182 wait_queue_head_t wait_vsync_queue
;
183 atomic_t wait_vsync_event
;
184 atomic_t win_updated
;
188 const struct fimd_driver_data
*driver_data
;
189 struct drm_encoder
*encoder
;
190 struct exynos_drm_clk dp_clk
;
193 static const struct of_device_id fimd_driver_dt_match
[] = {
194 { .compatible
= "samsung,s3c6400-fimd",
195 .data
= &s3c64xx_fimd_driver_data
},
196 { .compatible
= "samsung,s5pv210-fimd",
197 .data
= &s5pv210_fimd_driver_data
},
198 { .compatible
= "samsung,exynos3250-fimd",
199 .data
= &exynos3_fimd_driver_data
},
200 { .compatible
= "samsung,exynos4210-fimd",
201 .data
= &exynos4_fimd_driver_data
},
202 { .compatible
= "samsung,exynos5250-fimd",
203 .data
= &exynos5_fimd_driver_data
},
204 { .compatible
= "samsung,exynos5420-fimd",
205 .data
= &exynos5420_fimd_driver_data
},
208 MODULE_DEVICE_TABLE(of
, fimd_driver_dt_match
);
210 static const enum drm_plane_type fimd_win_types
[WINDOWS_NR
] = {
211 DRM_PLANE_TYPE_PRIMARY
,
212 DRM_PLANE_TYPE_OVERLAY
,
213 DRM_PLANE_TYPE_OVERLAY
,
214 DRM_PLANE_TYPE_OVERLAY
,
215 DRM_PLANE_TYPE_CURSOR
,
218 static const uint32_t fimd_formats
[] = {
226 static const unsigned int capabilities
[WINDOWS_NR
] = {
228 EXYNOS_DRM_PLANE_CAP_WIN_BLEND
| EXYNOS_DRM_PLANE_CAP_PIX_BLEND
,
229 EXYNOS_DRM_PLANE_CAP_WIN_BLEND
| EXYNOS_DRM_PLANE_CAP_PIX_BLEND
,
230 EXYNOS_DRM_PLANE_CAP_WIN_BLEND
| EXYNOS_DRM_PLANE_CAP_PIX_BLEND
,
231 EXYNOS_DRM_PLANE_CAP_WIN_BLEND
| EXYNOS_DRM_PLANE_CAP_PIX_BLEND
,
234 static inline void fimd_set_bits(struct fimd_context
*ctx
, u32 reg
, u32 mask
,
237 val
= (val
& mask
) | (readl(ctx
->regs
+ reg
) & ~mask
);
238 writel(val
, ctx
->regs
+ reg
);
241 static int fimd_enable_vblank(struct exynos_drm_crtc
*crtc
)
243 struct fimd_context
*ctx
= crtc
->ctx
;
249 if (!test_and_set_bit(0, &ctx
->irq_flags
)) {
250 val
= readl(ctx
->regs
+ VIDINTCON0
);
252 val
|= VIDINTCON0_INT_ENABLE
;
255 val
|= VIDINTCON0_INT_I80IFDONE
;
256 val
|= VIDINTCON0_INT_SYSMAINCON
;
257 val
&= ~VIDINTCON0_INT_SYSSUBCON
;
259 val
|= VIDINTCON0_INT_FRAME
;
261 val
&= ~VIDINTCON0_FRAMESEL0_MASK
;
262 val
|= VIDINTCON0_FRAMESEL0_FRONTPORCH
;
263 val
&= ~VIDINTCON0_FRAMESEL1_MASK
;
264 val
|= VIDINTCON0_FRAMESEL1_NONE
;
267 writel(val
, ctx
->regs
+ VIDINTCON0
);
273 static void fimd_disable_vblank(struct exynos_drm_crtc
*crtc
)
275 struct fimd_context
*ctx
= crtc
->ctx
;
281 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
282 val
= readl(ctx
->regs
+ VIDINTCON0
);
284 val
&= ~VIDINTCON0_INT_ENABLE
;
287 val
&= ~VIDINTCON0_INT_I80IFDONE
;
288 val
&= ~VIDINTCON0_INT_SYSMAINCON
;
289 val
&= ~VIDINTCON0_INT_SYSSUBCON
;
291 val
&= ~VIDINTCON0_INT_FRAME
;
293 writel(val
, ctx
->regs
+ VIDINTCON0
);
297 static void fimd_wait_for_vblank(struct exynos_drm_crtc
*crtc
)
299 struct fimd_context
*ctx
= crtc
->ctx
;
304 atomic_set(&ctx
->wait_vsync_event
, 1);
307 * wait for FIMD to signal VSYNC interrupt or return after
308 * timeout which is set to 50ms (refresh rate of 20).
310 if (!wait_event_timeout(ctx
->wait_vsync_queue
,
311 !atomic_read(&ctx
->wait_vsync_event
),
313 DRM_DEV_DEBUG_KMS(ctx
->dev
, "vblank wait timed out.\n");
316 static void fimd_enable_video_output(struct fimd_context
*ctx
, unsigned int win
,
319 u32 val
= readl(ctx
->regs
+ WINCON(win
));
322 val
|= WINCONx_ENWIN
;
324 val
&= ~WINCONx_ENWIN
;
326 writel(val
, ctx
->regs
+ WINCON(win
));
329 static void fimd_enable_shadow_channel_path(struct fimd_context
*ctx
,
333 u32 val
= readl(ctx
->regs
+ SHADOWCON
);
336 val
|= SHADOWCON_CHx_ENABLE(win
);
338 val
&= ~SHADOWCON_CHx_ENABLE(win
);
340 writel(val
, ctx
->regs
+ SHADOWCON
);
343 static void fimd_clear_channels(struct exynos_drm_crtc
*crtc
)
345 struct fimd_context
*ctx
= crtc
->ctx
;
346 unsigned int win
, ch_enabled
= 0;
348 /* Hardware is in unknown state, so ensure it gets enabled properly */
349 pm_runtime_get_sync(ctx
->dev
);
351 clk_prepare_enable(ctx
->bus_clk
);
352 clk_prepare_enable(ctx
->lcd_clk
);
354 /* Check if any channel is enabled. */
355 for (win
= 0; win
< WINDOWS_NR
; win
++) {
356 u32 val
= readl(ctx
->regs
+ WINCON(win
));
358 if (val
& WINCONx_ENWIN
) {
359 fimd_enable_video_output(ctx
, win
, false);
361 if (ctx
->driver_data
->has_shadowcon
)
362 fimd_enable_shadow_channel_path(ctx
, win
,
369 /* Wait for vsync, as disable channel takes effect at next vsync */
371 ctx
->suspended
= false;
373 fimd_enable_vblank(ctx
->crtc
);
374 fimd_wait_for_vblank(ctx
->crtc
);
375 fimd_disable_vblank(ctx
->crtc
);
377 ctx
->suspended
= true;
380 clk_disable_unprepare(ctx
->lcd_clk
);
381 clk_disable_unprepare(ctx
->bus_clk
);
383 pm_runtime_put(ctx
->dev
);
387 static int fimd_atomic_check(struct exynos_drm_crtc
*crtc
,
388 struct drm_crtc_state
*state
)
390 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
391 struct fimd_context
*ctx
= crtc
->ctx
;
392 unsigned long ideal_clk
, lcd_rate
;
395 if (mode
->clock
== 0) {
396 DRM_DEV_ERROR(ctx
->dev
, "Mode has zero clock value.\n");
400 ideal_clk
= mode
->clock
* 1000;
404 * The frame done interrupt should be occurred prior to the
410 lcd_rate
= clk_get_rate(ctx
->lcd_clk
);
411 if (2 * lcd_rate
< ideal_clk
) {
412 DRM_DEV_ERROR(ctx
->dev
,
413 "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
414 lcd_rate
, ideal_clk
);
418 /* Find the clock divider value that gets us closest to ideal_clk */
419 clkdiv
= DIV_ROUND_CLOSEST(lcd_rate
, ideal_clk
);
420 if (clkdiv
>= 0x200) {
421 DRM_DEV_ERROR(ctx
->dev
, "requested pixel clock(%lu) too low\n",
426 ctx
->clkdiv
= (clkdiv
< 0x100) ? clkdiv
: 0xff;
431 static void fimd_setup_trigger(struct fimd_context
*ctx
)
433 void __iomem
*timing_base
= ctx
->regs
+ ctx
->driver_data
->timing_base
;
434 u32 trg_type
= ctx
->driver_data
->trg_type
;
435 u32 val
= readl(timing_base
+ TRIGCON
);
437 val
&= ~(TRGMODE_ENABLE
);
439 if (trg_type
== I80_HW_TRG
) {
440 if (ctx
->driver_data
->has_hw_trigger
)
441 val
|= HWTRGEN_ENABLE
| HWTRGMASK_ENABLE
;
442 if (ctx
->driver_data
->has_trigger_per_te
)
443 val
|= HWTRIGEN_PER_ENABLE
;
445 val
|= TRGMODE_ENABLE
;
448 writel(val
, timing_base
+ TRIGCON
);
451 static void fimd_commit(struct exynos_drm_crtc
*crtc
)
453 struct fimd_context
*ctx
= crtc
->ctx
;
454 struct drm_display_mode
*mode
= &crtc
->base
.state
->adjusted_mode
;
455 const struct fimd_driver_data
*driver_data
= ctx
->driver_data
;
456 void *timing_base
= ctx
->regs
+ driver_data
->timing_base
;
462 /* nothing to do if we haven't set the mode yet */
463 if (mode
->htotal
== 0 || mode
->vtotal
== 0)
467 val
= ctx
->i80ifcon
| I80IFEN_ENABLE
;
468 writel(val
, timing_base
+ I80IFCONFAx(0));
470 /* disable auto frame rate */
471 writel(0, timing_base
+ I80IFCONFBx(0));
473 /* set video type selection to I80 interface */
474 if (driver_data
->has_vtsel
&& ctx
->sysreg
&&
475 regmap_update_bits(ctx
->sysreg
,
476 driver_data
->lcdblk_offset
,
477 0x3 << driver_data
->lcdblk_vt_shift
,
478 0x1 << driver_data
->lcdblk_vt_shift
)) {
479 DRM_DEV_ERROR(ctx
->dev
,
480 "Failed to update sysreg for I80 i/f.\n");
484 int vsync_len
, vbpd
, vfpd
, hsync_len
, hbpd
, hfpd
;
487 /* setup polarity values */
488 vidcon1
= ctx
->vidcon1
;
489 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
490 vidcon1
|= VIDCON1_INV_VSYNC
;
491 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
492 vidcon1
|= VIDCON1_INV_HSYNC
;
493 writel(vidcon1
, ctx
->regs
+ driver_data
->timing_base
+ VIDCON1
);
495 /* setup vertical timing values. */
496 vsync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
497 vbpd
= mode
->crtc_vtotal
- mode
->crtc_vsync_end
;
498 vfpd
= mode
->crtc_vsync_start
- mode
->crtc_vdisplay
;
500 val
= VIDTCON0_VBPD(vbpd
- 1) |
501 VIDTCON0_VFPD(vfpd
- 1) |
502 VIDTCON0_VSPW(vsync_len
- 1);
503 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON0
);
505 /* setup horizontal timing values. */
506 hsync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
507 hbpd
= mode
->crtc_htotal
- mode
->crtc_hsync_end
;
508 hfpd
= mode
->crtc_hsync_start
- mode
->crtc_hdisplay
;
510 val
= VIDTCON1_HBPD(hbpd
- 1) |
511 VIDTCON1_HFPD(hfpd
- 1) |
512 VIDTCON1_HSPW(hsync_len
- 1);
513 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON1
);
516 if (driver_data
->has_vidoutcon
)
517 writel(ctx
->vidout_con
, timing_base
+ VIDOUT_CON
);
519 /* set bypass selection */
520 if (ctx
->sysreg
&& regmap_update_bits(ctx
->sysreg
,
521 driver_data
->lcdblk_offset
,
522 0x1 << driver_data
->lcdblk_bypass_shift
,
523 0x1 << driver_data
->lcdblk_bypass_shift
)) {
524 DRM_DEV_ERROR(ctx
->dev
,
525 "Failed to update sysreg for bypass setting.\n");
529 /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
530 * bit should be cleared.
532 if (driver_data
->has_mic_bypass
&& ctx
->sysreg
&&
533 regmap_update_bits(ctx
->sysreg
,
534 driver_data
->lcdblk_offset
,
535 0x1 << driver_data
->lcdblk_mic_bypass_shift
,
536 0x1 << driver_data
->lcdblk_mic_bypass_shift
)) {
537 DRM_DEV_ERROR(ctx
->dev
,
538 "Failed to update sysreg for bypass mic.\n");
542 /* setup horizontal and vertical display size. */
543 val
= VIDTCON2_LINEVAL(mode
->vdisplay
- 1) |
544 VIDTCON2_HOZVAL(mode
->hdisplay
- 1) |
545 VIDTCON2_LINEVAL_E(mode
->vdisplay
- 1) |
546 VIDTCON2_HOZVAL_E(mode
->hdisplay
- 1);
547 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON2
);
549 fimd_setup_trigger(ctx
);
552 * fields of register with prefix '_F' would be updated
553 * at vsync(same as dma start)
556 val
|= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
558 if (ctx
->driver_data
->has_clksel
)
559 val
|= VIDCON0_CLKSEL_LCD
;
562 val
|= VIDCON0_CLKVAL_F(ctx
->clkdiv
- 1) | VIDCON0_CLKDIR
;
564 writel(val
, ctx
->regs
+ VIDCON0
);
567 static void fimd_win_set_bldeq(struct fimd_context
*ctx
, unsigned int win
,
568 unsigned int alpha
, unsigned int pixel_alpha
)
570 u32 mask
= BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
573 switch (pixel_alpha
) {
574 case DRM_MODE_BLEND_PIXEL_NONE
:
575 case DRM_MODE_BLEND_COVERAGE
:
576 val
|= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A
);
577 val
|= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A
);
579 case DRM_MODE_BLEND_PREMULTI
:
581 if (alpha
!= DRM_BLEND_ALPHA_OPAQUE
) {
582 val
|= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0
);
583 val
|= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A
);
585 val
|= BLENDEQ_A_FUNC_F(BLENDEQ_ONE
);
586 val
|= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A
);
590 fimd_set_bits(ctx
, BLENDEQx(win
), mask
, val
);
593 static void fimd_win_set_bldmod(struct fimd_context
*ctx
, unsigned int win
,
594 unsigned int alpha
, unsigned int pixel_alpha
)
596 u32 win_alpha_l
= (alpha
>> 8) & 0xf;
597 u32 win_alpha_h
= alpha
>> 12;
600 switch (pixel_alpha
) {
601 case DRM_MODE_BLEND_PIXEL_NONE
:
603 case DRM_MODE_BLEND_COVERAGE
:
604 case DRM_MODE_BLEND_PREMULTI
:
606 val
|= WINCON1_ALPHA_SEL
;
607 val
|= WINCON1_BLD_PIX
;
608 val
|= WINCON1_ALPHA_MUL
;
611 fimd_set_bits(ctx
, WINCON(win
), WINCONx_BLEND_MODE_MASK
, val
);
614 val
= VIDISD14C_ALPHA0_R(win_alpha_h
) |
615 VIDISD14C_ALPHA0_G(win_alpha_h
) |
616 VIDISD14C_ALPHA0_B(win_alpha_h
) |
617 VIDISD14C_ALPHA1_R(0x0) |
618 VIDISD14C_ALPHA1_G(0x0) |
619 VIDISD14C_ALPHA1_B(0x0);
620 writel(val
, ctx
->regs
+ VIDOSD_C(win
));
622 val
= VIDW_ALPHA_R(win_alpha_l
) | VIDW_ALPHA_G(win_alpha_l
) |
623 VIDW_ALPHA_B(win_alpha_l
);
624 writel(val
, ctx
->regs
+ VIDWnALPHA0(win
));
626 val
= VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
628 writel(val
, ctx
->regs
+ VIDWnALPHA1(win
));
630 fimd_set_bits(ctx
, BLENDCON
, BLENDCON_NEW_MASK
,
631 BLENDCON_NEW_8BIT_ALPHA_VALUE
);
634 static void fimd_win_set_pixfmt(struct fimd_context
*ctx
, unsigned int win
,
635 struct drm_framebuffer
*fb
, int width
)
637 struct exynos_drm_plane plane
= ctx
->planes
[win
];
638 struct exynos_drm_plane_state
*state
=
639 to_exynos_plane_state(plane
.base
.state
);
640 uint32_t pixel_format
= fb
->format
->format
;
641 unsigned int alpha
= state
->base
.alpha
;
642 u32 val
= WINCONx_ENWIN
;
643 unsigned int pixel_alpha
;
645 if (fb
->format
->has_alpha
)
646 pixel_alpha
= state
->base
.pixel_blend_mode
;
648 pixel_alpha
= DRM_MODE_BLEND_PIXEL_NONE
;
651 * In case of s3c64xx, window 0 doesn't support alpha channel.
652 * So the request format is ARGB8888 then change it to XRGB8888.
654 if (ctx
->driver_data
->has_limited_fmt
&& !win
) {
655 if (pixel_format
== DRM_FORMAT_ARGB8888
)
656 pixel_format
= DRM_FORMAT_XRGB8888
;
659 switch (pixel_format
) {
661 val
|= WINCON0_BPPMODE_8BPP_PALETTE
;
662 val
|= WINCONx_BURSTLEN_8WORD
;
663 val
|= WINCONx_BYTSWP
;
665 case DRM_FORMAT_XRGB1555
:
666 val
|= WINCON0_BPPMODE_16BPP_1555
;
667 val
|= WINCONx_HAWSWP
;
668 val
|= WINCONx_BURSTLEN_16WORD
;
670 case DRM_FORMAT_RGB565
:
671 val
|= WINCON0_BPPMODE_16BPP_565
;
672 val
|= WINCONx_HAWSWP
;
673 val
|= WINCONx_BURSTLEN_16WORD
;
675 case DRM_FORMAT_XRGB8888
:
676 val
|= WINCON0_BPPMODE_24BPP_888
;
678 val
|= WINCONx_BURSTLEN_16WORD
;
680 case DRM_FORMAT_ARGB8888
:
682 val
|= WINCON1_BPPMODE_25BPP_A1888
;
684 val
|= WINCONx_BURSTLEN_16WORD
;
689 * Setting dma-burst to 16Word causes permanent tearing for very small
690 * buffers, e.g. cursor buffer. Burst Mode switching which based on
691 * plane size is not recommended as plane size varies alot towards the
692 * end of the screen and rapid movement causes unstable DMA, but it is
693 * still better to change dma-burst than displaying garbage.
696 if (width
< MIN_FB_WIDTH_FOR_16WORD_BURST
) {
697 val
&= ~WINCONx_BURSTLEN_MASK
;
698 val
|= WINCONx_BURSTLEN_4WORD
;
700 fimd_set_bits(ctx
, WINCON(win
), ~WINCONx_BLEND_MODE_MASK
, val
);
702 /* hardware window 0 doesn't support alpha channel. */
704 fimd_win_set_bldmod(ctx
, win
, alpha
, pixel_alpha
);
705 fimd_win_set_bldeq(ctx
, win
, alpha
, pixel_alpha
);
709 static void fimd_win_set_colkey(struct fimd_context
*ctx
, unsigned int win
)
711 unsigned int keycon0
= 0, keycon1
= 0;
713 keycon0
= ~(WxKEYCON0_KEYBL_EN
| WxKEYCON0_KEYEN_F
|
714 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
716 keycon1
= WxKEYCON1_COLVAL(0xffffffff);
718 writel(keycon0
, ctx
->regs
+ WKEYCON0_BASE(win
));
719 writel(keycon1
, ctx
->regs
+ WKEYCON1_BASE(win
));
723 * shadow_protect_win() - disable updating values from shadow registers at vsync
725 * @win: window to protect registers for
726 * @protect: 1 to protect (disable updates)
728 static void fimd_shadow_protect_win(struct fimd_context
*ctx
,
729 unsigned int win
, bool protect
)
734 * SHADOWCON/PRTCON register is used for enabling timing.
736 * for example, once only width value of a register is set,
737 * if the dma is started then fimd hardware could malfunction so
738 * with protect window setting, the register fields with prefix '_F'
739 * wouldn't be updated at vsync also but updated once unprotect window
743 if (ctx
->driver_data
->has_shadowcon
) {
745 bits
= SHADOWCON_WINx_PROTECT(win
);
748 bits
= PRTCON_PROTECT
;
751 val
= readl(ctx
->regs
+ reg
);
756 writel(val
, ctx
->regs
+ reg
);
759 static void fimd_atomic_begin(struct exynos_drm_crtc
*crtc
)
761 struct fimd_context
*ctx
= crtc
->ctx
;
767 for (i
= 0; i
< WINDOWS_NR
; i
++)
768 fimd_shadow_protect_win(ctx
, i
, true);
771 static void fimd_atomic_flush(struct exynos_drm_crtc
*crtc
)
773 struct fimd_context
*ctx
= crtc
->ctx
;
779 for (i
= 0; i
< WINDOWS_NR
; i
++)
780 fimd_shadow_protect_win(ctx
, i
, false);
782 exynos_crtc_handle_event(crtc
);
785 static void fimd_update_plane(struct exynos_drm_crtc
*crtc
,
786 struct exynos_drm_plane
*plane
)
788 struct exynos_drm_plane_state
*state
=
789 to_exynos_plane_state(plane
->base
.state
);
790 struct fimd_context
*ctx
= crtc
->ctx
;
791 struct drm_framebuffer
*fb
= state
->base
.fb
;
793 unsigned long val
, size
, offset
;
794 unsigned int last_x
, last_y
, buf_offsize
, line_size
;
795 unsigned int win
= plane
->index
;
796 unsigned int cpp
= fb
->format
->cpp
[0];
797 unsigned int pitch
= fb
->pitches
[0];
802 offset
= state
->src
.x
* cpp
;
803 offset
+= state
->src
.y
* pitch
;
805 /* buffer start address */
806 dma_addr
= exynos_drm_fb_dma_addr(fb
, 0) + offset
;
807 val
= (unsigned long)dma_addr
;
808 writel(val
, ctx
->regs
+ VIDWx_BUF_START(win
, 0));
810 /* buffer end address */
811 size
= pitch
* state
->crtc
.h
;
812 val
= (unsigned long)(dma_addr
+ size
);
813 writel(val
, ctx
->regs
+ VIDWx_BUF_END(win
, 0));
815 DRM_DEV_DEBUG_KMS(ctx
->dev
,
816 "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
817 (unsigned long)dma_addr
, val
, size
);
818 DRM_DEV_DEBUG_KMS(ctx
->dev
, "ovl_width = %d, ovl_height = %d\n",
819 state
->crtc
.w
, state
->crtc
.h
);
822 buf_offsize
= pitch
- (state
->crtc
.w
* cpp
);
823 line_size
= state
->crtc
.w
* cpp
;
824 val
= VIDW_BUF_SIZE_OFFSET(buf_offsize
) |
825 VIDW_BUF_SIZE_PAGEWIDTH(line_size
) |
826 VIDW_BUF_SIZE_OFFSET_E(buf_offsize
) |
827 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size
);
828 writel(val
, ctx
->regs
+ VIDWx_BUF_SIZE(win
, 0));
831 val
= VIDOSDxA_TOPLEFT_X(state
->crtc
.x
) |
832 VIDOSDxA_TOPLEFT_Y(state
->crtc
.y
) |
833 VIDOSDxA_TOPLEFT_X_E(state
->crtc
.x
) |
834 VIDOSDxA_TOPLEFT_Y_E(state
->crtc
.y
);
835 writel(val
, ctx
->regs
+ VIDOSD_A(win
));
837 last_x
= state
->crtc
.x
+ state
->crtc
.w
;
840 last_y
= state
->crtc
.y
+ state
->crtc
.h
;
844 val
= VIDOSDxB_BOTRIGHT_X(last_x
) | VIDOSDxB_BOTRIGHT_Y(last_y
) |
845 VIDOSDxB_BOTRIGHT_X_E(last_x
) | VIDOSDxB_BOTRIGHT_Y_E(last_y
);
847 writel(val
, ctx
->regs
+ VIDOSD_B(win
));
849 DRM_DEV_DEBUG_KMS(ctx
->dev
,
850 "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
851 state
->crtc
.x
, state
->crtc
.y
, last_x
, last_y
);
854 if (win
!= 3 && win
!= 4) {
855 u32 offset
= VIDOSD_D(win
);
857 offset
= VIDOSD_C(win
);
858 val
= state
->crtc
.w
* state
->crtc
.h
;
859 writel(val
, ctx
->regs
+ offset
);
861 DRM_DEV_DEBUG_KMS(ctx
->dev
, "osd size = 0x%x\n",
865 fimd_win_set_pixfmt(ctx
, win
, fb
, state
->src
.w
);
867 /* hardware window 0 doesn't support color key. */
869 fimd_win_set_colkey(ctx
, win
);
871 fimd_enable_video_output(ctx
, win
, true);
873 if (ctx
->driver_data
->has_shadowcon
)
874 fimd_enable_shadow_channel_path(ctx
, win
, true);
877 atomic_set(&ctx
->win_updated
, 1);
880 static void fimd_disable_plane(struct exynos_drm_crtc
*crtc
,
881 struct exynos_drm_plane
*plane
)
883 struct fimd_context
*ctx
= crtc
->ctx
;
884 unsigned int win
= plane
->index
;
889 fimd_enable_video_output(ctx
, win
, false);
891 if (ctx
->driver_data
->has_shadowcon
)
892 fimd_enable_shadow_channel_path(ctx
, win
, false);
895 static void fimd_enable(struct exynos_drm_crtc
*crtc
)
897 struct fimd_context
*ctx
= crtc
->ctx
;
902 ctx
->suspended
= false;
904 pm_runtime_get_sync(ctx
->dev
);
906 /* if vblank was enabled status, enable it again. */
907 if (test_and_clear_bit(0, &ctx
->irq_flags
))
908 fimd_enable_vblank(ctx
->crtc
);
910 fimd_commit(ctx
->crtc
);
913 static void fimd_disable(struct exynos_drm_crtc
*crtc
)
915 struct fimd_context
*ctx
= crtc
->ctx
;
922 * We need to make sure that all windows are disabled before we
923 * suspend that connector. Otherwise we might try to scan from
924 * a destroyed buffer later.
926 for (i
= 0; i
< WINDOWS_NR
; i
++)
927 fimd_disable_plane(crtc
, &ctx
->planes
[i
]);
929 fimd_enable_vblank(crtc
);
930 fimd_wait_for_vblank(crtc
);
931 fimd_disable_vblank(crtc
);
933 writel(0, ctx
->regs
+ VIDCON0
);
935 pm_runtime_put_sync(ctx
->dev
);
936 ctx
->suspended
= true;
939 static void fimd_trigger(struct device
*dev
)
941 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
942 const struct fimd_driver_data
*driver_data
= ctx
->driver_data
;
943 void *timing_base
= ctx
->regs
+ driver_data
->timing_base
;
947 * Skips triggering if in triggering state, because multiple triggering
948 * requests can cause panel reset.
950 if (atomic_read(&ctx
->triggering
))
953 /* Enters triggering mode */
954 atomic_set(&ctx
->triggering
, 1);
956 reg
= readl(timing_base
+ TRIGCON
);
957 reg
|= (TRGMODE_ENABLE
| SWTRGCMD_ENABLE
);
958 writel(reg
, timing_base
+ TRIGCON
);
961 * Exits triggering mode if vblank is not enabled yet, because when the
962 * VIDINTCON0 register is not set, it can not exit from triggering mode.
964 if (!test_bit(0, &ctx
->irq_flags
))
965 atomic_set(&ctx
->triggering
, 0);
968 static void fimd_te_handler(struct exynos_drm_crtc
*crtc
)
970 struct fimd_context
*ctx
= crtc
->ctx
;
971 u32 trg_type
= ctx
->driver_data
->trg_type
;
973 /* Checks the crtc is detached already from encoder */
977 if (trg_type
== I80_HW_TRG
)
981 * If there is a page flip request, triggers and handles the page flip
982 * event so that current fb can be updated into panel GRAM.
984 if (atomic_add_unless(&ctx
->win_updated
, -1, 0))
985 fimd_trigger(ctx
->dev
);
988 /* Wakes up vsync event queue */
989 if (atomic_read(&ctx
->wait_vsync_event
)) {
990 atomic_set(&ctx
->wait_vsync_event
, 0);
991 wake_up(&ctx
->wait_vsync_queue
);
994 if (test_bit(0, &ctx
->irq_flags
))
995 drm_crtc_handle_vblank(&ctx
->crtc
->base
);
998 static void fimd_dp_clock_enable(struct exynos_drm_clk
*clk
, bool enable
)
1000 struct fimd_context
*ctx
= container_of(clk
, struct fimd_context
,
1002 u32 val
= enable
? DP_MIE_CLK_DP_ENABLE
: DP_MIE_CLK_DISABLE
;
1003 writel(val
, ctx
->regs
+ DP_MIE_CLKCON
);
1006 static const struct exynos_drm_crtc_ops fimd_crtc_ops
= {
1007 .enable
= fimd_enable
,
1008 .disable
= fimd_disable
,
1009 .enable_vblank
= fimd_enable_vblank
,
1010 .disable_vblank
= fimd_disable_vblank
,
1011 .atomic_begin
= fimd_atomic_begin
,
1012 .update_plane
= fimd_update_plane
,
1013 .disable_plane
= fimd_disable_plane
,
1014 .atomic_flush
= fimd_atomic_flush
,
1015 .atomic_check
= fimd_atomic_check
,
1016 .te_handler
= fimd_te_handler
,
1019 static irqreturn_t
fimd_irq_handler(int irq
, void *dev_id
)
1021 struct fimd_context
*ctx
= (struct fimd_context
*)dev_id
;
1024 val
= readl(ctx
->regs
+ VIDINTCON1
);
1026 clear_bit
= ctx
->i80_if
? VIDINTCON1_INT_I80
: VIDINTCON1_INT_FRAME
;
1027 if (val
& clear_bit
)
1028 writel(clear_bit
, ctx
->regs
+ VIDINTCON1
);
1030 /* check the crtc is detached already from encoder */
1035 drm_crtc_handle_vblank(&ctx
->crtc
->base
);
1038 /* Exits triggering mode */
1039 atomic_set(&ctx
->triggering
, 0);
1041 /* set wait vsync event to zero and wake up queue. */
1042 if (atomic_read(&ctx
->wait_vsync_event
)) {
1043 atomic_set(&ctx
->wait_vsync_event
, 0);
1044 wake_up(&ctx
->wait_vsync_queue
);
1052 static int fimd_bind(struct device
*dev
, struct device
*master
, void *data
)
1054 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1055 struct drm_device
*drm_dev
= data
;
1056 struct exynos_drm_plane
*exynos_plane
;
1060 ctx
->drm_dev
= drm_dev
;
1062 for (i
= 0; i
< WINDOWS_NR
; i
++) {
1063 ctx
->configs
[i
].pixel_formats
= fimd_formats
;
1064 ctx
->configs
[i
].num_pixel_formats
= ARRAY_SIZE(fimd_formats
);
1065 ctx
->configs
[i
].zpos
= i
;
1066 ctx
->configs
[i
].type
= fimd_win_types
[i
];
1067 ctx
->configs
[i
].capabilities
= capabilities
[i
];
1068 ret
= exynos_plane_init(drm_dev
, &ctx
->planes
[i
], i
,
1074 exynos_plane
= &ctx
->planes
[DEFAULT_WIN
];
1075 ctx
->crtc
= exynos_drm_crtc_create(drm_dev
, &exynos_plane
->base
,
1076 EXYNOS_DISPLAY_TYPE_LCD
, &fimd_crtc_ops
, ctx
);
1077 if (IS_ERR(ctx
->crtc
))
1078 return PTR_ERR(ctx
->crtc
);
1080 if (ctx
->driver_data
->has_dp_clk
) {
1081 ctx
->dp_clk
.enable
= fimd_dp_clock_enable
;
1082 ctx
->crtc
->pipe_clk
= &ctx
->dp_clk
;
1086 exynos_dpi_bind(drm_dev
, ctx
->encoder
);
1088 if (is_drm_iommu_supported(drm_dev
))
1089 fimd_clear_channels(ctx
->crtc
);
1091 return exynos_drm_register_dma(drm_dev
, dev
);
1094 static void fimd_unbind(struct device
*dev
, struct device
*master
,
1097 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1099 fimd_disable(ctx
->crtc
);
1101 exynos_drm_unregister_dma(ctx
->drm_dev
, ctx
->dev
);
1104 exynos_dpi_remove(ctx
->encoder
);
1107 static const struct component_ops fimd_component_ops
= {
1109 .unbind
= fimd_unbind
,
1112 static int fimd_probe(struct platform_device
*pdev
)
1114 struct device
*dev
= &pdev
->dev
;
1115 struct fimd_context
*ctx
;
1116 struct device_node
*i80_if_timings
;
1117 struct resource
*res
;
1123 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
1128 ctx
->suspended
= true;
1129 ctx
->driver_data
= of_device_get_match_data(dev
);
1131 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vden"))
1132 ctx
->vidcon1
|= VIDCON1_INV_VDEN
;
1133 if (of_property_read_bool(dev
->of_node
, "samsung,invert-vclk"))
1134 ctx
->vidcon1
|= VIDCON1_INV_VCLK
;
1136 i80_if_timings
= of_get_child_by_name(dev
->of_node
, "i80-if-timings");
1137 if (i80_if_timings
) {
1142 if (ctx
->driver_data
->has_vidoutcon
)
1143 ctx
->vidout_con
|= VIDOUT_CON_F_I80_LDI0
;
1145 ctx
->vidcon0
|= VIDCON0_VIDOUT_I80_LDI0
;
1147 * The user manual describes that this "DSI_EN" bit is required
1148 * to enable I80 24-bit data interface.
1150 ctx
->vidcon0
|= VIDCON0_DSI_EN
;
1152 if (of_property_read_u32(i80_if_timings
, "cs-setup", &val
))
1154 ctx
->i80ifcon
= LCD_CS_SETUP(val
);
1155 if (of_property_read_u32(i80_if_timings
, "wr-setup", &val
))
1157 ctx
->i80ifcon
|= LCD_WR_SETUP(val
);
1158 if (of_property_read_u32(i80_if_timings
, "wr-active", &val
))
1160 ctx
->i80ifcon
|= LCD_WR_ACTIVE(val
);
1161 if (of_property_read_u32(i80_if_timings
, "wr-hold", &val
))
1163 ctx
->i80ifcon
|= LCD_WR_HOLD(val
);
1165 of_node_put(i80_if_timings
);
1167 ctx
->sysreg
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
1169 if (IS_ERR(ctx
->sysreg
)) {
1170 dev_warn(dev
, "failed to get system register.\n");
1174 ctx
->bus_clk
= devm_clk_get(dev
, "fimd");
1175 if (IS_ERR(ctx
->bus_clk
)) {
1176 dev_err(dev
, "failed to get bus clock\n");
1177 return PTR_ERR(ctx
->bus_clk
);
1180 ctx
->lcd_clk
= devm_clk_get(dev
, "sclk_fimd");
1181 if (IS_ERR(ctx
->lcd_clk
)) {
1182 dev_err(dev
, "failed to get lcd clock\n");
1183 return PTR_ERR(ctx
->lcd_clk
);
1186 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1188 ctx
->regs
= devm_ioremap_resource(dev
, res
);
1189 if (IS_ERR(ctx
->regs
))
1190 return PTR_ERR(ctx
->regs
);
1192 res
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
,
1193 ctx
->i80_if
? "lcd_sys" : "vsync");
1195 dev_err(dev
, "irq request failed.\n");
1199 ret
= devm_request_irq(dev
, res
->start
, fimd_irq_handler
,
1200 0, "drm_fimd", ctx
);
1202 dev_err(dev
, "irq request failed.\n");
1206 init_waitqueue_head(&ctx
->wait_vsync_queue
);
1207 atomic_set(&ctx
->wait_vsync_event
, 0);
1209 platform_set_drvdata(pdev
, ctx
);
1211 ctx
->encoder
= exynos_dpi_probe(dev
);
1212 if (IS_ERR(ctx
->encoder
))
1213 return PTR_ERR(ctx
->encoder
);
1215 pm_runtime_enable(dev
);
1217 ret
= component_add(dev
, &fimd_component_ops
);
1219 goto err_disable_pm_runtime
;
1223 err_disable_pm_runtime
:
1224 pm_runtime_disable(dev
);
1229 static int fimd_remove(struct platform_device
*pdev
)
1231 pm_runtime_disable(&pdev
->dev
);
1233 component_del(&pdev
->dev
, &fimd_component_ops
);
1239 static int exynos_fimd_suspend(struct device
*dev
)
1241 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1243 clk_disable_unprepare(ctx
->lcd_clk
);
1244 clk_disable_unprepare(ctx
->bus_clk
);
1249 static int exynos_fimd_resume(struct device
*dev
)
1251 struct fimd_context
*ctx
= dev_get_drvdata(dev
);
1254 ret
= clk_prepare_enable(ctx
->bus_clk
);
1257 "Failed to prepare_enable the bus clk [%d]\n",
1262 ret
= clk_prepare_enable(ctx
->lcd_clk
);
1265 "Failed to prepare_enable the lcd clk [%d]\n",
1274 static const struct dev_pm_ops exynos_fimd_pm_ops
= {
1275 SET_RUNTIME_PM_OPS(exynos_fimd_suspend
, exynos_fimd_resume
, NULL
)
1276 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
1277 pm_runtime_force_resume
)
1280 struct platform_driver fimd_driver
= {
1281 .probe
= fimd_probe
,
1282 .remove
= fimd_remove
,
1284 .name
= "exynos4-fb",
1285 .owner
= THIS_MODULE
,
1286 .pm
= &exynos_fimd_pm_ops
,
1287 .of_match_table
= fimd_driver_dt_match
,