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[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / exynos / exynos_drm_gsc.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2012 Samsung Electronics Co.Ltd
4 * Authors:
5 * Eunchul Kim <chulspro.kim@samsung.com>
6 * Jinyoung Jeon <jy0.jeon@samsung.com>
7 * Sangmin Lee <lsmin.lee@samsung.com>
8 */
9 #include <linux/kernel.h>
10 #include <linux/component.h>
11 #include <linux/platform_device.h>
12 #include <linux/clk.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of_device.h>
16 #include <linux/regmap.h>
17
18 #include <drm/drmP.h>
19 #include <drm/exynos_drm.h>
20 #include "regs-gsc.h"
21 #include "exynos_drm_drv.h"
22 #include "exynos_drm_ipp.h"
23
24 /*
25 * GSC stands for General SCaler and
26 * supports image scaler/rotator and input/output DMA operations.
27 * input DMA reads image data from the memory.
28 * output DMA writes image data to memory.
29 * GSC supports image rotation and image effect functions.
30 */
31
32
33 #define GSC_MAX_CLOCKS 8
34 #define GSC_MAX_SRC 4
35 #define GSC_MAX_DST 16
36 #define GSC_RESET_TIMEOUT 50
37 #define GSC_BUF_STOP 1
38 #define GSC_BUF_START 2
39 #define GSC_REG_SZ 16
40 #define GSC_WIDTH_ITU_709 1280
41 #define GSC_SC_UP_MAX_RATIO 65536
42 #define GSC_SC_DOWN_RATIO_7_8 74898
43 #define GSC_SC_DOWN_RATIO_6_8 87381
44 #define GSC_SC_DOWN_RATIO_5_8 104857
45 #define GSC_SC_DOWN_RATIO_4_8 131072
46 #define GSC_SC_DOWN_RATIO_3_8 174762
47 #define GSC_SC_DOWN_RATIO_2_8 262144
48 #define GSC_CROP_MAX 8192
49 #define GSC_CROP_MIN 32
50 #define GSC_SCALE_MAX 4224
51 #define GSC_SCALE_MIN 32
52 #define GSC_COEF_RATIO 7
53 #define GSC_COEF_PHASE 9
54 #define GSC_COEF_ATTR 16
55 #define GSC_COEF_H_8T 8
56 #define GSC_COEF_V_4T 4
57 #define GSC_COEF_DEPTH 3
58 #define GSC_AUTOSUSPEND_DELAY 2000
59
60 #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev))
61 #define gsc_read(offset) readl(ctx->regs + (offset))
62 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
63
64 /*
65 * A structure of scaler.
66 *
67 * @range: narrow, wide.
68 * @pre_shfactor: pre sclaer shift factor.
69 * @pre_hratio: horizontal ratio of the prescaler.
70 * @pre_vratio: vertical ratio of the prescaler.
71 * @main_hratio: the main scaler's horizontal ratio.
72 * @main_vratio: the main scaler's vertical ratio.
73 */
74 struct gsc_scaler {
75 bool range;
76 u32 pre_shfactor;
77 u32 pre_hratio;
78 u32 pre_vratio;
79 unsigned long main_hratio;
80 unsigned long main_vratio;
81 };
82
83 /*
84 * A structure of gsc context.
85 *
86 * @regs_res: register resources.
87 * @regs: memory mapped io registers.
88 * @gsc_clk: gsc gate clock.
89 * @sc: scaler infomations.
90 * @id: gsc id.
91 * @irq: irq number.
92 * @rotation: supports rotation of src.
93 */
94 struct gsc_context {
95 struct exynos_drm_ipp ipp;
96 struct drm_device *drm_dev;
97 struct device *dev;
98 struct exynos_drm_ipp_task *task;
99 struct exynos_drm_ipp_formats *formats;
100 unsigned int num_formats;
101
102 struct resource *regs_res;
103 void __iomem *regs;
104 const char **clk_names;
105 struct clk *clocks[GSC_MAX_CLOCKS];
106 int num_clocks;
107 struct gsc_scaler sc;
108 int id;
109 int irq;
110 bool rotation;
111 };
112
113 /**
114 * struct gsc_driverdata - per device type driver data for init time.
115 *
116 * @limits: picture size limits array
117 * @clk_names: names of clocks needed by this variant
118 * @num_clocks: the number of clocks needed by this variant
119 */
120 struct gsc_driverdata {
121 const struct drm_exynos_ipp_limit *limits;
122 int num_limits;
123 const char *clk_names[GSC_MAX_CLOCKS];
124 int num_clocks;
125 };
126
127 /* 8-tap Filter Coefficient */
128 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
129 { /* Ratio <= 65536 (~8:8) */
130 { 0, 0, 0, 128, 0, 0, 0, 0 },
131 { -1, 2, -6, 127, 7, -2, 1, 0 },
132 { -1, 4, -12, 125, 16, -5, 1, 0 },
133 { -1, 5, -15, 120, 25, -8, 2, 0 },
134 { -1, 6, -18, 114, 35, -10, 3, -1 },
135 { -1, 6, -20, 107, 46, -13, 4, -1 },
136 { -2, 7, -21, 99, 57, -16, 5, -1 },
137 { -1, 6, -20, 89, 68, -18, 5, -1 },
138 { -1, 6, -20, 79, 79, -20, 6, -1 },
139 { -1, 5, -18, 68, 89, -20, 6, -1 },
140 { -1, 5, -16, 57, 99, -21, 7, -2 },
141 { -1, 4, -13, 46, 107, -20, 6, -1 },
142 { -1, 3, -10, 35, 114, -18, 6, -1 },
143 { 0, 2, -8, 25, 120, -15, 5, -1 },
144 { 0, 1, -5, 16, 125, -12, 4, -1 },
145 { 0, 1, -2, 7, 127, -6, 2, -1 }
146 }, { /* 65536 < Ratio <= 74898 (~8:7) */
147 { 3, -8, 14, 111, 13, -8, 3, 0 },
148 { 2, -6, 7, 112, 21, -10, 3, -1 },
149 { 2, -4, 1, 110, 28, -12, 4, -1 },
150 { 1, -2, -3, 106, 36, -13, 4, -1 },
151 { 1, -1, -7, 103, 44, -15, 4, -1 },
152 { 1, 1, -11, 97, 53, -16, 4, -1 },
153 { 0, 2, -13, 91, 61, -16, 4, -1 },
154 { 0, 3, -15, 85, 69, -17, 4, -1 },
155 { 0, 3, -16, 77, 77, -16, 3, 0 },
156 { -1, 4, -17, 69, 85, -15, 3, 0 },
157 { -1, 4, -16, 61, 91, -13, 2, 0 },
158 { -1, 4, -16, 53, 97, -11, 1, 1 },
159 { -1, 4, -15, 44, 103, -7, -1, 1 },
160 { -1, 4, -13, 36, 106, -3, -2, 1 },
161 { -1, 4, -12, 28, 110, 1, -4, 2 },
162 { -1, 3, -10, 21, 112, 7, -6, 2 }
163 }, { /* 74898 < Ratio <= 87381 (~8:6) */
164 { 2, -11, 25, 96, 25, -11, 2, 0 },
165 { 2, -10, 19, 96, 31, -12, 2, 0 },
166 { 2, -9, 14, 94, 37, -12, 2, 0 },
167 { 2, -8, 10, 92, 43, -12, 1, 0 },
168 { 2, -7, 5, 90, 49, -12, 1, 0 },
169 { 2, -5, 1, 86, 55, -12, 0, 1 },
170 { 2, -4, -2, 82, 61, -11, -1, 1 },
171 { 1, -3, -5, 77, 67, -9, -1, 1 },
172 { 1, -2, -7, 72, 72, -7, -2, 1 },
173 { 1, -1, -9, 67, 77, -5, -3, 1 },
174 { 1, -1, -11, 61, 82, -2, -4, 2 },
175 { 1, 0, -12, 55, 86, 1, -5, 2 },
176 { 0, 1, -12, 49, 90, 5, -7, 2 },
177 { 0, 1, -12, 43, 92, 10, -8, 2 },
178 { 0, 2, -12, 37, 94, 14, -9, 2 },
179 { 0, 2, -12, 31, 96, 19, -10, 2 }
180 }, { /* 87381 < Ratio <= 104857 (~8:5) */
181 { -1, -8, 33, 80, 33, -8, -1, 0 },
182 { -1, -8, 28, 80, 37, -7, -2, 1 },
183 { 0, -8, 24, 79, 41, -7, -2, 1 },
184 { 0, -8, 20, 78, 46, -6, -3, 1 },
185 { 0, -8, 16, 76, 50, -4, -3, 1 },
186 { 0, -7, 13, 74, 54, -3, -4, 1 },
187 { 1, -7, 10, 71, 58, -1, -5, 1 },
188 { 1, -6, 6, 68, 62, 1, -5, 1 },
189 { 1, -6, 4, 65, 65, 4, -6, 1 },
190 { 1, -5, 1, 62, 68, 6, -6, 1 },
191 { 1, -5, -1, 58, 71, 10, -7, 1 },
192 { 1, -4, -3, 54, 74, 13, -7, 0 },
193 { 1, -3, -4, 50, 76, 16, -8, 0 },
194 { 1, -3, -6, 46, 78, 20, -8, 0 },
195 { 1, -2, -7, 41, 79, 24, -8, 0 },
196 { 1, -2, -7, 37, 80, 28, -8, -1 }
197 }, { /* 104857 < Ratio <= 131072 (~8:4) */
198 { -3, 0, 35, 64, 35, 0, -3, 0 },
199 { -3, -1, 32, 64, 38, 1, -3, 0 },
200 { -2, -2, 29, 63, 41, 2, -3, 0 },
201 { -2, -3, 27, 63, 43, 4, -4, 0 },
202 { -2, -3, 24, 61, 46, 6, -4, 0 },
203 { -2, -3, 21, 60, 49, 7, -4, 0 },
204 { -1, -4, 19, 59, 51, 9, -4, -1 },
205 { -1, -4, 16, 57, 53, 12, -4, -1 },
206 { -1, -4, 14, 55, 55, 14, -4, -1 },
207 { -1, -4, 12, 53, 57, 16, -4, -1 },
208 { -1, -4, 9, 51, 59, 19, -4, -1 },
209 { 0, -4, 7, 49, 60, 21, -3, -2 },
210 { 0, -4, 6, 46, 61, 24, -3, -2 },
211 { 0, -4, 4, 43, 63, 27, -3, -2 },
212 { 0, -3, 2, 41, 63, 29, -2, -2 },
213 { 0, -3, 1, 38, 64, 32, -1, -3 }
214 }, { /* 131072 < Ratio <= 174762 (~8:3) */
215 { -1, 8, 33, 48, 33, 8, -1, 0 },
216 { -1, 7, 31, 49, 35, 9, -1, -1 },
217 { -1, 6, 30, 49, 36, 10, -1, -1 },
218 { -1, 5, 28, 48, 38, 12, -1, -1 },
219 { -1, 4, 26, 48, 39, 13, 0, -1 },
220 { -1, 3, 24, 47, 41, 15, 0, -1 },
221 { -1, 2, 23, 47, 42, 16, 0, -1 },
222 { -1, 2, 21, 45, 43, 18, 1, -1 },
223 { -1, 1, 19, 45, 45, 19, 1, -1 },
224 { -1, 1, 18, 43, 45, 21, 2, -1 },
225 { -1, 0, 16, 42, 47, 23, 2, -1 },
226 { -1, 0, 15, 41, 47, 24, 3, -1 },
227 { -1, 0, 13, 39, 48, 26, 4, -1 },
228 { -1, -1, 12, 38, 48, 28, 5, -1 },
229 { -1, -1, 10, 36, 49, 30, 6, -1 },
230 { -1, -1, 9, 35, 49, 31, 7, -1 }
231 }, { /* 174762 < Ratio <= 262144 (~8:2) */
232 { 2, 13, 30, 38, 30, 13, 2, 0 },
233 { 2, 12, 29, 38, 30, 14, 3, 0 },
234 { 2, 11, 28, 38, 31, 15, 3, 0 },
235 { 2, 10, 26, 38, 32, 16, 4, 0 },
236 { 1, 10, 26, 37, 33, 17, 4, 0 },
237 { 1, 9, 24, 37, 34, 18, 5, 0 },
238 { 1, 8, 24, 37, 34, 19, 5, 0 },
239 { 1, 7, 22, 36, 35, 20, 6, 1 },
240 { 1, 6, 21, 36, 36, 21, 6, 1 },
241 { 1, 6, 20, 35, 36, 22, 7, 1 },
242 { 0, 5, 19, 34, 37, 24, 8, 1 },
243 { 0, 5, 18, 34, 37, 24, 9, 1 },
244 { 0, 4, 17, 33, 37, 26, 10, 1 },
245 { 0, 4, 16, 32, 38, 26, 10, 2 },
246 { 0, 3, 15, 31, 38, 28, 11, 2 },
247 { 0, 3, 14, 30, 38, 29, 12, 2 }
248 }
249 };
250
251 /* 4-tap Filter Coefficient */
252 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
253 { /* Ratio <= 65536 (~8:8) */
254 { 0, 128, 0, 0 },
255 { -4, 127, 5, 0 },
256 { -6, 124, 11, -1 },
257 { -8, 118, 19, -1 },
258 { -8, 111, 27, -2 },
259 { -8, 102, 37, -3 },
260 { -8, 92, 48, -4 },
261 { -7, 81, 59, -5 },
262 { -6, 70, 70, -6 },
263 { -5, 59, 81, -7 },
264 { -4, 48, 92, -8 },
265 { -3, 37, 102, -8 },
266 { -2, 27, 111, -8 },
267 { -1, 19, 118, -8 },
268 { -1, 11, 124, -6 },
269 { 0, 5, 127, -4 }
270 }, { /* 65536 < Ratio <= 74898 (~8:7) */
271 { 8, 112, 8, 0 },
272 { 4, 111, 14, -1 },
273 { 1, 109, 20, -2 },
274 { -2, 105, 27, -2 },
275 { -3, 100, 34, -3 },
276 { -5, 93, 43, -3 },
277 { -5, 86, 51, -4 },
278 { -5, 77, 60, -4 },
279 { -5, 69, 69, -5 },
280 { -4, 60, 77, -5 },
281 { -4, 51, 86, -5 },
282 { -3, 43, 93, -5 },
283 { -3, 34, 100, -3 },
284 { -2, 27, 105, -2 },
285 { -2, 20, 109, 1 },
286 { -1, 14, 111, 4 }
287 }, { /* 74898 < Ratio <= 87381 (~8:6) */
288 { 16, 96, 16, 0 },
289 { 12, 97, 21, -2 },
290 { 8, 96, 26, -2 },
291 { 5, 93, 32, -2 },
292 { 2, 89, 39, -2 },
293 { 0, 84, 46, -2 },
294 { -1, 79, 53, -3 },
295 { -2, 73, 59, -2 },
296 { -2, 66, 66, -2 },
297 { -2, 59, 73, -2 },
298 { -3, 53, 79, -1 },
299 { -2, 46, 84, 0 },
300 { -2, 39, 89, 2 },
301 { -2, 32, 93, 5 },
302 { -2, 26, 96, 8 },
303 { -2, 21, 97, 12 }
304 }, { /* 87381 < Ratio <= 104857 (~8:5) */
305 { 22, 84, 22, 0 },
306 { 18, 85, 26, -1 },
307 { 14, 84, 31, -1 },
308 { 11, 82, 36, -1 },
309 { 8, 79, 42, -1 },
310 { 6, 76, 47, -1 },
311 { 4, 72, 52, 0 },
312 { 2, 68, 58, 0 },
313 { 1, 63, 63, 1 },
314 { 0, 58, 68, 2 },
315 { 0, 52, 72, 4 },
316 { -1, 47, 76, 6 },
317 { -1, 42, 79, 8 },
318 { -1, 36, 82, 11 },
319 { -1, 31, 84, 14 },
320 { -1, 26, 85, 18 }
321 }, { /* 104857 < Ratio <= 131072 (~8:4) */
322 { 26, 76, 26, 0 },
323 { 22, 76, 30, 0 },
324 { 19, 75, 34, 0 },
325 { 16, 73, 38, 1 },
326 { 13, 71, 43, 1 },
327 { 10, 69, 47, 2 },
328 { 8, 66, 51, 3 },
329 { 6, 63, 55, 4 },
330 { 5, 59, 59, 5 },
331 { 4, 55, 63, 6 },
332 { 3, 51, 66, 8 },
333 { 2, 47, 69, 10 },
334 { 1, 43, 71, 13 },
335 { 1, 38, 73, 16 },
336 { 0, 34, 75, 19 },
337 { 0, 30, 76, 22 }
338 }, { /* 131072 < Ratio <= 174762 (~8:3) */
339 { 29, 70, 29, 0 },
340 { 26, 68, 32, 2 },
341 { 23, 67, 36, 2 },
342 { 20, 66, 39, 3 },
343 { 17, 65, 43, 3 },
344 { 15, 63, 46, 4 },
345 { 12, 61, 50, 5 },
346 { 10, 58, 53, 7 },
347 { 8, 56, 56, 8 },
348 { 7, 53, 58, 10 },
349 { 5, 50, 61, 12 },
350 { 4, 46, 63, 15 },
351 { 3, 43, 65, 17 },
352 { 3, 39, 66, 20 },
353 { 2, 36, 67, 23 },
354 { 2, 32, 68, 26 }
355 }, { /* 174762 < Ratio <= 262144 (~8:2) */
356 { 32, 64, 32, 0 },
357 { 28, 63, 34, 3 },
358 { 25, 62, 37, 4 },
359 { 22, 62, 40, 4 },
360 { 19, 61, 43, 5 },
361 { 17, 59, 46, 6 },
362 { 15, 58, 48, 7 },
363 { 13, 55, 51, 9 },
364 { 11, 53, 53, 11 },
365 { 9, 51, 55, 13 },
366 { 7, 48, 58, 15 },
367 { 6, 46, 59, 17 },
368 { 5, 43, 61, 19 },
369 { 4, 40, 62, 22 },
370 { 4, 37, 62, 25 },
371 { 3, 34, 63, 28 }
372 }
373 };
374
375 static int gsc_sw_reset(struct gsc_context *ctx)
376 {
377 u32 cfg;
378 int count = GSC_RESET_TIMEOUT;
379
380 /* s/w reset */
381 cfg = (GSC_SW_RESET_SRESET);
382 gsc_write(cfg, GSC_SW_RESET);
383
384 /* wait s/w reset complete */
385 while (count--) {
386 cfg = gsc_read(GSC_SW_RESET);
387 if (!cfg)
388 break;
389 usleep_range(1000, 2000);
390 }
391
392 if (cfg) {
393 DRM_DEV_ERROR(ctx->dev, "failed to reset gsc h/w.\n");
394 return -EBUSY;
395 }
396
397 /* reset sequence */
398 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
399 cfg |= (GSC_IN_BASE_ADDR_MASK |
400 GSC_IN_BASE_ADDR_PINGPONG(0));
401 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
402 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
403 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
404
405 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
406 cfg |= (GSC_OUT_BASE_ADDR_MASK |
407 GSC_OUT_BASE_ADDR_PINGPONG(0));
408 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
409 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
410 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
411
412 return 0;
413 }
414
415 static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
416 bool overflow, bool done)
417 {
418 u32 cfg;
419
420 DRM_DEV_DEBUG_KMS(ctx->dev, "enable[%d]overflow[%d]level[%d]\n",
421 enable, overflow, done);
422
423 cfg = gsc_read(GSC_IRQ);
424 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
425
426 if (enable)
427 cfg |= GSC_IRQ_ENABLE;
428 else
429 cfg &= ~GSC_IRQ_ENABLE;
430
431 if (overflow)
432 cfg &= ~GSC_IRQ_OR_MASK;
433 else
434 cfg |= GSC_IRQ_OR_MASK;
435
436 if (done)
437 cfg &= ~GSC_IRQ_FRMDONE_MASK;
438 else
439 cfg |= GSC_IRQ_FRMDONE_MASK;
440
441 gsc_write(cfg, GSC_IRQ);
442 }
443
444
445 static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
446 {
447 u32 cfg;
448
449 DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
450
451 cfg = gsc_read(GSC_IN_CON);
452 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
453 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
454 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
455 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
456
457 switch (fmt) {
458 case DRM_FORMAT_RGB565:
459 cfg |= GSC_IN_RGB565;
460 break;
461 case DRM_FORMAT_XRGB8888:
462 case DRM_FORMAT_ARGB8888:
463 cfg |= GSC_IN_XRGB8888;
464 break;
465 case DRM_FORMAT_BGRX8888:
466 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
467 break;
468 case DRM_FORMAT_YUYV:
469 cfg |= (GSC_IN_YUV422_1P |
470 GSC_IN_YUV422_1P_ORDER_LSB_Y |
471 GSC_IN_CHROMA_ORDER_CBCR);
472 break;
473 case DRM_FORMAT_YVYU:
474 cfg |= (GSC_IN_YUV422_1P |
475 GSC_IN_YUV422_1P_ORDER_LSB_Y |
476 GSC_IN_CHROMA_ORDER_CRCB);
477 break;
478 case DRM_FORMAT_UYVY:
479 cfg |= (GSC_IN_YUV422_1P |
480 GSC_IN_YUV422_1P_OEDER_LSB_C |
481 GSC_IN_CHROMA_ORDER_CBCR);
482 break;
483 case DRM_FORMAT_VYUY:
484 cfg |= (GSC_IN_YUV422_1P |
485 GSC_IN_YUV422_1P_OEDER_LSB_C |
486 GSC_IN_CHROMA_ORDER_CRCB);
487 break;
488 case DRM_FORMAT_NV21:
489 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
490 break;
491 case DRM_FORMAT_NV61:
492 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
493 break;
494 case DRM_FORMAT_YUV422:
495 cfg |= GSC_IN_YUV422_3P;
496 break;
497 case DRM_FORMAT_YUV420:
498 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
499 break;
500 case DRM_FORMAT_YVU420:
501 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
502 break;
503 case DRM_FORMAT_NV12:
504 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
505 break;
506 case DRM_FORMAT_NV16:
507 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
508 break;
509 }
510
511 if (tiled)
512 cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
513
514 gsc_write(cfg, GSC_IN_CON);
515 }
516
517 static void gsc_src_set_transf(struct gsc_context *ctx, unsigned int rotation)
518 {
519 unsigned int degree = rotation & DRM_MODE_ROTATE_MASK;
520 u32 cfg;
521
522 cfg = gsc_read(GSC_IN_CON);
523 cfg &= ~GSC_IN_ROT_MASK;
524
525 switch (degree) {
526 case DRM_MODE_ROTATE_0:
527 if (rotation & DRM_MODE_REFLECT_X)
528 cfg |= GSC_IN_ROT_XFLIP;
529 if (rotation & DRM_MODE_REFLECT_Y)
530 cfg |= GSC_IN_ROT_YFLIP;
531 break;
532 case DRM_MODE_ROTATE_90:
533 cfg |= GSC_IN_ROT_90;
534 if (rotation & DRM_MODE_REFLECT_X)
535 cfg |= GSC_IN_ROT_XFLIP;
536 if (rotation & DRM_MODE_REFLECT_Y)
537 cfg |= GSC_IN_ROT_YFLIP;
538 break;
539 case DRM_MODE_ROTATE_180:
540 cfg |= GSC_IN_ROT_180;
541 if (rotation & DRM_MODE_REFLECT_X)
542 cfg &= ~GSC_IN_ROT_XFLIP;
543 if (rotation & DRM_MODE_REFLECT_Y)
544 cfg &= ~GSC_IN_ROT_YFLIP;
545 break;
546 case DRM_MODE_ROTATE_270:
547 cfg |= GSC_IN_ROT_270;
548 if (rotation & DRM_MODE_REFLECT_X)
549 cfg &= ~GSC_IN_ROT_XFLIP;
550 if (rotation & DRM_MODE_REFLECT_Y)
551 cfg &= ~GSC_IN_ROT_YFLIP;
552 break;
553 }
554
555 gsc_write(cfg, GSC_IN_CON);
556
557 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
558 }
559
560 static void gsc_src_set_size(struct gsc_context *ctx,
561 struct exynos_drm_ipp_buffer *buf)
562 {
563 struct gsc_scaler *sc = &ctx->sc;
564 u32 cfg;
565
566 /* pixel offset */
567 cfg = (GSC_SRCIMG_OFFSET_X(buf->rect.x) |
568 GSC_SRCIMG_OFFSET_Y(buf->rect.y));
569 gsc_write(cfg, GSC_SRCIMG_OFFSET);
570
571 /* cropped size */
572 cfg = (GSC_CROPPED_WIDTH(buf->rect.w) |
573 GSC_CROPPED_HEIGHT(buf->rect.h));
574 gsc_write(cfg, GSC_CROPPED_SIZE);
575
576 /* original size */
577 cfg = gsc_read(GSC_SRCIMG_SIZE);
578 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
579 GSC_SRCIMG_WIDTH_MASK);
580
581 cfg |= (GSC_SRCIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
582 GSC_SRCIMG_HEIGHT(buf->buf.height));
583
584 gsc_write(cfg, GSC_SRCIMG_SIZE);
585
586 cfg = gsc_read(GSC_IN_CON);
587 cfg &= ~GSC_IN_RGB_TYPE_MASK;
588
589 if (buf->rect.w >= GSC_WIDTH_ITU_709)
590 if (sc->range)
591 cfg |= GSC_IN_RGB_HD_WIDE;
592 else
593 cfg |= GSC_IN_RGB_HD_NARROW;
594 else
595 if (sc->range)
596 cfg |= GSC_IN_RGB_SD_WIDE;
597 else
598 cfg |= GSC_IN_RGB_SD_NARROW;
599
600 gsc_write(cfg, GSC_IN_CON);
601 }
602
603 static void gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
604 bool enqueue)
605 {
606 bool masked = !enqueue;
607 u32 cfg;
608 u32 mask = 0x00000001 << buf_id;
609
610 /* mask register set */
611 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
612
613 /* sequence id */
614 cfg &= ~mask;
615 cfg |= masked << buf_id;
616 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
617 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
618 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
619 }
620
621 static void gsc_src_set_addr(struct gsc_context *ctx, u32 buf_id,
622 struct exynos_drm_ipp_buffer *buf)
623 {
624 /* address register set */
625 gsc_write(buf->dma_addr[0], GSC_IN_BASE_ADDR_Y(buf_id));
626 gsc_write(buf->dma_addr[1], GSC_IN_BASE_ADDR_CB(buf_id));
627 gsc_write(buf->dma_addr[2], GSC_IN_BASE_ADDR_CR(buf_id));
628
629 gsc_src_set_buf_seq(ctx, buf_id, true);
630 }
631
632 static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
633 {
634 u32 cfg;
635
636 DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
637
638 cfg = gsc_read(GSC_OUT_CON);
639 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
640 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
641 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
642 GSC_OUT_GLOBAL_ALPHA_MASK);
643
644 switch (fmt) {
645 case DRM_FORMAT_RGB565:
646 cfg |= GSC_OUT_RGB565;
647 break;
648 case DRM_FORMAT_ARGB8888:
649 case DRM_FORMAT_XRGB8888:
650 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_GLOBAL_ALPHA(0xff));
651 break;
652 case DRM_FORMAT_BGRX8888:
653 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
654 break;
655 case DRM_FORMAT_YUYV:
656 cfg |= (GSC_OUT_YUV422_1P |
657 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
658 GSC_OUT_CHROMA_ORDER_CBCR);
659 break;
660 case DRM_FORMAT_YVYU:
661 cfg |= (GSC_OUT_YUV422_1P |
662 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
663 GSC_OUT_CHROMA_ORDER_CRCB);
664 break;
665 case DRM_FORMAT_UYVY:
666 cfg |= (GSC_OUT_YUV422_1P |
667 GSC_OUT_YUV422_1P_OEDER_LSB_C |
668 GSC_OUT_CHROMA_ORDER_CBCR);
669 break;
670 case DRM_FORMAT_VYUY:
671 cfg |= (GSC_OUT_YUV422_1P |
672 GSC_OUT_YUV422_1P_OEDER_LSB_C |
673 GSC_OUT_CHROMA_ORDER_CRCB);
674 break;
675 case DRM_FORMAT_NV21:
676 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
677 break;
678 case DRM_FORMAT_NV61:
679 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
680 break;
681 case DRM_FORMAT_YUV422:
682 cfg |= GSC_OUT_YUV422_3P;
683 break;
684 case DRM_FORMAT_YUV420:
685 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
686 break;
687 case DRM_FORMAT_YVU420:
688 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
689 break;
690 case DRM_FORMAT_NV12:
691 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
692 break;
693 case DRM_FORMAT_NV16:
694 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
695 break;
696 }
697
698 if (tiled)
699 cfg |= (GSC_IN_TILE_C_16x8 | GSC_OUT_TILE_MODE);
700
701 gsc_write(cfg, GSC_OUT_CON);
702 }
703
704 static int gsc_get_ratio_shift(struct gsc_context *ctx, u32 src, u32 dst,
705 u32 *ratio)
706 {
707 DRM_DEV_DEBUG_KMS(ctx->dev, "src[%d]dst[%d]\n", src, dst);
708
709 if (src >= dst * 8) {
710 DRM_DEV_ERROR(ctx->dev, "failed to make ratio and shift.\n");
711 return -EINVAL;
712 } else if (src >= dst * 4)
713 *ratio = 4;
714 else if (src >= dst * 2)
715 *ratio = 2;
716 else
717 *ratio = 1;
718
719 return 0;
720 }
721
722 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
723 {
724 if (hratio == 4 && vratio == 4)
725 *shfactor = 4;
726 else if ((hratio == 4 && vratio == 2) ||
727 (hratio == 2 && vratio == 4))
728 *shfactor = 3;
729 else if ((hratio == 4 && vratio == 1) ||
730 (hratio == 1 && vratio == 4) ||
731 (hratio == 2 && vratio == 2))
732 *shfactor = 2;
733 else if (hratio == 1 && vratio == 1)
734 *shfactor = 0;
735 else
736 *shfactor = 1;
737 }
738
739 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
740 struct drm_exynos_ipp_task_rect *src,
741 struct drm_exynos_ipp_task_rect *dst)
742 {
743 u32 cfg;
744 u32 src_w, src_h, dst_w, dst_h;
745 int ret = 0;
746
747 src_w = src->w;
748 src_h = src->h;
749
750 if (ctx->rotation) {
751 dst_w = dst->h;
752 dst_h = dst->w;
753 } else {
754 dst_w = dst->w;
755 dst_h = dst->h;
756 }
757
758 ret = gsc_get_ratio_shift(ctx, src_w, dst_w, &sc->pre_hratio);
759 if (ret) {
760 DRM_DEV_ERROR(ctx->dev, "failed to get ratio horizontal.\n");
761 return ret;
762 }
763
764 ret = gsc_get_ratio_shift(ctx, src_h, dst_h, &sc->pre_vratio);
765 if (ret) {
766 DRM_DEV_ERROR(ctx->dev, "failed to get ratio vertical.\n");
767 return ret;
768 }
769
770 DRM_DEV_DEBUG_KMS(ctx->dev, "pre_hratio[%d]pre_vratio[%d]\n",
771 sc->pre_hratio, sc->pre_vratio);
772
773 sc->main_hratio = (src_w << 16) / dst_w;
774 sc->main_vratio = (src_h << 16) / dst_h;
775
776 DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
777 sc->main_hratio, sc->main_vratio);
778
779 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
780 &sc->pre_shfactor);
781
782 DRM_DEV_DEBUG_KMS(ctx->dev, "pre_shfactor[%d]\n", sc->pre_shfactor);
783
784 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
785 GSC_PRESC_H_RATIO(sc->pre_hratio) |
786 GSC_PRESC_V_RATIO(sc->pre_vratio));
787 gsc_write(cfg, GSC_PRE_SCALE_RATIO);
788
789 return ret;
790 }
791
792 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
793 {
794 int i, j, k, sc_ratio;
795
796 if (main_hratio <= GSC_SC_UP_MAX_RATIO)
797 sc_ratio = 0;
798 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
799 sc_ratio = 1;
800 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
801 sc_ratio = 2;
802 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
803 sc_ratio = 3;
804 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
805 sc_ratio = 4;
806 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
807 sc_ratio = 5;
808 else
809 sc_ratio = 6;
810
811 for (i = 0; i < GSC_COEF_PHASE; i++)
812 for (j = 0; j < GSC_COEF_H_8T; j++)
813 for (k = 0; k < GSC_COEF_DEPTH; k++)
814 gsc_write(h_coef_8t[sc_ratio][i][j],
815 GSC_HCOEF(i, j, k));
816 }
817
818 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
819 {
820 int i, j, k, sc_ratio;
821
822 if (main_vratio <= GSC_SC_UP_MAX_RATIO)
823 sc_ratio = 0;
824 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
825 sc_ratio = 1;
826 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
827 sc_ratio = 2;
828 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
829 sc_ratio = 3;
830 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
831 sc_ratio = 4;
832 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
833 sc_ratio = 5;
834 else
835 sc_ratio = 6;
836
837 for (i = 0; i < GSC_COEF_PHASE; i++)
838 for (j = 0; j < GSC_COEF_V_4T; j++)
839 for (k = 0; k < GSC_COEF_DEPTH; k++)
840 gsc_write(v_coef_4t[sc_ratio][i][j],
841 GSC_VCOEF(i, j, k));
842 }
843
844 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
845 {
846 u32 cfg;
847
848 DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
849 sc->main_hratio, sc->main_vratio);
850
851 gsc_set_h_coef(ctx, sc->main_hratio);
852 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
853 gsc_write(cfg, GSC_MAIN_H_RATIO);
854
855 gsc_set_v_coef(ctx, sc->main_vratio);
856 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
857 gsc_write(cfg, GSC_MAIN_V_RATIO);
858 }
859
860 static void gsc_dst_set_size(struct gsc_context *ctx,
861 struct exynos_drm_ipp_buffer *buf)
862 {
863 struct gsc_scaler *sc = &ctx->sc;
864 u32 cfg;
865
866 /* pixel offset */
867 cfg = (GSC_DSTIMG_OFFSET_X(buf->rect.x) |
868 GSC_DSTIMG_OFFSET_Y(buf->rect.y));
869 gsc_write(cfg, GSC_DSTIMG_OFFSET);
870
871 /* scaled size */
872 if (ctx->rotation)
873 cfg = (GSC_SCALED_WIDTH(buf->rect.h) |
874 GSC_SCALED_HEIGHT(buf->rect.w));
875 else
876 cfg = (GSC_SCALED_WIDTH(buf->rect.w) |
877 GSC_SCALED_HEIGHT(buf->rect.h));
878 gsc_write(cfg, GSC_SCALED_SIZE);
879
880 /* original size */
881 cfg = gsc_read(GSC_DSTIMG_SIZE);
882 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | GSC_DSTIMG_WIDTH_MASK);
883 cfg |= GSC_DSTIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
884 GSC_DSTIMG_HEIGHT(buf->buf.height);
885 gsc_write(cfg, GSC_DSTIMG_SIZE);
886
887 cfg = gsc_read(GSC_OUT_CON);
888 cfg &= ~GSC_OUT_RGB_TYPE_MASK;
889
890 if (buf->rect.w >= GSC_WIDTH_ITU_709)
891 if (sc->range)
892 cfg |= GSC_OUT_RGB_HD_WIDE;
893 else
894 cfg |= GSC_OUT_RGB_HD_NARROW;
895 else
896 if (sc->range)
897 cfg |= GSC_OUT_RGB_SD_WIDE;
898 else
899 cfg |= GSC_OUT_RGB_SD_NARROW;
900
901 gsc_write(cfg, GSC_OUT_CON);
902 }
903
904 static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
905 {
906 u32 cfg, i, buf_num = GSC_REG_SZ;
907 u32 mask = 0x00000001;
908
909 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
910
911 for (i = 0; i < GSC_REG_SZ; i++)
912 if (cfg & (mask << i))
913 buf_num--;
914
915 DRM_DEV_DEBUG_KMS(ctx->dev, "buf_num[%d]\n", buf_num);
916
917 return buf_num;
918 }
919
920 static void gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
921 bool enqueue)
922 {
923 bool masked = !enqueue;
924 u32 cfg;
925 u32 mask = 0x00000001 << buf_id;
926
927 /* mask register set */
928 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
929
930 /* sequence id */
931 cfg &= ~mask;
932 cfg |= masked << buf_id;
933 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
934 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
935 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
936
937 /* interrupt enable */
938 if (enqueue && gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
939 gsc_handle_irq(ctx, true, false, true);
940
941 /* interrupt disable */
942 if (!enqueue && gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
943 gsc_handle_irq(ctx, false, false, true);
944 }
945
946 static void gsc_dst_set_addr(struct gsc_context *ctx,
947 u32 buf_id, struct exynos_drm_ipp_buffer *buf)
948 {
949 /* address register set */
950 gsc_write(buf->dma_addr[0], GSC_OUT_BASE_ADDR_Y(buf_id));
951 gsc_write(buf->dma_addr[1], GSC_OUT_BASE_ADDR_CB(buf_id));
952 gsc_write(buf->dma_addr[2], GSC_OUT_BASE_ADDR_CR(buf_id));
953
954 gsc_dst_set_buf_seq(ctx, buf_id, true);
955 }
956
957 static int gsc_get_src_buf_index(struct gsc_context *ctx)
958 {
959 u32 cfg, curr_index, i;
960 u32 buf_id = GSC_MAX_SRC;
961
962 DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
963
964 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
965 curr_index = GSC_IN_CURR_GET_INDEX(cfg);
966
967 for (i = curr_index; i < GSC_MAX_SRC; i++) {
968 if (!((cfg >> i) & 0x1)) {
969 buf_id = i;
970 break;
971 }
972 }
973
974 DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
975 curr_index, buf_id);
976
977 if (buf_id == GSC_MAX_SRC) {
978 DRM_DEV_ERROR(ctx->dev, "failed to get in buffer index.\n");
979 return -EINVAL;
980 }
981
982 gsc_src_set_buf_seq(ctx, buf_id, false);
983
984 return buf_id;
985 }
986
987 static int gsc_get_dst_buf_index(struct gsc_context *ctx)
988 {
989 u32 cfg, curr_index, i;
990 u32 buf_id = GSC_MAX_DST;
991
992 DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
993
994 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
995 curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
996
997 for (i = curr_index; i < GSC_MAX_DST; i++) {
998 if (!((cfg >> i) & 0x1)) {
999 buf_id = i;
1000 break;
1001 }
1002 }
1003
1004 if (buf_id == GSC_MAX_DST) {
1005 DRM_DEV_ERROR(ctx->dev, "failed to get out buffer index.\n");
1006 return -EINVAL;
1007 }
1008
1009 gsc_dst_set_buf_seq(ctx, buf_id, false);
1010
1011 DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1012 curr_index, buf_id);
1013
1014 return buf_id;
1015 }
1016
1017 static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1018 {
1019 struct gsc_context *ctx = dev_id;
1020 u32 status;
1021 int err = 0;
1022
1023 DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
1024
1025 status = gsc_read(GSC_IRQ);
1026 if (status & GSC_IRQ_STATUS_OR_IRQ) {
1027 dev_err(ctx->dev, "occurred overflow at %d, status 0x%x.\n",
1028 ctx->id, status);
1029 err = -EINVAL;
1030 }
1031
1032 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1033 int src_buf_id, dst_buf_id;
1034
1035 dev_dbg(ctx->dev, "occurred frame done at %d, status 0x%x.\n",
1036 ctx->id, status);
1037
1038 src_buf_id = gsc_get_src_buf_index(ctx);
1039 dst_buf_id = gsc_get_dst_buf_index(ctx);
1040
1041 DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id_src[%d]buf_id_dst[%d]\n",
1042 src_buf_id, dst_buf_id);
1043
1044 if (src_buf_id < 0 || dst_buf_id < 0)
1045 err = -EINVAL;
1046 }
1047
1048 if (ctx->task) {
1049 struct exynos_drm_ipp_task *task = ctx->task;
1050
1051 ctx->task = NULL;
1052 pm_runtime_mark_last_busy(ctx->dev);
1053 pm_runtime_put_autosuspend(ctx->dev);
1054 exynos_drm_ipp_task_done(task, err);
1055 }
1056
1057 return IRQ_HANDLED;
1058 }
1059
1060 static int gsc_reset(struct gsc_context *ctx)
1061 {
1062 struct gsc_scaler *sc = &ctx->sc;
1063 int ret;
1064
1065 /* reset h/w block */
1066 ret = gsc_sw_reset(ctx);
1067 if (ret < 0) {
1068 dev_err(ctx->dev, "failed to reset hardware.\n");
1069 return ret;
1070 }
1071
1072 /* scaler setting */
1073 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1074 sc->range = true;
1075
1076 return 0;
1077 }
1078
1079 static void gsc_start(struct gsc_context *ctx)
1080 {
1081 u32 cfg;
1082
1083 gsc_handle_irq(ctx, true, false, true);
1084
1085 /* enable one shot */
1086 cfg = gsc_read(GSC_ENABLE);
1087 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1088 GSC_ENABLE_CLK_GATE_MODE_MASK);
1089 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1090 gsc_write(cfg, GSC_ENABLE);
1091
1092 /* src dma memory */
1093 cfg = gsc_read(GSC_IN_CON);
1094 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1095 cfg |= GSC_IN_PATH_MEMORY;
1096 gsc_write(cfg, GSC_IN_CON);
1097
1098 /* dst dma memory */
1099 cfg = gsc_read(GSC_OUT_CON);
1100 cfg |= GSC_OUT_PATH_MEMORY;
1101 gsc_write(cfg, GSC_OUT_CON);
1102
1103 gsc_set_scaler(ctx, &ctx->sc);
1104
1105 cfg = gsc_read(GSC_ENABLE);
1106 cfg |= GSC_ENABLE_ON;
1107 gsc_write(cfg, GSC_ENABLE);
1108 }
1109
1110 static int gsc_commit(struct exynos_drm_ipp *ipp,
1111 struct exynos_drm_ipp_task *task)
1112 {
1113 struct gsc_context *ctx = container_of(ipp, struct gsc_context, ipp);
1114 int ret;
1115
1116 pm_runtime_get_sync(ctx->dev);
1117 ctx->task = task;
1118
1119 ret = gsc_reset(ctx);
1120 if (ret) {
1121 pm_runtime_put_autosuspend(ctx->dev);
1122 ctx->task = NULL;
1123 return ret;
1124 }
1125
1126 gsc_src_set_fmt(ctx, task->src.buf.fourcc, task->src.buf.modifier);
1127 gsc_src_set_transf(ctx, task->transform.rotation);
1128 gsc_src_set_size(ctx, &task->src);
1129 gsc_src_set_addr(ctx, 0, &task->src);
1130 gsc_dst_set_fmt(ctx, task->dst.buf.fourcc, task->dst.buf.modifier);
1131 gsc_dst_set_size(ctx, &task->dst);
1132 gsc_dst_set_addr(ctx, 0, &task->dst);
1133 gsc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect);
1134 gsc_start(ctx);
1135
1136 return 0;
1137 }
1138
1139 static void gsc_abort(struct exynos_drm_ipp *ipp,
1140 struct exynos_drm_ipp_task *task)
1141 {
1142 struct gsc_context *ctx =
1143 container_of(ipp, struct gsc_context, ipp);
1144
1145 gsc_reset(ctx);
1146 if (ctx->task) {
1147 struct exynos_drm_ipp_task *task = ctx->task;
1148
1149 ctx->task = NULL;
1150 pm_runtime_mark_last_busy(ctx->dev);
1151 pm_runtime_put_autosuspend(ctx->dev);
1152 exynos_drm_ipp_task_done(task, -EIO);
1153 }
1154 }
1155
1156 static struct exynos_drm_ipp_funcs ipp_funcs = {
1157 .commit = gsc_commit,
1158 .abort = gsc_abort,
1159 };
1160
1161 static int gsc_bind(struct device *dev, struct device *master, void *data)
1162 {
1163 struct gsc_context *ctx = dev_get_drvdata(dev);
1164 struct drm_device *drm_dev = data;
1165 struct exynos_drm_ipp *ipp = &ctx->ipp;
1166
1167 ctx->drm_dev = drm_dev;
1168 ctx->drm_dev = drm_dev;
1169 exynos_drm_register_dma(drm_dev, dev);
1170
1171 exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
1172 DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
1173 DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
1174 ctx->formats, ctx->num_formats, "gsc");
1175
1176 dev_info(dev, "The exynos gscaler has been probed successfully\n");
1177
1178 return 0;
1179 }
1180
1181 static void gsc_unbind(struct device *dev, struct device *master,
1182 void *data)
1183 {
1184 struct gsc_context *ctx = dev_get_drvdata(dev);
1185 struct drm_device *drm_dev = data;
1186 struct exynos_drm_ipp *ipp = &ctx->ipp;
1187
1188 exynos_drm_ipp_unregister(dev, ipp);
1189 exynos_drm_unregister_dma(drm_dev, dev);
1190 }
1191
1192 static const struct component_ops gsc_component_ops = {
1193 .bind = gsc_bind,
1194 .unbind = gsc_unbind,
1195 };
1196
1197 static const unsigned int gsc_formats[] = {
1198 DRM_FORMAT_ARGB8888,
1199 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_BGRX8888,
1200 DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61,
1201 DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
1202 DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422,
1203 };
1204
1205 static const unsigned int gsc_tiled_formats[] = {
1206 DRM_FORMAT_NV12, DRM_FORMAT_NV21,
1207 };
1208
1209 static int gsc_probe(struct platform_device *pdev)
1210 {
1211 struct device *dev = &pdev->dev;
1212 struct gsc_driverdata *driver_data;
1213 struct exynos_drm_ipp_formats *formats;
1214 struct gsc_context *ctx;
1215 struct resource *res;
1216 int num_formats, ret, i, j;
1217
1218 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1219 if (!ctx)
1220 return -ENOMEM;
1221
1222 driver_data = (struct gsc_driverdata *)of_device_get_match_data(dev);
1223 ctx->dev = dev;
1224 ctx->num_clocks = driver_data->num_clocks;
1225 ctx->clk_names = driver_data->clk_names;
1226
1227 /* construct formats/limits array */
1228 num_formats = ARRAY_SIZE(gsc_formats) + ARRAY_SIZE(gsc_tiled_formats);
1229 formats = devm_kcalloc(dev, num_formats, sizeof(*formats), GFP_KERNEL);
1230 if (!formats)
1231 return -ENOMEM;
1232
1233 /* linear formats */
1234 for (i = 0; i < ARRAY_SIZE(gsc_formats); i++) {
1235 formats[i].fourcc = gsc_formats[i];
1236 formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1237 DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1238 formats[i].limits = driver_data->limits;
1239 formats[i].num_limits = driver_data->num_limits;
1240 }
1241
1242 /* tiled formats */
1243 for (j = i, i = 0; i < ARRAY_SIZE(gsc_tiled_formats); j++, i++) {
1244 formats[j].fourcc = gsc_tiled_formats[i];
1245 formats[j].modifier = DRM_FORMAT_MOD_SAMSUNG_16_16_TILE;
1246 formats[j].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1247 DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1248 formats[j].limits = driver_data->limits;
1249 formats[j].num_limits = driver_data->num_limits;
1250 }
1251
1252 ctx->formats = formats;
1253 ctx->num_formats = num_formats;
1254
1255 /* clock control */
1256 for (i = 0; i < ctx->num_clocks; i++) {
1257 ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]);
1258 if (IS_ERR(ctx->clocks[i])) {
1259 dev_err(dev, "failed to get clock: %s\n",
1260 ctx->clk_names[i]);
1261 return PTR_ERR(ctx->clocks[i]);
1262 }
1263 }
1264
1265 /* resource memory */
1266 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1267 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1268 if (IS_ERR(ctx->regs))
1269 return PTR_ERR(ctx->regs);
1270
1271 /* resource irq */
1272 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1273 if (!res) {
1274 dev_err(dev, "failed to request irq resource.\n");
1275 return -ENOENT;
1276 }
1277
1278 ctx->irq = res->start;
1279 ret = devm_request_irq(dev, ctx->irq, gsc_irq_handler, 0,
1280 dev_name(dev), ctx);
1281 if (ret < 0) {
1282 dev_err(dev, "failed to request irq.\n");
1283 return ret;
1284 }
1285
1286 /* context initailization */
1287 ctx->id = pdev->id;
1288
1289 platform_set_drvdata(pdev, ctx);
1290
1291 pm_runtime_use_autosuspend(dev);
1292 pm_runtime_set_autosuspend_delay(dev, GSC_AUTOSUSPEND_DELAY);
1293 pm_runtime_enable(dev);
1294
1295 ret = component_add(dev, &gsc_component_ops);
1296 if (ret)
1297 goto err_pm_dis;
1298
1299 dev_info(dev, "drm gsc registered successfully.\n");
1300
1301 return 0;
1302
1303 err_pm_dis:
1304 pm_runtime_dont_use_autosuspend(dev);
1305 pm_runtime_disable(dev);
1306 return ret;
1307 }
1308
1309 static int gsc_remove(struct platform_device *pdev)
1310 {
1311 struct device *dev = &pdev->dev;
1312
1313 pm_runtime_dont_use_autosuspend(dev);
1314 pm_runtime_disable(dev);
1315
1316 return 0;
1317 }
1318
1319 static int __maybe_unused gsc_runtime_suspend(struct device *dev)
1320 {
1321 struct gsc_context *ctx = get_gsc_context(dev);
1322 int i;
1323
1324 DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1325
1326 for (i = ctx->num_clocks - 1; i >= 0; i--)
1327 clk_disable_unprepare(ctx->clocks[i]);
1328
1329 return 0;
1330 }
1331
1332 static int __maybe_unused gsc_runtime_resume(struct device *dev)
1333 {
1334 struct gsc_context *ctx = get_gsc_context(dev);
1335 int i, ret;
1336
1337 DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1338
1339 for (i = 0; i < ctx->num_clocks; i++) {
1340 ret = clk_prepare_enable(ctx->clocks[i]);
1341 if (ret) {
1342 while (--i > 0)
1343 clk_disable_unprepare(ctx->clocks[i]);
1344 return ret;
1345 }
1346 }
1347 return 0;
1348 }
1349
1350 static const struct dev_pm_ops gsc_pm_ops = {
1351 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1352 pm_runtime_force_resume)
1353 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1354 };
1355
1356 static const struct drm_exynos_ipp_limit gsc_5250_limits[] = {
1357 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1358 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1359 { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2048 }, .v = { 16, 2048 }) },
1360 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1361 .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1362 };
1363
1364 static const struct drm_exynos_ipp_limit gsc_5420_limits[] = {
1365 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1366 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1367 { IPP_SIZE_LIMIT(ROTATED, .h = { 16, 2016 }, .v = { 8, 2016 }) },
1368 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1369 .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1370 };
1371
1372 static const struct drm_exynos_ipp_limit gsc_5433_limits[] = {
1373 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191, 16 }, .v = { 16, 8191, 2 }) },
1374 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) },
1375 { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2047 }, .v = { 8, 8191 }) },
1376 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1377 .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1378 };
1379
1380 static struct gsc_driverdata gsc_exynos5250_drvdata = {
1381 .clk_names = {"gscl"},
1382 .num_clocks = 1,
1383 .limits = gsc_5250_limits,
1384 .num_limits = ARRAY_SIZE(gsc_5250_limits),
1385 };
1386
1387 static struct gsc_driverdata gsc_exynos5420_drvdata = {
1388 .clk_names = {"gscl"},
1389 .num_clocks = 1,
1390 .limits = gsc_5420_limits,
1391 .num_limits = ARRAY_SIZE(gsc_5420_limits),
1392 };
1393
1394 static struct gsc_driverdata gsc_exynos5433_drvdata = {
1395 .clk_names = {"pclk", "aclk", "aclk_xiu", "aclk_gsclbend"},
1396 .num_clocks = 4,
1397 .limits = gsc_5433_limits,
1398 .num_limits = ARRAY_SIZE(gsc_5433_limits),
1399 };
1400
1401 static const struct of_device_id exynos_drm_gsc_of_match[] = {
1402 {
1403 .compatible = "samsung,exynos5-gsc",
1404 .data = &gsc_exynos5250_drvdata,
1405 }, {
1406 .compatible = "samsung,exynos5250-gsc",
1407 .data = &gsc_exynos5250_drvdata,
1408 }, {
1409 .compatible = "samsung,exynos5420-gsc",
1410 .data = &gsc_exynos5420_drvdata,
1411 }, {
1412 .compatible = "samsung,exynos5433-gsc",
1413 .data = &gsc_exynos5433_drvdata,
1414 }, {
1415 },
1416 };
1417 MODULE_DEVICE_TABLE(of, exynos_drm_gsc_of_match);
1418
1419 struct platform_driver gsc_driver = {
1420 .probe = gsc_probe,
1421 .remove = gsc_remove,
1422 .driver = {
1423 .name = "exynos-drm-gsc",
1424 .owner = THIS_MODULE,
1425 .pm = &gsc_pm_ops,
1426 .of_match_table = of_match_ptr(exynos_drm_gsc_of_match),
1427 },
1428 };
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