1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * Eunchul Kim <chulspro.kim@samsung.com>
6 * Jinyoung Jeon <jy0.jeon@samsung.com>
7 * Sangmin Lee <lsmin.lee@samsung.com>
10 #include <linux/clk.h>
11 #include <linux/component.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
19 #include <drm/exynos_drm.h>
21 #include "exynos_drm_drv.h"
22 #include "exynos_drm_ipp.h"
26 * GSC stands for General SCaler and
27 * supports image scaler/rotator and input/output DMA operations.
28 * input DMA reads image data from the memory.
29 * output DMA writes image data to memory.
30 * GSC supports image rotation and image effect functions.
34 #define GSC_MAX_CLOCKS 8
36 #define GSC_MAX_DST 16
37 #define GSC_RESET_TIMEOUT 50
38 #define GSC_BUF_STOP 1
39 #define GSC_BUF_START 2
41 #define GSC_WIDTH_ITU_709 1280
42 #define GSC_SC_UP_MAX_RATIO 65536
43 #define GSC_SC_DOWN_RATIO_7_8 74898
44 #define GSC_SC_DOWN_RATIO_6_8 87381
45 #define GSC_SC_DOWN_RATIO_5_8 104857
46 #define GSC_SC_DOWN_RATIO_4_8 131072
47 #define GSC_SC_DOWN_RATIO_3_8 174762
48 #define GSC_SC_DOWN_RATIO_2_8 262144
49 #define GSC_CROP_MAX 8192
50 #define GSC_CROP_MIN 32
51 #define GSC_SCALE_MAX 4224
52 #define GSC_SCALE_MIN 32
53 #define GSC_COEF_RATIO 7
54 #define GSC_COEF_PHASE 9
55 #define GSC_COEF_ATTR 16
56 #define GSC_COEF_H_8T 8
57 #define GSC_COEF_V_4T 4
58 #define GSC_COEF_DEPTH 3
59 #define GSC_AUTOSUSPEND_DELAY 2000
61 #define get_gsc_context(dev) dev_get_drvdata(dev)
62 #define gsc_read(offset) readl(ctx->regs + (offset))
63 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
66 * A structure of scaler.
68 * @range: narrow, wide.
69 * @pre_shfactor: pre sclaer shift factor.
70 * @pre_hratio: horizontal ratio of the prescaler.
71 * @pre_vratio: vertical ratio of the prescaler.
72 * @main_hratio: the main scaler's horizontal ratio.
73 * @main_vratio: the main scaler's vertical ratio.
80 unsigned long main_hratio
;
81 unsigned long main_vratio
;
85 * A structure of gsc context.
87 * @regs_res: register resources.
88 * @regs: memory mapped io registers.
89 * @gsc_clk: gsc gate clock.
90 * @sc: scaler infomations.
93 * @rotation: supports rotation of src.
96 struct exynos_drm_ipp ipp
;
97 struct drm_device
*drm_dev
;
99 struct exynos_drm_ipp_task
*task
;
100 struct exynos_drm_ipp_formats
*formats
;
101 unsigned int num_formats
;
103 struct resource
*regs_res
;
105 const char **clk_names
;
106 struct clk
*clocks
[GSC_MAX_CLOCKS
];
108 struct gsc_scaler sc
;
115 * struct gsc_driverdata - per device type driver data for init time.
117 * @limits: picture size limits array
118 * @clk_names: names of clocks needed by this variant
119 * @num_clocks: the number of clocks needed by this variant
121 struct gsc_driverdata
{
122 const struct drm_exynos_ipp_limit
*limits
;
124 const char *clk_names
[GSC_MAX_CLOCKS
];
128 /* 8-tap Filter Coefficient */
129 static const int h_coef_8t
[GSC_COEF_RATIO
][GSC_COEF_ATTR
][GSC_COEF_H_8T
] = {
130 { /* Ratio <= 65536 (~8:8) */
131 { 0, 0, 0, 128, 0, 0, 0, 0 },
132 { -1, 2, -6, 127, 7, -2, 1, 0 },
133 { -1, 4, -12, 125, 16, -5, 1, 0 },
134 { -1, 5, -15, 120, 25, -8, 2, 0 },
135 { -1, 6, -18, 114, 35, -10, 3, -1 },
136 { -1, 6, -20, 107, 46, -13, 4, -1 },
137 { -2, 7, -21, 99, 57, -16, 5, -1 },
138 { -1, 6, -20, 89, 68, -18, 5, -1 },
139 { -1, 6, -20, 79, 79, -20, 6, -1 },
140 { -1, 5, -18, 68, 89, -20, 6, -1 },
141 { -1, 5, -16, 57, 99, -21, 7, -2 },
142 { -1, 4, -13, 46, 107, -20, 6, -1 },
143 { -1, 3, -10, 35, 114, -18, 6, -1 },
144 { 0, 2, -8, 25, 120, -15, 5, -1 },
145 { 0, 1, -5, 16, 125, -12, 4, -1 },
146 { 0, 1, -2, 7, 127, -6, 2, -1 }
147 }, { /* 65536 < Ratio <= 74898 (~8:7) */
148 { 3, -8, 14, 111, 13, -8, 3, 0 },
149 { 2, -6, 7, 112, 21, -10, 3, -1 },
150 { 2, -4, 1, 110, 28, -12, 4, -1 },
151 { 1, -2, -3, 106, 36, -13, 4, -1 },
152 { 1, -1, -7, 103, 44, -15, 4, -1 },
153 { 1, 1, -11, 97, 53, -16, 4, -1 },
154 { 0, 2, -13, 91, 61, -16, 4, -1 },
155 { 0, 3, -15, 85, 69, -17, 4, -1 },
156 { 0, 3, -16, 77, 77, -16, 3, 0 },
157 { -1, 4, -17, 69, 85, -15, 3, 0 },
158 { -1, 4, -16, 61, 91, -13, 2, 0 },
159 { -1, 4, -16, 53, 97, -11, 1, 1 },
160 { -1, 4, -15, 44, 103, -7, -1, 1 },
161 { -1, 4, -13, 36, 106, -3, -2, 1 },
162 { -1, 4, -12, 28, 110, 1, -4, 2 },
163 { -1, 3, -10, 21, 112, 7, -6, 2 }
164 }, { /* 74898 < Ratio <= 87381 (~8:6) */
165 { 2, -11, 25, 96, 25, -11, 2, 0 },
166 { 2, -10, 19, 96, 31, -12, 2, 0 },
167 { 2, -9, 14, 94, 37, -12, 2, 0 },
168 { 2, -8, 10, 92, 43, -12, 1, 0 },
169 { 2, -7, 5, 90, 49, -12, 1, 0 },
170 { 2, -5, 1, 86, 55, -12, 0, 1 },
171 { 2, -4, -2, 82, 61, -11, -1, 1 },
172 { 1, -3, -5, 77, 67, -9, -1, 1 },
173 { 1, -2, -7, 72, 72, -7, -2, 1 },
174 { 1, -1, -9, 67, 77, -5, -3, 1 },
175 { 1, -1, -11, 61, 82, -2, -4, 2 },
176 { 1, 0, -12, 55, 86, 1, -5, 2 },
177 { 0, 1, -12, 49, 90, 5, -7, 2 },
178 { 0, 1, -12, 43, 92, 10, -8, 2 },
179 { 0, 2, -12, 37, 94, 14, -9, 2 },
180 { 0, 2, -12, 31, 96, 19, -10, 2 }
181 }, { /* 87381 < Ratio <= 104857 (~8:5) */
182 { -1, -8, 33, 80, 33, -8, -1, 0 },
183 { -1, -8, 28, 80, 37, -7, -2, 1 },
184 { 0, -8, 24, 79, 41, -7, -2, 1 },
185 { 0, -8, 20, 78, 46, -6, -3, 1 },
186 { 0, -8, 16, 76, 50, -4, -3, 1 },
187 { 0, -7, 13, 74, 54, -3, -4, 1 },
188 { 1, -7, 10, 71, 58, -1, -5, 1 },
189 { 1, -6, 6, 68, 62, 1, -5, 1 },
190 { 1, -6, 4, 65, 65, 4, -6, 1 },
191 { 1, -5, 1, 62, 68, 6, -6, 1 },
192 { 1, -5, -1, 58, 71, 10, -7, 1 },
193 { 1, -4, -3, 54, 74, 13, -7, 0 },
194 { 1, -3, -4, 50, 76, 16, -8, 0 },
195 { 1, -3, -6, 46, 78, 20, -8, 0 },
196 { 1, -2, -7, 41, 79, 24, -8, 0 },
197 { 1, -2, -7, 37, 80, 28, -8, -1 }
198 }, { /* 104857 < Ratio <= 131072 (~8:4) */
199 { -3, 0, 35, 64, 35, 0, -3, 0 },
200 { -3, -1, 32, 64, 38, 1, -3, 0 },
201 { -2, -2, 29, 63, 41, 2, -3, 0 },
202 { -2, -3, 27, 63, 43, 4, -4, 0 },
203 { -2, -3, 24, 61, 46, 6, -4, 0 },
204 { -2, -3, 21, 60, 49, 7, -4, 0 },
205 { -1, -4, 19, 59, 51, 9, -4, -1 },
206 { -1, -4, 16, 57, 53, 12, -4, -1 },
207 { -1, -4, 14, 55, 55, 14, -4, -1 },
208 { -1, -4, 12, 53, 57, 16, -4, -1 },
209 { -1, -4, 9, 51, 59, 19, -4, -1 },
210 { 0, -4, 7, 49, 60, 21, -3, -2 },
211 { 0, -4, 6, 46, 61, 24, -3, -2 },
212 { 0, -4, 4, 43, 63, 27, -3, -2 },
213 { 0, -3, 2, 41, 63, 29, -2, -2 },
214 { 0, -3, 1, 38, 64, 32, -1, -3 }
215 }, { /* 131072 < Ratio <= 174762 (~8:3) */
216 { -1, 8, 33, 48, 33, 8, -1, 0 },
217 { -1, 7, 31, 49, 35, 9, -1, -1 },
218 { -1, 6, 30, 49, 36, 10, -1, -1 },
219 { -1, 5, 28, 48, 38, 12, -1, -1 },
220 { -1, 4, 26, 48, 39, 13, 0, -1 },
221 { -1, 3, 24, 47, 41, 15, 0, -1 },
222 { -1, 2, 23, 47, 42, 16, 0, -1 },
223 { -1, 2, 21, 45, 43, 18, 1, -1 },
224 { -1, 1, 19, 45, 45, 19, 1, -1 },
225 { -1, 1, 18, 43, 45, 21, 2, -1 },
226 { -1, 0, 16, 42, 47, 23, 2, -1 },
227 { -1, 0, 15, 41, 47, 24, 3, -1 },
228 { -1, 0, 13, 39, 48, 26, 4, -1 },
229 { -1, -1, 12, 38, 48, 28, 5, -1 },
230 { -1, -1, 10, 36, 49, 30, 6, -1 },
231 { -1, -1, 9, 35, 49, 31, 7, -1 }
232 }, { /* 174762 < Ratio <= 262144 (~8:2) */
233 { 2, 13, 30, 38, 30, 13, 2, 0 },
234 { 2, 12, 29, 38, 30, 14, 3, 0 },
235 { 2, 11, 28, 38, 31, 15, 3, 0 },
236 { 2, 10, 26, 38, 32, 16, 4, 0 },
237 { 1, 10, 26, 37, 33, 17, 4, 0 },
238 { 1, 9, 24, 37, 34, 18, 5, 0 },
239 { 1, 8, 24, 37, 34, 19, 5, 0 },
240 { 1, 7, 22, 36, 35, 20, 6, 1 },
241 { 1, 6, 21, 36, 36, 21, 6, 1 },
242 { 1, 6, 20, 35, 36, 22, 7, 1 },
243 { 0, 5, 19, 34, 37, 24, 8, 1 },
244 { 0, 5, 18, 34, 37, 24, 9, 1 },
245 { 0, 4, 17, 33, 37, 26, 10, 1 },
246 { 0, 4, 16, 32, 38, 26, 10, 2 },
247 { 0, 3, 15, 31, 38, 28, 11, 2 },
248 { 0, 3, 14, 30, 38, 29, 12, 2 }
252 /* 4-tap Filter Coefficient */
253 static const int v_coef_4t
[GSC_COEF_RATIO
][GSC_COEF_ATTR
][GSC_COEF_V_4T
] = {
254 { /* Ratio <= 65536 (~8:8) */
271 }, { /* 65536 < Ratio <= 74898 (~8:7) */
288 }, { /* 74898 < Ratio <= 87381 (~8:6) */
305 }, { /* 87381 < Ratio <= 104857 (~8:5) */
322 }, { /* 104857 < Ratio <= 131072 (~8:4) */
339 }, { /* 131072 < Ratio <= 174762 (~8:3) */
356 }, { /* 174762 < Ratio <= 262144 (~8:2) */
376 static int gsc_sw_reset(struct gsc_context
*ctx
)
379 int count
= GSC_RESET_TIMEOUT
;
382 cfg
= (GSC_SW_RESET_SRESET
);
383 gsc_write(cfg
, GSC_SW_RESET
);
385 /* wait s/w reset complete */
387 cfg
= gsc_read(GSC_SW_RESET
);
390 usleep_range(1000, 2000);
394 DRM_DEV_ERROR(ctx
->dev
, "failed to reset gsc h/w.\n");
399 cfg
= gsc_read(GSC_IN_BASE_ADDR_Y_MASK
);
400 cfg
|= (GSC_IN_BASE_ADDR_MASK
|
401 GSC_IN_BASE_ADDR_PINGPONG(0));
402 gsc_write(cfg
, GSC_IN_BASE_ADDR_Y_MASK
);
403 gsc_write(cfg
, GSC_IN_BASE_ADDR_CB_MASK
);
404 gsc_write(cfg
, GSC_IN_BASE_ADDR_CR_MASK
);
406 cfg
= gsc_read(GSC_OUT_BASE_ADDR_Y_MASK
);
407 cfg
|= (GSC_OUT_BASE_ADDR_MASK
|
408 GSC_OUT_BASE_ADDR_PINGPONG(0));
409 gsc_write(cfg
, GSC_OUT_BASE_ADDR_Y_MASK
);
410 gsc_write(cfg
, GSC_OUT_BASE_ADDR_CB_MASK
);
411 gsc_write(cfg
, GSC_OUT_BASE_ADDR_CR_MASK
);
416 static void gsc_handle_irq(struct gsc_context
*ctx
, bool enable
,
417 bool overflow
, bool done
)
421 DRM_DEV_DEBUG_KMS(ctx
->dev
, "enable[%d]overflow[%d]level[%d]\n",
422 enable
, overflow
, done
);
424 cfg
= gsc_read(GSC_IRQ
);
425 cfg
|= (GSC_IRQ_OR_MASK
| GSC_IRQ_FRMDONE_MASK
);
428 cfg
|= GSC_IRQ_ENABLE
;
430 cfg
&= ~GSC_IRQ_ENABLE
;
433 cfg
&= ~GSC_IRQ_OR_MASK
;
435 cfg
|= GSC_IRQ_OR_MASK
;
438 cfg
&= ~GSC_IRQ_FRMDONE_MASK
;
440 cfg
|= GSC_IRQ_FRMDONE_MASK
;
442 gsc_write(cfg
, GSC_IRQ
);
446 static void gsc_src_set_fmt(struct gsc_context
*ctx
, u32 fmt
, bool tiled
)
450 DRM_DEV_DEBUG_KMS(ctx
->dev
, "fmt[0x%x]\n", fmt
);
452 cfg
= gsc_read(GSC_IN_CON
);
453 cfg
&= ~(GSC_IN_RGB_TYPE_MASK
| GSC_IN_YUV422_1P_ORDER_MASK
|
454 GSC_IN_CHROMA_ORDER_MASK
| GSC_IN_FORMAT_MASK
|
455 GSC_IN_TILE_TYPE_MASK
| GSC_IN_TILE_MODE
|
456 GSC_IN_CHROM_STRIDE_SEL_MASK
| GSC_IN_RB_SWAP_MASK
);
459 case DRM_FORMAT_RGB565
:
460 cfg
|= GSC_IN_RGB565
;
462 case DRM_FORMAT_XRGB8888
:
463 case DRM_FORMAT_ARGB8888
:
464 cfg
|= GSC_IN_XRGB8888
;
466 case DRM_FORMAT_BGRX8888
:
467 cfg
|= (GSC_IN_XRGB8888
| GSC_IN_RB_SWAP
);
469 case DRM_FORMAT_YUYV
:
470 cfg
|= (GSC_IN_YUV422_1P
|
471 GSC_IN_YUV422_1P_ORDER_LSB_Y
|
472 GSC_IN_CHROMA_ORDER_CBCR
);
474 case DRM_FORMAT_YVYU
:
475 cfg
|= (GSC_IN_YUV422_1P
|
476 GSC_IN_YUV422_1P_ORDER_LSB_Y
|
477 GSC_IN_CHROMA_ORDER_CRCB
);
479 case DRM_FORMAT_UYVY
:
480 cfg
|= (GSC_IN_YUV422_1P
|
481 GSC_IN_YUV422_1P_OEDER_LSB_C
|
482 GSC_IN_CHROMA_ORDER_CBCR
);
484 case DRM_FORMAT_VYUY
:
485 cfg
|= (GSC_IN_YUV422_1P
|
486 GSC_IN_YUV422_1P_OEDER_LSB_C
|
487 GSC_IN_CHROMA_ORDER_CRCB
);
489 case DRM_FORMAT_NV21
:
490 cfg
|= (GSC_IN_CHROMA_ORDER_CRCB
| GSC_IN_YUV420_2P
);
492 case DRM_FORMAT_NV61
:
493 cfg
|= (GSC_IN_CHROMA_ORDER_CRCB
| GSC_IN_YUV422_2P
);
495 case DRM_FORMAT_YUV422
:
496 cfg
|= GSC_IN_YUV422_3P
;
498 case DRM_FORMAT_YUV420
:
499 cfg
|= (GSC_IN_CHROMA_ORDER_CBCR
| GSC_IN_YUV420_3P
);
501 case DRM_FORMAT_YVU420
:
502 cfg
|= (GSC_IN_CHROMA_ORDER_CRCB
| GSC_IN_YUV420_3P
);
504 case DRM_FORMAT_NV12
:
505 cfg
|= (GSC_IN_CHROMA_ORDER_CBCR
| GSC_IN_YUV420_2P
);
507 case DRM_FORMAT_NV16
:
508 cfg
|= (GSC_IN_CHROMA_ORDER_CBCR
| GSC_IN_YUV422_2P
);
513 cfg
|= (GSC_IN_TILE_C_16x8
| GSC_IN_TILE_MODE
);
515 gsc_write(cfg
, GSC_IN_CON
);
518 static void gsc_src_set_transf(struct gsc_context
*ctx
, unsigned int rotation
)
520 unsigned int degree
= rotation
& DRM_MODE_ROTATE_MASK
;
523 cfg
= gsc_read(GSC_IN_CON
);
524 cfg
&= ~GSC_IN_ROT_MASK
;
527 case DRM_MODE_ROTATE_0
:
528 if (rotation
& DRM_MODE_REFLECT_X
)
529 cfg
|= GSC_IN_ROT_XFLIP
;
530 if (rotation
& DRM_MODE_REFLECT_Y
)
531 cfg
|= GSC_IN_ROT_YFLIP
;
533 case DRM_MODE_ROTATE_90
:
534 cfg
|= GSC_IN_ROT_90
;
535 if (rotation
& DRM_MODE_REFLECT_X
)
536 cfg
|= GSC_IN_ROT_XFLIP
;
537 if (rotation
& DRM_MODE_REFLECT_Y
)
538 cfg
|= GSC_IN_ROT_YFLIP
;
540 case DRM_MODE_ROTATE_180
:
541 cfg
|= GSC_IN_ROT_180
;
542 if (rotation
& DRM_MODE_REFLECT_X
)
543 cfg
&= ~GSC_IN_ROT_XFLIP
;
544 if (rotation
& DRM_MODE_REFLECT_Y
)
545 cfg
&= ~GSC_IN_ROT_YFLIP
;
547 case DRM_MODE_ROTATE_270
:
548 cfg
|= GSC_IN_ROT_270
;
549 if (rotation
& DRM_MODE_REFLECT_X
)
550 cfg
&= ~GSC_IN_ROT_XFLIP
;
551 if (rotation
& DRM_MODE_REFLECT_Y
)
552 cfg
&= ~GSC_IN_ROT_YFLIP
;
556 gsc_write(cfg
, GSC_IN_CON
);
558 ctx
->rotation
= (cfg
& GSC_IN_ROT_90
) ? 1 : 0;
561 static void gsc_src_set_size(struct gsc_context
*ctx
,
562 struct exynos_drm_ipp_buffer
*buf
)
564 struct gsc_scaler
*sc
= &ctx
->sc
;
568 cfg
= (GSC_SRCIMG_OFFSET_X(buf
->rect
.x
) |
569 GSC_SRCIMG_OFFSET_Y(buf
->rect
.y
));
570 gsc_write(cfg
, GSC_SRCIMG_OFFSET
);
573 cfg
= (GSC_CROPPED_WIDTH(buf
->rect
.w
) |
574 GSC_CROPPED_HEIGHT(buf
->rect
.h
));
575 gsc_write(cfg
, GSC_CROPPED_SIZE
);
578 cfg
= gsc_read(GSC_SRCIMG_SIZE
);
579 cfg
&= ~(GSC_SRCIMG_HEIGHT_MASK
|
580 GSC_SRCIMG_WIDTH_MASK
);
582 cfg
|= (GSC_SRCIMG_WIDTH(buf
->buf
.pitch
[0] / buf
->format
->cpp
[0]) |
583 GSC_SRCIMG_HEIGHT(buf
->buf
.height
));
585 gsc_write(cfg
, GSC_SRCIMG_SIZE
);
587 cfg
= gsc_read(GSC_IN_CON
);
588 cfg
&= ~GSC_IN_RGB_TYPE_MASK
;
590 if (buf
->rect
.w
>= GSC_WIDTH_ITU_709
)
592 cfg
|= GSC_IN_RGB_HD_WIDE
;
594 cfg
|= GSC_IN_RGB_HD_NARROW
;
597 cfg
|= GSC_IN_RGB_SD_WIDE
;
599 cfg
|= GSC_IN_RGB_SD_NARROW
;
601 gsc_write(cfg
, GSC_IN_CON
);
604 static void gsc_src_set_buf_seq(struct gsc_context
*ctx
, u32 buf_id
,
607 bool masked
= !enqueue
;
609 u32 mask
= 0x00000001 << buf_id
;
611 /* mask register set */
612 cfg
= gsc_read(GSC_IN_BASE_ADDR_Y_MASK
);
616 cfg
|= masked
<< buf_id
;
617 gsc_write(cfg
, GSC_IN_BASE_ADDR_Y_MASK
);
618 gsc_write(cfg
, GSC_IN_BASE_ADDR_CB_MASK
);
619 gsc_write(cfg
, GSC_IN_BASE_ADDR_CR_MASK
);
622 static void gsc_src_set_addr(struct gsc_context
*ctx
, u32 buf_id
,
623 struct exynos_drm_ipp_buffer
*buf
)
625 /* address register set */
626 gsc_write(buf
->dma_addr
[0], GSC_IN_BASE_ADDR_Y(buf_id
));
627 gsc_write(buf
->dma_addr
[1], GSC_IN_BASE_ADDR_CB(buf_id
));
628 gsc_write(buf
->dma_addr
[2], GSC_IN_BASE_ADDR_CR(buf_id
));
630 gsc_src_set_buf_seq(ctx
, buf_id
, true);
633 static void gsc_dst_set_fmt(struct gsc_context
*ctx
, u32 fmt
, bool tiled
)
637 DRM_DEV_DEBUG_KMS(ctx
->dev
, "fmt[0x%x]\n", fmt
);
639 cfg
= gsc_read(GSC_OUT_CON
);
640 cfg
&= ~(GSC_OUT_RGB_TYPE_MASK
| GSC_OUT_YUV422_1P_ORDER_MASK
|
641 GSC_OUT_CHROMA_ORDER_MASK
| GSC_OUT_FORMAT_MASK
|
642 GSC_OUT_CHROM_STRIDE_SEL_MASK
| GSC_OUT_RB_SWAP_MASK
|
643 GSC_OUT_GLOBAL_ALPHA_MASK
);
646 case DRM_FORMAT_RGB565
:
647 cfg
|= GSC_OUT_RGB565
;
649 case DRM_FORMAT_ARGB8888
:
650 case DRM_FORMAT_XRGB8888
:
651 cfg
|= (GSC_OUT_XRGB8888
| GSC_OUT_GLOBAL_ALPHA(0xff));
653 case DRM_FORMAT_BGRX8888
:
654 cfg
|= (GSC_OUT_XRGB8888
| GSC_OUT_RB_SWAP
);
656 case DRM_FORMAT_YUYV
:
657 cfg
|= (GSC_OUT_YUV422_1P
|
658 GSC_OUT_YUV422_1P_ORDER_LSB_Y
|
659 GSC_OUT_CHROMA_ORDER_CBCR
);
661 case DRM_FORMAT_YVYU
:
662 cfg
|= (GSC_OUT_YUV422_1P
|
663 GSC_OUT_YUV422_1P_ORDER_LSB_Y
|
664 GSC_OUT_CHROMA_ORDER_CRCB
);
666 case DRM_FORMAT_UYVY
:
667 cfg
|= (GSC_OUT_YUV422_1P
|
668 GSC_OUT_YUV422_1P_OEDER_LSB_C
|
669 GSC_OUT_CHROMA_ORDER_CBCR
);
671 case DRM_FORMAT_VYUY
:
672 cfg
|= (GSC_OUT_YUV422_1P
|
673 GSC_OUT_YUV422_1P_OEDER_LSB_C
|
674 GSC_OUT_CHROMA_ORDER_CRCB
);
676 case DRM_FORMAT_NV21
:
677 cfg
|= (GSC_OUT_CHROMA_ORDER_CRCB
| GSC_OUT_YUV420_2P
);
679 case DRM_FORMAT_NV61
:
680 cfg
|= (GSC_OUT_CHROMA_ORDER_CRCB
| GSC_OUT_YUV422_2P
);
682 case DRM_FORMAT_YUV422
:
683 cfg
|= GSC_OUT_YUV422_3P
;
685 case DRM_FORMAT_YUV420
:
686 cfg
|= (GSC_OUT_CHROMA_ORDER_CBCR
| GSC_OUT_YUV420_3P
);
688 case DRM_FORMAT_YVU420
:
689 cfg
|= (GSC_OUT_CHROMA_ORDER_CRCB
| GSC_OUT_YUV420_3P
);
691 case DRM_FORMAT_NV12
:
692 cfg
|= (GSC_OUT_CHROMA_ORDER_CBCR
| GSC_OUT_YUV420_2P
);
694 case DRM_FORMAT_NV16
:
695 cfg
|= (GSC_OUT_CHROMA_ORDER_CBCR
| GSC_OUT_YUV422_2P
);
700 cfg
|= (GSC_IN_TILE_C_16x8
| GSC_OUT_TILE_MODE
);
702 gsc_write(cfg
, GSC_OUT_CON
);
705 static int gsc_get_ratio_shift(struct gsc_context
*ctx
, u32 src
, u32 dst
,
708 DRM_DEV_DEBUG_KMS(ctx
->dev
, "src[%d]dst[%d]\n", src
, dst
);
710 if (src
>= dst
* 8) {
711 DRM_DEV_ERROR(ctx
->dev
, "failed to make ratio and shift.\n");
713 } else if (src
>= dst
* 4)
715 else if (src
>= dst
* 2)
723 static void gsc_get_prescaler_shfactor(u32 hratio
, u32 vratio
, u32
*shfactor
)
725 if (hratio
== 4 && vratio
== 4)
727 else if ((hratio
== 4 && vratio
== 2) ||
728 (hratio
== 2 && vratio
== 4))
730 else if ((hratio
== 4 && vratio
== 1) ||
731 (hratio
== 1 && vratio
== 4) ||
732 (hratio
== 2 && vratio
== 2))
734 else if (hratio
== 1 && vratio
== 1)
740 static int gsc_set_prescaler(struct gsc_context
*ctx
, struct gsc_scaler
*sc
,
741 struct drm_exynos_ipp_task_rect
*src
,
742 struct drm_exynos_ipp_task_rect
*dst
)
745 u32 src_w
, src_h
, dst_w
, dst_h
;
759 ret
= gsc_get_ratio_shift(ctx
, src_w
, dst_w
, &sc
->pre_hratio
);
761 DRM_DEV_ERROR(ctx
->dev
, "failed to get ratio horizontal.\n");
765 ret
= gsc_get_ratio_shift(ctx
, src_h
, dst_h
, &sc
->pre_vratio
);
767 DRM_DEV_ERROR(ctx
->dev
, "failed to get ratio vertical.\n");
771 DRM_DEV_DEBUG_KMS(ctx
->dev
, "pre_hratio[%d]pre_vratio[%d]\n",
772 sc
->pre_hratio
, sc
->pre_vratio
);
774 sc
->main_hratio
= (src_w
<< 16) / dst_w
;
775 sc
->main_vratio
= (src_h
<< 16) / dst_h
;
777 DRM_DEV_DEBUG_KMS(ctx
->dev
, "main_hratio[%ld]main_vratio[%ld]\n",
778 sc
->main_hratio
, sc
->main_vratio
);
780 gsc_get_prescaler_shfactor(sc
->pre_hratio
, sc
->pre_vratio
,
783 DRM_DEV_DEBUG_KMS(ctx
->dev
, "pre_shfactor[%d]\n", sc
->pre_shfactor
);
785 cfg
= (GSC_PRESC_SHFACTOR(sc
->pre_shfactor
) |
786 GSC_PRESC_H_RATIO(sc
->pre_hratio
) |
787 GSC_PRESC_V_RATIO(sc
->pre_vratio
));
788 gsc_write(cfg
, GSC_PRE_SCALE_RATIO
);
793 static void gsc_set_h_coef(struct gsc_context
*ctx
, unsigned long main_hratio
)
795 int i
, j
, k
, sc_ratio
;
797 if (main_hratio
<= GSC_SC_UP_MAX_RATIO
)
799 else if (main_hratio
<= GSC_SC_DOWN_RATIO_7_8
)
801 else if (main_hratio
<= GSC_SC_DOWN_RATIO_6_8
)
803 else if (main_hratio
<= GSC_SC_DOWN_RATIO_5_8
)
805 else if (main_hratio
<= GSC_SC_DOWN_RATIO_4_8
)
807 else if (main_hratio
<= GSC_SC_DOWN_RATIO_3_8
)
812 for (i
= 0; i
< GSC_COEF_PHASE
; i
++)
813 for (j
= 0; j
< GSC_COEF_H_8T
; j
++)
814 for (k
= 0; k
< GSC_COEF_DEPTH
; k
++)
815 gsc_write(h_coef_8t
[sc_ratio
][i
][j
],
819 static void gsc_set_v_coef(struct gsc_context
*ctx
, unsigned long main_vratio
)
821 int i
, j
, k
, sc_ratio
;
823 if (main_vratio
<= GSC_SC_UP_MAX_RATIO
)
825 else if (main_vratio
<= GSC_SC_DOWN_RATIO_7_8
)
827 else if (main_vratio
<= GSC_SC_DOWN_RATIO_6_8
)
829 else if (main_vratio
<= GSC_SC_DOWN_RATIO_5_8
)
831 else if (main_vratio
<= GSC_SC_DOWN_RATIO_4_8
)
833 else if (main_vratio
<= GSC_SC_DOWN_RATIO_3_8
)
838 for (i
= 0; i
< GSC_COEF_PHASE
; i
++)
839 for (j
= 0; j
< GSC_COEF_V_4T
; j
++)
840 for (k
= 0; k
< GSC_COEF_DEPTH
; k
++)
841 gsc_write(v_coef_4t
[sc_ratio
][i
][j
],
845 static void gsc_set_scaler(struct gsc_context
*ctx
, struct gsc_scaler
*sc
)
849 DRM_DEV_DEBUG_KMS(ctx
->dev
, "main_hratio[%ld]main_vratio[%ld]\n",
850 sc
->main_hratio
, sc
->main_vratio
);
852 gsc_set_h_coef(ctx
, sc
->main_hratio
);
853 cfg
= GSC_MAIN_H_RATIO_VALUE(sc
->main_hratio
);
854 gsc_write(cfg
, GSC_MAIN_H_RATIO
);
856 gsc_set_v_coef(ctx
, sc
->main_vratio
);
857 cfg
= GSC_MAIN_V_RATIO_VALUE(sc
->main_vratio
);
858 gsc_write(cfg
, GSC_MAIN_V_RATIO
);
861 static void gsc_dst_set_size(struct gsc_context
*ctx
,
862 struct exynos_drm_ipp_buffer
*buf
)
864 struct gsc_scaler
*sc
= &ctx
->sc
;
868 cfg
= (GSC_DSTIMG_OFFSET_X(buf
->rect
.x
) |
869 GSC_DSTIMG_OFFSET_Y(buf
->rect
.y
));
870 gsc_write(cfg
, GSC_DSTIMG_OFFSET
);
874 cfg
= (GSC_SCALED_WIDTH(buf
->rect
.h
) |
875 GSC_SCALED_HEIGHT(buf
->rect
.w
));
877 cfg
= (GSC_SCALED_WIDTH(buf
->rect
.w
) |
878 GSC_SCALED_HEIGHT(buf
->rect
.h
));
879 gsc_write(cfg
, GSC_SCALED_SIZE
);
882 cfg
= gsc_read(GSC_DSTIMG_SIZE
);
883 cfg
&= ~(GSC_DSTIMG_HEIGHT_MASK
| GSC_DSTIMG_WIDTH_MASK
);
884 cfg
|= GSC_DSTIMG_WIDTH(buf
->buf
.pitch
[0] / buf
->format
->cpp
[0]) |
885 GSC_DSTIMG_HEIGHT(buf
->buf
.height
);
886 gsc_write(cfg
, GSC_DSTIMG_SIZE
);
888 cfg
= gsc_read(GSC_OUT_CON
);
889 cfg
&= ~GSC_OUT_RGB_TYPE_MASK
;
891 if (buf
->rect
.w
>= GSC_WIDTH_ITU_709
)
893 cfg
|= GSC_OUT_RGB_HD_WIDE
;
895 cfg
|= GSC_OUT_RGB_HD_NARROW
;
898 cfg
|= GSC_OUT_RGB_SD_WIDE
;
900 cfg
|= GSC_OUT_RGB_SD_NARROW
;
902 gsc_write(cfg
, GSC_OUT_CON
);
905 static int gsc_dst_get_buf_seq(struct gsc_context
*ctx
)
907 u32 cfg
, i
, buf_num
= GSC_REG_SZ
;
908 u32 mask
= 0x00000001;
910 cfg
= gsc_read(GSC_OUT_BASE_ADDR_Y_MASK
);
912 for (i
= 0; i
< GSC_REG_SZ
; i
++)
913 if (cfg
& (mask
<< i
))
916 DRM_DEV_DEBUG_KMS(ctx
->dev
, "buf_num[%d]\n", buf_num
);
921 static void gsc_dst_set_buf_seq(struct gsc_context
*ctx
, u32 buf_id
,
924 bool masked
= !enqueue
;
926 u32 mask
= 0x00000001 << buf_id
;
928 /* mask register set */
929 cfg
= gsc_read(GSC_OUT_BASE_ADDR_Y_MASK
);
933 cfg
|= masked
<< buf_id
;
934 gsc_write(cfg
, GSC_OUT_BASE_ADDR_Y_MASK
);
935 gsc_write(cfg
, GSC_OUT_BASE_ADDR_CB_MASK
);
936 gsc_write(cfg
, GSC_OUT_BASE_ADDR_CR_MASK
);
938 /* interrupt enable */
939 if (enqueue
&& gsc_dst_get_buf_seq(ctx
) >= GSC_BUF_START
)
940 gsc_handle_irq(ctx
, true, false, true);
942 /* interrupt disable */
943 if (!enqueue
&& gsc_dst_get_buf_seq(ctx
) <= GSC_BUF_STOP
)
944 gsc_handle_irq(ctx
, false, false, true);
947 static void gsc_dst_set_addr(struct gsc_context
*ctx
,
948 u32 buf_id
, struct exynos_drm_ipp_buffer
*buf
)
950 /* address register set */
951 gsc_write(buf
->dma_addr
[0], GSC_OUT_BASE_ADDR_Y(buf_id
));
952 gsc_write(buf
->dma_addr
[1], GSC_OUT_BASE_ADDR_CB(buf_id
));
953 gsc_write(buf
->dma_addr
[2], GSC_OUT_BASE_ADDR_CR(buf_id
));
955 gsc_dst_set_buf_seq(ctx
, buf_id
, true);
958 static int gsc_get_src_buf_index(struct gsc_context
*ctx
)
960 u32 cfg
, curr_index
, i
;
961 u32 buf_id
= GSC_MAX_SRC
;
963 DRM_DEV_DEBUG_KMS(ctx
->dev
, "gsc id[%d]\n", ctx
->id
);
965 cfg
= gsc_read(GSC_IN_BASE_ADDR_Y_MASK
);
966 curr_index
= GSC_IN_CURR_GET_INDEX(cfg
);
968 for (i
= curr_index
; i
< GSC_MAX_SRC
; i
++) {
969 if (!((cfg
>> i
) & 0x1)) {
975 DRM_DEV_DEBUG_KMS(ctx
->dev
, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg
,
978 if (buf_id
== GSC_MAX_SRC
) {
979 DRM_DEV_ERROR(ctx
->dev
, "failed to get in buffer index.\n");
983 gsc_src_set_buf_seq(ctx
, buf_id
, false);
988 static int gsc_get_dst_buf_index(struct gsc_context
*ctx
)
990 u32 cfg
, curr_index
, i
;
991 u32 buf_id
= GSC_MAX_DST
;
993 DRM_DEV_DEBUG_KMS(ctx
->dev
, "gsc id[%d]\n", ctx
->id
);
995 cfg
= gsc_read(GSC_OUT_BASE_ADDR_Y_MASK
);
996 curr_index
= GSC_OUT_CURR_GET_INDEX(cfg
);
998 for (i
= curr_index
; i
< GSC_MAX_DST
; i
++) {
999 if (!((cfg
>> i
) & 0x1)) {
1005 if (buf_id
== GSC_MAX_DST
) {
1006 DRM_DEV_ERROR(ctx
->dev
, "failed to get out buffer index.\n");
1010 gsc_dst_set_buf_seq(ctx
, buf_id
, false);
1012 DRM_DEV_DEBUG_KMS(ctx
->dev
, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg
,
1013 curr_index
, buf_id
);
1018 static irqreturn_t
gsc_irq_handler(int irq
, void *dev_id
)
1020 struct gsc_context
*ctx
= dev_id
;
1024 DRM_DEV_DEBUG_KMS(ctx
->dev
, "gsc id[%d]\n", ctx
->id
);
1026 status
= gsc_read(GSC_IRQ
);
1027 if (status
& GSC_IRQ_STATUS_OR_IRQ
) {
1028 dev_err(ctx
->dev
, "occurred overflow at %d, status 0x%x.\n",
1033 if (status
& GSC_IRQ_STATUS_OR_FRM_DONE
) {
1034 int src_buf_id
, dst_buf_id
;
1036 dev_dbg(ctx
->dev
, "occurred frame done at %d, status 0x%x.\n",
1039 src_buf_id
= gsc_get_src_buf_index(ctx
);
1040 dst_buf_id
= gsc_get_dst_buf_index(ctx
);
1042 DRM_DEV_DEBUG_KMS(ctx
->dev
, "buf_id_src[%d]buf_id_dst[%d]\n",
1043 src_buf_id
, dst_buf_id
);
1045 if (src_buf_id
< 0 || dst_buf_id
< 0)
1050 struct exynos_drm_ipp_task
*task
= ctx
->task
;
1053 pm_runtime_mark_last_busy(ctx
->dev
);
1054 pm_runtime_put_autosuspend(ctx
->dev
);
1055 exynos_drm_ipp_task_done(task
, err
);
1061 static int gsc_reset(struct gsc_context
*ctx
)
1063 struct gsc_scaler
*sc
= &ctx
->sc
;
1066 /* reset h/w block */
1067 ret
= gsc_sw_reset(ctx
);
1069 dev_err(ctx
->dev
, "failed to reset hardware.\n");
1073 /* scaler setting */
1074 memset(&ctx
->sc
, 0x0, sizeof(ctx
->sc
));
1080 static void gsc_start(struct gsc_context
*ctx
)
1084 gsc_handle_irq(ctx
, true, false, true);
1086 /* enable one shot */
1087 cfg
= gsc_read(GSC_ENABLE
);
1088 cfg
&= ~(GSC_ENABLE_ON_CLEAR_MASK
|
1089 GSC_ENABLE_CLK_GATE_MODE_MASK
);
1090 cfg
|= GSC_ENABLE_ON_CLEAR_ONESHOT
;
1091 gsc_write(cfg
, GSC_ENABLE
);
1093 /* src dma memory */
1094 cfg
= gsc_read(GSC_IN_CON
);
1095 cfg
&= ~(GSC_IN_PATH_MASK
| GSC_IN_LOCAL_SEL_MASK
);
1096 cfg
|= GSC_IN_PATH_MEMORY
;
1097 gsc_write(cfg
, GSC_IN_CON
);
1099 /* dst dma memory */
1100 cfg
= gsc_read(GSC_OUT_CON
);
1101 cfg
|= GSC_OUT_PATH_MEMORY
;
1102 gsc_write(cfg
, GSC_OUT_CON
);
1104 gsc_set_scaler(ctx
, &ctx
->sc
);
1106 cfg
= gsc_read(GSC_ENABLE
);
1107 cfg
|= GSC_ENABLE_ON
;
1108 gsc_write(cfg
, GSC_ENABLE
);
1111 static int gsc_commit(struct exynos_drm_ipp
*ipp
,
1112 struct exynos_drm_ipp_task
*task
)
1114 struct gsc_context
*ctx
= container_of(ipp
, struct gsc_context
, ipp
);
1117 pm_runtime_get_sync(ctx
->dev
);
1120 ret
= gsc_reset(ctx
);
1122 pm_runtime_put_autosuspend(ctx
->dev
);
1127 gsc_src_set_fmt(ctx
, task
->src
.buf
.fourcc
, task
->src
.buf
.modifier
);
1128 gsc_src_set_transf(ctx
, task
->transform
.rotation
);
1129 gsc_src_set_size(ctx
, &task
->src
);
1130 gsc_src_set_addr(ctx
, 0, &task
->src
);
1131 gsc_dst_set_fmt(ctx
, task
->dst
.buf
.fourcc
, task
->dst
.buf
.modifier
);
1132 gsc_dst_set_size(ctx
, &task
->dst
);
1133 gsc_dst_set_addr(ctx
, 0, &task
->dst
);
1134 gsc_set_prescaler(ctx
, &ctx
->sc
, &task
->src
.rect
, &task
->dst
.rect
);
1140 static void gsc_abort(struct exynos_drm_ipp
*ipp
,
1141 struct exynos_drm_ipp_task
*task
)
1143 struct gsc_context
*ctx
=
1144 container_of(ipp
, struct gsc_context
, ipp
);
1148 struct exynos_drm_ipp_task
*task
= ctx
->task
;
1151 pm_runtime_mark_last_busy(ctx
->dev
);
1152 pm_runtime_put_autosuspend(ctx
->dev
);
1153 exynos_drm_ipp_task_done(task
, -EIO
);
1157 static struct exynos_drm_ipp_funcs ipp_funcs
= {
1158 .commit
= gsc_commit
,
1162 static int gsc_bind(struct device
*dev
, struct device
*master
, void *data
)
1164 struct gsc_context
*ctx
= dev_get_drvdata(dev
);
1165 struct drm_device
*drm_dev
= data
;
1166 struct exynos_drm_ipp
*ipp
= &ctx
->ipp
;
1168 ctx
->drm_dev
= drm_dev
;
1169 ctx
->drm_dev
= drm_dev
;
1170 exynos_drm_register_dma(drm_dev
, dev
);
1172 exynos_drm_ipp_register(dev
, ipp
, &ipp_funcs
,
1173 DRM_EXYNOS_IPP_CAP_CROP
| DRM_EXYNOS_IPP_CAP_ROTATE
|
1174 DRM_EXYNOS_IPP_CAP_SCALE
| DRM_EXYNOS_IPP_CAP_CONVERT
,
1175 ctx
->formats
, ctx
->num_formats
, "gsc");
1177 dev_info(dev
, "The exynos gscaler has been probed successfully\n");
1182 static void gsc_unbind(struct device
*dev
, struct device
*master
,
1185 struct gsc_context
*ctx
= dev_get_drvdata(dev
);
1186 struct drm_device
*drm_dev
= data
;
1187 struct exynos_drm_ipp
*ipp
= &ctx
->ipp
;
1189 exynos_drm_ipp_unregister(dev
, ipp
);
1190 exynos_drm_unregister_dma(drm_dev
, dev
);
1193 static const struct component_ops gsc_component_ops
= {
1195 .unbind
= gsc_unbind
,
1198 static const unsigned int gsc_formats
[] = {
1199 DRM_FORMAT_ARGB8888
,
1200 DRM_FORMAT_XRGB8888
, DRM_FORMAT_RGB565
, DRM_FORMAT_BGRX8888
,
1201 DRM_FORMAT_NV12
, DRM_FORMAT_NV16
, DRM_FORMAT_NV21
, DRM_FORMAT_NV61
,
1202 DRM_FORMAT_UYVY
, DRM_FORMAT_VYUY
, DRM_FORMAT_YUYV
, DRM_FORMAT_YVYU
,
1203 DRM_FORMAT_YUV420
, DRM_FORMAT_YVU420
, DRM_FORMAT_YUV422
,
1206 static const unsigned int gsc_tiled_formats
[] = {
1207 DRM_FORMAT_NV12
, DRM_FORMAT_NV21
,
1210 static int gsc_probe(struct platform_device
*pdev
)
1212 struct device
*dev
= &pdev
->dev
;
1213 struct gsc_driverdata
*driver_data
;
1214 struct exynos_drm_ipp_formats
*formats
;
1215 struct gsc_context
*ctx
;
1216 struct resource
*res
;
1217 int num_formats
, ret
, i
, j
;
1219 ctx
= devm_kzalloc(dev
, sizeof(*ctx
), GFP_KERNEL
);
1223 driver_data
= (struct gsc_driverdata
*)of_device_get_match_data(dev
);
1225 ctx
->num_clocks
= driver_data
->num_clocks
;
1226 ctx
->clk_names
= driver_data
->clk_names
;
1228 /* construct formats/limits array */
1229 num_formats
= ARRAY_SIZE(gsc_formats
) + ARRAY_SIZE(gsc_tiled_formats
);
1230 formats
= devm_kcalloc(dev
, num_formats
, sizeof(*formats
), GFP_KERNEL
);
1234 /* linear formats */
1235 for (i
= 0; i
< ARRAY_SIZE(gsc_formats
); i
++) {
1236 formats
[i
].fourcc
= gsc_formats
[i
];
1237 formats
[i
].type
= DRM_EXYNOS_IPP_FORMAT_SOURCE
|
1238 DRM_EXYNOS_IPP_FORMAT_DESTINATION
;
1239 formats
[i
].limits
= driver_data
->limits
;
1240 formats
[i
].num_limits
= driver_data
->num_limits
;
1244 for (j
= i
, i
= 0; i
< ARRAY_SIZE(gsc_tiled_formats
); j
++, i
++) {
1245 formats
[j
].fourcc
= gsc_tiled_formats
[i
];
1246 formats
[j
].modifier
= DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
;
1247 formats
[j
].type
= DRM_EXYNOS_IPP_FORMAT_SOURCE
|
1248 DRM_EXYNOS_IPP_FORMAT_DESTINATION
;
1249 formats
[j
].limits
= driver_data
->limits
;
1250 formats
[j
].num_limits
= driver_data
->num_limits
;
1253 ctx
->formats
= formats
;
1254 ctx
->num_formats
= num_formats
;
1257 for (i
= 0; i
< ctx
->num_clocks
; i
++) {
1258 ctx
->clocks
[i
] = devm_clk_get(dev
, ctx
->clk_names
[i
]);
1259 if (IS_ERR(ctx
->clocks
[i
])) {
1260 dev_err(dev
, "failed to get clock: %s\n",
1262 return PTR_ERR(ctx
->clocks
[i
]);
1266 /* resource memory */
1267 ctx
->regs_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1268 ctx
->regs
= devm_ioremap_resource(dev
, ctx
->regs_res
);
1269 if (IS_ERR(ctx
->regs
))
1270 return PTR_ERR(ctx
->regs
);
1273 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1275 dev_err(dev
, "failed to request irq resource.\n");
1279 ctx
->irq
= res
->start
;
1280 ret
= devm_request_irq(dev
, ctx
->irq
, gsc_irq_handler
, 0,
1281 dev_name(dev
), ctx
);
1283 dev_err(dev
, "failed to request irq.\n");
1287 /* context initailization */
1290 platform_set_drvdata(pdev
, ctx
);
1292 pm_runtime_use_autosuspend(dev
);
1293 pm_runtime_set_autosuspend_delay(dev
, GSC_AUTOSUSPEND_DELAY
);
1294 pm_runtime_enable(dev
);
1296 ret
= component_add(dev
, &gsc_component_ops
);
1300 dev_info(dev
, "drm gsc registered successfully.\n");
1305 pm_runtime_dont_use_autosuspend(dev
);
1306 pm_runtime_disable(dev
);
1310 static int gsc_remove(struct platform_device
*pdev
)
1312 struct device
*dev
= &pdev
->dev
;
1314 pm_runtime_dont_use_autosuspend(dev
);
1315 pm_runtime_disable(dev
);
1320 static int __maybe_unused
gsc_runtime_suspend(struct device
*dev
)
1322 struct gsc_context
*ctx
= get_gsc_context(dev
);
1325 DRM_DEV_DEBUG_KMS(dev
, "id[%d]\n", ctx
->id
);
1327 for (i
= ctx
->num_clocks
- 1; i
>= 0; i
--)
1328 clk_disable_unprepare(ctx
->clocks
[i
]);
1333 static int __maybe_unused
gsc_runtime_resume(struct device
*dev
)
1335 struct gsc_context
*ctx
= get_gsc_context(dev
);
1338 DRM_DEV_DEBUG_KMS(dev
, "id[%d]\n", ctx
->id
);
1340 for (i
= 0; i
< ctx
->num_clocks
; i
++) {
1341 ret
= clk_prepare_enable(ctx
->clocks
[i
]);
1344 clk_disable_unprepare(ctx
->clocks
[i
]);
1351 static const struct dev_pm_ops gsc_pm_ops
= {
1352 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
1353 pm_runtime_force_resume
)
1354 SET_RUNTIME_PM_OPS(gsc_runtime_suspend
, gsc_runtime_resume
, NULL
)
1357 static const struct drm_exynos_ipp_limit gsc_5250_limits
[] = {
1358 { IPP_SIZE_LIMIT(BUFFER
, .h
= { 32, 4800, 8 }, .v
= { 16, 3344, 8 }) },
1359 { IPP_SIZE_LIMIT(AREA
, .h
= { 16, 4800, 2 }, .v
= { 8, 3344, 2 }) },
1360 { IPP_SIZE_LIMIT(ROTATED
, .h
= { 32, 2048 }, .v
= { 16, 2048 }) },
1361 { IPP_SCALE_LIMIT(.h
= { (1 << 16) / 16, (1 << 16) * 8 },
1362 .v
= { (1 << 16) / 16, (1 << 16) * 8 }) },
1365 static const struct drm_exynos_ipp_limit gsc_5420_limits
[] = {
1366 { IPP_SIZE_LIMIT(BUFFER
, .h
= { 32, 4800, 8 }, .v
= { 16, 3344, 8 }) },
1367 { IPP_SIZE_LIMIT(AREA
, .h
= { 16, 4800, 2 }, .v
= { 8, 3344, 2 }) },
1368 { IPP_SIZE_LIMIT(ROTATED
, .h
= { 16, 2016 }, .v
= { 8, 2016 }) },
1369 { IPP_SCALE_LIMIT(.h
= { (1 << 16) / 16, (1 << 16) * 8 },
1370 .v
= { (1 << 16) / 16, (1 << 16) * 8 }) },
1373 static const struct drm_exynos_ipp_limit gsc_5433_limits
[] = {
1374 { IPP_SIZE_LIMIT(BUFFER
, .h
= { 32, 8191, 16 }, .v
= { 16, 8191, 2 }) },
1375 { IPP_SIZE_LIMIT(AREA
, .h
= { 16, 4800, 1 }, .v
= { 8, 3344, 1 }) },
1376 { IPP_SIZE_LIMIT(ROTATED
, .h
= { 32, 2047 }, .v
= { 8, 8191 }) },
1377 { IPP_SCALE_LIMIT(.h
= { (1 << 16) / 16, (1 << 16) * 8 },
1378 .v
= { (1 << 16) / 16, (1 << 16) * 8 }) },
1381 static struct gsc_driverdata gsc_exynos5250_drvdata
= {
1382 .clk_names
= {"gscl"},
1384 .limits
= gsc_5250_limits
,
1385 .num_limits
= ARRAY_SIZE(gsc_5250_limits
),
1388 static struct gsc_driverdata gsc_exynos5420_drvdata
= {
1389 .clk_names
= {"gscl"},
1391 .limits
= gsc_5420_limits
,
1392 .num_limits
= ARRAY_SIZE(gsc_5420_limits
),
1395 static struct gsc_driverdata gsc_exynos5433_drvdata
= {
1396 .clk_names
= {"pclk", "aclk", "aclk_xiu", "aclk_gsclbend"},
1398 .limits
= gsc_5433_limits
,
1399 .num_limits
= ARRAY_SIZE(gsc_5433_limits
),
1402 static const struct of_device_id exynos_drm_gsc_of_match
[] = {
1404 .compatible
= "samsung,exynos5-gsc",
1405 .data
= &gsc_exynos5250_drvdata
,
1407 .compatible
= "samsung,exynos5250-gsc",
1408 .data
= &gsc_exynos5250_drvdata
,
1410 .compatible
= "samsung,exynos5420-gsc",
1411 .data
= &gsc_exynos5420_drvdata
,
1413 .compatible
= "samsung,exynos5433-gsc",
1414 .data
= &gsc_exynos5433_drvdata
,
1418 MODULE_DEVICE_TABLE(of
, exynos_drm_gsc_of_match
);
1420 struct platform_driver gsc_driver
= {
1422 .remove
= gsc_remove
,
1424 .name
= "exynos-drm-gsc",
1425 .owner
= THIS_MODULE
,
1427 .of_match_table
= of_match_ptr(exynos_drm_gsc_of_match
),