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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / exynos / exynos_hdmi.c
1 /*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17 #include <drm/drmP.h>
18 #include <drm/drm_edid.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_atomic_helper.h>
21
22 #include "regs-hdmi.h"
23
24 #include <linux/kernel.h>
25 #include <linux/wait.h>
26 #include <linux/i2c.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
29 #include <linux/irq.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/clk.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/io.h>
36 #include <linux/of_address.h>
37 #include <linux/of_device.h>
38 #include <linux/of_graph.h>
39 #include <linux/hdmi.h>
40 #include <linux/component.h>
41 #include <linux/mfd/syscon.h>
42 #include <linux/regmap.h>
43
44 #include <drm/exynos_drm.h>
45
46 #include <media/cec-notifier.h>
47
48 #include "exynos_drm_crtc.h"
49
50 #define HOTPLUG_DEBOUNCE_MS 1100
51
52 enum hdmi_type {
53 HDMI_TYPE13,
54 HDMI_TYPE14,
55 HDMI_TYPE_COUNT
56 };
57
58 #define HDMI_MAPPED_BASE 0xffff0000
59
60 enum hdmi_mapped_regs {
61 HDMI_PHY_STATUS = HDMI_MAPPED_BASE,
62 HDMI_PHY_RSTOUT,
63 HDMI_ACR_CON,
64 HDMI_ACR_MCTS0,
65 HDMI_ACR_CTS0,
66 HDMI_ACR_N0
67 };
68
69 static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = {
70 { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 },
71 { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT },
72 { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON },
73 { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 },
74 { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 },
75 { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 },
76 };
77
78 static const char * const supply[] = {
79 "vdd",
80 "vdd_osc",
81 "vdd_pll",
82 };
83
84 struct hdmiphy_config {
85 int pixel_clock;
86 u8 conf[32];
87 };
88
89 struct hdmiphy_configs {
90 int count;
91 const struct hdmiphy_config *data;
92 };
93
94 struct string_array_spec {
95 int count;
96 const char * const *data;
97 };
98
99 #define INIT_ARRAY_SPEC(a) { .count = ARRAY_SIZE(a), .data = a }
100
101 struct hdmi_driver_data {
102 unsigned int type;
103 unsigned int is_apb_phy:1;
104 unsigned int has_sysreg:1;
105 struct hdmiphy_configs phy_confs;
106 struct string_array_spec clk_gates;
107 /*
108 * Array of triplets (p_off, p_on, clock), where p_off and p_on are
109 * required parents of clock when HDMI-PHY is respectively off or on.
110 */
111 struct string_array_spec clk_muxes;
112 };
113
114 struct hdmi_context {
115 struct drm_encoder encoder;
116 struct device *dev;
117 struct drm_device *drm_dev;
118 struct drm_connector connector;
119 bool powered;
120 bool dvi_mode;
121 struct delayed_work hotplug_work;
122 struct drm_display_mode current_mode;
123 struct cec_notifier *notifier;
124 const struct hdmi_driver_data *drv_data;
125
126 void __iomem *regs;
127 void __iomem *regs_hdmiphy;
128 struct i2c_client *hdmiphy_port;
129 struct i2c_adapter *ddc_adpt;
130 struct gpio_desc *hpd_gpio;
131 int irq;
132 struct regmap *pmureg;
133 struct regmap *sysreg;
134 struct clk **clk_gates;
135 struct clk **clk_muxes;
136 struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)];
137 struct regulator *reg_hdmi_en;
138 struct exynos_drm_clk phy_clk;
139 struct drm_bridge *bridge;
140 };
141
142 static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
143 {
144 return container_of(e, struct hdmi_context, encoder);
145 }
146
147 static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c)
148 {
149 return container_of(c, struct hdmi_context, connector);
150 }
151
152 static const struct hdmiphy_config hdmiphy_v13_configs[] = {
153 {
154 .pixel_clock = 27000000,
155 .conf = {
156 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
157 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
158 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
159 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
160 },
161 },
162 {
163 .pixel_clock = 27027000,
164 .conf = {
165 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
166 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
167 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
168 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
169 },
170 },
171 {
172 .pixel_clock = 74176000,
173 .conf = {
174 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
175 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
176 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
177 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80,
178 },
179 },
180 {
181 .pixel_clock = 74250000,
182 .conf = {
183 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
184 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
185 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
186 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80,
187 },
188 },
189 {
190 .pixel_clock = 148500000,
191 .conf = {
192 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
193 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
194 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
195 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80,
196 },
197 },
198 };
199
200 static const struct hdmiphy_config hdmiphy_v14_configs[] = {
201 {
202 .pixel_clock = 25200000,
203 .conf = {
204 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
205 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
206 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
207 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
208 },
209 },
210 {
211 .pixel_clock = 27000000,
212 .conf = {
213 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
214 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
215 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
216 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
217 },
218 },
219 {
220 .pixel_clock = 27027000,
221 .conf = {
222 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
223 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
224 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
225 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
226 },
227 },
228 {
229 .pixel_clock = 36000000,
230 .conf = {
231 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
232 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
233 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
234 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
235 },
236 },
237 {
238 .pixel_clock = 40000000,
239 .conf = {
240 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
241 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
242 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
243 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
244 },
245 },
246 {
247 .pixel_clock = 65000000,
248 .conf = {
249 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
250 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
251 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
252 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
253 },
254 },
255 {
256 .pixel_clock = 71000000,
257 .conf = {
258 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
259 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
260 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
261 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
262 },
263 },
264 {
265 .pixel_clock = 73250000,
266 .conf = {
267 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
268 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
269 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
270 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
271 },
272 },
273 {
274 .pixel_clock = 74176000,
275 .conf = {
276 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
277 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
278 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
279 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
280 },
281 },
282 {
283 .pixel_clock = 74250000,
284 .conf = {
285 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
286 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
287 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
288 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
289 },
290 },
291 {
292 .pixel_clock = 83500000,
293 .conf = {
294 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
295 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
296 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
297 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
298 },
299 },
300 {
301 .pixel_clock = 106500000,
302 .conf = {
303 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
304 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
305 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
306 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
307 },
308 },
309 {
310 .pixel_clock = 108000000,
311 .conf = {
312 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
313 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
314 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
315 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
316 },
317 },
318 {
319 .pixel_clock = 115500000,
320 .conf = {
321 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
322 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
323 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
324 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
325 },
326 },
327 {
328 .pixel_clock = 119000000,
329 .conf = {
330 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
331 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
332 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
333 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
334 },
335 },
336 {
337 .pixel_clock = 146250000,
338 .conf = {
339 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
340 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
341 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
342 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
343 },
344 },
345 {
346 .pixel_clock = 148500000,
347 .conf = {
348 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
349 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
350 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
351 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
352 },
353 },
354 };
355
356 static const struct hdmiphy_config hdmiphy_5420_configs[] = {
357 {
358 .pixel_clock = 25200000,
359 .conf = {
360 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
361 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
362 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
363 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
364 },
365 },
366 {
367 .pixel_clock = 27000000,
368 .conf = {
369 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
370 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
371 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
372 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
373 },
374 },
375 {
376 .pixel_clock = 27027000,
377 .conf = {
378 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
379 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
380 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
381 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
382 },
383 },
384 {
385 .pixel_clock = 36000000,
386 .conf = {
387 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
388 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
389 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
390 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
391 },
392 },
393 {
394 .pixel_clock = 40000000,
395 .conf = {
396 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
397 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
398 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
399 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
400 },
401 },
402 {
403 .pixel_clock = 65000000,
404 .conf = {
405 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
406 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
407 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
408 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
409 },
410 },
411 {
412 .pixel_clock = 71000000,
413 .conf = {
414 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
415 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
416 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
417 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
418 },
419 },
420 {
421 .pixel_clock = 73250000,
422 .conf = {
423 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
424 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
425 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
426 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
427 },
428 },
429 {
430 .pixel_clock = 74176000,
431 .conf = {
432 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
433 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
434 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
435 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
436 },
437 },
438 {
439 .pixel_clock = 74250000,
440 .conf = {
441 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
442 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
443 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
444 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
445 },
446 },
447 {
448 .pixel_clock = 83500000,
449 .conf = {
450 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
451 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
452 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
453 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
454 },
455 },
456 {
457 .pixel_clock = 88750000,
458 .conf = {
459 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
460 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
461 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
462 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
463 },
464 },
465 {
466 .pixel_clock = 106500000,
467 .conf = {
468 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
469 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
470 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
471 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
472 },
473 },
474 {
475 .pixel_clock = 108000000,
476 .conf = {
477 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
478 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
479 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
480 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
481 },
482 },
483 {
484 .pixel_clock = 115500000,
485 .conf = {
486 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
487 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
488 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
489 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
490 },
491 },
492 {
493 .pixel_clock = 146250000,
494 .conf = {
495 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
496 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
497 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
498 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
499 },
500 },
501 {
502 .pixel_clock = 148500000,
503 .conf = {
504 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
505 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
506 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
507 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
508 },
509 },
510 };
511
512 static const struct hdmiphy_config hdmiphy_5433_configs[] = {
513 {
514 .pixel_clock = 27000000,
515 .conf = {
516 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
517 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
518 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
519 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
520 },
521 },
522 {
523 .pixel_clock = 27027000,
524 .conf = {
525 0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
526 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
527 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
528 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
529 },
530 },
531 {
532 .pixel_clock = 40000000,
533 .conf = {
534 0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02,
535 0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
536 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
537 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
538 },
539 },
540 {
541 .pixel_clock = 50000000,
542 .conf = {
543 0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3,
544 0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
545 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
546 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
547 },
548 },
549 {
550 .pixel_clock = 65000000,
551 .conf = {
552 0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6,
553 0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
554 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
555 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
556 },
557 },
558 {
559 .pixel_clock = 74176000,
560 .conf = {
561 0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42,
562 0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
563 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
564 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
565 },
566 },
567 {
568 .pixel_clock = 74250000,
569 .conf = {
570 0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2,
571 0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
572 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
573 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
574 },
575 },
576 {
577 .pixel_clock = 108000000,
578 .conf = {
579 0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02,
580 0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
581 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
582 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
583 },
584 },
585 {
586 .pixel_clock = 148500000,
587 .conf = {
588 0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1,
589 0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
590 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
591 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
592 },
593 },
594 {
595 .pixel_clock = 297000000,
596 .conf = {
597 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2,
598 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
599 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
600 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
601 },
602 },
603 };
604
605 static const char * const hdmi_clk_gates4[] = {
606 "hdmi", "sclk_hdmi"
607 };
608
609 static const char * const hdmi_clk_muxes4[] = {
610 "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"
611 };
612
613 static const char * const hdmi_clk_gates5433[] = {
614 "hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk"
615 };
616
617 static const char * const hdmi_clk_muxes5433[] = {
618 "oscclk", "tmds_clko", "tmds_clko_user",
619 "oscclk", "pixel_clko", "pixel_clko_user"
620 };
621
622 static const struct hdmi_driver_data exynos4210_hdmi_driver_data = {
623 .type = HDMI_TYPE13,
624 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v13_configs),
625 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4),
626 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
627 };
628
629 static const struct hdmi_driver_data exynos4212_hdmi_driver_data = {
630 .type = HDMI_TYPE14,
631 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v14_configs),
632 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4),
633 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
634 };
635
636 static const struct hdmi_driver_data exynos5420_hdmi_driver_data = {
637 .type = HDMI_TYPE14,
638 .is_apb_phy = 1,
639 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5420_configs),
640 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4),
641 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
642 };
643
644 static const struct hdmi_driver_data exynos5433_hdmi_driver_data = {
645 .type = HDMI_TYPE14,
646 .is_apb_phy = 1,
647 .has_sysreg = 1,
648 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5433_configs),
649 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates5433),
650 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes5433),
651 };
652
653 static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id)
654 {
655 if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE)
656 return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type];
657 return reg_id;
658 }
659
660 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
661 {
662 return readl(hdata->regs + hdmi_map_reg(hdata, reg_id));
663 }
664
665 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
666 u32 reg_id, u8 value)
667 {
668 writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id));
669 }
670
671 static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id,
672 int bytes, u32 val)
673 {
674 reg_id = hdmi_map_reg(hdata, reg_id);
675
676 while (--bytes >= 0) {
677 writel(val & 0xff, hdata->regs + reg_id);
678 val >>= 8;
679 reg_id += 4;
680 }
681 }
682
683 static inline void hdmi_reg_write_buf(struct hdmi_context *hdata, u32 reg_id,
684 u8 *buf, int size)
685 {
686 for (reg_id = hdmi_map_reg(hdata, reg_id); size; --size, reg_id += 4)
687 writel(*buf++, hdata->regs + reg_id);
688 }
689
690 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
691 u32 reg_id, u32 value, u32 mask)
692 {
693 u32 old;
694
695 reg_id = hdmi_map_reg(hdata, reg_id);
696 old = readl(hdata->regs + reg_id);
697 value = (value & mask) | (old & ~mask);
698 writel(value, hdata->regs + reg_id);
699 }
700
701 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
702 u32 reg_offset, const u8 *buf, u32 len)
703 {
704 if ((reg_offset + len) > 32)
705 return -EINVAL;
706
707 if (hdata->hdmiphy_port) {
708 int ret;
709
710 ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
711 if (ret == len)
712 return 0;
713 return ret;
714 } else {
715 int i;
716 for (i = 0; i < len; i++)
717 writel(buf[i], hdata->regs_hdmiphy +
718 ((reg_offset + i)<<2));
719 return 0;
720 }
721 }
722
723 static int hdmi_clk_enable_gates(struct hdmi_context *hdata)
724 {
725 int i, ret;
726
727 for (i = 0; i < hdata->drv_data->clk_gates.count; ++i) {
728 ret = clk_prepare_enable(hdata->clk_gates[i]);
729 if (!ret)
730 continue;
731
732 dev_err(hdata->dev, "Cannot enable clock '%s', %d\n",
733 hdata->drv_data->clk_gates.data[i], ret);
734 while (i--)
735 clk_disable_unprepare(hdata->clk_gates[i]);
736 return ret;
737 }
738
739 return 0;
740 }
741
742 static void hdmi_clk_disable_gates(struct hdmi_context *hdata)
743 {
744 int i = hdata->drv_data->clk_gates.count;
745
746 while (i--)
747 clk_disable_unprepare(hdata->clk_gates[i]);
748 }
749
750 static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy)
751 {
752 struct device *dev = hdata->dev;
753 int ret = 0;
754 int i;
755
756 for (i = 0; i < hdata->drv_data->clk_muxes.count; i += 3) {
757 struct clk **c = &hdata->clk_muxes[i];
758
759 ret = clk_set_parent(c[2], c[to_phy]);
760 if (!ret)
761 continue;
762
763 dev_err(dev, "Cannot set clock parent of '%s' to '%s', %d\n",
764 hdata->drv_data->clk_muxes.data[i + 2],
765 hdata->drv_data->clk_muxes.data[i + to_phy], ret);
766 }
767
768 return ret;
769 }
770
771 static void hdmi_reg_infoframes(struct hdmi_context *hdata)
772 {
773 union hdmi_infoframe frm;
774 u8 buf[25];
775 int ret;
776
777 if (hdata->dvi_mode) {
778 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
779 HDMI_AVI_CON_DO_NOT_TRANSMIT);
780 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
781 HDMI_VSI_CON_DO_NOT_TRANSMIT);
782 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
783 return;
784 }
785
786 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi,
787 &hdata->current_mode);
788 if (!ret)
789 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf));
790 if (ret > 0) {
791 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
792 hdmi_reg_write_buf(hdata, HDMI_AVI_HEADER0, buf, ret);
793 } else {
794 DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret);
795 }
796
797 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi,
798 &hdata->current_mode);
799 if (!ret)
800 ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf,
801 sizeof(buf));
802 if (ret > 0) {
803 hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC);
804 hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3);
805 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3);
806 }
807
808 ret = hdmi_audio_infoframe_init(&frm.audio);
809 if (!ret) {
810 frm.audio.channels = 2;
811 ret = hdmi_audio_infoframe_pack(&frm.audio, buf, sizeof(buf));
812 }
813 if (ret > 0) {
814 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC);
815 hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, ret);
816 }
817 }
818
819 static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
820 bool force)
821 {
822 struct hdmi_context *hdata = connector_to_hdmi(connector);
823
824 if (gpiod_get_value(hdata->hpd_gpio))
825 return connector_status_connected;
826
827 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID);
828 return connector_status_disconnected;
829 }
830
831 static void hdmi_connector_destroy(struct drm_connector *connector)
832 {
833 drm_connector_unregister(connector);
834 drm_connector_cleanup(connector);
835 }
836
837 static const struct drm_connector_funcs hdmi_connector_funcs = {
838 .dpms = drm_atomic_helper_connector_dpms,
839 .fill_modes = drm_helper_probe_single_connector_modes,
840 .detect = hdmi_detect,
841 .destroy = hdmi_connector_destroy,
842 .reset = drm_atomic_helper_connector_reset,
843 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
844 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
845 };
846
847 static int hdmi_get_modes(struct drm_connector *connector)
848 {
849 struct hdmi_context *hdata = connector_to_hdmi(connector);
850 struct edid *edid;
851 int ret;
852
853 if (!hdata->ddc_adpt)
854 return -ENODEV;
855
856 edid = drm_get_edid(connector, hdata->ddc_adpt);
857 if (!edid)
858 return -ENODEV;
859
860 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
861 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
862 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
863 edid->width_cm, edid->height_cm);
864
865 drm_mode_connector_update_edid_property(connector, edid);
866 cec_notifier_set_phys_addr_from_edid(hdata->notifier, edid);
867
868 ret = drm_add_edid_modes(connector, edid);
869
870 kfree(edid);
871
872 return ret;
873 }
874
875 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
876 {
877 const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs;
878 int i;
879
880 for (i = 0; i < confs->count; i++)
881 if (confs->data[i].pixel_clock == pixel_clock)
882 return i;
883
884 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
885 return -EINVAL;
886 }
887
888 static int hdmi_mode_valid(struct drm_connector *connector,
889 struct drm_display_mode *mode)
890 {
891 struct hdmi_context *hdata = connector_to_hdmi(connector);
892 int ret;
893
894 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
895 mode->hdisplay, mode->vdisplay, mode->vrefresh,
896 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
897 false, mode->clock * 1000);
898
899 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
900 if (ret < 0)
901 return MODE_BAD;
902
903 return MODE_OK;
904 }
905
906 static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
907 .get_modes = hdmi_get_modes,
908 .mode_valid = hdmi_mode_valid,
909 };
910
911 static int hdmi_create_connector(struct drm_encoder *encoder)
912 {
913 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
914 struct drm_connector *connector = &hdata->connector;
915 int ret;
916
917 connector->interlace_allowed = true;
918 connector->polled = DRM_CONNECTOR_POLL_HPD;
919
920 ret = drm_connector_init(hdata->drm_dev, connector,
921 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
922 if (ret) {
923 DRM_ERROR("Failed to initialize connector with drm\n");
924 return ret;
925 }
926
927 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
928 drm_mode_connector_attach_encoder(connector, encoder);
929
930 if (hdata->bridge) {
931 encoder->bridge = hdata->bridge;
932 hdata->bridge->encoder = encoder;
933 ret = drm_bridge_attach(encoder, hdata->bridge, NULL);
934 if (ret)
935 DRM_ERROR("Failed to attach bridge\n");
936 }
937
938 return ret;
939 }
940
941 static bool hdmi_mode_fixup(struct drm_encoder *encoder,
942 const struct drm_display_mode *mode,
943 struct drm_display_mode *adjusted_mode)
944 {
945 struct drm_device *dev = encoder->dev;
946 struct drm_connector *connector;
947 struct drm_display_mode *m;
948 int mode_ok;
949
950 drm_mode_set_crtcinfo(adjusted_mode, 0);
951
952 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
953 if (connector->encoder == encoder)
954 break;
955 }
956
957 if (connector->encoder != encoder)
958 return true;
959
960 mode_ok = hdmi_mode_valid(connector, adjusted_mode);
961
962 if (mode_ok == MODE_OK)
963 return true;
964
965 /*
966 * Find the most suitable mode and copy it to adjusted_mode.
967 */
968 list_for_each_entry(m, &connector->modes, head) {
969 mode_ok = hdmi_mode_valid(connector, m);
970
971 if (mode_ok == MODE_OK) {
972 DRM_INFO("desired mode doesn't exist so\n");
973 DRM_INFO("use the most suitable mode among modes.\n");
974
975 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
976 m->hdisplay, m->vdisplay, m->vrefresh);
977
978 drm_mode_copy(adjusted_mode, m);
979 break;
980 }
981 }
982
983 return true;
984 }
985
986 static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq)
987 {
988 u32 n, cts;
989
990 cts = (freq % 9) ? 27000 : 30000;
991 n = 128 * freq / (27000000 / cts);
992
993 hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n);
994 hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts);
995 hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts);
996 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
997 }
998
999 static void hdmi_audio_init(struct hdmi_context *hdata)
1000 {
1001 u32 sample_rate, bits_per_sample;
1002 u32 data_num, bit_ch, sample_frq;
1003 u32 val;
1004
1005 sample_rate = 44100;
1006 bits_per_sample = 16;
1007
1008 switch (bits_per_sample) {
1009 case 20:
1010 data_num = 2;
1011 bit_ch = 1;
1012 break;
1013 case 24:
1014 data_num = 3;
1015 bit_ch = 1;
1016 break;
1017 default:
1018 data_num = 1;
1019 bit_ch = 0;
1020 break;
1021 }
1022
1023 hdmi_reg_acr(hdata, sample_rate);
1024
1025 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1026 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1027 | HDMI_I2S_MUX_ENABLE);
1028
1029 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1030 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1031
1032 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1033
1034 sample_frq = (sample_rate == 44100) ? 0 :
1035 (sample_rate == 48000) ? 2 :
1036 (sample_rate == 32000) ? 3 :
1037 (sample_rate == 96000) ? 0xa : 0x0;
1038
1039 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1040 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1041
1042 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1043 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1044
1045 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1046 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1047 | HDMI_I2S_SEL_LRCK(6));
1048 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1049 | HDMI_I2S_SEL_SDATA2(4));
1050 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1051 | HDMI_I2S_SEL_SDATA2(2));
1052 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1053
1054 /* I2S_CON_1 & 2 */
1055 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1056 | HDMI_I2S_L_CH_LOW_POL);
1057 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1058 | HDMI_I2S_SET_BIT_CH(bit_ch)
1059 | HDMI_I2S_SET_SDATA_BIT(data_num)
1060 | HDMI_I2S_BASIC_FORMAT);
1061
1062 /* Configure register related to CUV information */
1063 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1064 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1065 | HDMI_I2S_COPYRIGHT
1066 | HDMI_I2S_LINEAR_PCM
1067 | HDMI_I2S_CONSUMER_FORMAT);
1068 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1069 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1070 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1071 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1072 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1073 HDMI_I2S_ORG_SMP_FREQ_44_1
1074 | HDMI_I2S_WORD_LEN_MAX24_24BITS
1075 | HDMI_I2S_WORD_LEN_MAX_24BITS);
1076
1077 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1078 }
1079
1080 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1081 {
1082 if (hdata->dvi_mode)
1083 return;
1084
1085 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1086 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1087 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1088 }
1089
1090 static void hdmi_start(struct hdmi_context *hdata, bool start)
1091 {
1092 u32 val = start ? HDMI_TG_EN : 0;
1093
1094 if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE)
1095 val |= HDMI_FIELD_EN;
1096
1097 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1098 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
1099 }
1100
1101 static void hdmi_conf_init(struct hdmi_context *hdata)
1102 {
1103 /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1104 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1105 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1106
1107 /* choose HDMI mode */
1108 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1109 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1110 /* apply video pre-amble and guard band in HDMI mode only */
1111 hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
1112 /* disable bluescreen */
1113 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1114
1115 if (hdata->dvi_mode) {
1116 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1117 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1118 hdmi_reg_writeb(hdata, HDMI_CON_2,
1119 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1120 }
1121
1122 if (hdata->drv_data->type == HDMI_TYPE13) {
1123 /* choose bluescreen (fecal) color */
1124 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1125 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1126 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1127
1128 /* enable AVI packet every vsync, fixes purple line problem */
1129 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1130 /* force RGB, look to CEA-861-D, table 7 for more detail */
1131 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1132 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1133
1134 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1135 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1136 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1137 } else {
1138 hdmi_reg_infoframes(hdata);
1139
1140 /* enable AVI packet every vsync, fixes purple line problem */
1141 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1142 }
1143 }
1144
1145 static void hdmiphy_wait_for_pll(struct hdmi_context *hdata)
1146 {
1147 int tries;
1148
1149 for (tries = 0; tries < 10; ++tries) {
1150 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS);
1151
1152 if (val & HDMI_PHY_STATUS_READY) {
1153 DRM_DEBUG_KMS("PLL stabilized after %d tries\n", tries);
1154 return;
1155 }
1156 usleep_range(10, 20);
1157 }
1158
1159 DRM_ERROR("PLL could not reach steady state\n");
1160 }
1161
1162 static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1163 {
1164 struct drm_display_mode *m = &hdata->current_mode;
1165 unsigned int val;
1166
1167 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1168 hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3,
1169 (m->htotal << 12) | m->vtotal);
1170
1171 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1172 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val);
1173
1174 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1175 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val);
1176
1177 val = (m->hsync_start - m->hdisplay - 2);
1178 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1179 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1180 hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val);
1181
1182 /*
1183 * Quirk requirement for exynos HDMI IP design,
1184 * 2 pixels less than the actual calculation for hsync_start
1185 * and end.
1186 */
1187
1188 /* Following values & calculations differ for different type of modes */
1189 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1190 val = ((m->vsync_end - m->vdisplay) / 2);
1191 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1192 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1193
1194 val = m->vtotal / 2;
1195 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1196 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1197
1198 val = (m->vtotal +
1199 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1200 val |= m->vtotal << 11;
1201 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val);
1202
1203 val = ((m->vtotal / 2) + 7);
1204 val |= ((m->vtotal / 2) + 2) << 12;
1205 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val);
1206
1207 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1208 val |= ((m->htotal / 2) +
1209 (m->hsync_start - m->hdisplay)) << 12;
1210 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val);
1211
1212 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1213 (m->vtotal - m->vdisplay) / 2);
1214 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1215
1216 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249);
1217 } else {
1218 val = m->vtotal;
1219 val |= (m->vtotal - m->vdisplay) << 11;
1220 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1221
1222 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0);
1223
1224 val = (m->vsync_end - m->vdisplay);
1225 val |= ((m->vsync_start - m->vdisplay) << 12);
1226 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1227
1228 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001);
1229 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001);
1230 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1231 m->vtotal - m->vdisplay);
1232 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1233 }
1234
1235 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1236 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
1237 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
1238 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1239 }
1240
1241 static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1242 {
1243 struct drm_display_mode *m = &hdata->current_mode;
1244
1245 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1246 hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal);
1247 hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal);
1248 hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1,
1249 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1250 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1,
1251 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1252 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1,
1253 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1254
1255 /*
1256 * Quirk requirement for exynos 5 HDMI IP design,
1257 * 2 pixels less than the actual calculation for hsync_start
1258 * and end.
1259 */
1260
1261 /* Following values & calculations differ for different type of modes */
1262 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1263 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1264 (m->vsync_end - m->vdisplay) / 2);
1265 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1266 (m->vsync_start - m->vdisplay) / 2);
1267 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2);
1268 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1269 (m->vtotal - m->vdisplay) / 2);
1270 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2,
1271 m->vtotal - m->vdisplay / 2);
1272 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal);
1273 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2,
1274 (m->vtotal / 2) + 7);
1275 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2,
1276 (m->vtotal / 2) + 2);
1277 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2,
1278 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1279 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2,
1280 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1281 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1282 (m->vtotal - m->vdisplay) / 2);
1283 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1284 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2,
1285 m->vtotal - m->vdisplay / 2);
1286 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2,
1287 (m->vtotal / 2) + 1);
1288 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2,
1289 (m->vtotal / 2) + 1);
1290 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2,
1291 (m->vtotal / 2) + 1);
1292 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0);
1293 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0);
1294 } else {
1295 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1296 m->vsync_end - m->vdisplay);
1297 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1298 m->vsync_start - m->vdisplay);
1299 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal);
1300 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1301 m->vtotal - m->vdisplay);
1302 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff);
1303 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff);
1304 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff);
1305 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff);
1306 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff);
1307 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff);
1308 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1309 m->vtotal - m->vdisplay);
1310 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1311 }
1312
1313 hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2,
1314 m->hsync_start - m->hdisplay - 2);
1315 hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2,
1316 m->hsync_end - m->hdisplay - 2);
1317 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff);
1318 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff);
1319 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff);
1320 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff);
1321 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff);
1322 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff);
1323 hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff);
1324 hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff);
1325 hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff);
1326 hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff);
1327 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff);
1328 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff);
1329 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff);
1330 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff);
1331 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff);
1332 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff);
1333 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff);
1334 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff);
1335
1336 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1337 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
1338 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
1339 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1340 if (hdata->drv_data == &exynos5433_hdmi_driver_data)
1341 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1);
1342 }
1343
1344 static void hdmi_mode_apply(struct hdmi_context *hdata)
1345 {
1346 if (hdata->drv_data->type == HDMI_TYPE13)
1347 hdmi_v13_mode_apply(hdata);
1348 else
1349 hdmi_v14_mode_apply(hdata);
1350
1351 hdmi_start(hdata, true);
1352 }
1353
1354 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1355 {
1356 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, 1);
1357 usleep_range(10000, 12000);
1358 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, 1);
1359 usleep_range(10000, 12000);
1360 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
1361 usleep_range(10000, 12000);
1362 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
1363 usleep_range(10000, 12000);
1364 }
1365
1366 static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable)
1367 {
1368 u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET;
1369
1370 if (hdata->drv_data == &exynos5433_hdmi_driver_data)
1371 writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE);
1372 }
1373
1374 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1375 {
1376 int ret;
1377 const u8 *phy_conf;
1378
1379 ret = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000);
1380 if (ret < 0) {
1381 DRM_ERROR("failed to find hdmiphy conf\n");
1382 return;
1383 }
1384 phy_conf = hdata->drv_data->phy_confs.data[ret].conf;
1385
1386 hdmi_clk_set_parents(hdata, false);
1387
1388 hdmiphy_conf_reset(hdata);
1389
1390 hdmiphy_enable_mode_set(hdata, true);
1391 ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32);
1392 if (ret) {
1393 DRM_ERROR("failed to configure hdmiphy\n");
1394 return;
1395 }
1396 hdmiphy_enable_mode_set(hdata, false);
1397 hdmi_clk_set_parents(hdata, true);
1398 usleep_range(10000, 12000);
1399 hdmiphy_wait_for_pll(hdata);
1400 }
1401
1402 static void hdmi_conf_apply(struct hdmi_context *hdata)
1403 {
1404 hdmi_start(hdata, false);
1405 hdmi_conf_init(hdata);
1406 hdmi_audio_init(hdata);
1407 hdmi_mode_apply(hdata);
1408 hdmi_audio_control(hdata, true);
1409 }
1410
1411 static void hdmi_mode_set(struct drm_encoder *encoder,
1412 struct drm_display_mode *mode,
1413 struct drm_display_mode *adjusted_mode)
1414 {
1415 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1416 struct drm_display_mode *m = adjusted_mode;
1417
1418 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
1419 m->hdisplay, m->vdisplay,
1420 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1421 "INTERLACED" : "PROGRESSIVE");
1422
1423 drm_mode_copy(&hdata->current_mode, m);
1424 }
1425
1426 static void hdmi_set_refclk(struct hdmi_context *hdata, bool on)
1427 {
1428 if (!hdata->sysreg)
1429 return;
1430
1431 regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY,
1432 SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
1433 }
1434
1435 static void hdmiphy_enable(struct hdmi_context *hdata)
1436 {
1437 if (hdata->powered)
1438 return;
1439
1440 pm_runtime_get_sync(hdata->dev);
1441
1442 if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk))
1443 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
1444
1445 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1446 PMU_HDMI_PHY_ENABLE_BIT, 1);
1447
1448 hdmi_set_refclk(hdata, true);
1449
1450 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN);
1451
1452 hdmiphy_conf_apply(hdata);
1453
1454 hdata->powered = true;
1455 }
1456
1457 static void hdmiphy_disable(struct hdmi_context *hdata)
1458 {
1459 if (!hdata->powered)
1460 return;
1461
1462 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
1463
1464 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN);
1465
1466 hdmi_set_refclk(hdata, false);
1467
1468 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1469 PMU_HDMI_PHY_ENABLE_BIT, 0);
1470
1471 regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk);
1472
1473 pm_runtime_put_sync(hdata->dev);
1474
1475 hdata->powered = false;
1476 }
1477
1478 static void hdmi_enable(struct drm_encoder *encoder)
1479 {
1480 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1481
1482 hdmiphy_enable(hdata);
1483 hdmi_conf_apply(hdata);
1484 }
1485
1486 static void hdmi_disable(struct drm_encoder *encoder)
1487 {
1488 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1489
1490 if (!hdata->powered)
1491 return;
1492
1493 /*
1494 * The SFRs of VP and Mixer are updated by Vertical Sync of
1495 * Timing generator which is a part of HDMI so the sequence
1496 * to disable TV Subsystem should be as following,
1497 * VP -> Mixer -> HDMI
1498 *
1499 * To achieve such sequence HDMI is disabled together with HDMI PHY, via
1500 * pipe clock callback.
1501 */
1502 cancel_delayed_work(&hdata->hotplug_work);
1503 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID);
1504
1505 hdmiphy_disable(hdata);
1506 }
1507
1508 static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = {
1509 .mode_fixup = hdmi_mode_fixup,
1510 .mode_set = hdmi_mode_set,
1511 .enable = hdmi_enable,
1512 .disable = hdmi_disable,
1513 };
1514
1515 static const struct drm_encoder_funcs exynos_hdmi_encoder_funcs = {
1516 .destroy = drm_encoder_cleanup,
1517 };
1518
1519 static void hdmi_hotplug_work_func(struct work_struct *work)
1520 {
1521 struct hdmi_context *hdata;
1522
1523 hdata = container_of(work, struct hdmi_context, hotplug_work.work);
1524
1525 if (hdata->drm_dev)
1526 drm_helper_hpd_irq_event(hdata->drm_dev);
1527 }
1528
1529 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
1530 {
1531 struct hdmi_context *hdata = arg;
1532
1533 mod_delayed_work(system_wq, &hdata->hotplug_work,
1534 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
1535
1536 return IRQ_HANDLED;
1537 }
1538
1539 static int hdmi_clks_get(struct hdmi_context *hdata,
1540 const struct string_array_spec *names,
1541 struct clk **clks)
1542 {
1543 struct device *dev = hdata->dev;
1544 int i;
1545
1546 for (i = 0; i < names->count; ++i) {
1547 struct clk *clk = devm_clk_get(dev, names->data[i]);
1548
1549 if (IS_ERR(clk)) {
1550 int ret = PTR_ERR(clk);
1551
1552 dev_err(dev, "Cannot get clock %s, %d\n",
1553 names->data[i], ret);
1554
1555 return ret;
1556 }
1557
1558 clks[i] = clk;
1559 }
1560
1561 return 0;
1562 }
1563
1564 static int hdmi_clk_init(struct hdmi_context *hdata)
1565 {
1566 const struct hdmi_driver_data *drv_data = hdata->drv_data;
1567 int count = drv_data->clk_gates.count + drv_data->clk_muxes.count;
1568 struct device *dev = hdata->dev;
1569 struct clk **clks;
1570 int ret;
1571
1572 if (!count)
1573 return 0;
1574
1575 clks = devm_kzalloc(dev, sizeof(*clks) * count, GFP_KERNEL);
1576 if (!clks)
1577 return -ENOMEM;
1578
1579 hdata->clk_gates = clks;
1580 hdata->clk_muxes = clks + drv_data->clk_gates.count;
1581
1582 ret = hdmi_clks_get(hdata, &drv_data->clk_gates, hdata->clk_gates);
1583 if (ret)
1584 return ret;
1585
1586 return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes);
1587 }
1588
1589
1590 static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable)
1591 {
1592 struct hdmi_context *hdata = container_of(clk, struct hdmi_context,
1593 phy_clk);
1594
1595 if (enable)
1596 hdmiphy_enable(hdata);
1597 else
1598 hdmiphy_disable(hdata);
1599 }
1600
1601 static int hdmi_bridge_init(struct hdmi_context *hdata)
1602 {
1603 struct device *dev = hdata->dev;
1604 struct device_node *ep, *np;
1605
1606 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
1607 if (!ep)
1608 return 0;
1609
1610 np = of_graph_get_remote_port_parent(ep);
1611 of_node_put(ep);
1612 if (!np) {
1613 DRM_ERROR("failed to get remote port parent");
1614 return -EINVAL;
1615 }
1616
1617 hdata->bridge = of_drm_find_bridge(np);
1618 of_node_put(np);
1619
1620 if (!hdata->bridge)
1621 return -EPROBE_DEFER;
1622
1623 return 0;
1624 }
1625
1626 static int hdmi_resources_init(struct hdmi_context *hdata)
1627 {
1628 struct device *dev = hdata->dev;
1629 int i, ret;
1630
1631 DRM_DEBUG_KMS("HDMI resource init\n");
1632
1633 hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN);
1634 if (IS_ERR(hdata->hpd_gpio)) {
1635 DRM_ERROR("cannot get hpd gpio property\n");
1636 return PTR_ERR(hdata->hpd_gpio);
1637 }
1638
1639 hdata->irq = gpiod_to_irq(hdata->hpd_gpio);
1640 if (hdata->irq < 0) {
1641 DRM_ERROR("failed to get GPIO irq\n");
1642 return hdata->irq;
1643 }
1644
1645 ret = hdmi_clk_init(hdata);
1646 if (ret)
1647 return ret;
1648
1649 ret = hdmi_clk_set_parents(hdata, false);
1650 if (ret)
1651 return ret;
1652
1653 for (i = 0; i < ARRAY_SIZE(supply); ++i)
1654 hdata->regul_bulk[i].supply = supply[i];
1655
1656 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk);
1657 if (ret) {
1658 if (ret != -EPROBE_DEFER)
1659 DRM_ERROR("failed to get regulators\n");
1660 return ret;
1661 }
1662
1663 hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
1664
1665 if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) {
1666 if (IS_ERR(hdata->reg_hdmi_en))
1667 return PTR_ERR(hdata->reg_hdmi_en);
1668
1669 ret = regulator_enable(hdata->reg_hdmi_en);
1670 if (ret) {
1671 DRM_ERROR("failed to enable hdmi-en regulator\n");
1672 return ret;
1673 }
1674 }
1675
1676 return hdmi_bridge_init(hdata);
1677 }
1678
1679 static struct of_device_id hdmi_match_types[] = {
1680 {
1681 .compatible = "samsung,exynos4210-hdmi",
1682 .data = &exynos4210_hdmi_driver_data,
1683 }, {
1684 .compatible = "samsung,exynos4212-hdmi",
1685 .data = &exynos4212_hdmi_driver_data,
1686 }, {
1687 .compatible = "samsung,exynos5420-hdmi",
1688 .data = &exynos5420_hdmi_driver_data,
1689 }, {
1690 .compatible = "samsung,exynos5433-hdmi",
1691 .data = &exynos5433_hdmi_driver_data,
1692 }, {
1693 /* end node */
1694 }
1695 };
1696 MODULE_DEVICE_TABLE (of, hdmi_match_types);
1697
1698 static int hdmi_bind(struct device *dev, struct device *master, void *data)
1699 {
1700 struct drm_device *drm_dev = data;
1701 struct hdmi_context *hdata = dev_get_drvdata(dev);
1702 struct drm_encoder *encoder = &hdata->encoder;
1703 struct exynos_drm_crtc *exynos_crtc;
1704 struct drm_crtc *crtc;
1705 int ret, pipe;
1706
1707 hdata->drm_dev = drm_dev;
1708
1709 pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
1710 EXYNOS_DISPLAY_TYPE_HDMI);
1711 if (pipe < 0)
1712 return pipe;
1713
1714 hdata->phy_clk.enable = hdmiphy_clk_enable;
1715
1716 crtc = drm_crtc_from_index(drm_dev, pipe);
1717 exynos_crtc = to_exynos_crtc(crtc);
1718 exynos_crtc->pipe_clk = &hdata->phy_clk;
1719
1720 encoder->possible_crtcs = 1 << pipe;
1721
1722 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
1723
1724 drm_encoder_init(drm_dev, encoder, &exynos_hdmi_encoder_funcs,
1725 DRM_MODE_ENCODER_TMDS, NULL);
1726
1727 drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs);
1728
1729 ret = hdmi_create_connector(encoder);
1730 if (ret) {
1731 DRM_ERROR("failed to create connector ret = %d\n", ret);
1732 drm_encoder_cleanup(encoder);
1733 return ret;
1734 }
1735
1736 return 0;
1737 }
1738
1739 static void hdmi_unbind(struct device *dev, struct device *master, void *data)
1740 {
1741 }
1742
1743 static const struct component_ops hdmi_component_ops = {
1744 .bind = hdmi_bind,
1745 .unbind = hdmi_unbind,
1746 };
1747
1748 static int hdmi_get_ddc_adapter(struct hdmi_context *hdata)
1749 {
1750 const char *compatible_str = "samsung,exynos4210-hdmiddc";
1751 struct device_node *np;
1752 struct i2c_adapter *adpt;
1753
1754 np = of_find_compatible_node(NULL, NULL, compatible_str);
1755 if (np)
1756 np = of_get_next_parent(np);
1757 else
1758 np = of_parse_phandle(hdata->dev->of_node, "ddc", 0);
1759
1760 if (!np) {
1761 DRM_ERROR("Failed to find ddc node in device tree\n");
1762 return -ENODEV;
1763 }
1764
1765 adpt = of_find_i2c_adapter_by_node(np);
1766 of_node_put(np);
1767
1768 if (!adpt) {
1769 DRM_INFO("Failed to get ddc i2c adapter by node\n");
1770 return -EPROBE_DEFER;
1771 }
1772
1773 hdata->ddc_adpt = adpt;
1774
1775 return 0;
1776 }
1777
1778 static int hdmi_get_phy_io(struct hdmi_context *hdata)
1779 {
1780 const char *compatible_str = "samsung,exynos4212-hdmiphy";
1781 struct device_node *np;
1782 int ret = 0;
1783
1784 np = of_find_compatible_node(NULL, NULL, compatible_str);
1785 if (!np) {
1786 np = of_parse_phandle(hdata->dev->of_node, "phy", 0);
1787 if (!np) {
1788 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
1789 return -ENODEV;
1790 }
1791 }
1792
1793 if (hdata->drv_data->is_apb_phy) {
1794 hdata->regs_hdmiphy = of_iomap(np, 0);
1795 if (!hdata->regs_hdmiphy) {
1796 DRM_ERROR("failed to ioremap hdmi phy\n");
1797 ret = -ENOMEM;
1798 goto out;
1799 }
1800 } else {
1801 hdata->hdmiphy_port = of_find_i2c_device_by_node(np);
1802 if (!hdata->hdmiphy_port) {
1803 DRM_INFO("Failed to get hdmi phy i2c client\n");
1804 ret = -EPROBE_DEFER;
1805 goto out;
1806 }
1807 }
1808
1809 out:
1810 of_node_put(np);
1811 return ret;
1812 }
1813
1814 static int hdmi_probe(struct platform_device *pdev)
1815 {
1816 struct device *dev = &pdev->dev;
1817 struct hdmi_context *hdata;
1818 struct resource *res;
1819 int ret;
1820
1821 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
1822 if (!hdata)
1823 return -ENOMEM;
1824
1825 hdata->drv_data = of_device_get_match_data(dev);
1826
1827 platform_set_drvdata(pdev, hdata);
1828
1829 hdata->dev = dev;
1830
1831 ret = hdmi_resources_init(hdata);
1832 if (ret) {
1833 if (ret != -EPROBE_DEFER)
1834 DRM_ERROR("hdmi_resources_init failed\n");
1835 return ret;
1836 }
1837
1838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1839 hdata->regs = devm_ioremap_resource(dev, res);
1840 if (IS_ERR(hdata->regs)) {
1841 ret = PTR_ERR(hdata->regs);
1842 return ret;
1843 }
1844
1845 ret = hdmi_get_ddc_adapter(hdata);
1846 if (ret)
1847 return ret;
1848
1849 ret = hdmi_get_phy_io(hdata);
1850 if (ret)
1851 goto err_ddc;
1852
1853 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
1854
1855 ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
1856 hdmi_irq_thread, IRQF_TRIGGER_RISING |
1857 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1858 "hdmi", hdata);
1859 if (ret) {
1860 DRM_ERROR("failed to register hdmi interrupt\n");
1861 goto err_hdmiphy;
1862 }
1863
1864 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
1865 "samsung,syscon-phandle");
1866 if (IS_ERR(hdata->pmureg)) {
1867 DRM_ERROR("syscon regmap lookup failed.\n");
1868 ret = -EPROBE_DEFER;
1869 goto err_hdmiphy;
1870 }
1871
1872 if (hdata->drv_data->has_sysreg) {
1873 hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1874 "samsung,sysreg-phandle");
1875 if (IS_ERR(hdata->sysreg)) {
1876 DRM_ERROR("sysreg regmap lookup failed.\n");
1877 ret = -EPROBE_DEFER;
1878 goto err_hdmiphy;
1879 }
1880 }
1881
1882 hdata->notifier = cec_notifier_get(&pdev->dev);
1883 if (hdata->notifier == NULL) {
1884 ret = -ENOMEM;
1885 goto err_hdmiphy;
1886 }
1887
1888 pm_runtime_enable(dev);
1889
1890 ret = component_add(&pdev->dev, &hdmi_component_ops);
1891 if (ret)
1892 goto err_notifier_put;
1893
1894 return ret;
1895
1896 err_notifier_put:
1897 cec_notifier_put(hdata->notifier);
1898 pm_runtime_disable(dev);
1899
1900 err_hdmiphy:
1901 if (hdata->hdmiphy_port)
1902 put_device(&hdata->hdmiphy_port->dev);
1903 if (hdata->regs_hdmiphy)
1904 iounmap(hdata->regs_hdmiphy);
1905 err_ddc:
1906 put_device(&hdata->ddc_adpt->dev);
1907
1908 return ret;
1909 }
1910
1911 static int hdmi_remove(struct platform_device *pdev)
1912 {
1913 struct hdmi_context *hdata = platform_get_drvdata(pdev);
1914
1915 cancel_delayed_work_sync(&hdata->hotplug_work);
1916 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID);
1917
1918 component_del(&pdev->dev, &hdmi_component_ops);
1919
1920 cec_notifier_put(hdata->notifier);
1921 pm_runtime_disable(&pdev->dev);
1922
1923 if (!IS_ERR(hdata->reg_hdmi_en))
1924 regulator_disable(hdata->reg_hdmi_en);
1925
1926 if (hdata->hdmiphy_port)
1927 put_device(&hdata->hdmiphy_port->dev);
1928
1929 if (hdata->regs_hdmiphy)
1930 iounmap(hdata->regs_hdmiphy);
1931
1932 put_device(&hdata->ddc_adpt->dev);
1933
1934 return 0;
1935 }
1936
1937 #ifdef CONFIG_PM
1938 static int exynos_hdmi_suspend(struct device *dev)
1939 {
1940 struct hdmi_context *hdata = dev_get_drvdata(dev);
1941
1942 hdmi_clk_disable_gates(hdata);
1943
1944 return 0;
1945 }
1946
1947 static int exynos_hdmi_resume(struct device *dev)
1948 {
1949 struct hdmi_context *hdata = dev_get_drvdata(dev);
1950 int ret;
1951
1952 ret = hdmi_clk_enable_gates(hdata);
1953 if (ret < 0)
1954 return ret;
1955
1956 return 0;
1957 }
1958 #endif
1959
1960 static const struct dev_pm_ops exynos_hdmi_pm_ops = {
1961 SET_RUNTIME_PM_OPS(exynos_hdmi_suspend, exynos_hdmi_resume, NULL)
1962 };
1963
1964 struct platform_driver hdmi_driver = {
1965 .probe = hdmi_probe,
1966 .remove = hdmi_remove,
1967 .driver = {
1968 .name = "exynos-hdmi",
1969 .owner = THIS_MODULE,
1970 .pm = &exynos_hdmi_pm_ops,
1971 .of_match_table = hdmi_match_types,
1972 },
1973 };
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