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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / exynos / exynos_hdmi.c
1 /*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17 #include <drm/drmP.h>
18 #include <drm/drm_edid.h>
19 #include <drm/drm_crtc_helper.h>
20
21 #include "regs-hdmi.h"
22
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/wait.h>
26 #include <linux/i2c.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
29 #include <linux/irq.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/clk.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/io.h>
35 #include <linux/of.h>
36 #include <linux/i2c.h>
37 #include <linux/of_gpio.h>
38 #include <linux/hdmi.h>
39
40 #include <drm/exynos_drm.h>
41
42 #include "exynos_drm_drv.h"
43 #include "exynos_mixer.h"
44
45 #include <linux/gpio.h>
46 #include <media/s5p_hdmi.h>
47
48 #define MAX_WIDTH 1920
49 #define MAX_HEIGHT 1080
50 #define get_hdmi_display(dev) platform_get_drvdata(to_platform_device(dev))
51
52 /* AVI header and aspect ratio */
53 #define HDMI_AVI_VERSION 0x02
54 #define HDMI_AVI_LENGTH 0x0D
55
56 /* AUI header info */
57 #define HDMI_AUI_VERSION 0x01
58 #define HDMI_AUI_LENGTH 0x0A
59 #define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8
60 #define AVI_4_3_CENTER_RATIO 0x9
61 #define AVI_16_9_CENTER_RATIO 0xa
62
63 enum hdmi_type {
64 HDMI_TYPE13,
65 HDMI_TYPE14,
66 };
67
68 struct hdmi_resources {
69 struct clk *hdmi;
70 struct clk *sclk_hdmi;
71 struct clk *sclk_pixel;
72 struct clk *sclk_hdmiphy;
73 struct clk *hdmiphy;
74 struct clk *mout_hdmi;
75 struct regulator_bulk_data *regul_bulk;
76 int regul_count;
77 };
78
79 struct hdmi_tg_regs {
80 u8 cmd[1];
81 u8 h_fsz[2];
82 u8 hact_st[2];
83 u8 hact_sz[2];
84 u8 v_fsz[2];
85 u8 vsync[2];
86 u8 vsync2[2];
87 u8 vact_st[2];
88 u8 vact_sz[2];
89 u8 field_chg[2];
90 u8 vact_st2[2];
91 u8 vact_st3[2];
92 u8 vact_st4[2];
93 u8 vsync_top_hdmi[2];
94 u8 vsync_bot_hdmi[2];
95 u8 field_top_hdmi[2];
96 u8 field_bot_hdmi[2];
97 u8 tg_3d[1];
98 };
99
100 struct hdmi_v13_core_regs {
101 u8 h_blank[2];
102 u8 v_blank[3];
103 u8 h_v_line[3];
104 u8 vsync_pol[1];
105 u8 int_pro_mode[1];
106 u8 v_blank_f[3];
107 u8 h_sync_gen[3];
108 u8 v_sync_gen1[3];
109 u8 v_sync_gen2[3];
110 u8 v_sync_gen3[3];
111 };
112
113 struct hdmi_v14_core_regs {
114 u8 h_blank[2];
115 u8 v2_blank[2];
116 u8 v1_blank[2];
117 u8 v_line[2];
118 u8 h_line[2];
119 u8 hsync_pol[1];
120 u8 vsync_pol[1];
121 u8 int_pro_mode[1];
122 u8 v_blank_f0[2];
123 u8 v_blank_f1[2];
124 u8 h_sync_start[2];
125 u8 h_sync_end[2];
126 u8 v_sync_line_bef_2[2];
127 u8 v_sync_line_bef_1[2];
128 u8 v_sync_line_aft_2[2];
129 u8 v_sync_line_aft_1[2];
130 u8 v_sync_line_aft_pxl_2[2];
131 u8 v_sync_line_aft_pxl_1[2];
132 u8 v_blank_f2[2]; /* for 3D mode */
133 u8 v_blank_f3[2]; /* for 3D mode */
134 u8 v_blank_f4[2]; /* for 3D mode */
135 u8 v_blank_f5[2]; /* for 3D mode */
136 u8 v_sync_line_aft_3[2];
137 u8 v_sync_line_aft_4[2];
138 u8 v_sync_line_aft_5[2];
139 u8 v_sync_line_aft_6[2];
140 u8 v_sync_line_aft_pxl_3[2];
141 u8 v_sync_line_aft_pxl_4[2];
142 u8 v_sync_line_aft_pxl_5[2];
143 u8 v_sync_line_aft_pxl_6[2];
144 u8 vact_space_1[2];
145 u8 vact_space_2[2];
146 u8 vact_space_3[2];
147 u8 vact_space_4[2];
148 u8 vact_space_5[2];
149 u8 vact_space_6[2];
150 };
151
152 struct hdmi_v13_conf {
153 struct hdmi_v13_core_regs core;
154 struct hdmi_tg_regs tg;
155 };
156
157 struct hdmi_v14_conf {
158 struct hdmi_v14_core_regs core;
159 struct hdmi_tg_regs tg;
160 };
161
162 struct hdmi_conf_regs {
163 int pixel_clock;
164 int cea_video_id;
165 enum hdmi_picture_aspect aspect_ratio;
166 union {
167 struct hdmi_v13_conf v13_conf;
168 struct hdmi_v14_conf v14_conf;
169 } conf;
170 };
171
172 struct hdmi_context {
173 struct device *dev;
174 struct drm_device *drm_dev;
175 bool hpd;
176 bool powered;
177 bool dvi_mode;
178 struct mutex hdmi_mutex;
179
180 void __iomem *regs;
181 int irq;
182
183 struct i2c_client *ddc_port;
184 struct i2c_client *hdmiphy_port;
185
186 /* current hdmiphy conf regs */
187 struct hdmi_conf_regs mode_conf;
188
189 struct hdmi_resources res;
190
191 int hpd_gpio;
192
193 enum hdmi_type type;
194 };
195
196 struct hdmiphy_config {
197 int pixel_clock;
198 u8 conf[32];
199 };
200
201 /* list of phy config settings */
202 static const struct hdmiphy_config hdmiphy_v13_configs[] = {
203 {
204 .pixel_clock = 27000000,
205 .conf = {
206 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
207 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
208 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
209 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
210 },
211 },
212 {
213 .pixel_clock = 27027000,
214 .conf = {
215 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
216 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
217 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
218 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
219 },
220 },
221 {
222 .pixel_clock = 74176000,
223 .conf = {
224 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
225 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
226 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
227 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
228 },
229 },
230 {
231 .pixel_clock = 74250000,
232 .conf = {
233 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
234 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
235 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
236 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
237 },
238 },
239 {
240 .pixel_clock = 148500000,
241 .conf = {
242 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
243 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
244 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
245 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
246 },
247 },
248 };
249
250 static const struct hdmiphy_config hdmiphy_v14_configs[] = {
251 {
252 .pixel_clock = 25200000,
253 .conf = {
254 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
255 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
256 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
257 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
258 },
259 },
260 {
261 .pixel_clock = 27000000,
262 .conf = {
263 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
264 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
265 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
266 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
267 },
268 },
269 {
270 .pixel_clock = 27027000,
271 .conf = {
272 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
273 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
274 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
275 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
276 },
277 },
278 {
279 .pixel_clock = 36000000,
280 .conf = {
281 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
282 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
283 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
284 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
285 },
286 },
287 {
288 .pixel_clock = 40000000,
289 .conf = {
290 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
291 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
292 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
293 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
294 },
295 },
296 {
297 .pixel_clock = 65000000,
298 .conf = {
299 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
300 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
301 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
302 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
303 },
304 },
305 {
306 .pixel_clock = 71000000,
307 .conf = {
308 0x01, 0x91, 0x1e, 0x15, 0x40, 0x3c, 0xce, 0x08,
309 0x04, 0x20, 0xb2, 0xd8, 0x45, 0xa0, 0xac, 0x80,
310 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
311 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
312 },
313 },
314 {
315 .pixel_clock = 73250000,
316 .conf = {
317 0x01, 0xd1, 0x1f, 0x15, 0x40, 0x18, 0xe9, 0x08,
318 0x02, 0xa0, 0xb7, 0xd8, 0x45, 0xa0, 0xac, 0x80,
319 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
320 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
321 },
322 },
323 {
324 .pixel_clock = 74176000,
325 .conf = {
326 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
327 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
328 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
329 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
330 },
331 },
332 {
333 .pixel_clock = 74250000,
334 .conf = {
335 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
336 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
337 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
338 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
339 },
340 },
341 {
342 .pixel_clock = 83500000,
343 .conf = {
344 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
345 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
346 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
347 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
348 },
349 },
350 {
351 .pixel_clock = 88750000,
352 .conf = {
353 0x01, 0x91, 0x25, 0x17, 0x40, 0x30, 0xfe, 0x08,
354 0x06, 0x20, 0xde, 0xd8, 0x45, 0xa0, 0xac, 0x80,
355 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
356 0x54, 0x8a, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
357 },
358 },
359 {
360 .pixel_clock = 106500000,
361 .conf = {
362 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
363 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
364 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
365 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
366 },
367 },
368 {
369 .pixel_clock = 108000000,
370 .conf = {
371 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
372 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
373 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
374 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
375 },
376 },
377 {
378 .pixel_clock = 115500000,
379 .conf = {
380 0x01, 0xd1, 0x30, 0x1a, 0x40, 0x40, 0x10, 0x04,
381 0x04, 0xa0, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
382 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
383 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
384 },
385 },
386 {
387 .pixel_clock = 119000000,
388 .conf = {
389 0x01, 0x91, 0x32, 0x14, 0x40, 0x60, 0xd8, 0x08,
390 0x06, 0x20, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
391 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
392 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
393 },
394 },
395 {
396 .pixel_clock = 146250000,
397 .conf = {
398 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
399 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
400 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
401 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
402 },
403 },
404 {
405 .pixel_clock = 148500000,
406 .conf = {
407 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
408 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
409 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
410 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
411 },
412 },
413 };
414
415 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
416 {
417 return readl(hdata->regs + reg_id);
418 }
419
420 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
421 u32 reg_id, u8 value)
422 {
423 writeb(value, hdata->regs + reg_id);
424 }
425
426 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
427 u32 reg_id, u32 value, u32 mask)
428 {
429 u32 old = readl(hdata->regs + reg_id);
430 value = (value & mask) | (old & ~mask);
431 writel(value, hdata->regs + reg_id);
432 }
433
434 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
435 {
436 #define DUMPREG(reg_id) \
437 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
438 readl(hdata->regs + reg_id))
439 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
440 DUMPREG(HDMI_INTC_FLAG);
441 DUMPREG(HDMI_INTC_CON);
442 DUMPREG(HDMI_HPD_STATUS);
443 DUMPREG(HDMI_V13_PHY_RSTOUT);
444 DUMPREG(HDMI_V13_PHY_VPLL);
445 DUMPREG(HDMI_V13_PHY_CMU);
446 DUMPREG(HDMI_V13_CORE_RSTOUT);
447
448 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
449 DUMPREG(HDMI_CON_0);
450 DUMPREG(HDMI_CON_1);
451 DUMPREG(HDMI_CON_2);
452 DUMPREG(HDMI_SYS_STATUS);
453 DUMPREG(HDMI_V13_PHY_STATUS);
454 DUMPREG(HDMI_STATUS_EN);
455 DUMPREG(HDMI_HPD);
456 DUMPREG(HDMI_MODE_SEL);
457 DUMPREG(HDMI_V13_HPD_GEN);
458 DUMPREG(HDMI_V13_DC_CONTROL);
459 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
460
461 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
462 DUMPREG(HDMI_H_BLANK_0);
463 DUMPREG(HDMI_H_BLANK_1);
464 DUMPREG(HDMI_V13_V_BLANK_0);
465 DUMPREG(HDMI_V13_V_BLANK_1);
466 DUMPREG(HDMI_V13_V_BLANK_2);
467 DUMPREG(HDMI_V13_H_V_LINE_0);
468 DUMPREG(HDMI_V13_H_V_LINE_1);
469 DUMPREG(HDMI_V13_H_V_LINE_2);
470 DUMPREG(HDMI_VSYNC_POL);
471 DUMPREG(HDMI_INT_PRO_MODE);
472 DUMPREG(HDMI_V13_V_BLANK_F_0);
473 DUMPREG(HDMI_V13_V_BLANK_F_1);
474 DUMPREG(HDMI_V13_V_BLANK_F_2);
475 DUMPREG(HDMI_V13_H_SYNC_GEN_0);
476 DUMPREG(HDMI_V13_H_SYNC_GEN_1);
477 DUMPREG(HDMI_V13_H_SYNC_GEN_2);
478 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
479 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
480 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
481 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
482 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
483 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
484 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
485 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
486 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
487
488 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
489 DUMPREG(HDMI_TG_CMD);
490 DUMPREG(HDMI_TG_H_FSZ_L);
491 DUMPREG(HDMI_TG_H_FSZ_H);
492 DUMPREG(HDMI_TG_HACT_ST_L);
493 DUMPREG(HDMI_TG_HACT_ST_H);
494 DUMPREG(HDMI_TG_HACT_SZ_L);
495 DUMPREG(HDMI_TG_HACT_SZ_H);
496 DUMPREG(HDMI_TG_V_FSZ_L);
497 DUMPREG(HDMI_TG_V_FSZ_H);
498 DUMPREG(HDMI_TG_VSYNC_L);
499 DUMPREG(HDMI_TG_VSYNC_H);
500 DUMPREG(HDMI_TG_VSYNC2_L);
501 DUMPREG(HDMI_TG_VSYNC2_H);
502 DUMPREG(HDMI_TG_VACT_ST_L);
503 DUMPREG(HDMI_TG_VACT_ST_H);
504 DUMPREG(HDMI_TG_VACT_SZ_L);
505 DUMPREG(HDMI_TG_VACT_SZ_H);
506 DUMPREG(HDMI_TG_FIELD_CHG_L);
507 DUMPREG(HDMI_TG_FIELD_CHG_H);
508 DUMPREG(HDMI_TG_VACT_ST2_L);
509 DUMPREG(HDMI_TG_VACT_ST2_H);
510 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
511 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
512 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
513 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
514 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
515 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
516 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
517 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
518 #undef DUMPREG
519 }
520
521 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
522 {
523 int i;
524
525 #define DUMPREG(reg_id) \
526 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
527 readl(hdata->regs + reg_id))
528
529 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
530 DUMPREG(HDMI_INTC_CON);
531 DUMPREG(HDMI_INTC_FLAG);
532 DUMPREG(HDMI_HPD_STATUS);
533 DUMPREG(HDMI_INTC_CON_1);
534 DUMPREG(HDMI_INTC_FLAG_1);
535 DUMPREG(HDMI_PHY_STATUS_0);
536 DUMPREG(HDMI_PHY_STATUS_PLL);
537 DUMPREG(HDMI_PHY_CON_0);
538 DUMPREG(HDMI_PHY_RSTOUT);
539 DUMPREG(HDMI_PHY_VPLL);
540 DUMPREG(HDMI_PHY_CMU);
541 DUMPREG(HDMI_CORE_RSTOUT);
542
543 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
544 DUMPREG(HDMI_CON_0);
545 DUMPREG(HDMI_CON_1);
546 DUMPREG(HDMI_CON_2);
547 DUMPREG(HDMI_SYS_STATUS);
548 DUMPREG(HDMI_PHY_STATUS_0);
549 DUMPREG(HDMI_STATUS_EN);
550 DUMPREG(HDMI_HPD);
551 DUMPREG(HDMI_MODE_SEL);
552 DUMPREG(HDMI_ENC_EN);
553 DUMPREG(HDMI_DC_CONTROL);
554 DUMPREG(HDMI_VIDEO_PATTERN_GEN);
555
556 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
557 DUMPREG(HDMI_H_BLANK_0);
558 DUMPREG(HDMI_H_BLANK_1);
559 DUMPREG(HDMI_V2_BLANK_0);
560 DUMPREG(HDMI_V2_BLANK_1);
561 DUMPREG(HDMI_V1_BLANK_0);
562 DUMPREG(HDMI_V1_BLANK_1);
563 DUMPREG(HDMI_V_LINE_0);
564 DUMPREG(HDMI_V_LINE_1);
565 DUMPREG(HDMI_H_LINE_0);
566 DUMPREG(HDMI_H_LINE_1);
567 DUMPREG(HDMI_HSYNC_POL);
568
569 DUMPREG(HDMI_VSYNC_POL);
570 DUMPREG(HDMI_INT_PRO_MODE);
571 DUMPREG(HDMI_V_BLANK_F0_0);
572 DUMPREG(HDMI_V_BLANK_F0_1);
573 DUMPREG(HDMI_V_BLANK_F1_0);
574 DUMPREG(HDMI_V_BLANK_F1_1);
575
576 DUMPREG(HDMI_H_SYNC_START_0);
577 DUMPREG(HDMI_H_SYNC_START_1);
578 DUMPREG(HDMI_H_SYNC_END_0);
579 DUMPREG(HDMI_H_SYNC_END_1);
580
581 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
582 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
583 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
584 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
585
586 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
587 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
588 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
589 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
590
591 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
592 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
593 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
594 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
595
596 DUMPREG(HDMI_V_BLANK_F2_0);
597 DUMPREG(HDMI_V_BLANK_F2_1);
598 DUMPREG(HDMI_V_BLANK_F3_0);
599 DUMPREG(HDMI_V_BLANK_F3_1);
600 DUMPREG(HDMI_V_BLANK_F4_0);
601 DUMPREG(HDMI_V_BLANK_F4_1);
602 DUMPREG(HDMI_V_BLANK_F5_0);
603 DUMPREG(HDMI_V_BLANK_F5_1);
604
605 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
606 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
607 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
608 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
609 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
610 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
611 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
612 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
613
614 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
615 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
616 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
617 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
618 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
619 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
620 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
621 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
622
623 DUMPREG(HDMI_VACT_SPACE_1_0);
624 DUMPREG(HDMI_VACT_SPACE_1_1);
625 DUMPREG(HDMI_VACT_SPACE_2_0);
626 DUMPREG(HDMI_VACT_SPACE_2_1);
627 DUMPREG(HDMI_VACT_SPACE_3_0);
628 DUMPREG(HDMI_VACT_SPACE_3_1);
629 DUMPREG(HDMI_VACT_SPACE_4_0);
630 DUMPREG(HDMI_VACT_SPACE_4_1);
631 DUMPREG(HDMI_VACT_SPACE_5_0);
632 DUMPREG(HDMI_VACT_SPACE_5_1);
633 DUMPREG(HDMI_VACT_SPACE_6_0);
634 DUMPREG(HDMI_VACT_SPACE_6_1);
635
636 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
637 DUMPREG(HDMI_TG_CMD);
638 DUMPREG(HDMI_TG_H_FSZ_L);
639 DUMPREG(HDMI_TG_H_FSZ_H);
640 DUMPREG(HDMI_TG_HACT_ST_L);
641 DUMPREG(HDMI_TG_HACT_ST_H);
642 DUMPREG(HDMI_TG_HACT_SZ_L);
643 DUMPREG(HDMI_TG_HACT_SZ_H);
644 DUMPREG(HDMI_TG_V_FSZ_L);
645 DUMPREG(HDMI_TG_V_FSZ_H);
646 DUMPREG(HDMI_TG_VSYNC_L);
647 DUMPREG(HDMI_TG_VSYNC_H);
648 DUMPREG(HDMI_TG_VSYNC2_L);
649 DUMPREG(HDMI_TG_VSYNC2_H);
650 DUMPREG(HDMI_TG_VACT_ST_L);
651 DUMPREG(HDMI_TG_VACT_ST_H);
652 DUMPREG(HDMI_TG_VACT_SZ_L);
653 DUMPREG(HDMI_TG_VACT_SZ_H);
654 DUMPREG(HDMI_TG_FIELD_CHG_L);
655 DUMPREG(HDMI_TG_FIELD_CHG_H);
656 DUMPREG(HDMI_TG_VACT_ST2_L);
657 DUMPREG(HDMI_TG_VACT_ST2_H);
658 DUMPREG(HDMI_TG_VACT_ST3_L);
659 DUMPREG(HDMI_TG_VACT_ST3_H);
660 DUMPREG(HDMI_TG_VACT_ST4_L);
661 DUMPREG(HDMI_TG_VACT_ST4_H);
662 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
663 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
664 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
665 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
666 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
667 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
668 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
669 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
670 DUMPREG(HDMI_TG_3D);
671
672 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
673 DUMPREG(HDMI_AVI_CON);
674 DUMPREG(HDMI_AVI_HEADER0);
675 DUMPREG(HDMI_AVI_HEADER1);
676 DUMPREG(HDMI_AVI_HEADER2);
677 DUMPREG(HDMI_AVI_CHECK_SUM);
678 DUMPREG(HDMI_VSI_CON);
679 DUMPREG(HDMI_VSI_HEADER0);
680 DUMPREG(HDMI_VSI_HEADER1);
681 DUMPREG(HDMI_VSI_HEADER2);
682 for (i = 0; i < 7; ++i)
683 DUMPREG(HDMI_VSI_DATA(i));
684
685 #undef DUMPREG
686 }
687
688 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
689 {
690 if (hdata->type == HDMI_TYPE13)
691 hdmi_v13_regs_dump(hdata, prefix);
692 else
693 hdmi_v14_regs_dump(hdata, prefix);
694 }
695
696 static u8 hdmi_chksum(struct hdmi_context *hdata,
697 u32 start, u8 len, u32 hdr_sum)
698 {
699 int i;
700
701 /* hdr_sum : header0 + header1 + header2
702 * start : start address of packet byte1
703 * len : packet bytes - 1 */
704 for (i = 0; i < len; ++i)
705 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
706
707 /* return 2's complement of 8 bit hdr_sum */
708 return (u8)(~(hdr_sum & 0xff) + 1);
709 }
710
711 static void hdmi_reg_infoframe(struct hdmi_context *hdata,
712 union hdmi_infoframe *infoframe)
713 {
714 u32 hdr_sum;
715 u8 chksum;
716 u32 mod;
717 u32 vic;
718
719 mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
720 if (hdata->dvi_mode) {
721 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
722 HDMI_VSI_CON_DO_NOT_TRANSMIT);
723 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
724 HDMI_AVI_CON_DO_NOT_TRANSMIT);
725 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
726 return;
727 }
728
729 switch (infoframe->any.type) {
730 case HDMI_INFOFRAME_TYPE_AVI:
731 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
732 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
733 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
734 infoframe->any.version);
735 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
736 hdr_sum = infoframe->any.type + infoframe->any.version +
737 infoframe->any.length;
738
739 /* Output format zero hardcoded ,RGB YBCR selection */
740 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
741 AVI_ACTIVE_FORMAT_VALID |
742 AVI_UNDERSCANNED_DISPLAY_VALID);
743
744 /*
745 * Set the aspect ratio as per the mode, mentioned in
746 * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
747 */
748 switch (hdata->mode_conf.aspect_ratio) {
749 case HDMI_PICTURE_ASPECT_4_3:
750 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
751 hdata->mode_conf.aspect_ratio |
752 AVI_4_3_CENTER_RATIO);
753 break;
754 case HDMI_PICTURE_ASPECT_16_9:
755 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
756 hdata->mode_conf.aspect_ratio |
757 AVI_16_9_CENTER_RATIO);
758 break;
759 case HDMI_PICTURE_ASPECT_NONE:
760 default:
761 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
762 hdata->mode_conf.aspect_ratio |
763 AVI_SAME_AS_PIC_ASPECT_RATIO);
764 break;
765 }
766
767 vic = hdata->mode_conf.cea_video_id;
768 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
769
770 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
771 infoframe->any.length, hdr_sum);
772 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
773 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
774 break;
775 case HDMI_INFOFRAME_TYPE_AUDIO:
776 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
777 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
778 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
779 infoframe->any.version);
780 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
781 hdr_sum = infoframe->any.type + infoframe->any.version +
782 infoframe->any.length;
783 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
784 infoframe->any.length, hdr_sum);
785 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
786 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
787 break;
788 default:
789 break;
790 }
791 }
792
793 static int hdmi_initialize(struct exynos_drm_display *display,
794 struct drm_device *drm_dev)
795 {
796 struct hdmi_context *hdata = display->ctx;
797
798 hdata->drm_dev = drm_dev;
799
800 return 0;
801 }
802
803 static bool hdmi_is_connected(struct exynos_drm_display *display)
804 {
805 struct hdmi_context *hdata = display->ctx;
806
807 return hdata->hpd;
808 }
809
810 static struct edid *hdmi_get_edid(struct exynos_drm_display *display,
811 struct drm_connector *connector)
812 {
813 struct edid *raw_edid;
814 struct hdmi_context *hdata = display->ctx;
815
816 if (!hdata->ddc_port)
817 return ERR_PTR(-ENODEV);
818
819 raw_edid = drm_get_edid(connector, hdata->ddc_port->adapter);
820 if (!raw_edid)
821 return ERR_PTR(-ENODEV);
822
823 hdata->dvi_mode = !drm_detect_hdmi_monitor(raw_edid);
824 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
825 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
826 raw_edid->width_cm, raw_edid->height_cm);
827
828 return raw_edid;
829 }
830
831 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
832 {
833 const struct hdmiphy_config *confs;
834 int count, i;
835
836 if (hdata->type == HDMI_TYPE13) {
837 confs = hdmiphy_v13_configs;
838 count = ARRAY_SIZE(hdmiphy_v13_configs);
839 } else if (hdata->type == HDMI_TYPE14) {
840 confs = hdmiphy_v14_configs;
841 count = ARRAY_SIZE(hdmiphy_v14_configs);
842 } else
843 return -EINVAL;
844
845 for (i = 0; i < count; i++)
846 if (confs[i].pixel_clock == pixel_clock)
847 return i;
848
849 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
850 return -EINVAL;
851 }
852
853 static int hdmi_check_mode(struct exynos_drm_display *display,
854 struct drm_display_mode *mode)
855 {
856 struct hdmi_context *hdata = display->ctx;
857 int ret;
858
859 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
860 mode->hdisplay, mode->vdisplay, mode->vrefresh,
861 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
862 false, mode->clock * 1000);
863
864 ret = mixer_check_mode(mode);
865 if (ret)
866 return ret;
867
868 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
869 if (ret < 0)
870 return ret;
871 return 0;
872 }
873
874 static void hdmi_mode_fixup(struct exynos_drm_display *display,
875 struct drm_connector *connector,
876 const struct drm_display_mode *mode,
877 struct drm_display_mode *adjusted_mode)
878 {
879 struct drm_display_mode *m;
880 int mode_ok;
881
882 DRM_DEBUG_KMS("%s\n", __FILE__);
883
884 drm_mode_set_crtcinfo(adjusted_mode, 0);
885
886 mode_ok = hdmi_check_mode(display, adjusted_mode);
887
888 /* just return if user desired mode exists. */
889 if (mode_ok == 0)
890 return;
891
892 /*
893 * otherwise, find the most suitable mode among modes and change it
894 * to adjusted_mode.
895 */
896 list_for_each_entry(m, &connector->modes, head) {
897 mode_ok = hdmi_check_mode(display, m);
898
899 if (mode_ok == 0) {
900 DRM_INFO("desired mode doesn't exist so\n");
901 DRM_INFO("use the most suitable mode among modes.\n");
902
903 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
904 m->hdisplay, m->vdisplay, m->vrefresh);
905
906 drm_mode_copy(adjusted_mode, m);
907 break;
908 }
909 }
910 }
911
912 static void hdmi_set_acr(u32 freq, u8 *acr)
913 {
914 u32 n, cts;
915
916 switch (freq) {
917 case 32000:
918 n = 4096;
919 cts = 27000;
920 break;
921 case 44100:
922 n = 6272;
923 cts = 30000;
924 break;
925 case 88200:
926 n = 12544;
927 cts = 30000;
928 break;
929 case 176400:
930 n = 25088;
931 cts = 30000;
932 break;
933 case 48000:
934 n = 6144;
935 cts = 27000;
936 break;
937 case 96000:
938 n = 12288;
939 cts = 27000;
940 break;
941 case 192000:
942 n = 24576;
943 cts = 27000;
944 break;
945 default:
946 n = 0;
947 cts = 0;
948 break;
949 }
950
951 acr[1] = cts >> 16;
952 acr[2] = cts >> 8 & 0xff;
953 acr[3] = cts & 0xff;
954
955 acr[4] = n >> 16;
956 acr[5] = n >> 8 & 0xff;
957 acr[6] = n & 0xff;
958 }
959
960 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
961 {
962 hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
963 hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
964 hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
965 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
966 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
967 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
968 hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
969 hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
970 hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
971
972 if (hdata->type == HDMI_TYPE13)
973 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
974 else
975 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
976 }
977
978 static void hdmi_audio_init(struct hdmi_context *hdata)
979 {
980 u32 sample_rate, bits_per_sample, frame_size_code;
981 u32 data_num, bit_ch, sample_frq;
982 u32 val;
983 u8 acr[7];
984
985 sample_rate = 44100;
986 bits_per_sample = 16;
987 frame_size_code = 0;
988
989 switch (bits_per_sample) {
990 case 20:
991 data_num = 2;
992 bit_ch = 1;
993 break;
994 case 24:
995 data_num = 3;
996 bit_ch = 1;
997 break;
998 default:
999 data_num = 1;
1000 bit_ch = 0;
1001 break;
1002 }
1003
1004 hdmi_set_acr(sample_rate, acr);
1005 hdmi_reg_acr(hdata, acr);
1006
1007 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1008 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1009 | HDMI_I2S_MUX_ENABLE);
1010
1011 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1012 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1013
1014 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1015
1016 sample_frq = (sample_rate == 44100) ? 0 :
1017 (sample_rate == 48000) ? 2 :
1018 (sample_rate == 32000) ? 3 :
1019 (sample_rate == 96000) ? 0xa : 0x0;
1020
1021 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1022 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1023
1024 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1025 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1026
1027 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1028 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1029 | HDMI_I2S_SEL_LRCK(6));
1030 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1031 | HDMI_I2S_SEL_SDATA2(4));
1032 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1033 | HDMI_I2S_SEL_SDATA2(2));
1034 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1035
1036 /* I2S_CON_1 & 2 */
1037 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1038 | HDMI_I2S_L_CH_LOW_POL);
1039 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1040 | HDMI_I2S_SET_BIT_CH(bit_ch)
1041 | HDMI_I2S_SET_SDATA_BIT(data_num)
1042 | HDMI_I2S_BASIC_FORMAT);
1043
1044 /* Configure register related to CUV information */
1045 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1046 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1047 | HDMI_I2S_COPYRIGHT
1048 | HDMI_I2S_LINEAR_PCM
1049 | HDMI_I2S_CONSUMER_FORMAT);
1050 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1051 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1052 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1053 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1054 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1055 HDMI_I2S_ORG_SMP_FREQ_44_1
1056 | HDMI_I2S_WORD_LEN_MAX24_24BITS
1057 | HDMI_I2S_WORD_LEN_MAX_24BITS);
1058
1059 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1060 }
1061
1062 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1063 {
1064 if (hdata->dvi_mode)
1065 return;
1066
1067 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1068 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1069 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1070 }
1071
1072 static void hdmi_conf_reset(struct hdmi_context *hdata)
1073 {
1074 u32 reg;
1075
1076 if (hdata->type == HDMI_TYPE13)
1077 reg = HDMI_V13_CORE_RSTOUT;
1078 else
1079 reg = HDMI_CORE_RSTOUT;
1080
1081 /* resetting HDMI core */
1082 hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT);
1083 usleep_range(10000, 12000);
1084 hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1085 usleep_range(10000, 12000);
1086 }
1087
1088 static void hdmi_conf_init(struct hdmi_context *hdata)
1089 {
1090 union hdmi_infoframe infoframe;
1091
1092 /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1093 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1094 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1095
1096 /* choose HDMI mode */
1097 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1098 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1099 /* disable bluescreen */
1100 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1101
1102 if (hdata->dvi_mode) {
1103 /* choose DVI mode */
1104 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1105 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1106 hdmi_reg_writeb(hdata, HDMI_CON_2,
1107 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1108 }
1109
1110 if (hdata->type == HDMI_TYPE13) {
1111 /* choose bluescreen (fecal) color */
1112 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1113 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1114 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1115
1116 /* enable AVI packet every vsync, fixes purple line problem */
1117 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1118 /* force RGB, look to CEA-861-D, table 7 for more detail */
1119 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1120 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1121
1122 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1123 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1124 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1125 } else {
1126 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1127 infoframe.any.version = HDMI_AVI_VERSION;
1128 infoframe.any.length = HDMI_AVI_LENGTH;
1129 hdmi_reg_infoframe(hdata, &infoframe);
1130
1131 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1132 infoframe.any.version = HDMI_AUI_VERSION;
1133 infoframe.any.length = HDMI_AUI_LENGTH;
1134 hdmi_reg_infoframe(hdata, &infoframe);
1135
1136 /* enable AVI packet every vsync, fixes purple line problem */
1137 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1138 }
1139 }
1140
1141 static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1142 {
1143 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1144 const struct hdmi_v13_core_regs *core =
1145 &hdata->mode_conf.conf.v13_conf.core;
1146 int tries;
1147
1148 /* setting core registers */
1149 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1150 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1151 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1152 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1153 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1154 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1155 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1156 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1157 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1158 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1159 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1160 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1161 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1162 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1163 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1164 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1165 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1166 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1167 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1168 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1169 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1170 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1171 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1172 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1173 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1174 /* Timing generator registers */
1175 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1176 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1177 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1178 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1179 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1180 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1181 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1182 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1183 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1184 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1185 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1186 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1187 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1188 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1189 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1190 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1191 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1192 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1193 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1194 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1195 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1196 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1197 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1198 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1199 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1200 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1201 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1202 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1203
1204 /* waiting for HDMIPHY's PLL to get to steady state */
1205 for (tries = 100; tries; --tries) {
1206 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1207 if (val & HDMI_PHY_STATUS_READY)
1208 break;
1209 usleep_range(1000, 2000);
1210 }
1211 /* steady state not achieved */
1212 if (tries == 0) {
1213 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1214 hdmi_regs_dump(hdata, "timing apply");
1215 }
1216
1217 clk_disable_unprepare(hdata->res.sclk_hdmi);
1218 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1219 clk_prepare_enable(hdata->res.sclk_hdmi);
1220
1221 /* enable HDMI and timing generator */
1222 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1223 if (core->int_pro_mode[0])
1224 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1225 HDMI_FIELD_EN);
1226 else
1227 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1228 }
1229
1230 static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1231 {
1232 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1233 const struct hdmi_v14_core_regs *core =
1234 &hdata->mode_conf.conf.v14_conf.core;
1235 int tries;
1236
1237 /* setting core registers */
1238 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1239 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1240 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1241 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1242 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1243 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1244 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1245 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1246 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1247 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1248 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1249 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1250 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1251 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1252 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1253 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1254 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1255 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1256 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1257 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1258 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1259 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1260 core->v_sync_line_bef_2[0]);
1261 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1262 core->v_sync_line_bef_2[1]);
1263 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1264 core->v_sync_line_bef_1[0]);
1265 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1266 core->v_sync_line_bef_1[1]);
1267 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1268 core->v_sync_line_aft_2[0]);
1269 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1270 core->v_sync_line_aft_2[1]);
1271 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1272 core->v_sync_line_aft_1[0]);
1273 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1274 core->v_sync_line_aft_1[1]);
1275 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1276 core->v_sync_line_aft_pxl_2[0]);
1277 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1278 core->v_sync_line_aft_pxl_2[1]);
1279 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1280 core->v_sync_line_aft_pxl_1[0]);
1281 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1282 core->v_sync_line_aft_pxl_1[1]);
1283 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1284 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1285 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1286 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1287 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1288 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1289 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1290 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1291 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1292 core->v_sync_line_aft_3[0]);
1293 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1294 core->v_sync_line_aft_3[1]);
1295 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1296 core->v_sync_line_aft_4[0]);
1297 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1298 core->v_sync_line_aft_4[1]);
1299 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1300 core->v_sync_line_aft_5[0]);
1301 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1302 core->v_sync_line_aft_5[1]);
1303 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1304 core->v_sync_line_aft_6[0]);
1305 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1306 core->v_sync_line_aft_6[1]);
1307 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1308 core->v_sync_line_aft_pxl_3[0]);
1309 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1310 core->v_sync_line_aft_pxl_3[1]);
1311 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1312 core->v_sync_line_aft_pxl_4[0]);
1313 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1314 core->v_sync_line_aft_pxl_4[1]);
1315 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1316 core->v_sync_line_aft_pxl_5[0]);
1317 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1318 core->v_sync_line_aft_pxl_5[1]);
1319 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1320 core->v_sync_line_aft_pxl_6[0]);
1321 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1322 core->v_sync_line_aft_pxl_6[1]);
1323 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1324 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1325 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1326 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1327 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1328 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1329 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1330 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1331 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1332 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1333 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1334 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1335
1336 /* Timing generator registers */
1337 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1338 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1339 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1340 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1341 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1342 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1343 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1344 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1345 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1346 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1347 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1348 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1349 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1350 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1351 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1352 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1353 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1354 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1355 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1356 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1357 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1358 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1359 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1360 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1361 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1362 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1363 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1364 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1365 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1366 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1367 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1368 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1369 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1370
1371 /* waiting for HDMIPHY's PLL to get to steady state */
1372 for (tries = 100; tries; --tries) {
1373 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1374 if (val & HDMI_PHY_STATUS_READY)
1375 break;
1376 usleep_range(1000, 2000);
1377 }
1378 /* steady state not achieved */
1379 if (tries == 0) {
1380 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1381 hdmi_regs_dump(hdata, "timing apply");
1382 }
1383
1384 clk_disable_unprepare(hdata->res.sclk_hdmi);
1385 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1386 clk_prepare_enable(hdata->res.sclk_hdmi);
1387
1388 /* enable HDMI and timing generator */
1389 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1390 if (core->int_pro_mode[0])
1391 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1392 HDMI_FIELD_EN);
1393 else
1394 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1395 }
1396
1397 static void hdmi_mode_apply(struct hdmi_context *hdata)
1398 {
1399 if (hdata->type == HDMI_TYPE13)
1400 hdmi_v13_mode_apply(hdata);
1401 else
1402 hdmi_v14_mode_apply(hdata);
1403 }
1404
1405 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1406 {
1407 u8 buffer[2];
1408 u32 reg;
1409
1410 clk_disable_unprepare(hdata->res.sclk_hdmi);
1411 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
1412 clk_prepare_enable(hdata->res.sclk_hdmi);
1413
1414 /* operation mode */
1415 buffer[0] = 0x1f;
1416 buffer[1] = 0x00;
1417
1418 if (hdata->hdmiphy_port)
1419 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1420
1421 if (hdata->type == HDMI_TYPE13)
1422 reg = HDMI_V13_PHY_RSTOUT;
1423 else
1424 reg = HDMI_PHY_RSTOUT;
1425
1426 /* reset hdmiphy */
1427 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1428 usleep_range(10000, 12000);
1429 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
1430 usleep_range(10000, 12000);
1431 }
1432
1433 static void hdmiphy_poweron(struct hdmi_context *hdata)
1434 {
1435 if (hdata->type == HDMI_TYPE14)
1436 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0,
1437 HDMI_PHY_POWER_OFF_EN);
1438 }
1439
1440 static void hdmiphy_poweroff(struct hdmi_context *hdata)
1441 {
1442 if (hdata->type == HDMI_TYPE14)
1443 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0,
1444 HDMI_PHY_POWER_OFF_EN);
1445 }
1446
1447 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1448 {
1449 const u8 *hdmiphy_data;
1450 u8 buffer[32];
1451 u8 operation[2];
1452 u8 read_buffer[32] = {0, };
1453 int ret;
1454 int i;
1455
1456 if (!hdata->hdmiphy_port) {
1457 DRM_ERROR("hdmiphy is not attached\n");
1458 return;
1459 }
1460
1461 /* pixel clock */
1462 i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1463 if (i < 0) {
1464 DRM_ERROR("failed to find hdmiphy conf\n");
1465 return;
1466 }
1467
1468 if (hdata->type == HDMI_TYPE13)
1469 hdmiphy_data = hdmiphy_v13_configs[i].conf;
1470 else
1471 hdmiphy_data = hdmiphy_v14_configs[i].conf;
1472
1473 memcpy(buffer, hdmiphy_data, 32);
1474 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1475 if (ret != 32) {
1476 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1477 return;
1478 }
1479
1480 usleep_range(10000, 12000);
1481
1482 /* operation mode */
1483 operation[0] = 0x1f;
1484 operation[1] = 0x80;
1485
1486 ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1487 if (ret != 2) {
1488 DRM_ERROR("failed to enable hdmiphy\n");
1489 return;
1490 }
1491
1492 ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1493 if (ret < 0) {
1494 DRM_ERROR("failed to read hdmiphy config\n");
1495 return;
1496 }
1497
1498 for (i = 0; i < ret; i++)
1499 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1500 "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1501 }
1502
1503 static void hdmi_conf_apply(struct hdmi_context *hdata)
1504 {
1505 hdmiphy_conf_reset(hdata);
1506 hdmiphy_conf_apply(hdata);
1507
1508 mutex_lock(&hdata->hdmi_mutex);
1509 hdmi_conf_reset(hdata);
1510 hdmi_conf_init(hdata);
1511 mutex_unlock(&hdata->hdmi_mutex);
1512
1513 hdmi_audio_init(hdata);
1514
1515 /* setting core registers */
1516 hdmi_mode_apply(hdata);
1517 hdmi_audio_control(hdata, true);
1518
1519 hdmi_regs_dump(hdata, "start");
1520 }
1521
1522 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1523 {
1524 int i;
1525 BUG_ON(num_bytes > 4);
1526 for (i = 0; i < num_bytes; i++)
1527 reg_pair[i] = (value >> (8 * i)) & 0xff;
1528 }
1529
1530 static void hdmi_v13_mode_set(struct hdmi_context *hdata,
1531 struct drm_display_mode *m)
1532 {
1533 struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1534 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1535 unsigned int val;
1536
1537 hdata->mode_conf.cea_video_id =
1538 drm_match_cea_mode((struct drm_display_mode *)m);
1539 hdata->mode_conf.pixel_clock = m->clock * 1000;
1540 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1541
1542 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1543 hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1544
1545 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1546 hdmi_set_reg(core->vsync_pol, 1, val);
1547
1548 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1549 hdmi_set_reg(core->int_pro_mode, 1, val);
1550
1551 val = (m->hsync_start - m->hdisplay - 2);
1552 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1553 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1554 hdmi_set_reg(core->h_sync_gen, 3, val);
1555
1556 /*
1557 * Quirk requirement for exynos HDMI IP design,
1558 * 2 pixels less than the actual calculation for hsync_start
1559 * and end.
1560 */
1561
1562 /* Following values & calculations differ for different type of modes */
1563 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1564 /* Interlaced Mode */
1565 val = ((m->vsync_end - m->vdisplay) / 2);
1566 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1567 hdmi_set_reg(core->v_sync_gen1, 3, val);
1568
1569 val = m->vtotal / 2;
1570 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1571 hdmi_set_reg(core->v_blank, 3, val);
1572
1573 val = (m->vtotal +
1574 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1575 val |= m->vtotal << 11;
1576 hdmi_set_reg(core->v_blank_f, 3, val);
1577
1578 val = ((m->vtotal / 2) + 7);
1579 val |= ((m->vtotal / 2) + 2) << 12;
1580 hdmi_set_reg(core->v_sync_gen2, 3, val);
1581
1582 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1583 val |= ((m->htotal / 2) +
1584 (m->hsync_start - m->hdisplay)) << 12;
1585 hdmi_set_reg(core->v_sync_gen3, 3, val);
1586
1587 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1588 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1589
1590 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1591 } else {
1592 /* Progressive Mode */
1593
1594 val = m->vtotal;
1595 val |= (m->vtotal - m->vdisplay) << 11;
1596 hdmi_set_reg(core->v_blank, 3, val);
1597
1598 hdmi_set_reg(core->v_blank_f, 3, 0);
1599
1600 val = (m->vsync_end - m->vdisplay);
1601 val |= ((m->vsync_start - m->vdisplay) << 12);
1602 hdmi_set_reg(core->v_sync_gen1, 3, val);
1603
1604 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */
1605 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */
1606 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1607 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1608 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1609 }
1610
1611 /* Timing generator registers */
1612 hdmi_set_reg(tg->cmd, 1, 0x0);
1613 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1614 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1615 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1616 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1617 hdmi_set_reg(tg->vsync, 2, 0x1);
1618 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1619 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1620 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1621 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1622 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1623 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1624 hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1625 }
1626
1627 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1628 struct drm_display_mode *m)
1629 {
1630 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1631 struct hdmi_v14_core_regs *core =
1632 &hdata->mode_conf.conf.v14_conf.core;
1633
1634 hdata->mode_conf.cea_video_id =
1635 drm_match_cea_mode((struct drm_display_mode *)m);
1636 hdata->mode_conf.pixel_clock = m->clock * 1000;
1637 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1638
1639 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1640 hdmi_set_reg(core->v_line, 2, m->vtotal);
1641 hdmi_set_reg(core->h_line, 2, m->htotal);
1642 hdmi_set_reg(core->hsync_pol, 1,
1643 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1644 hdmi_set_reg(core->vsync_pol, 1,
1645 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1646 hdmi_set_reg(core->int_pro_mode, 1,
1647 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1648
1649 /*
1650 * Quirk requirement for exynos 5 HDMI IP design,
1651 * 2 pixels less than the actual calculation for hsync_start
1652 * and end.
1653 */
1654
1655 /* Following values & calculations differ for different type of modes */
1656 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1657 /* Interlaced Mode */
1658 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1659 (m->vsync_end - m->vdisplay) / 2);
1660 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1661 (m->vsync_start - m->vdisplay) / 2);
1662 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1663 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1664 hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2);
1665 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1666 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1667 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1668 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1669 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1670 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1671 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1672 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1673 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1674 hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2);
1675 hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1);
1676 hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1);
1677 hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1);
1678 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1679 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1680 } else {
1681 /* Progressive Mode */
1682 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1683 m->vsync_end - m->vdisplay);
1684 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1685 m->vsync_start - m->vdisplay);
1686 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1687 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1688 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1689 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1690 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1691 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1692 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1693 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1694 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1695 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1696 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1697 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1698 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1699 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1700 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1701 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1702 }
1703
1704 /* Following values & calculations are same irrespective of mode type */
1705 hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1706 hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1707 hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1708 hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1709 hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1710 hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1711 hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1712 hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1713 hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1714 hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1715 hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1716 hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1717 hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1718 hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1719 hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1720 hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1721 hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1722 hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1723 hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1724 hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1725
1726 /* Timing generator registers */
1727 hdmi_set_reg(tg->cmd, 1, 0x0);
1728 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1729 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1730 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1731 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1732 hdmi_set_reg(tg->vsync, 2, 0x1);
1733 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1734 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1735 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1736 hdmi_set_reg(tg->tg_3d, 1, 0x0);
1737 }
1738
1739 static void hdmi_mode_set(struct exynos_drm_display *display,
1740 struct drm_display_mode *mode)
1741 {
1742 struct hdmi_context *hdata = display->ctx;
1743 struct drm_display_mode *m = mode;
1744
1745 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
1746 m->hdisplay, m->vdisplay,
1747 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1748 "INTERLACED" : "PROGERESSIVE");
1749
1750 if (hdata->type == HDMI_TYPE13)
1751 hdmi_v13_mode_set(hdata, mode);
1752 else
1753 hdmi_v14_mode_set(hdata, mode);
1754 }
1755
1756 static void hdmi_get_max_resol(struct exynos_drm_display *display,
1757 unsigned int *width, unsigned int *height)
1758 {
1759 *width = MAX_WIDTH;
1760 *height = MAX_HEIGHT;
1761 }
1762
1763 static void hdmi_commit(struct exynos_drm_display *display)
1764 {
1765 struct hdmi_context *hdata = display->ctx;
1766
1767 mutex_lock(&hdata->hdmi_mutex);
1768 if (!hdata->powered) {
1769 mutex_unlock(&hdata->hdmi_mutex);
1770 return;
1771 }
1772 mutex_unlock(&hdata->hdmi_mutex);
1773
1774 hdmi_conf_apply(hdata);
1775 }
1776
1777 static void hdmi_poweron(struct exynos_drm_display *display)
1778 {
1779 struct hdmi_context *hdata = display->ctx;
1780 struct hdmi_resources *res = &hdata->res;
1781
1782 mutex_lock(&hdata->hdmi_mutex);
1783 if (hdata->powered) {
1784 mutex_unlock(&hdata->hdmi_mutex);
1785 return;
1786 }
1787
1788 hdata->powered = true;
1789
1790 mutex_unlock(&hdata->hdmi_mutex);
1791
1792 if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
1793 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
1794
1795 clk_prepare_enable(res->hdmiphy);
1796 clk_prepare_enable(res->hdmi);
1797 clk_prepare_enable(res->sclk_hdmi);
1798
1799 hdmiphy_poweron(hdata);
1800 hdmi_commit(display);
1801 }
1802
1803 static void hdmi_poweroff(struct exynos_drm_display *display)
1804 {
1805 struct hdmi_context *hdata = display->ctx;
1806 struct hdmi_resources *res = &hdata->res;
1807
1808 mutex_lock(&hdata->hdmi_mutex);
1809 if (!hdata->powered)
1810 goto out;
1811 mutex_unlock(&hdata->hdmi_mutex);
1812
1813 /*
1814 * The TV power domain needs any condition of hdmiphy to turn off and
1815 * its reset state seems to meet the condition.
1816 */
1817 hdmiphy_conf_reset(hdata);
1818 hdmiphy_poweroff(hdata);
1819
1820 clk_disable_unprepare(res->sclk_hdmi);
1821 clk_disable_unprepare(res->hdmi);
1822 clk_disable_unprepare(res->hdmiphy);
1823 regulator_bulk_disable(res->regul_count, res->regul_bulk);
1824
1825 mutex_lock(&hdata->hdmi_mutex);
1826
1827 hdata->powered = false;
1828
1829 out:
1830 mutex_unlock(&hdata->hdmi_mutex);
1831 }
1832
1833 static void hdmi_dpms(struct exynos_drm_display *display, int mode)
1834 {
1835 struct hdmi_context *hdata = display->ctx;
1836
1837 DRM_DEBUG_KMS("mode %d\n", mode);
1838
1839 switch (mode) {
1840 case DRM_MODE_DPMS_ON:
1841 if (pm_runtime_suspended(hdata->dev))
1842 pm_runtime_get_sync(hdata->dev);
1843 break;
1844 case DRM_MODE_DPMS_STANDBY:
1845 case DRM_MODE_DPMS_SUSPEND:
1846 case DRM_MODE_DPMS_OFF:
1847 if (!pm_runtime_suspended(hdata->dev))
1848 pm_runtime_put_sync(hdata->dev);
1849 break;
1850 default:
1851 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
1852 break;
1853 }
1854 }
1855
1856 static struct exynos_drm_display_ops hdmi_display_ops = {
1857 .initialize = hdmi_initialize,
1858 .is_connected = hdmi_is_connected,
1859 .get_max_resol = hdmi_get_max_resol,
1860 .get_edid = hdmi_get_edid,
1861 .check_mode = hdmi_check_mode,
1862 .mode_fixup = hdmi_mode_fixup,
1863 .mode_set = hdmi_mode_set,
1864 .dpms = hdmi_dpms,
1865 .commit = hdmi_commit,
1866 };
1867
1868 static struct exynos_drm_display hdmi_display = {
1869 .type = EXYNOS_DISPLAY_TYPE_HDMI,
1870 .ops = &hdmi_display_ops,
1871 };
1872
1873 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
1874 {
1875 struct hdmi_context *hdata = arg;
1876
1877 mutex_lock(&hdata->hdmi_mutex);
1878 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
1879 mutex_unlock(&hdata->hdmi_mutex);
1880
1881 if (hdata->drm_dev)
1882 drm_helper_hpd_irq_event(hdata->drm_dev);
1883
1884 return IRQ_HANDLED;
1885 }
1886
1887 static int hdmi_resources_init(struct hdmi_context *hdata)
1888 {
1889 struct device *dev = hdata->dev;
1890 struct hdmi_resources *res = &hdata->res;
1891 static char *supply[] = {
1892 "hdmi-en",
1893 "vdd",
1894 "vdd_osc",
1895 "vdd_pll",
1896 };
1897 int i, ret;
1898
1899 DRM_DEBUG_KMS("HDMI resource init\n");
1900
1901 memset(res, 0, sizeof(*res));
1902
1903 /* get clocks, power */
1904 res->hdmi = devm_clk_get(dev, "hdmi");
1905 if (IS_ERR(res->hdmi)) {
1906 DRM_ERROR("failed to get clock 'hdmi'\n");
1907 goto fail;
1908 }
1909 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
1910 if (IS_ERR(res->sclk_hdmi)) {
1911 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
1912 goto fail;
1913 }
1914 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
1915 if (IS_ERR(res->sclk_pixel)) {
1916 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
1917 goto fail;
1918 }
1919 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
1920 if (IS_ERR(res->sclk_hdmiphy)) {
1921 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
1922 goto fail;
1923 }
1924 res->hdmiphy = devm_clk_get(dev, "hdmiphy");
1925 if (IS_ERR(res->hdmiphy)) {
1926 DRM_ERROR("failed to get clock 'hdmiphy'\n");
1927 goto fail;
1928 }
1929 res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
1930 if (IS_ERR(res->mout_hdmi)) {
1931 DRM_ERROR("failed to get clock 'mout_hdmi'\n");
1932 goto fail;
1933 }
1934
1935 clk_set_parent(res->mout_hdmi, res->sclk_pixel);
1936
1937 res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
1938 sizeof(res->regul_bulk[0]), GFP_KERNEL);
1939 if (!res->regul_bulk)
1940 goto fail;
1941 for (i = 0; i < ARRAY_SIZE(supply); ++i) {
1942 res->regul_bulk[i].supply = supply[i];
1943 res->regul_bulk[i].consumer = NULL;
1944 }
1945 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
1946 if (ret) {
1947 DRM_ERROR("failed to get regulators\n");
1948 goto fail;
1949 }
1950 res->regul_count = ARRAY_SIZE(supply);
1951
1952 return 0;
1953 fail:
1954 DRM_ERROR("HDMI resource init - failed\n");
1955 return -ENODEV;
1956 }
1957
1958 static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
1959 (struct device *dev)
1960 {
1961 struct device_node *np = dev->of_node;
1962 struct s5p_hdmi_platform_data *pd;
1963 u32 value;
1964
1965 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1966 if (!pd)
1967 goto err_data;
1968
1969 if (!of_find_property(np, "hpd-gpio", &value)) {
1970 DRM_ERROR("no hpd gpio property found\n");
1971 goto err_data;
1972 }
1973
1974 pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
1975
1976 return pd;
1977
1978 err_data:
1979 return NULL;
1980 }
1981
1982 static struct of_device_id hdmi_match_types[] = {
1983 {
1984 .compatible = "samsung,exynos5-hdmi",
1985 .data = (void *)HDMI_TYPE14,
1986 }, {
1987 .compatible = "samsung,exynos4212-hdmi",
1988 .data = (void *)HDMI_TYPE14,
1989 }, {
1990 /* end node */
1991 }
1992 };
1993
1994 static int hdmi_probe(struct platform_device *pdev)
1995 {
1996 struct device *dev = &pdev->dev;
1997 struct hdmi_context *hdata;
1998 struct s5p_hdmi_platform_data *pdata;
1999 struct resource *res;
2000 const struct of_device_id *match;
2001 struct device_node *ddc_node, *phy_node;
2002 int ret;
2003
2004 if (!dev->of_node)
2005 return -ENODEV;
2006
2007 pdata = drm_hdmi_dt_parse_pdata(dev);
2008 if (!pdata)
2009 return -EINVAL;
2010
2011 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
2012 if (!hdata)
2013 return -ENOMEM;
2014
2015 mutex_init(&hdata->hdmi_mutex);
2016
2017 platform_set_drvdata(pdev, &hdmi_display);
2018
2019 match = of_match_node(hdmi_match_types, dev->of_node);
2020 if (!match)
2021 return -ENODEV;
2022 hdata->type = (enum hdmi_type)match->data;
2023
2024 hdata->hpd_gpio = pdata->hpd_gpio;
2025 hdata->dev = dev;
2026
2027 ret = hdmi_resources_init(hdata);
2028 if (ret) {
2029 DRM_ERROR("hdmi_resources_init failed\n");
2030 return -EINVAL;
2031 }
2032
2033 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2034 hdata->regs = devm_ioremap_resource(dev, res);
2035 if (IS_ERR(hdata->regs))
2036 return PTR_ERR(hdata->regs);
2037
2038 ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
2039 if (ret) {
2040 DRM_ERROR("failed to request HPD gpio\n");
2041 return ret;
2042 }
2043
2044 /* DDC i2c driver */
2045 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2046 if (!ddc_node) {
2047 DRM_ERROR("Failed to find ddc node in device tree\n");
2048 return -ENODEV;
2049 }
2050 hdata->ddc_port = of_find_i2c_device_by_node(ddc_node);
2051 if (!hdata->ddc_port) {
2052 DRM_ERROR("Failed to get ddc i2c client by node\n");
2053 return -ENODEV;
2054 }
2055
2056 /* hdmiphy i2c driver */
2057 phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2058 if (!phy_node) {
2059 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2060 ret = -ENODEV;
2061 goto err_ddc;
2062 }
2063 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2064 if (!hdata->hdmiphy_port) {
2065 DRM_ERROR("Failed to get hdmi phy i2c client from node\n");
2066 ret = -ENODEV;
2067 goto err_ddc;
2068 }
2069
2070 hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2071 if (hdata->irq < 0) {
2072 DRM_ERROR("failed to get GPIO irq\n");
2073 ret = hdata->irq;
2074 goto err_hdmiphy;
2075 }
2076
2077 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2078
2079 ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
2080 hdmi_irq_thread, IRQF_TRIGGER_RISING |
2081 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2082 "hdmi", hdata);
2083 if (ret) {
2084 DRM_ERROR("failed to register hdmi interrupt\n");
2085 goto err_hdmiphy;
2086 }
2087
2088 hdmi_display.ctx = hdata;
2089 exynos_drm_display_register(&hdmi_display);
2090
2091 pm_runtime_enable(dev);
2092
2093 return 0;
2094
2095 err_hdmiphy:
2096 put_device(&hdata->hdmiphy_port->dev);
2097 err_ddc:
2098 put_device(&hdata->ddc_port->dev);
2099 return ret;
2100 }
2101
2102 static int hdmi_remove(struct platform_device *pdev)
2103 {
2104 struct device *dev = &pdev->dev;
2105 struct exynos_drm_display *display = get_hdmi_display(dev);
2106 struct hdmi_context *hdata = display->ctx;
2107
2108 pm_runtime_disable(dev);
2109
2110 put_device(&hdata->hdmiphy_port->dev);
2111 put_device(&hdata->ddc_port->dev);
2112
2113 return 0;
2114 }
2115
2116 #ifdef CONFIG_PM_SLEEP
2117 static int hdmi_suspend(struct device *dev)
2118 {
2119 struct exynos_drm_display *display = get_hdmi_display(dev);
2120 struct hdmi_context *hdata = display->ctx;
2121
2122 disable_irq(hdata->irq);
2123
2124 hdata->hpd = false;
2125 if (hdata->drm_dev)
2126 drm_helper_hpd_irq_event(hdata->drm_dev);
2127
2128 if (pm_runtime_suspended(dev)) {
2129 DRM_DEBUG_KMS("Already suspended\n");
2130 return 0;
2131 }
2132
2133 hdmi_poweroff(display);
2134
2135 return 0;
2136 }
2137
2138 static int hdmi_resume(struct device *dev)
2139 {
2140 struct exynos_drm_display *display = get_hdmi_display(dev);
2141 struct hdmi_context *hdata = display->ctx;
2142
2143 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2144
2145 enable_irq(hdata->irq);
2146
2147 if (!pm_runtime_suspended(dev)) {
2148 DRM_DEBUG_KMS("Already resumed\n");
2149 return 0;
2150 }
2151
2152 hdmi_poweron(display);
2153
2154 return 0;
2155 }
2156 #endif
2157
2158 #ifdef CONFIG_PM_RUNTIME
2159 static int hdmi_runtime_suspend(struct device *dev)
2160 {
2161 struct exynos_drm_display *display = get_hdmi_display(dev);
2162
2163 hdmi_poweroff(display);
2164
2165 return 0;
2166 }
2167
2168 static int hdmi_runtime_resume(struct device *dev)
2169 {
2170 struct exynos_drm_display *display = get_hdmi_display(dev);
2171
2172 hdmi_poweron(display);
2173
2174 return 0;
2175 }
2176 #endif
2177
2178 static const struct dev_pm_ops hdmi_pm_ops = {
2179 SET_SYSTEM_SLEEP_PM_OPS(hdmi_suspend, hdmi_resume)
2180 SET_RUNTIME_PM_OPS(hdmi_runtime_suspend, hdmi_runtime_resume, NULL)
2181 };
2182
2183 struct platform_driver hdmi_driver = {
2184 .probe = hdmi_probe,
2185 .remove = hdmi_remove,
2186 .driver = {
2187 .name = "exynos-hdmi",
2188 .owner = THIS_MODULE,
2189 .pm = &hdmi_pm_ops,
2190 .of_match_table = hdmi_match_types,
2191 },
2192 };
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