1 /**************************************************************************
2 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 **************************************************************************/
20 #include <linux/backlight.h>
23 #include <drm/gma_drm.h>
26 #include "psb_intel_reg.h"
27 #include "intel_bios.h"
28 #include "cdv_device.h"
30 #define VGA_SR_INDEX 0x3c4
31 #define VGA_SR_DATA 0x3c5
33 static void cdv_disable_vga(struct drm_device
*dev
)
40 outb(1, VGA_SR_INDEX
);
41 sr1
= inb(VGA_SR_DATA
);
42 outb(sr1
| 1<<5, VGA_SR_DATA
);
45 REG_WRITE(vga_reg
, VGA_DISP_DISABLE
);
49 static int cdv_output_init(struct drm_device
*dev
)
51 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
53 drm_mode_create_scaling_mode_property(dev
);
57 cdv_intel_crt_init(dev
, &dev_priv
->mode_dev
);
58 cdv_intel_lvds_init(dev
, &dev_priv
->mode_dev
);
60 /* These bits indicate HDMI not SDVO on CDV */
61 if (REG_READ(SDVOB
) & SDVO_DETECTED
) {
62 cdv_hdmi_init(dev
, &dev_priv
->mode_dev
, SDVOB
);
63 if (REG_READ(DP_B
) & DP_DETECTED
)
64 cdv_intel_dp_init(dev
, &dev_priv
->mode_dev
, DP_B
);
67 if (REG_READ(SDVOC
) & SDVO_DETECTED
) {
68 cdv_hdmi_init(dev
, &dev_priv
->mode_dev
, SDVOC
);
69 if (REG_READ(DP_C
) & DP_DETECTED
)
70 cdv_intel_dp_init(dev
, &dev_priv
->mode_dev
, DP_C
);
75 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
78 * Cedartrail Backlght Interfaces
81 static struct backlight_device
*cdv_backlight_device
;
83 static int cdv_backlight_combination_mode(struct drm_device
*dev
)
85 return REG_READ(BLC_PWM_CTL2
) & PWM_LEGACY_MODE
;
88 static u32
cdv_get_max_backlight(struct drm_device
*dev
)
90 u32 max
= REG_READ(BLC_PWM_CTL
);
93 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n");
94 /* i915 does this, I believe which means that we should not
95 * smash PWM control as firmware will take control of it. */
100 if (cdv_backlight_combination_mode(dev
))
105 static int cdv_get_brightness(struct backlight_device
*bd
)
107 struct drm_device
*dev
= bl_get_data(bd
);
108 u32 val
= REG_READ(BLC_PWM_CTL
) & BACKLIGHT_DUTY_CYCLE_MASK
;
110 if (cdv_backlight_combination_mode(dev
)) {
114 pci_read_config_byte(dev
->pdev
, 0xF4, &lbpc
);
117 return (val
* 100)/cdv_get_max_backlight(dev
);
121 static int cdv_set_brightness(struct backlight_device
*bd
)
123 struct drm_device
*dev
= bl_get_data(bd
);
124 int level
= bd
->props
.brightness
;
127 /* Percentage 1-100% being valid */
131 level
*= cdv_get_max_backlight(dev
);
134 if (cdv_backlight_combination_mode(dev
)) {
135 u32 max
= cdv_get_max_backlight(dev
);
138 lbpc
= level
* 0xfe / max
+ 1;
141 pci_write_config_byte(dev
->pdev
, 0xF4, lbpc
);
144 blc_pwm_ctl
= REG_READ(BLC_PWM_CTL
) & ~BACKLIGHT_DUTY_CYCLE_MASK
;
145 REG_WRITE(BLC_PWM_CTL
, (blc_pwm_ctl
|
146 (level
<< BACKLIGHT_DUTY_CYCLE_SHIFT
)));
150 static const struct backlight_ops cdv_ops
= {
151 .get_brightness
= cdv_get_brightness
,
152 .update_status
= cdv_set_brightness
,
155 static int cdv_backlight_init(struct drm_device
*dev
)
157 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
158 struct backlight_properties props
;
160 memset(&props
, 0, sizeof(struct backlight_properties
));
161 props
.max_brightness
= 100;
162 props
.type
= BACKLIGHT_PLATFORM
;
164 cdv_backlight_device
= backlight_device_register("psb-bl",
165 NULL
, (void *)dev
, &cdv_ops
, &props
);
166 if (IS_ERR(cdv_backlight_device
))
167 return PTR_ERR(cdv_backlight_device
);
169 cdv_backlight_device
->props
.brightness
=
170 cdv_get_brightness(cdv_backlight_device
);
171 backlight_update_status(cdv_backlight_device
);
172 dev_priv
->backlight_device
= cdv_backlight_device
;
173 dev_priv
->backlight_enabled
= true;
180 * Provide the Cedarview specific chip logic and low level methods
181 * for power management
183 * FIXME: we need to implement the apm/ospm base management bits
184 * for this and the MID devices.
187 static inline u32
CDV_MSG_READ32(uint port
, uint offset
)
189 int mcr
= (0x10<<24) | (port
<< 16) | (offset
<< 8);
190 uint32_t ret_val
= 0;
191 struct pci_dev
*pci_root
= pci_get_bus_and_slot(0, 0);
192 pci_write_config_dword(pci_root
, 0xD0, mcr
);
193 pci_read_config_dword(pci_root
, 0xD4, &ret_val
);
194 pci_dev_put(pci_root
);
198 static inline void CDV_MSG_WRITE32(uint port
, uint offset
, u32 value
)
200 int mcr
= (0x11<<24) | (port
<< 16) | (offset
<< 8) | 0xF0;
201 struct pci_dev
*pci_root
= pci_get_bus_and_slot(0, 0);
202 pci_write_config_dword(pci_root
, 0xD4, value
);
203 pci_write_config_dword(pci_root
, 0xD0, mcr
);
204 pci_dev_put(pci_root
);
207 #define PSB_PM_SSC 0x20
208 #define PSB_PM_SSS 0x30
209 #define PSB_PWRGT_GFX_ON 0x02
210 #define PSB_PWRGT_GFX_OFF 0x01
211 #define PSB_PWRGT_GFX_D0 0x00
212 #define PSB_PWRGT_GFX_D3 0x03
214 static void cdv_init_pm(struct drm_device
*dev
)
216 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
220 dev_priv
->apm_base
= CDV_MSG_READ32(PSB_PUNIT_PORT
,
222 dev_priv
->ospm_base
= CDV_MSG_READ32(PSB_PUNIT_PORT
,
223 PSB_OSPMBA
) & 0xFFFF;
226 pwr_cnt
= inl(dev_priv
->apm_base
+ PSB_APM_CMD
);
229 pwr_cnt
&= ~PSB_PWRGT_GFX_MASK
;
230 pwr_cnt
|= PSB_PWRGT_GFX_ON
;
231 outl(pwr_cnt
, dev_priv
->apm_base
+ PSB_APM_CMD
);
233 /* Wait for the GPU power */
234 for (i
= 0; i
< 5; i
++) {
235 u32 pwr_sts
= inl(dev_priv
->apm_base
+ PSB_APM_STS
);
236 if ((pwr_sts
& PSB_PWRGT_GFX_MASK
) == 0)
240 dev_err(dev
->dev
, "GPU: power management timed out.\n");
243 static void cdv_errata(struct drm_device
*dev
)
245 /* Disable bonus launch.
246 * CPU and GPU competes for memory and display misses updates and
247 * flickers. Worst with dual core, dual displays.
249 * Fixes were done to Win 7 gfx driver to disable a feature called
250 * Bonus Launch to work around the issue, by degrading
253 CDV_MSG_WRITE32(3, 0x30, 0x08027108);
257 * cdv_save_display_registers - save registers lost on suspend
258 * @dev: our DRM device
260 * Save the state we need in order to be able to restore the interface
261 * upon resume from suspend
263 static int cdv_save_display_registers(struct drm_device
*dev
)
265 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
266 struct psb_save_area
*regs
= &dev_priv
->regs
;
267 struct drm_connector
*connector
;
269 dev_dbg(dev
->dev
, "Saving GPU registers.\n");
271 pci_read_config_byte(dev
->pdev
, 0xF4, ®s
->cdv
.saveLBB
);
273 regs
->cdv
.saveDSPCLK_GATE_D
= REG_READ(DSPCLK_GATE_D
);
274 regs
->cdv
.saveRAMCLK_GATE_D
= REG_READ(RAMCLK_GATE_D
);
276 regs
->cdv
.saveDSPARB
= REG_READ(DSPARB
);
277 regs
->cdv
.saveDSPFW
[0] = REG_READ(DSPFW1
);
278 regs
->cdv
.saveDSPFW
[1] = REG_READ(DSPFW2
);
279 regs
->cdv
.saveDSPFW
[2] = REG_READ(DSPFW3
);
280 regs
->cdv
.saveDSPFW
[3] = REG_READ(DSPFW4
);
281 regs
->cdv
.saveDSPFW
[4] = REG_READ(DSPFW5
);
282 regs
->cdv
.saveDSPFW
[5] = REG_READ(DSPFW6
);
284 regs
->cdv
.saveADPA
= REG_READ(ADPA
);
286 regs
->cdv
.savePP_CONTROL
= REG_READ(PP_CONTROL
);
287 regs
->cdv
.savePFIT_PGM_RATIOS
= REG_READ(PFIT_PGM_RATIOS
);
288 regs
->saveBLC_PWM_CTL
= REG_READ(BLC_PWM_CTL
);
289 regs
->saveBLC_PWM_CTL2
= REG_READ(BLC_PWM_CTL2
);
290 regs
->cdv
.saveLVDS
= REG_READ(LVDS
);
292 regs
->cdv
.savePFIT_CONTROL
= REG_READ(PFIT_CONTROL
);
294 regs
->cdv
.savePP_ON_DELAYS
= REG_READ(PP_ON_DELAYS
);
295 regs
->cdv
.savePP_OFF_DELAYS
= REG_READ(PP_OFF_DELAYS
);
296 regs
->cdv
.savePP_CYCLE
= REG_READ(PP_CYCLE
);
298 regs
->cdv
.saveVGACNTRL
= REG_READ(VGACNTRL
);
300 regs
->cdv
.saveIER
= REG_READ(PSB_INT_ENABLE_R
);
301 regs
->cdv
.saveIMR
= REG_READ(PSB_INT_MASK_R
);
303 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
304 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_OFF
);
310 * cdv_restore_display_registers - restore lost register state
311 * @dev: our DRM device
313 * Restore register state that was lost during suspend and resume.
317 static int cdv_restore_display_registers(struct drm_device
*dev
)
319 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
320 struct psb_save_area
*regs
= &dev_priv
->regs
;
321 struct drm_connector
*connector
;
324 pci_write_config_byte(dev
->pdev
, 0xF4, regs
->cdv
.saveLBB
);
326 REG_WRITE(DSPCLK_GATE_D
, regs
->cdv
.saveDSPCLK_GATE_D
);
327 REG_WRITE(RAMCLK_GATE_D
, regs
->cdv
.saveRAMCLK_GATE_D
);
329 /* BIOS does below anyway */
330 REG_WRITE(DPIO_CFG
, 0);
331 REG_WRITE(DPIO_CFG
, DPIO_MODE_SELECT_0
| DPIO_CMN_RESET_N
);
333 temp
= REG_READ(DPLL_A
);
334 if ((temp
& DPLL_SYNCLOCK_ENABLE
) == 0) {
335 REG_WRITE(DPLL_A
, temp
| DPLL_SYNCLOCK_ENABLE
);
339 temp
= REG_READ(DPLL_B
);
340 if ((temp
& DPLL_SYNCLOCK_ENABLE
) == 0) {
341 REG_WRITE(DPLL_B
, temp
| DPLL_SYNCLOCK_ENABLE
);
347 REG_WRITE(DSPFW1
, regs
->cdv
.saveDSPFW
[0]);
348 REG_WRITE(DSPFW2
, regs
->cdv
.saveDSPFW
[1]);
349 REG_WRITE(DSPFW3
, regs
->cdv
.saveDSPFW
[2]);
350 REG_WRITE(DSPFW4
, regs
->cdv
.saveDSPFW
[3]);
351 REG_WRITE(DSPFW5
, regs
->cdv
.saveDSPFW
[4]);
352 REG_WRITE(DSPFW6
, regs
->cdv
.saveDSPFW
[5]);
354 REG_WRITE(DSPARB
, regs
->cdv
.saveDSPARB
);
355 REG_WRITE(ADPA
, regs
->cdv
.saveADPA
);
357 REG_WRITE(BLC_PWM_CTL2
, regs
->saveBLC_PWM_CTL2
);
358 REG_WRITE(LVDS
, regs
->cdv
.saveLVDS
);
359 REG_WRITE(PFIT_CONTROL
, regs
->cdv
.savePFIT_CONTROL
);
360 REG_WRITE(PFIT_PGM_RATIOS
, regs
->cdv
.savePFIT_PGM_RATIOS
);
361 REG_WRITE(BLC_PWM_CTL
, regs
->saveBLC_PWM_CTL
);
362 REG_WRITE(PP_ON_DELAYS
, regs
->cdv
.savePP_ON_DELAYS
);
363 REG_WRITE(PP_OFF_DELAYS
, regs
->cdv
.savePP_OFF_DELAYS
);
364 REG_WRITE(PP_CYCLE
, regs
->cdv
.savePP_CYCLE
);
365 REG_WRITE(PP_CONTROL
, regs
->cdv
.savePP_CONTROL
);
367 REG_WRITE(VGACNTRL
, regs
->cdv
.saveVGACNTRL
);
369 REG_WRITE(PSB_INT_ENABLE_R
, regs
->cdv
.saveIER
);
370 REG_WRITE(PSB_INT_MASK_R
, regs
->cdv
.saveIMR
);
372 /* Fix arbitration bug */
375 drm_mode_config_reset(dev
);
377 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
)
378 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
380 /* Resume the modeset for every activated CRTC */
381 drm_helper_resume_force_mode(dev
);
385 static int cdv_power_down(struct drm_device
*dev
)
387 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
388 u32 pwr_cnt
, pwr_mask
, pwr_sts
;
391 pwr_cnt
= inl(dev_priv
->apm_base
+ PSB_APM_CMD
);
392 pwr_cnt
&= ~PSB_PWRGT_GFX_MASK
;
393 pwr_cnt
|= PSB_PWRGT_GFX_OFF
;
394 pwr_mask
= PSB_PWRGT_GFX_MASK
;
396 outl(pwr_cnt
, dev_priv
->apm_base
+ PSB_APM_CMD
);
399 pwr_sts
= inl(dev_priv
->apm_base
+ PSB_APM_STS
);
400 if ((pwr_sts
& pwr_mask
) == PSB_PWRGT_GFX_D3
)
407 static int cdv_power_up(struct drm_device
*dev
)
409 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
410 u32 pwr_cnt
, pwr_mask
, pwr_sts
;
413 pwr_cnt
= inl(dev_priv
->apm_base
+ PSB_APM_CMD
);
414 pwr_cnt
&= ~PSB_PWRGT_GFX_MASK
;
415 pwr_cnt
|= PSB_PWRGT_GFX_ON
;
416 pwr_mask
= PSB_PWRGT_GFX_MASK
;
418 outl(pwr_cnt
, dev_priv
->apm_base
+ PSB_APM_CMD
);
421 pwr_sts
= inl(dev_priv
->apm_base
+ PSB_APM_STS
);
422 if ((pwr_sts
& pwr_mask
) == PSB_PWRGT_GFX_D0
)
429 /* FIXME ? - shared with Poulsbo */
430 static void cdv_get_core_freq(struct drm_device
*dev
)
433 struct pci_dev
*pci_root
= pci_get_bus_and_slot(0, 0);
434 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
436 pci_write_config_dword(pci_root
, 0xD0, 0xD0050300);
437 pci_read_config_dword(pci_root
, 0xD4, &clock
);
438 pci_dev_put(pci_root
);
440 switch (clock
& 0x07) {
442 dev_priv
->core_freq
= 100;
445 dev_priv
->core_freq
= 133;
448 dev_priv
->core_freq
= 150;
451 dev_priv
->core_freq
= 178;
454 dev_priv
->core_freq
= 200;
459 dev_priv
->core_freq
= 266;
462 dev_priv
->core_freq
= 0;
466 static void cdv_hotplug_work_func(struct work_struct
*work
)
468 struct drm_psb_private
*dev_priv
= container_of(work
, struct drm_psb_private
,
470 struct drm_device
*dev
= dev_priv
->dev
;
472 /* Just fire off a uevent and let userspace tell us what to do */
473 drm_helper_hpd_irq_event(dev
);
476 /* The core driver has received a hotplug IRQ. We are in IRQ context
477 so extract the needed information and kick off queued processing */
479 static int cdv_hotplug_event(struct drm_device
*dev
)
481 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
482 schedule_work(&dev_priv
->hotplug_work
);
483 REG_WRITE(PORT_HOTPLUG_STAT
, REG_READ(PORT_HOTPLUG_STAT
));
487 static void cdv_hotplug_enable(struct drm_device
*dev
, bool on
)
490 u32 hotplug
= REG_READ(PORT_HOTPLUG_EN
);
491 hotplug
|= HDMIB_HOTPLUG_INT_EN
| HDMIC_HOTPLUG_INT_EN
|
492 HDMID_HOTPLUG_INT_EN
| CRT_HOTPLUG_INT_EN
;
493 REG_WRITE(PORT_HOTPLUG_EN
, hotplug
);
495 REG_WRITE(PORT_HOTPLUG_EN
, 0);
496 REG_WRITE(PORT_HOTPLUG_STAT
, REG_READ(PORT_HOTPLUG_STAT
));
500 static const char *force_audio_names
[] = {
506 void cdv_intel_attach_force_audio_property(struct drm_connector
*connector
)
508 struct drm_device
*dev
= connector
->dev
;
509 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
510 struct drm_property
*prop
;
513 prop
= dev_priv
->force_audio_property
;
515 prop
= drm_property_create(dev
, DRM_MODE_PROP_ENUM
,
517 ARRAY_SIZE(force_audio_names
));
521 for (i
= 0; i
< ARRAY_SIZE(force_audio_names
); i
++)
522 drm_property_add_enum(prop
, i
, i
-1, force_audio_names
[i
]);
524 dev_priv
->force_audio_property
= prop
;
526 drm_connector_attach_property(connector
, prop
, 0);
530 static const char *broadcast_rgb_names
[] = {
535 void cdv_intel_attach_broadcast_rgb_property(struct drm_connector
*connector
)
537 struct drm_device
*dev
= connector
->dev
;
538 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
539 struct drm_property
*prop
;
542 prop
= dev_priv
->broadcast_rgb_property
;
544 prop
= drm_property_create(dev
, DRM_MODE_PROP_ENUM
,
546 ARRAY_SIZE(broadcast_rgb_names
));
550 for (i
= 0; i
< ARRAY_SIZE(broadcast_rgb_names
); i
++)
551 drm_property_add_enum(prop
, i
, i
, broadcast_rgb_names
[i
]);
553 dev_priv
->broadcast_rgb_property
= prop
;
556 drm_connector_attach_property(connector
, prop
, 0);
560 static const struct psb_offset cdv_regmap
[2] = {
568 .dpll_md
= DPLL_A_MD
,
575 .stride
= DSPASTRIDE
,
582 .linoff
= DSPALINOFF
,
583 .tileoff
= DSPATILEOFF
,
584 .palette
= PALETTE_A
,
593 .dpll_md
= DPLL_B_MD
,
600 .stride
= DSPBSTRIDE
,
607 .linoff
= DSPBLINOFF
,
608 .tileoff
= DSPBTILEOFF
,
609 .palette
= PALETTE_B
,
613 static int cdv_chip_setup(struct drm_device
*dev
)
615 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
616 INIT_WORK(&dev_priv
->hotplug_work
, cdv_hotplug_work_func
);
618 if (pci_enable_msi(dev
->pdev
))
619 dev_warn(dev
->dev
, "Enabling MSI failed!\n");
620 dev_priv
->regmap
= cdv_regmap
;
621 cdv_get_core_freq(dev
);
622 psb_intel_opregion_init(dev
);
623 psb_intel_init_bios(dev
);
624 cdv_hotplug_enable(dev
, false);
628 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
630 const struct psb_ops cdv_chip_ops
= {
631 .name
= "GMA3600/3650",
635 .hdmi_mask
= (1 << 0) | (1 << 1),
636 .lvds_mask
= (1 << 1),
637 .cursor_needs_phys
= 0,
638 .sgx_offset
= MRST_SGX_OFFSET
,
639 .chip_setup
= cdv_chip_setup
,
640 .errata
= cdv_errata
,
642 .crtc_helper
= &cdv_intel_helper_funcs
,
643 .crtc_funcs
= &cdv_intel_crtc_funcs
,
645 .output_init
= cdv_output_init
,
646 .hotplug
= cdv_hotplug_event
,
647 .hotplug_enable
= cdv_hotplug_enable
,
649 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
650 .backlight_init
= cdv_backlight_init
,
653 .init_pm
= cdv_init_pm
,
654 .save_regs
= cdv_save_display_registers
,
655 .restore_regs
= cdv_restore_display_registers
,
656 .power_down
= cdv_power_down
,
657 .power_up
= cdv_power_up
,