drivers/gpu/drm/gma500/psb_drv.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #ifndef _PSB_DRV_H_
  21 #define _PSB_DRV_H_
  22
  23 #include <linux/kref.h>
  24
  25 #include <drm/drmP.h>
  26 #include "drm_global.h"
  27 #include "gem_glue.h"
  28 #include "gma_drm.h"
  29 #include "psb_reg.h"
  30 #include "psb_intel_drv.h"
  31 #include "gtt.h"
  32 #include "power.h"
  33 #include "oaktrail.h"
  34
  35 /* Append new drm mode definition here, align with libdrm definition */
  36 #define DRM_MODE_SCALE_NO_SCALE         2
  37
  38 enum {
  39         CHIP_PSB_8108 = 0,              /* Poulsbo */
  40         CHIP_PSB_8109 = 1,              /* Poulsbo */
  41         CHIP_MRST_4100 = 2,             /* Moorestown/Oaktrail */
  42         CHIP_MFLD_0130 = 3,             /* Medfield */
  43 };
  44
  45 #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
  46 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
  47 #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
  48
  49 /*
  50  * Driver definitions
  51  */
  52
  53 #define DRIVER_NAME "gma500"
  54 #define DRIVER_DESC "DRM driver for the Intel GMA500"
  55
  56 #define PSB_DRM_DRIVER_DATE "2011-06-06"
  57 #define PSB_DRM_DRIVER_MAJOR 1
  58 #define PSB_DRM_DRIVER_MINOR 0
  59 #define PSB_DRM_DRIVER_PATCHLEVEL 0
  60
  61 /*
  62  *      Hardware offsets
  63  */
  64 #define PSB_VDC_OFFSET           0x00000000
  65 #define PSB_VDC_SIZE             0x000080000
  66 #define MRST_MMIO_SIZE           0x0000C0000
  67 #define MDFLD_MMIO_SIZE          0x000100000
  68 #define PSB_SGX_SIZE             0x8000
  69 #define PSB_SGX_OFFSET           0x00040000
  70 #define MRST_SGX_OFFSET          0x00080000
  71 /*
  72  *      PCI resource identifiers
  73  */
  74 #define PSB_MMIO_RESOURCE        0
  75 #define PSB_GATT_RESOURCE        2
  76 #define PSB_GTT_RESOURCE         3
  77 /*
  78  *      PCI configuration
  79  */
  80 #define PSB_GMCH_CTRL            0x52
  81 #define PSB_BSM                  0x5C
  82 #define _PSB_GMCH_ENABLED        0x4
  83 #define PSB_PGETBL_CTL           0x2020
  84 #define _PSB_PGETBL_ENABLED      0x00000001
  85 #define PSB_SGX_2D_SLAVE_PORT    0x4000
  86
  87 /* To get rid of */
  88 #define PSB_TT_PRIV0_LIMIT       (256*1024*1024)
  89 #define PSB_TT_PRIV0_PLIMIT      (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
  90
  91 /*
  92  *      SGX side MMU definitions (these can probably go)
  93  */
  94
  95 /*
  96  *      Flags for external memory type field.
  97  */
  98 #define PSB_MMU_CACHED_MEMORY     0x0001        /* Bind to MMU only */
  99 #define PSB_MMU_RO_MEMORY         0x0002        /* MMU RO memory */
 100 #define PSB_MMU_WO_MEMORY         0x0004        /* MMU WO memory */
 101 /*
 102  *      PTE's and PDE's
 103  */
 104 #define PSB_PDE_MASK              0x003FFFFF
 105 #define PSB_PDE_SHIFT             22
 106 #define PSB_PTE_SHIFT             12
 107 /*
 108  *      Cache control
 109  */
 110 #define PSB_PTE_VALID             0x0001        /* PTE / PDE valid */
 111 #define PSB_PTE_WO                0x0002        /* Write only */
 112 #define PSB_PTE_RO                0x0004        /* Read only */
 113 #define PSB_PTE_CACHED            0x0008        /* CPU cache coherent */
 114
 115 /*
 116  *      VDC registers and bits
 117  */
 118 #define PSB_MSVDX_CLOCKGATING     0x2064
 119 #define PSB_TOPAZ_CLOCKGATING     0x2068
 120 #define PSB_HWSTAM                0x2098
 121 #define PSB_INSTPM                0x20C0
 122 #define PSB_INT_IDENTITY_R        0x20A4
 123 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 124 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 125 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
 126 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 127 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
 128 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
 129 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
 130 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
 131 #define _MDFLD_MIPIA_FLAG         (1<<16)
 132 #define _MDFLD_MIPIC_FLAG         (1<<17)
 133 #define _PSB_IRQ_DISP_HOTSYNC     (1<<17)
 134 #define _PSB_IRQ_SGX_FLAG         (1<<18)
 135 #define _PSB_IRQ_MSVDX_FLAG       (1<<19)
 136 #define _LNC_IRQ_TOPAZ_FLAG       (1<<20)
 137
 138 #define _PSB_PIPE_EVENT_FLAG    (_PSB_VSYNC_PIPEA_FLAG | \
 139                                  _PSB_VSYNC_PIPEB_FLAG)
 140
 141 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
 142 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
 143                                   _MDFLD_PIPEB_EVENT_FLAG | \
 144                                   _PSB_PIPEA_EVENT_FLAG | \
 145                                   _PSB_VSYNC_PIPEA_FLAG | \
 146                                   _MDFLD_MIPIA_FLAG | \
 147                                   _MDFLD_MIPIC_FLAG)
 148 #define PSB_INT_IDENTITY_R        0x20A4
 149 #define PSB_INT_MASK_R            0x20A8
 150 #define PSB_INT_ENABLE_R          0x20A0
 151
 152 #define _PSB_MMU_ER_MASK      0x0001FF00
 153 #define _PSB_MMU_ER_HOST      (1 << 16)
 154 #define GPIOA                   0x5010
 155 #define GPIOB                   0x5014
 156 #define GPIOC                   0x5018
 157 #define GPIOD                   0x501c
 158 #define GPIOE                   0x5020
 159 #define GPIOF                   0x5024
 160 #define GPIOG                   0x5028
 161 #define GPIOH                   0x502c
 162 #define GPIO_CLOCK_DIR_MASK             (1 << 0)
 163 #define GPIO_CLOCK_DIR_IN               (0 << 1)
 164 #define GPIO_CLOCK_DIR_OUT              (1 << 1)
 165 #define GPIO_CLOCK_VAL_MASK             (1 << 2)
 166 #define GPIO_CLOCK_VAL_OUT              (1 << 3)
 167 #define GPIO_CLOCK_VAL_IN               (1 << 4)
 168 #define GPIO_CLOCK_PULLUP_DISABLE       (1 << 5)
 169 #define GPIO_DATA_DIR_MASK              (1 << 8)
 170 #define GPIO_DATA_DIR_IN                (0 << 9)
 171 #define GPIO_DATA_DIR_OUT               (1 << 9)
 172 #define GPIO_DATA_VAL_MASK              (1 << 10)
 173 #define GPIO_DATA_VAL_OUT               (1 << 11)
 174 #define GPIO_DATA_VAL_IN                (1 << 12)
 175 #define GPIO_DATA_PULLUP_DISABLE        (1 << 13)
 176
 177 #define VCLK_DIVISOR_VGA0   0x6000
 178 #define VCLK_DIVISOR_VGA1   0x6004
 179 #define VCLK_POST_DIV       0x6010
 180
 181 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
 182 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
 183 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
 184 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
 185 #define PSB_COMM_USER_IRQ (1024 >> 2)
 186 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
 187 #define PSB_COMM_FW (2048 >> 2)
 188
 189 #define PSB_UIRQ_VISTEST               1
 190 #define PSB_UIRQ_OOM_REPLY             2
 191 #define PSB_UIRQ_FIRE_TA_REPLY         3
 192 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
 193
 194 #define PSB_2D_SIZE (256*1024*1024)
 195 #define PSB_MAX_RELOC_PAGES 1024
 196
 197 #define PSB_LOW_REG_OFFS 0x0204
 198 #define PSB_HIGH_REG_OFFS 0x0600
 199
 200 #define PSB_NUM_VBLANKS 2
 201
 202
 203 #define PSB_2D_SIZE (256*1024*1024)
 204 #define PSB_MAX_RELOC_PAGES 1024
 205
 206 #define PSB_LOW_REG_OFFS 0x0204
 207 #define PSB_HIGH_REG_OFFS 0x0600
 208
 209 #define PSB_NUM_VBLANKS 2
 210 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
 211 #define PSB_LID_DELAY (DRM_HZ / 10)
 212
 213 #define MDFLD_PNW_B0 0x04
 214 #define MDFLD_PNW_C0 0x08
 215
 216 #define MDFLD_DSR_2D_3D_0       (1 << 0)
 217 #define MDFLD_DSR_2D_3D_2       (1 << 1)
 218 #define MDFLD_DSR_CURSOR_0      (1 << 2)
 219 #define MDFLD_DSR_CURSOR_2      (1 << 3)
 220 #define MDFLD_DSR_OVERLAY_0     (1 << 4)
 221 #define MDFLD_DSR_OVERLAY_2     (1 << 5)
 222 #define MDFLD_DSR_MIPI_CONTROL  (1 << 6)
 223 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
 224 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
 225 #define MDFLD_DSR_2D_3D         (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
 226
 227 #define MDFLD_DSR_RR            45
 228 #define MDFLD_DPU_ENABLE        (1 << 31)
 229 #define MDFLD_DSR_FULLSCREEN    (1 << 30)
 230 #define MDFLD_DSR_DELAY         (DRM_HZ / MDFLD_DSR_RR)
 231
 232 #define PSB_PWR_STATE_ON                1
 233 #define PSB_PWR_STATE_OFF               2
 234
 235 #define PSB_PMPOLICY_NOPM               0
 236 #define PSB_PMPOLICY_CLOCKGATING        1
 237 #define PSB_PMPOLICY_POWERDOWN          2
 238
 239 #define PSB_PMSTATE_POWERUP             0
 240 #define PSB_PMSTATE_CLOCKGATED          1
 241 #define PSB_PMSTATE_POWERDOWN           2
 242 #define PSB_PCIx_MSI_ADDR_LOC           0x94
 243 #define PSB_PCIx_MSI_DATA_LOC           0x98
 244
 245 /* Medfield crystal settings */
 246 #define KSEL_CRYSTAL_19 1
 247 #define KSEL_BYPASS_19 5
 248 #define KSEL_BYPASS_25 6
 249 #define KSEL_BYPASS_83_100 7
 250
 251 struct opregion_header;
 252 struct opregion_acpi;
 253 struct opregion_swsci;
 254 struct opregion_asle;
 255
 256 struct psb_intel_opregion {
 257         struct opregion_header *header;
 258         struct opregion_acpi *acpi;
 259         struct opregion_swsci *swsci;
 260         struct opregion_asle *asle;
 261         void *vbt;
 262         int enabled;
 263 };
 264
 265 struct sdvo_device_mapping {
 266         u8 initialized;
 267         u8 dvo_port;
 268         u8 slave_addr;
 269         u8 dvo_wiring;
 270         u8 i2c_pin;
 271         u8 i2c_speed;
 272         u8 ddc_pin;
 273 };
 274
 275 struct intel_gmbus {
 276         struct i2c_adapter adapter;
 277         struct i2c_adapter *force_bit;
 278         u32 reg0;
 279 };
 280
 281 /*
 282  *      Register save state. This is used to hold the context when the
 283  *      device is powered off. In the case of Oaktrail this can (but does not
 284  *      yet) include screen blank. Operations occuring during the save
 285  *      update the register cache instead.
 286  */
 287 struct psb_state {
 288         uint32_t saveDSPACNTR;
 289         uint32_t saveDSPBCNTR;
 290         uint32_t savePIPEACONF;
 291         uint32_t savePIPEBCONF;
 292         uint32_t savePIPEASRC;
 293         uint32_t savePIPEBSRC;
 294         uint32_t saveFPA0;
 295         uint32_t saveFPA1;
 296         uint32_t saveDPLL_A;
 297         uint32_t saveDPLL_A_MD;
 298         uint32_t saveHTOTAL_A;
 299         uint32_t saveHBLANK_A;
 300         uint32_t saveHSYNC_A;
 301         uint32_t saveVTOTAL_A;
 302         uint32_t saveVBLANK_A;
 303         uint32_t saveVSYNC_A;
 304         uint32_t saveDSPASTRIDE;
 305         uint32_t saveDSPASIZE;
 306         uint32_t saveDSPAPOS;
 307         uint32_t saveDSPABASE;
 308         uint32_t saveDSPASURF;
 309         uint32_t saveDSPASTATUS;
 310         uint32_t saveFPB0;
 311         uint32_t saveFPB1;
 312         uint32_t saveDPLL_B;
 313         uint32_t saveDPLL_B_MD;
 314         uint32_t saveHTOTAL_B;
 315         uint32_t saveHBLANK_B;
 316         uint32_t saveHSYNC_B;
 317         uint32_t saveVTOTAL_B;
 318         uint32_t saveVBLANK_B;
 319         uint32_t saveVSYNC_B;
 320         uint32_t saveDSPBSTRIDE;
 321         uint32_t saveDSPBSIZE;
 322         uint32_t saveDSPBPOS;
 323         uint32_t saveDSPBBASE;
 324         uint32_t saveDSPBSURF;
 325         uint32_t saveDSPBSTATUS;
 326         uint32_t saveVCLK_DIVISOR_VGA0;
 327         uint32_t saveVCLK_DIVISOR_VGA1;
 328         uint32_t saveVCLK_POST_DIV;
 329         uint32_t saveVGACNTRL;
 330         uint32_t saveADPA;
 331         uint32_t saveLVDS;
 332         uint32_t saveDVOA;
 333         uint32_t saveDVOB;
 334         uint32_t saveDVOC;
 335         uint32_t savePP_ON;
 336         uint32_t savePP_OFF;
 337         uint32_t savePP_CONTROL;
 338         uint32_t savePP_CYCLE;
 339         uint32_t savePFIT_CONTROL;
 340         uint32_t savePaletteA[256];
 341         uint32_t savePaletteB[256];
 342         uint32_t saveCLOCKGATING;
 343         uint32_t saveDSPARB;
 344         uint32_t saveDSPATILEOFF;
 345         uint32_t saveDSPBTILEOFF;
 346         uint32_t saveDSPAADDR;
 347         uint32_t saveDSPBADDR;
 348         uint32_t savePFIT_AUTO_RATIOS;
 349         uint32_t savePFIT_PGM_RATIOS;
 350         uint32_t savePP_ON_DELAYS;
 351         uint32_t savePP_OFF_DELAYS;
 352         uint32_t savePP_DIVISOR;
 353         uint32_t saveBCLRPAT_A;
 354         uint32_t saveBCLRPAT_B;
 355         uint32_t saveDSPALINOFF;
 356         uint32_t saveDSPBLINOFF;
 357         uint32_t savePERF_MODE;
 358         uint32_t saveDSPFW1;
 359         uint32_t saveDSPFW2;
 360         uint32_t saveDSPFW3;
 361         uint32_t saveDSPFW4;
 362         uint32_t saveDSPFW5;
 363         uint32_t saveDSPFW6;
 364         uint32_t saveCHICKENBIT;
 365         uint32_t saveDSPACURSOR_CTRL;
 366         uint32_t saveDSPBCURSOR_CTRL;
 367         uint32_t saveDSPACURSOR_BASE;
 368         uint32_t saveDSPBCURSOR_BASE;
 369         uint32_t saveDSPACURSOR_POS;
 370         uint32_t saveDSPBCURSOR_POS;
 371         uint32_t save_palette_a[256];
 372         uint32_t save_palette_b[256];
 373         uint32_t saveOV_OVADD;
 374         uint32_t saveOV_OGAMC0;
 375         uint32_t saveOV_OGAMC1;
 376         uint32_t saveOV_OGAMC2;
 377         uint32_t saveOV_OGAMC3;
 378         uint32_t saveOV_OGAMC4;
 379         uint32_t saveOV_OGAMC5;
 380         uint32_t saveOVC_OVADD;
 381         uint32_t saveOVC_OGAMC0;
 382         uint32_t saveOVC_OGAMC1;
 383         uint32_t saveOVC_OGAMC2;
 384         uint32_t saveOVC_OGAMC3;
 385         uint32_t saveOVC_OGAMC4;
 386         uint32_t saveOVC_OGAMC5;
 387
 388         /* DPST register save */
 389         uint32_t saveHISTOGRAM_INT_CONTROL_REG;
 390         uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
 391         uint32_t savePWM_CONTROL_LOGIC;
 392 };
 393
 394 struct medfield_state {
 395         uint32_t saveDPLL_A;
 396         uint32_t saveFPA0;
 397         uint32_t savePIPEACONF;
 398         uint32_t saveHTOTAL_A;
 399         uint32_t saveHBLANK_A;
 400         uint32_t saveHSYNC_A;
 401         uint32_t saveVTOTAL_A;
 402         uint32_t saveVBLANK_A;
 403         uint32_t saveVSYNC_A;
 404         uint32_t savePIPEASRC;
 405         uint32_t saveDSPASTRIDE;
 406         uint32_t saveDSPALINOFF;
 407         uint32_t saveDSPATILEOFF;
 408         uint32_t saveDSPASIZE;
 409         uint32_t saveDSPAPOS;
 410         uint32_t saveDSPASURF;
 411         uint32_t saveDSPACNTR;
 412         uint32_t saveDSPASTATUS;
 413         uint32_t save_palette_a[256];
 414         uint32_t saveMIPI;
 415
 416         uint32_t saveDPLL_B;
 417         uint32_t saveFPB0;
 418         uint32_t savePIPEBCONF;
 419         uint32_t saveHTOTAL_B;
 420         uint32_t saveHBLANK_B;
 421         uint32_t saveHSYNC_B;
 422         uint32_t saveVTOTAL_B;
 423         uint32_t saveVBLANK_B;
 424         uint32_t saveVSYNC_B;
 425         uint32_t savePIPEBSRC;
 426         uint32_t saveDSPBSTRIDE;
 427         uint32_t saveDSPBLINOFF;
 428         uint32_t saveDSPBTILEOFF;
 429         uint32_t saveDSPBSIZE;
 430         uint32_t saveDSPBPOS;
 431         uint32_t saveDSPBSURF;
 432         uint32_t saveDSPBCNTR;
 433         uint32_t saveDSPBSTATUS;
 434         uint32_t save_palette_b[256];
 435
 436         uint32_t savePIPECCONF;
 437         uint32_t saveHTOTAL_C;
 438         uint32_t saveHBLANK_C;
 439         uint32_t saveHSYNC_C;
 440         uint32_t saveVTOTAL_C;
 441         uint32_t saveVBLANK_C;
 442         uint32_t saveVSYNC_C;
 443         uint32_t savePIPECSRC;
 444         uint32_t saveDSPCSTRIDE;
 445         uint32_t saveDSPCLINOFF;
 446         uint32_t saveDSPCTILEOFF;
 447         uint32_t saveDSPCSIZE;
 448         uint32_t saveDSPCPOS;
 449         uint32_t saveDSPCSURF;
 450         uint32_t saveDSPCCNTR;
 451         uint32_t saveDSPCSTATUS;
 452         uint32_t save_palette_c[256];
 453         uint32_t saveMIPI_C;
 454
 455         uint32_t savePFIT_CONTROL;
 456         uint32_t savePFIT_PGM_RATIOS;
 457         uint32_t saveHDMIPHYMISCCTL;
 458         uint32_t saveHDMIB_CONTROL;
 459 };
 460
 461 struct cdv_state {
 462         uint32_t saveDSPCLK_GATE_D;
 463         uint32_t saveRAMCLK_GATE_D;
 464         uint32_t saveDSPARB;
 465         uint32_t saveDSPFW[6];
 466         uint32_t saveADPA;
 467         uint32_t savePP_CONTROL;
 468         uint32_t savePFIT_PGM_RATIOS;
 469         uint32_t saveLVDS;
 470         uint32_t savePFIT_CONTROL;
 471         uint32_t savePP_ON_DELAYS;
 472         uint32_t savePP_OFF_DELAYS;
 473         uint32_t savePP_CYCLE;
 474         uint32_t saveVGACNTRL;
 475         uint32_t saveIER;
 476         uint32_t saveIMR;
 477         u8       saveLBB;
 478 };
 479
 480 struct psb_save_area {
 481         uint32_t saveBSM;
 482         uint32_t saveVBT;
 483         union {
 484                 struct psb_state psb;
 485                 struct medfield_state mdfld;
 486                 struct cdv_state cdv;
 487         };
 488         uint32_t saveBLC_PWM_CTL2;
 489         uint32_t saveBLC_PWM_CTL;
 490 };
 491
 492 struct psb_ops;
 493
 494 #define PSB_NUM_PIPE            3
 495
 496 struct drm_psb_private {
 497         struct drm_device *dev;
 498         const struct psb_ops *ops;
 499
 500         struct child_device_config *child_dev;
 501         int child_dev_num;
 502
 503         struct psb_gtt gtt;
 504
 505         /* GTT Memory manager */
 506         struct psb_gtt_mm *gtt_mm;
 507         struct page *scratch_page;
 508         u32 *gtt_map;
 509         uint32_t stolen_base;
 510         void *vram_addr;
 511         unsigned long vram_stolen_size;
 512         int gtt_initialized;
 513         u16 gmch_ctrl;          /* Saved GTT setup */
 514         u32 pge_ctl;
 515
 516         struct mutex gtt_mutex;
 517         struct resource *gtt_mem;       /* Our PCI resource */
 518
 519         struct psb_mmu_driver *mmu;
 520         struct psb_mmu_pd *pf_pd;
 521
 522         /*
 523          * Register base
 524          */
 525
 526         uint8_t *sgx_reg;
 527         uint8_t *vdc_reg;
 528         uint32_t gatt_free_offset;
 529
 530         /*
 531          * Fencing / irq.
 532          */
 533
 534         uint32_t vdc_irq_mask;
 535         uint32_t pipestat[PSB_NUM_PIPE];
 536
 537         spinlock_t irqmask_lock;
 538
 539         /*
 540          * Power
 541          */
 542
 543         bool suspended;
 544         bool display_power;
 545         int display_count;
 546
 547         /*
 548          * Modesetting
 549          */
 550         struct psb_intel_mode_device mode_dev;
 551
 552         struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
 553         struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
 554         uint32_t num_pipe;
 555
 556         /*
 557          * OSPM info (Power management base) (can go ?)
 558          */
 559         uint32_t ospm_base;
 560
 561         /*
 562          * Sizes info
 563          */
 564
 565         u32 fuse_reg_value;
 566         u32 video_device_fuse;
 567
 568         /* PCI revision ID for B0:D2:F0 */
 569         uint8_t platform_rev_id;
 570
 571         /* gmbus */
 572         struct intel_gmbus *gmbus;
 573
 574         /* Used by SDVO */
 575         int crt_ddc_pin;
 576         /* FIXME: The mappings should be parsed from bios but for now we can
 577                   pretend there are no mappings available */
 578         struct sdvo_device_mapping sdvo_mappings[2];
 579         u32 hotplug_supported_mask;
 580         struct drm_property *broadcast_rgb_property;
 581         struct drm_property *force_audio_property;
 582
 583         /*
 584          * LVDS info
 585          */
 586         int backlight_duty_cycle;       /* restore backlight to this value */
 587         bool panel_wants_dither;
 588         struct drm_display_mode *panel_fixed_mode;
 589         struct drm_display_mode *lfp_lvds_vbt_mode;
 590         struct drm_display_mode *sdvo_lvds_vbt_mode;
 591
 592         struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
 593         struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
 594
 595         /* Feature bits from the VBIOS */
 596         unsigned int int_tv_support:1;
 597         unsigned int lvds_dither:1;
 598         unsigned int lvds_vbt:1;
 599         unsigned int int_crt_support:1;
 600         unsigned int lvds_use_ssc:1;
 601         int lvds_ssc_freq;
 602         bool is_lvds_on;
 603         bool is_mipi_on;
 604         u32 mipi_ctrl_display;
 605
 606         unsigned int core_freq;
 607         uint32_t iLVDS_enable;
 608
 609         /* Runtime PM state */
 610         int rpm_enabled;
 611
 612         /* MID specific */
 613         struct oaktrail_vbt vbt_data;
 614         struct oaktrail_gct_data gct_data;
 615
 616         /* Oaktrail HDMI state */
 617         struct oaktrail_hdmi_dev *hdmi_priv;
 618
 619         /*
 620          * Register state
 621          */
 622
 623         struct psb_save_area regs;
 624
 625         /* MSI reg save */
 626         uint32_t msi_addr;
 627         uint32_t msi_data;
 628
 629
 630         /*
 631          * LID-Switch
 632          */
 633         spinlock_t lid_lock;
 634         struct timer_list lid_timer;
 635         struct psb_intel_opregion opregion;
 636         u32 *lid_state;
 637         u32 lid_last_state;
 638
 639         /*
 640          * Watchdog
 641          */
 642
 643         uint32_t apm_reg;
 644         uint16_t apm_base;
 645
 646         /*
 647          * Used for modifying backlight from
 648          * xrandr -- consider removing and using HAL instead
 649          */
 650         struct backlight_device *backlight_device;
 651         struct drm_property *backlight_property;
 652         uint32_t blc_adj1;
 653         uint32_t blc_adj2;
 654
 655         void *fbdev;
 656
 657         /* 2D acceleration */
 658         spinlock_t lock_2d;
 659
 660         /*
 661          * Panel brightness
 662          */
 663         int brightness;
 664         int brightness_adjusted;
 665
 666         bool dsr_enable;
 667         u32 dsr_fb_update;
 668         bool dpi_panel_on[3];
 669         void *dsi_configs[2];
 670         u32 bpp;
 671         u32 bpp2;
 672
 673         u32 pipeconf[3];
 674         u32 dspcntr[3];
 675
 676         int mdfld_panel_id;
 677
 678         bool dplla_96mhz;       /* DPLL data from the VBT */
 679 };
 680
 681
 682 /*
 683  *      Operations for each board type
 684  */
 685
 686 struct psb_ops {
 687         const char *name;
 688         unsigned int accel_2d:1;
 689         int pipes;              /* Number of output pipes */
 690         int crtcs;              /* Number of CRTCs */
 691         int sgx_offset;         /* Base offset of SGX device */
 692         int hdmi_mask;          /* Mask of HDMI CRTCs */
 693         int lvds_mask;          /* Mask of LVDS CRTCs */
 694
 695         /* Sub functions */
 696         struct drm_crtc_helper_funcs const *crtc_helper;
 697         struct drm_crtc_funcs const *crtc_funcs;
 698
 699         /* Setup hooks */
 700         int (*chip_setup)(struct drm_device *dev);
 701         void (*chip_teardown)(struct drm_device *dev);
 702         /* Optional helper caller after modeset */
 703         void (*errata)(struct drm_device *dev);
 704
 705         /* Display management hooks */
 706         int (*output_init)(struct drm_device *dev);
 707         int (*hotplug)(struct drm_device *dev);
 708         void (*hotplug_enable)(struct drm_device *dev, bool on);
 709         /* Power management hooks */
 710         void (*init_pm)(struct drm_device *dev);
 711         int (*save_regs)(struct drm_device *dev);
 712         int (*restore_regs)(struct drm_device *dev);
 713         int (*power_up)(struct drm_device *dev);
 714         int (*power_down)(struct drm_device *dev);
 715
 716         void (*lvds_bl_power)(struct drm_device *dev, bool on);
 717 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 718         /* Backlight */
 719         int (*backlight_init)(struct drm_device *dev);
 720 #endif
 721         int i2c_bus;            /* I2C bus identifier for Moorestown */
 722 };
 723
 724
 725
 726 struct psb_mmu_driver;
 727
 728 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
 729 extern int drm_pick_crtcs(struct drm_device *dev);
 730
 731 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
 732 {
 733         return (struct drm_psb_private *) dev->dev_private;
 734 }
 735
 736 /*
 737  * MMU stuff.
 738  */
 739
 740 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
 741                                         int trap_pagefaults,
 742                                         int invalid_type,
 743                                         struct drm_psb_private *dev_priv);
 744 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
 745 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
 746                                                  *driver);
 747 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
 748                                uint32_t gtt_start, uint32_t gtt_pages);
 749 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
 750                                            int trap_pagefaults,
 751                                            int invalid_type);
 752 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
 753 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
 754 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
 755                                         unsigned long address,
 756                                         uint32_t num_pages);
 757 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
 758                                        uint32_t start_pfn,
 759                                        unsigned long address,
 760                                        uint32_t num_pages, int type);
 761 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
 762                                   unsigned long *pfn);
 763
 764 /*
 765  * Enable / disable MMU for different requestors.
 766  */
 767
 768
 769 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
 770 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
 771                                 unsigned long address, uint32_t num_pages,
 772                                 uint32_t desired_tile_stride,
 773                                 uint32_t hw_tile_stride, int type);
 774 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
 775                                  unsigned long address, uint32_t num_pages,
 776                                  uint32_t desired_tile_stride,
 777                                  uint32_t hw_tile_stride);
 778 /*
 779  *psb_irq.c
 780  */
 781
 782 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
 783 extern int psb_irq_enable_dpst(struct drm_device *dev);
 784 extern int psb_irq_disable_dpst(struct drm_device *dev);
 785 extern void psb_irq_preinstall(struct drm_device *dev);
 786 extern int psb_irq_postinstall(struct drm_device *dev);
 787 extern void psb_irq_uninstall(struct drm_device *dev);
 788 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
 789 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
 790
 791 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
 792 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
 793 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 794 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
 795 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
 796 void
 797 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 798
 799 void
 800 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 801
 802 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
 803
 804 /*
 805  * intel_opregion.c
 806  */
 807 extern int gma_intel_opregion_init(struct drm_device *dev);
 808 extern int gma_intel_opregion_exit(struct drm_device *dev);
 809
 810 /*
 811  * framebuffer.c
 812  */
 813 extern int psbfb_probed(struct drm_device *dev);
 814 extern int psbfb_remove(struct drm_device *dev,
 815                         struct drm_framebuffer *fb);
 816 /*
 817  * accel_2d.c
 818  */
 819 extern void psbfb_copyarea(struct fb_info *info,
 820                                         const struct fb_copyarea *region);
 821 extern int psbfb_sync(struct fb_info *info);
 822 extern void psb_spank(struct drm_psb_private *dev_priv);
 823
 824 /*
 825  * psb_reset.c
 826  */
 827
 828 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
 829 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
 830 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
 831
 832 /* modesetting */
 833 extern void psb_modeset_init(struct drm_device *dev);
 834 extern void psb_modeset_cleanup(struct drm_device *dev);
 835 extern int psb_fbdev_init(struct drm_device *dev);
 836
 837 /* backlight.c */
 838 int gma_backlight_init(struct drm_device *dev);
 839 void gma_backlight_exit(struct drm_device *dev);
 840
 841 /* oaktrail_crtc.c */
 842 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
 843
 844 /* oaktrail_lvds.c */
 845 extern void oaktrail_lvds_init(struct drm_device *dev,
 846                     struct psb_intel_mode_device *mode_dev);
 847
 848 /* psb_intel_display.c */
 849 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
 850 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
 851
 852 /* psb_intel_lvds.c */
 853 extern const struct drm_connector_helper_funcs
 854                                         psb_intel_lvds_connector_helper_funcs;
 855 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
 856
 857 /* gem.c */
 858 extern int psb_gem_init_object(struct drm_gem_object *obj);
 859 extern void psb_gem_free_object(struct drm_gem_object *obj);
 860 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
 861                         struct drm_file *file);
 862 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 863                         struct drm_mode_create_dumb *args);
 864 extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 865                         uint32_t handle);
 866 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
 867                         uint32_t handle, uint64_t *offset);
 868 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 869 extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
 870                         struct drm_file *file);
 871 extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
 872                                         struct drm_file *file);
 873
 874 /* psb_device.c */
 875 extern const struct psb_ops psb_chip_ops;
 876
 877 /* oaktrail_device.c */
 878 extern const struct psb_ops oaktrail_chip_ops;
 879
 880 /* mdlfd_device.c */
 881 extern const struct psb_ops mdfld_chip_ops;
 882
 883 /* cdv_device.c */
 884 extern const struct psb_ops cdv_chip_ops;
 885
 886 /*
 887  * Debug print bits setting
 888  */
 889 #define PSB_D_GENERAL (1 << 0)
 890 #define PSB_D_INIT    (1 << 1)
 891 #define PSB_D_IRQ     (1 << 2)
 892 #define PSB_D_ENTRY   (1 << 3)
 893 /* debug the get H/V BP/FP count */
 894 #define PSB_D_HV      (1 << 4)
 895 #define PSB_D_DBI_BF  (1 << 5)
 896 #define PSB_D_PM      (1 << 6)
 897 #define PSB_D_RENDER  (1 << 7)
 898 #define PSB_D_REG     (1 << 8)
 899 #define PSB_D_MSVDX   (1 << 9)
 900 #define PSB_D_TOPAZ   (1 << 10)
 901
 902 extern int drm_psb_no_fb;
 903 extern int drm_idle_check_interval;
 904
 905 /*
 906  *      Utilities
 907  */
 908
 909 static inline u32 MRST_MSG_READ32(uint port, uint offset)
 910 {
 911         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
 912         uint32_t ret_val = 0;
 913         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 914         pci_write_config_dword(pci_root, 0xD0, mcr);
 915         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 916         pci_dev_put(pci_root);
 917         return ret_val;
 918 }
 919 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
 920 {
 921         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
 922         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 923         pci_write_config_dword(pci_root, 0xD4, value);
 924         pci_write_config_dword(pci_root, 0xD0, mcr);
 925         pci_dev_put(pci_root);
 926 }
 927 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
 928 {
 929         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 930         uint32_t ret_val = 0;
 931         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 932         pci_write_config_dword(pci_root, 0xD0, mcr);
 933         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 934         pci_dev_put(pci_root);
 935         return ret_val;
 936 }
 937 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
 938 {
 939         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 940         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 941         pci_write_config_dword(pci_root, 0xD4, value);
 942         pci_write_config_dword(pci_root, 0xD0, mcr);
 943         pci_dev_put(pci_root);
 944 }
 945
 946 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
 947 {
 948         struct drm_psb_private *dev_priv = dev->dev_private;
 949         return ioread32(dev_priv->vdc_reg + reg);
 950 }
 951
 952 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
 953
 954 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
 955                                       uint32_t val)
 956 {
 957         struct drm_psb_private *dev_priv = dev->dev_private;
 958         iowrite32((val), dev_priv->vdc_reg + (reg));
 959 }
 960
 961 #define REG_WRITE(reg, val)     REGISTER_WRITE(dev, (reg), (val))
 962
 963 static inline void REGISTER_WRITE16(struct drm_device *dev,
 964                                         uint32_t reg, uint32_t val)
 965 {
 966         struct drm_psb_private *dev_priv = dev->dev_private;
 967         iowrite16((val), dev_priv->vdc_reg + (reg));
 968 }
 969
 970 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
 971
 972 static inline void REGISTER_WRITE8(struct drm_device *dev,
 973                                        uint32_t reg, uint32_t val)
 974 {
 975         struct drm_psb_private *dev_priv = dev->dev_private;
 976         iowrite8((val), dev_priv->vdc_reg + (reg));
 977 }
 978
 979 #define REG_WRITE8(reg, val)            REGISTER_WRITE8(dev, (reg), (val))
 980
 981 #define PSB_WVDC32(_val, _offs)         iowrite32(_val, dev_priv->vdc_reg + (_offs))
 982 #define PSB_RVDC32(_offs)               ioread32(dev_priv->vdc_reg + (_offs))
 983
 984 /* #define TRAP_SGX_PM_FAULT 1 */
 985 #ifdef TRAP_SGX_PM_FAULT
 986 #define PSB_RSGX32(_offs)                                               \
 987 ({                                                                      \
 988         if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {              \
 989                 printk(KERN_ERR                                         \
 990                         "access sgx when it's off!! (READ) %s, %d\n",   \
 991                __FILE__, __LINE__);                                     \
 992                 melay(1000);                                            \
 993         }                                                               \
 994         ioread32(dev_priv->sgx_reg + (_offs));                          \
 995 })
 996 #else
 997 #define PSB_RSGX32(_offs)               ioread32(dev_priv->sgx_reg + (_offs))
 998 #endif
 999 #define PSB_WSGX32(_val, _offs)         iowrite32(_val, dev_priv->sgx_reg + (_offs))
1000
1001 #define MSVDX_REG_DUMP 0
1002
1003 #define PSB_WMSVDX32(_val, _offs)       iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1004 #define PSB_RMSVDX32(_offs)             ioread32(dev_priv->msvdx_reg + (_offs))
1005
1006 #endif