2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/component.h>
19 #include <linux/hdmi.h>
20 #include <linux/module.h>
21 #include <linux/irq.h>
22 #include <sound/asoundef.h>
25 #include <drm/drm_crtc_helper.h>
26 #include <drm/drm_encoder_slave.h>
27 #include <drm/drm_edid.h>
28 #include <drm/i2c/tda998x.h>
30 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
33 struct i2c_client
*cec
;
34 struct i2c_client
*hdmi
;
42 struct tda998x_encoder_params params
;
44 wait_queue_head_t wq_edid
;
45 volatile int wq_edid_wait
;
46 struct drm_encoder
*encoder
;
49 #define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
51 /* The TDA9988 series of devices use a paged register scheme.. to simplify
52 * things we encode the page # in upper bits of the register #. To read/
53 * write a given register, we need to make sure CURPAGE register is set
54 * appropriately. Which implies reads/writes are not atomic. Fun!
57 #define REG(page, addr) (((page) << 8) | (addr))
58 #define REG2ADDR(reg) ((reg) & 0xff)
59 #define REG2PAGE(reg) (((reg) >> 8) & 0xff)
61 #define REG_CURPAGE 0xff /* write */
64 /* Page 00h: General Control */
65 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
66 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
67 # define MAIN_CNTRL0_SR (1 << 0)
68 # define MAIN_CNTRL0_DECS (1 << 1)
69 # define MAIN_CNTRL0_DEHS (1 << 2)
70 # define MAIN_CNTRL0_CECS (1 << 3)
71 # define MAIN_CNTRL0_CEHS (1 << 4)
72 # define MAIN_CNTRL0_SCALER (1 << 7)
73 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
74 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
75 # define SOFTRESET_AUDIO (1 << 0)
76 # define SOFTRESET_I2C_MASTER (1 << 1)
77 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
78 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
79 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
80 # define I2C_MASTER_DIS_MM (1 << 0)
81 # define I2C_MASTER_DIS_FILT (1 << 1)
82 # define I2C_MASTER_APP_STRT_LAT (1 << 2)
83 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
84 # define FEAT_POWERDOWN_SPDIF (1 << 3)
85 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
86 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
87 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
88 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
89 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
90 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
91 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
92 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
93 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
94 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
95 # define VIP_CNTRL_0_MIRR_A (1 << 7)
96 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
97 # define VIP_CNTRL_0_MIRR_B (1 << 3)
98 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
99 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
100 # define VIP_CNTRL_1_MIRR_C (1 << 7)
101 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
102 # define VIP_CNTRL_1_MIRR_D (1 << 3)
103 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
104 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
105 # define VIP_CNTRL_2_MIRR_E (1 << 7)
106 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
107 # define VIP_CNTRL_2_MIRR_F (1 << 3)
108 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
109 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
110 # define VIP_CNTRL_3_X_TGL (1 << 0)
111 # define VIP_CNTRL_3_H_TGL (1 << 1)
112 # define VIP_CNTRL_3_V_TGL (1 << 2)
113 # define VIP_CNTRL_3_EMB (1 << 3)
114 # define VIP_CNTRL_3_SYNC_DE (1 << 4)
115 # define VIP_CNTRL_3_SYNC_HS (1 << 5)
116 # define VIP_CNTRL_3_DE_INT (1 << 6)
117 # define VIP_CNTRL_3_EDGE (1 << 7)
118 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
119 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
120 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
121 # define VIP_CNTRL_4_CCIR656 (1 << 4)
122 # define VIP_CNTRL_4_656_ALT (1 << 5)
123 # define VIP_CNTRL_4_TST_656 (1 << 6)
124 # define VIP_CNTRL_4_TST_PAT (1 << 7)
125 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
126 # define VIP_CNTRL_5_CKCASE (1 << 0)
127 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
128 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */
129 # define MUX_AP_SELECT_I2S 0x64
130 # define MUX_AP_SELECT_SPDIF 0x40
131 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
132 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
133 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
134 # define MAT_CONTRL_MAT_BP (1 << 2)
135 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
136 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
137 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
138 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
139 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
140 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
141 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
142 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
143 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
144 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
145 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
146 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
147 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
148 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
149 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
150 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
151 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
152 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
153 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
154 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
155 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
156 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
157 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
158 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
159 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
160 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
161 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
162 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
163 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
164 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
165 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
166 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
167 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
168 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
169 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
170 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
171 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
172 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
173 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
174 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
175 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
176 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
177 # define TBG_CNTRL_0_TOP_TGL (1 << 0)
178 # define TBG_CNTRL_0_TOP_SEL (1 << 1)
179 # define TBG_CNTRL_0_DE_EXT (1 << 2)
180 # define TBG_CNTRL_0_TOP_EXT (1 << 3)
181 # define TBG_CNTRL_0_FRAME_DIS (1 << 5)
182 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
183 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
184 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
185 # define TBG_CNTRL_1_H_TGL (1 << 0)
186 # define TBG_CNTRL_1_V_TGL (1 << 1)
187 # define TBG_CNTRL_1_TGL_EN (1 << 2)
188 # define TBG_CNTRL_1_X_EXT (1 << 3)
189 # define TBG_CNTRL_1_H_EXT (1 << 4)
190 # define TBG_CNTRL_1_V_EXT (1 << 5)
191 # define TBG_CNTRL_1_DWIN_DIS (1 << 6)
192 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
193 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
194 # define HVF_CNTRL_0_SM (1 << 7)
195 # define HVF_CNTRL_0_RWB (1 << 6)
196 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
197 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
198 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
199 # define HVF_CNTRL_1_FOR (1 << 0)
200 # define HVF_CNTRL_1_YUVBLK (1 << 1)
201 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
202 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
203 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
204 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
205 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
206 # define I2S_FORMAT(x) (((x) & 3) << 0)
207 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
208 # define AIP_CLKSEL_AIP_SPDIF (0 << 3)
209 # define AIP_CLKSEL_AIP_I2S (1 << 3)
210 # define AIP_CLKSEL_FS_ACLK (0 << 0)
211 # define AIP_CLKSEL_FS_MCLK (1 << 0)
212 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
214 /* Page 02h: PLL settings */
215 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
216 # define PLL_SERIAL_1_SRL_FDN (1 << 0)
217 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
218 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
219 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
220 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
221 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
222 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
223 # define PLL_SERIAL_3_SRL_CCIR (1 << 0)
224 # define PLL_SERIAL_3_SRL_DE (1 << 2)
225 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
226 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
227 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
228 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
229 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
230 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
231 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
232 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
233 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
234 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
235 # define AUDIO_DIV_SERCLK_1 0
236 # define AUDIO_DIV_SERCLK_2 1
237 # define AUDIO_DIV_SERCLK_4 2
238 # define AUDIO_DIV_SERCLK_8 3
239 # define AUDIO_DIV_SERCLK_16 4
240 # define AUDIO_DIV_SERCLK_32 5
241 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
242 # define SEL_CLK_SEL_CLK1 (1 << 0)
243 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
244 # define SEL_CLK_ENA_SC_CLK (1 << 3)
245 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
248 /* Page 09h: EDID Control */
249 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
250 /* next 127 successive registers are the EDID block */
251 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
252 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
253 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
254 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
255 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
258 /* Page 10h: information frames and packets */
259 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
260 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
261 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
262 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
263 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
266 /* Page 11h: audio settings and content info packets */
267 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
268 # define AIP_CNTRL_0_RST_FIFO (1 << 0)
269 # define AIP_CNTRL_0_SWAP (1 << 1)
270 # define AIP_CNTRL_0_LAYOUT (1 << 2)
271 # define AIP_CNTRL_0_ACR_MAN (1 << 5)
272 # define AIP_CNTRL_0_RST_CTS (1 << 6)
273 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */
274 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
275 # define CA_I2S_HBR_CHSTAT (1 << 6)
276 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
277 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
278 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
279 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
280 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
281 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
282 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
283 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */
284 # define CTS_N_K(x) (((x) & 7) << 0)
285 # define CTS_N_M(x) (((x) & 3) << 4)
286 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
287 # define ENC_CNTRL_RST_ENC (1 << 0)
288 # define ENC_CNTRL_RST_SEL (1 << 1)
289 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
290 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
291 # define DIP_FLAGS_ACR (1 << 0)
292 # define DIP_FLAGS_GC (1 << 1)
293 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
294 # define DIP_IF_FLAGS_IF1 (1 << 1)
295 # define DIP_IF_FLAGS_IF2 (1 << 2)
296 # define DIP_IF_FLAGS_IF3 (1 << 3)
297 # define DIP_IF_FLAGS_IF4 (1 << 4)
298 # define DIP_IF_FLAGS_IF5 (1 << 5)
299 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
302 /* Page 12h: HDCP and OTP */
303 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
304 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
305 # define TX4_PD_RAM (1 << 1)
306 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
307 # define TX33_HDMI (1 << 1)
310 /* Page 13h: Gamut related metadata packets */
314 /* CEC registers: (not paged)
316 #define REG_CEC_INTSTATUS 0xee /* read */
317 # define CEC_INTSTATUS_CEC (1 << 0)
318 # define CEC_INTSTATUS_HDMI (1 << 1)
319 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
320 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
321 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
322 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
323 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
324 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
325 #define REG_CEC_RXSHPDINT 0xfd /* read */
326 #define REG_CEC_RXSHPDLEV 0xfe /* read */
327 # define CEC_RXSHPDLEV_RXSENS (1 << 0)
328 # define CEC_RXSHPDLEV_HPD (1 << 1)
330 #define REG_CEC_ENAMODS 0xff /* read/write */
331 # define CEC_ENAMODS_DIS_FRO (1 << 6)
332 # define CEC_ENAMODS_DIS_CCLK (1 << 5)
333 # define CEC_ENAMODS_EN_RXSENS (1 << 2)
334 # define CEC_ENAMODS_EN_HDMI (1 << 1)
335 # define CEC_ENAMODS_EN_CEC (1 << 0)
338 /* Device versions: */
339 #define TDA9989N2 0x0101
340 #define TDA19989 0x0201
341 #define TDA19989N2 0x0202
342 #define TDA19988 0x0301
345 cec_write(struct tda998x_priv
*priv
, uint16_t addr
, uint8_t val
)
347 struct i2c_client
*client
= priv
->cec
;
348 uint8_t buf
[] = {addr
, val
};
351 ret
= i2c_master_send(client
, buf
, sizeof(buf
));
353 dev_err(&client
->dev
, "Error %d writing to cec:0x%x\n", ret
, addr
);
357 cec_read(struct tda998x_priv
*priv
, uint8_t addr
)
359 struct i2c_client
*client
= priv
->cec
;
363 ret
= i2c_master_send(client
, &addr
, sizeof(addr
));
367 ret
= i2c_master_recv(client
, &val
, sizeof(val
));
374 dev_err(&client
->dev
, "Error %d reading from cec:0x%x\n", ret
, addr
);
379 set_page(struct tda998x_priv
*priv
, uint16_t reg
)
381 if (REG2PAGE(reg
) != priv
->current_page
) {
382 struct i2c_client
*client
= priv
->hdmi
;
384 REG_CURPAGE
, REG2PAGE(reg
)
386 int ret
= i2c_master_send(client
, buf
, sizeof(buf
));
388 dev_err(&client
->dev
, "setpage %04x err %d\n",
393 priv
->current_page
= REG2PAGE(reg
);
399 reg_read_range(struct tda998x_priv
*priv
, uint16_t reg
, char *buf
, int cnt
)
401 struct i2c_client
*client
= priv
->hdmi
;
402 uint8_t addr
= REG2ADDR(reg
);
405 ret
= set_page(priv
, reg
);
409 ret
= i2c_master_send(client
, &addr
, sizeof(addr
));
413 ret
= i2c_master_recv(client
, buf
, cnt
);
420 dev_err(&client
->dev
, "Error %d reading from 0x%x\n", ret
, reg
);
425 reg_write_range(struct tda998x_priv
*priv
, uint16_t reg
, uint8_t *p
, int cnt
)
427 struct i2c_client
*client
= priv
->hdmi
;
431 buf
[0] = REG2ADDR(reg
);
432 memcpy(&buf
[1], p
, cnt
);
434 ret
= set_page(priv
, reg
);
438 ret
= i2c_master_send(client
, buf
, cnt
+ 1);
440 dev_err(&client
->dev
, "Error %d writing to 0x%x\n", ret
, reg
);
444 reg_read(struct tda998x_priv
*priv
, uint16_t reg
)
449 ret
= reg_read_range(priv
, reg
, &val
, sizeof(val
));
456 reg_write(struct tda998x_priv
*priv
, uint16_t reg
, uint8_t val
)
458 struct i2c_client
*client
= priv
->hdmi
;
459 uint8_t buf
[] = {REG2ADDR(reg
), val
};
462 ret
= set_page(priv
, reg
);
466 ret
= i2c_master_send(client
, buf
, sizeof(buf
));
468 dev_err(&client
->dev
, "Error %d writing to 0x%x\n", ret
, reg
);
472 reg_write16(struct tda998x_priv
*priv
, uint16_t reg
, uint16_t val
)
474 struct i2c_client
*client
= priv
->hdmi
;
475 uint8_t buf
[] = {REG2ADDR(reg
), val
>> 8, val
};
478 ret
= set_page(priv
, reg
);
482 ret
= i2c_master_send(client
, buf
, sizeof(buf
));
484 dev_err(&client
->dev
, "Error %d writing to 0x%x\n", ret
, reg
);
488 reg_set(struct tda998x_priv
*priv
, uint16_t reg
, uint8_t val
)
492 old_val
= reg_read(priv
, reg
);
494 reg_write(priv
, reg
, old_val
| val
);
498 reg_clear(struct tda998x_priv
*priv
, uint16_t reg
, uint8_t val
)
502 old_val
= reg_read(priv
, reg
);
504 reg_write(priv
, reg
, old_val
& ~val
);
508 tda998x_reset(struct tda998x_priv
*priv
)
510 /* reset audio and i2c master: */
511 reg_write(priv
, REG_SOFTRESET
, SOFTRESET_AUDIO
| SOFTRESET_I2C_MASTER
);
513 reg_write(priv
, REG_SOFTRESET
, 0);
516 /* reset transmitter: */
517 reg_set(priv
, REG_MAIN_CNTRL0
, MAIN_CNTRL0_SR
);
518 reg_clear(priv
, REG_MAIN_CNTRL0
, MAIN_CNTRL0_SR
);
520 /* PLL registers common configuration */
521 reg_write(priv
, REG_PLL_SERIAL_1
, 0x00);
522 reg_write(priv
, REG_PLL_SERIAL_2
, PLL_SERIAL_2_SRL_NOSC(1));
523 reg_write(priv
, REG_PLL_SERIAL_3
, 0x00);
524 reg_write(priv
, REG_SERIALIZER
, 0x00);
525 reg_write(priv
, REG_BUFFER_OUT
, 0x00);
526 reg_write(priv
, REG_PLL_SCG1
, 0x00);
527 reg_write(priv
, REG_AUDIO_DIV
, AUDIO_DIV_SERCLK_8
);
528 reg_write(priv
, REG_SEL_CLK
, SEL_CLK_SEL_CLK1
| SEL_CLK_ENA_SC_CLK
);
529 reg_write(priv
, REG_PLL_SCGN1
, 0xfa);
530 reg_write(priv
, REG_PLL_SCGN2
, 0x00);
531 reg_write(priv
, REG_PLL_SCGR1
, 0x5b);
532 reg_write(priv
, REG_PLL_SCGR2
, 0x00);
533 reg_write(priv
, REG_PLL_SCG2
, 0x10);
535 /* Write the default value MUX register */
536 reg_write(priv
, REG_MUX_VP_VIP_OUT
, 0x24);
540 * only 2 interrupts may occur: screen plug/unplug and EDID read
542 static irqreturn_t
tda998x_irq_thread(int irq
, void *data
)
544 struct tda998x_priv
*priv
= data
;
545 u8 sta
, cec
, lvl
, flag0
, flag1
, flag2
;
549 sta
= cec_read(priv
, REG_CEC_INTSTATUS
);
550 cec
= cec_read(priv
, REG_CEC_RXSHPDINT
);
551 lvl
= cec_read(priv
, REG_CEC_RXSHPDLEV
);
552 flag0
= reg_read(priv
, REG_INT_FLAGS_0
);
553 flag1
= reg_read(priv
, REG_INT_FLAGS_1
);
554 flag2
= reg_read(priv
, REG_INT_FLAGS_2
);
556 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
557 sta
, cec
, lvl
, flag0
, flag1
, flag2
);
558 if ((flag2
& INT_FLAGS_2_EDID_BLK_RD
) && priv
->wq_edid_wait
) {
559 priv
->wq_edid_wait
= 0;
560 wake_up(&priv
->wq_edid
);
561 } else if (cec
!= 0) { /* HPD change */
562 if (priv
->encoder
&& priv
->encoder
->dev
)
563 drm_helper_hpd_irq_event(priv
->encoder
->dev
);
568 static uint8_t tda998x_cksum(uint8_t *buf
, size_t bytes
)
578 #define PB(x) (HB(2) + 1 + (x))
581 tda998x_write_if(struct tda998x_priv
*priv
, uint8_t bit
, uint16_t addr
,
582 uint8_t *buf
, size_t size
)
584 buf
[PB(0)] = tda998x_cksum(buf
, size
);
586 reg_clear(priv
, REG_DIP_IF_FLAGS
, bit
);
587 reg_write_range(priv
, addr
, buf
, size
);
588 reg_set(priv
, REG_DIP_IF_FLAGS
, bit
);
592 tda998x_write_aif(struct tda998x_priv
*priv
, struct tda998x_encoder_params
*p
)
594 u8 buf
[PB(HDMI_AUDIO_INFOFRAME_SIZE
) + 1];
596 memset(buf
, 0, sizeof(buf
));
597 buf
[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO
;
599 buf
[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE
;
600 buf
[PB(1)] = p
->audio_frame
[1] & 0x07; /* CC */
601 buf
[PB(2)] = p
->audio_frame
[2] & 0x1c; /* SF */
602 buf
[PB(4)] = p
->audio_frame
[4];
603 buf
[PB(5)] = p
->audio_frame
[5] & 0xf8; /* DM_INH + LSV */
605 tda998x_write_if(priv
, DIP_IF_FLAGS_IF4
, REG_IF4_HB0
, buf
,
610 tda998x_write_avi(struct tda998x_priv
*priv
, struct drm_display_mode
*mode
)
612 u8 buf
[PB(HDMI_AVI_INFOFRAME_SIZE
) + 1];
614 memset(buf
, 0, sizeof(buf
));
615 buf
[HB(0)] = HDMI_INFOFRAME_TYPE_AVI
;
617 buf
[HB(2)] = HDMI_AVI_INFOFRAME_SIZE
;
618 buf
[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN
;
619 buf
[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE
;
620 buf
[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL
<< 2;
621 buf
[PB(4)] = drm_match_cea_mode(mode
);
623 tda998x_write_if(priv
, DIP_IF_FLAGS_IF2
, REG_IF2_HB0
, buf
,
627 static void tda998x_audio_mute(struct tda998x_priv
*priv
, bool on
)
630 reg_set(priv
, REG_SOFTRESET
, SOFTRESET_AUDIO
);
631 reg_clear(priv
, REG_SOFTRESET
, SOFTRESET_AUDIO
);
632 reg_set(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_FIFO
);
634 reg_clear(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_FIFO
);
639 tda998x_configure_audio(struct tda998x_priv
*priv
,
640 struct drm_display_mode
*mode
, struct tda998x_encoder_params
*p
)
642 uint8_t buf
[6], clksel_aip
, clksel_fs
, cts_n
, adiv
;
645 /* Enable audio ports */
646 reg_write(priv
, REG_ENA_AP
, p
->audio_cfg
);
647 reg_write(priv
, REG_ENA_ACLK
, p
->audio_clk_cfg
);
649 /* Set audio input source */
650 switch (p
->audio_format
) {
652 reg_write(priv
, REG_MUX_AP
, MUX_AP_SELECT_SPDIF
);
653 clksel_aip
= AIP_CLKSEL_AIP_SPDIF
;
654 clksel_fs
= AIP_CLKSEL_FS_FS64SPDIF
;
655 cts_n
= CTS_N_M(3) | CTS_N_K(3);
659 reg_write(priv
, REG_MUX_AP
, MUX_AP_SELECT_I2S
);
660 clksel_aip
= AIP_CLKSEL_AIP_I2S
;
661 clksel_fs
= AIP_CLKSEL_FS_ACLK
;
662 cts_n
= CTS_N_M(3) | CTS_N_K(3);
670 reg_write(priv
, REG_AIP_CLKSEL
, clksel_aip
);
671 reg_clear(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_LAYOUT
|
672 AIP_CNTRL_0_ACR_MAN
); /* auto CTS */
673 reg_write(priv
, REG_CTS_N
, cts_n
);
676 * Audio input somehow depends on HDMI line rate which is
677 * related to pixclk. Testing showed that modes with pixclk
678 * >100MHz need a larger divider while <40MHz need the default.
679 * There is no detailed info in the datasheet, so we just
680 * assume 100MHz requires larger divider.
682 adiv
= AUDIO_DIV_SERCLK_8
;
683 if (mode
->clock
> 100000)
684 adiv
++; /* AUDIO_DIV_SERCLK_16 */
686 /* S/PDIF asks for a larger divider */
687 if (p
->audio_format
== AFMT_SPDIF
)
688 adiv
++; /* AUDIO_DIV_SERCLK_16 or _32 */
690 reg_write(priv
, REG_AUDIO_DIV
, adiv
);
693 * This is the approximate value of N, which happens to be
694 * the recommended values for non-coherent clocks.
696 n
= 128 * p
->audio_sample_rate
/ 1000;
698 /* Write the CTS and N values */
705 reg_write_range(priv
, REG_ACR_CTS_0
, buf
, 6);
707 /* Set CTS clock reference */
708 reg_write(priv
, REG_AIP_CLKSEL
, clksel_aip
| clksel_fs
);
710 /* Reset CTS generator */
711 reg_set(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_CTS
);
712 reg_clear(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_CTS
);
714 /* Write the channel status */
715 buf
[0] = IEC958_AES0_CON_NOT_COPYRIGHT
;
717 buf
[2] = IEC958_AES3_CON_FS_NOTID
;
718 buf
[3] = IEC958_AES4_CON_ORIGFS_NOTID
|
719 IEC958_AES4_CON_MAX_WORDLEN_24
;
720 reg_write_range(priv
, REG_CH_STAT_B(0), buf
, 4);
722 tda998x_audio_mute(priv
, true);
724 tda998x_audio_mute(priv
, false);
726 /* Write the audio information packet */
727 tda998x_write_aif(priv
, p
);
730 /* DRM encoder functions */
732 static void tda998x_encoder_set_config(struct tda998x_priv
*priv
,
733 const struct tda998x_encoder_params
*p
)
735 priv
->vip_cntrl_0
= VIP_CNTRL_0_SWAP_A(p
->swap_a
) |
736 (p
->mirr_a
? VIP_CNTRL_0_MIRR_A
: 0) |
737 VIP_CNTRL_0_SWAP_B(p
->swap_b
) |
738 (p
->mirr_b
? VIP_CNTRL_0_MIRR_B
: 0);
739 priv
->vip_cntrl_1
= VIP_CNTRL_1_SWAP_C(p
->swap_c
) |
740 (p
->mirr_c
? VIP_CNTRL_1_MIRR_C
: 0) |
741 VIP_CNTRL_1_SWAP_D(p
->swap_d
) |
742 (p
->mirr_d
? VIP_CNTRL_1_MIRR_D
: 0);
743 priv
->vip_cntrl_2
= VIP_CNTRL_2_SWAP_E(p
->swap_e
) |
744 (p
->mirr_e
? VIP_CNTRL_2_MIRR_E
: 0) |
745 VIP_CNTRL_2_SWAP_F(p
->swap_f
) |
746 (p
->mirr_f
? VIP_CNTRL_2_MIRR_F
: 0);
751 static void tda998x_encoder_dpms(struct tda998x_priv
*priv
, int mode
)
753 /* we only care about on or off: */
754 if (mode
!= DRM_MODE_DPMS_ON
)
755 mode
= DRM_MODE_DPMS_OFF
;
757 if (mode
== priv
->dpms
)
761 case DRM_MODE_DPMS_ON
:
762 /* enable video ports, audio will be enabled later */
763 reg_write(priv
, REG_ENA_VP_0
, 0xff);
764 reg_write(priv
, REG_ENA_VP_1
, 0xff);
765 reg_write(priv
, REG_ENA_VP_2
, 0xff);
766 /* set muxing after enabling ports: */
767 reg_write(priv
, REG_VIP_CNTRL_0
, priv
->vip_cntrl_0
);
768 reg_write(priv
, REG_VIP_CNTRL_1
, priv
->vip_cntrl_1
);
769 reg_write(priv
, REG_VIP_CNTRL_2
, priv
->vip_cntrl_2
);
771 case DRM_MODE_DPMS_OFF
:
772 /* disable video ports */
773 reg_write(priv
, REG_ENA_VP_0
, 0x00);
774 reg_write(priv
, REG_ENA_VP_1
, 0x00);
775 reg_write(priv
, REG_ENA_VP_2
, 0x00);
783 tda998x_encoder_save(struct drm_encoder
*encoder
)
789 tda998x_encoder_restore(struct drm_encoder
*encoder
)
795 tda998x_encoder_mode_fixup(struct drm_encoder
*encoder
,
796 const struct drm_display_mode
*mode
,
797 struct drm_display_mode
*adjusted_mode
)
802 static int tda998x_encoder_mode_valid(struct tda998x_priv
*priv
,
803 struct drm_display_mode
*mode
)
805 if (mode
->clock
> 150000)
806 return MODE_CLOCK_HIGH
;
807 if (mode
->htotal
>= BIT(13))
808 return MODE_BAD_HVALUE
;
809 if (mode
->vtotal
>= BIT(11))
810 return MODE_BAD_VVALUE
;
815 tda998x_encoder_mode_set(struct tda998x_priv
*priv
,
816 struct drm_display_mode
*mode
,
817 struct drm_display_mode
*adjusted_mode
)
819 uint16_t ref_pix
, ref_line
, n_pix
, n_line
;
820 uint16_t hs_pix_s
, hs_pix_e
;
821 uint16_t vs1_pix_s
, vs1_pix_e
, vs1_line_s
, vs1_line_e
;
822 uint16_t vs2_pix_s
, vs2_pix_e
, vs2_line_s
, vs2_line_e
;
823 uint16_t vwin1_line_s
, vwin1_line_e
;
824 uint16_t vwin2_line_s
, vwin2_line_e
;
825 uint16_t de_pix_s
, de_pix_e
;
826 uint8_t reg
, div
, rep
;
829 * Internally TDA998x is using ITU-R BT.656 style sync but
830 * we get VESA style sync. TDA998x is using a reference pixel
831 * relative to ITU to sync to the input frame and for output
832 * sync generation. Currently, we are using reference detection
833 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
834 * which is position of rising VS with coincident rising HS.
836 * Now there is some issues to take care of:
837 * - HDMI data islands require sync-before-active
838 * - TDA998x register values must be > 0 to be enabled
839 * - REFLINE needs an additional offset of +1
840 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
842 * So we add +1 to all horizontal and vertical register values,
843 * plus an additional +3 for REFPIX as we are using RGB input only.
845 n_pix
= mode
->htotal
;
846 n_line
= mode
->vtotal
;
848 hs_pix_e
= mode
->hsync_end
- mode
->hdisplay
;
849 hs_pix_s
= mode
->hsync_start
- mode
->hdisplay
;
850 de_pix_e
= mode
->htotal
;
851 de_pix_s
= mode
->htotal
- mode
->hdisplay
;
852 ref_pix
= 3 + hs_pix_s
;
855 * Attached LCD controllers may generate broken sync. Allow
856 * those to adjust the position of the rising VS edge by adding
859 if (adjusted_mode
->flags
& DRM_MODE_FLAG_HSKEW
)
860 ref_pix
+= adjusted_mode
->hskew
;
862 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) == 0) {
863 ref_line
= 1 + mode
->vsync_start
- mode
->vdisplay
;
864 vwin1_line_s
= mode
->vtotal
- mode
->vdisplay
- 1;
865 vwin1_line_e
= vwin1_line_s
+ mode
->vdisplay
;
866 vs1_pix_s
= vs1_pix_e
= hs_pix_s
;
867 vs1_line_s
= mode
->vsync_start
- mode
->vdisplay
;
868 vs1_line_e
= vs1_line_s
+
869 mode
->vsync_end
- mode
->vsync_start
;
870 vwin2_line_s
= vwin2_line_e
= 0;
871 vs2_pix_s
= vs2_pix_e
= 0;
872 vs2_line_s
= vs2_line_e
= 0;
874 ref_line
= 1 + (mode
->vsync_start
- mode
->vdisplay
)/2;
875 vwin1_line_s
= (mode
->vtotal
- mode
->vdisplay
)/2;
876 vwin1_line_e
= vwin1_line_s
+ mode
->vdisplay
/2;
877 vs1_pix_s
= vs1_pix_e
= hs_pix_s
;
878 vs1_line_s
= (mode
->vsync_start
- mode
->vdisplay
)/2;
879 vs1_line_e
= vs1_line_s
+
880 (mode
->vsync_end
- mode
->vsync_start
)/2;
881 vwin2_line_s
= vwin1_line_s
+ mode
->vtotal
/2;
882 vwin2_line_e
= vwin2_line_s
+ mode
->vdisplay
/2;
883 vs2_pix_s
= vs2_pix_e
= hs_pix_s
+ mode
->htotal
/2;
884 vs2_line_s
= vs1_line_s
+ mode
->vtotal
/2 ;
885 vs2_line_e
= vs2_line_s
+
886 (mode
->vsync_end
- mode
->vsync_start
)/2;
889 div
= 148500 / mode
->clock
;
896 /* mute the audio FIFO: */
897 reg_set(priv
, REG_AIP_CNTRL_0
, AIP_CNTRL_0_RST_FIFO
);
899 /* set HDMI HDCP mode off: */
900 reg_write(priv
, REG_TBG_CNTRL_1
, TBG_CNTRL_1_DWIN_DIS
);
901 reg_clear(priv
, REG_TX33
, TX33_HDMI
);
902 reg_write(priv
, REG_ENC_CNTRL
, ENC_CNTRL_CTL_CODE(0));
904 /* no pre-filter or interpolator: */
905 reg_write(priv
, REG_HVF_CNTRL_0
, HVF_CNTRL_0_PREFIL(0) |
906 HVF_CNTRL_0_INTPOL(0));
907 reg_write(priv
, REG_VIP_CNTRL_5
, VIP_CNTRL_5_SP_CNT(0));
908 reg_write(priv
, REG_VIP_CNTRL_4
, VIP_CNTRL_4_BLANKIT(0) |
911 reg_clear(priv
, REG_PLL_SERIAL_1
, PLL_SERIAL_1_SRL_MAN_IZ
);
912 reg_clear(priv
, REG_PLL_SERIAL_3
, PLL_SERIAL_3_SRL_CCIR
|
913 PLL_SERIAL_3_SRL_DE
);
914 reg_write(priv
, REG_SERIALIZER
, 0);
915 reg_write(priv
, REG_HVF_CNTRL_1
, HVF_CNTRL_1_VQR(0));
917 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
919 reg_write(priv
, REG_RPT_CNTRL
, 0);
920 reg_write(priv
, REG_SEL_CLK
, SEL_CLK_SEL_VRF_CLK(0) |
921 SEL_CLK_SEL_CLK1
| SEL_CLK_ENA_SC_CLK
);
923 reg_write(priv
, REG_PLL_SERIAL_2
, PLL_SERIAL_2_SRL_NOSC(div
) |
924 PLL_SERIAL_2_SRL_PR(rep
));
926 /* set color matrix bypass flag: */
927 reg_write(priv
, REG_MAT_CONTRL
, MAT_CONTRL_MAT_BP
|
928 MAT_CONTRL_MAT_SC(1));
930 /* set BIAS tmds value: */
931 reg_write(priv
, REG_ANA_GENERAL
, 0x09);
934 * Sync on rising HSYNC/VSYNC
936 reg
= VIP_CNTRL_3_SYNC_HS
;
939 * TDA19988 requires high-active sync at input stage,
940 * so invert low-active sync provided by master encoder here
942 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
943 reg
|= VIP_CNTRL_3_H_TGL
;
944 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
945 reg
|= VIP_CNTRL_3_V_TGL
;
946 reg_write(priv
, REG_VIP_CNTRL_3
, reg
);
948 reg_write(priv
, REG_VIDFORMAT
, 0x00);
949 reg_write16(priv
, REG_REFPIX_MSB
, ref_pix
);
950 reg_write16(priv
, REG_REFLINE_MSB
, ref_line
);
951 reg_write16(priv
, REG_NPIX_MSB
, n_pix
);
952 reg_write16(priv
, REG_NLINE_MSB
, n_line
);
953 reg_write16(priv
, REG_VS_LINE_STRT_1_MSB
, vs1_line_s
);
954 reg_write16(priv
, REG_VS_PIX_STRT_1_MSB
, vs1_pix_s
);
955 reg_write16(priv
, REG_VS_LINE_END_1_MSB
, vs1_line_e
);
956 reg_write16(priv
, REG_VS_PIX_END_1_MSB
, vs1_pix_e
);
957 reg_write16(priv
, REG_VS_LINE_STRT_2_MSB
, vs2_line_s
);
958 reg_write16(priv
, REG_VS_PIX_STRT_2_MSB
, vs2_pix_s
);
959 reg_write16(priv
, REG_VS_LINE_END_2_MSB
, vs2_line_e
);
960 reg_write16(priv
, REG_VS_PIX_END_2_MSB
, vs2_pix_e
);
961 reg_write16(priv
, REG_HS_PIX_START_MSB
, hs_pix_s
);
962 reg_write16(priv
, REG_HS_PIX_STOP_MSB
, hs_pix_e
);
963 reg_write16(priv
, REG_VWIN_START_1_MSB
, vwin1_line_s
);
964 reg_write16(priv
, REG_VWIN_END_1_MSB
, vwin1_line_e
);
965 reg_write16(priv
, REG_VWIN_START_2_MSB
, vwin2_line_s
);
966 reg_write16(priv
, REG_VWIN_END_2_MSB
, vwin2_line_e
);
967 reg_write16(priv
, REG_DE_START_MSB
, de_pix_s
);
968 reg_write16(priv
, REG_DE_STOP_MSB
, de_pix_e
);
970 if (priv
->rev
== TDA19988
) {
971 /* let incoming pixels fill the active space (if any) */
972 reg_write(priv
, REG_ENABLE_SPACE
, 0x00);
976 * Always generate sync polarity relative to input sync and
977 * revert input stage toggled sync at output stage
979 reg
= TBG_CNTRL_1_DWIN_DIS
| TBG_CNTRL_1_TGL_EN
;
980 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
981 reg
|= TBG_CNTRL_1_H_TGL
;
982 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
983 reg
|= TBG_CNTRL_1_V_TGL
;
984 reg_write(priv
, REG_TBG_CNTRL_1
, reg
);
986 /* must be last register set: */
987 reg_write(priv
, REG_TBG_CNTRL_0
, 0);
989 /* Only setup the info frames if the sink is HDMI */
990 if (priv
->is_hdmi_sink
) {
991 /* We need to turn HDMI HDCP stuff on to get audio through */
992 reg
&= ~TBG_CNTRL_1_DWIN_DIS
;
993 reg_write(priv
, REG_TBG_CNTRL_1
, reg
);
994 reg_write(priv
, REG_ENC_CNTRL
, ENC_CNTRL_CTL_CODE(1));
995 reg_set(priv
, REG_TX33
, TX33_HDMI
);
997 tda998x_write_avi(priv
, adjusted_mode
);
999 if (priv
->params
.audio_cfg
)
1000 tda998x_configure_audio(priv
, adjusted_mode
,
1005 static enum drm_connector_status
1006 tda998x_encoder_detect(struct tda998x_priv
*priv
)
1008 uint8_t val
= cec_read(priv
, REG_CEC_RXSHPDLEV
);
1010 return (val
& CEC_RXSHPDLEV_HPD
) ? connector_status_connected
:
1011 connector_status_disconnected
;
1014 static int read_edid_block(struct tda998x_priv
*priv
, uint8_t *buf
, int blk
)
1016 uint8_t offset
, segptr
;
1019 offset
= (blk
& 1) ? 128 : 0;
1022 reg_write(priv
, REG_DDC_ADDR
, 0xa0);
1023 reg_write(priv
, REG_DDC_OFFS
, offset
);
1024 reg_write(priv
, REG_DDC_SEGM_ADDR
, 0x60);
1025 reg_write(priv
, REG_DDC_SEGM
, segptr
);
1027 /* enable reading EDID: */
1028 priv
->wq_edid_wait
= 1;
1029 reg_write(priv
, REG_EDID_CTRL
, 0x1);
1031 /* flag must be cleared by sw: */
1032 reg_write(priv
, REG_EDID_CTRL
, 0x0);
1034 /* wait for block read to complete: */
1035 if (priv
->hdmi
->irq
) {
1036 i
= wait_event_timeout(priv
->wq_edid
,
1037 !priv
->wq_edid_wait
,
1038 msecs_to_jiffies(100));
1040 dev_err(&priv
->hdmi
->dev
, "read edid wait err %d\n", i
);
1044 for (i
= 100; i
> 0; i
--) {
1046 ret
= reg_read(priv
, REG_INT_FLAGS_2
);
1049 if (ret
& INT_FLAGS_2_EDID_BLK_RD
)
1055 dev_err(&priv
->hdmi
->dev
, "read edid timeout\n");
1059 ret
= reg_read_range(priv
, REG_EDID_DATA_0
, buf
, EDID_LENGTH
);
1060 if (ret
!= EDID_LENGTH
) {
1061 dev_err(&priv
->hdmi
->dev
, "failed to read edid block %d: %d\n",
1069 static uint8_t *do_get_edid(struct tda998x_priv
*priv
)
1071 int j
, valid_extensions
= 0;
1072 uint8_t *block
, *new;
1073 bool print_bad_edid
= drm_debug
& DRM_UT_KMS
;
1075 if ((block
= kmalloc(EDID_LENGTH
, GFP_KERNEL
)) == NULL
)
1078 if (priv
->rev
== TDA19988
)
1079 reg_clear(priv
, REG_TX4
, TX4_PD_RAM
);
1081 /* base block fetch */
1082 if (read_edid_block(priv
, block
, 0))
1085 if (!drm_edid_block_valid(block
, 0, print_bad_edid
))
1088 /* if there's no extensions, we're done */
1089 if (block
[0x7e] == 0)
1092 new = krealloc(block
, (block
[0x7e] + 1) * EDID_LENGTH
, GFP_KERNEL
);
1097 for (j
= 1; j
<= block
[0x7e]; j
++) {
1098 uint8_t *ext_block
= block
+ (valid_extensions
+ 1) * EDID_LENGTH
;
1099 if (read_edid_block(priv
, ext_block
, j
))
1102 if (!drm_edid_block_valid(ext_block
, j
, print_bad_edid
))
1108 if (valid_extensions
!= block
[0x7e]) {
1109 block
[EDID_LENGTH
-1] += block
[0x7e] - valid_extensions
;
1110 block
[0x7e] = valid_extensions
;
1111 new = krealloc(block
, (valid_extensions
+ 1) * EDID_LENGTH
, GFP_KERNEL
);
1118 if (priv
->rev
== TDA19988
)
1119 reg_set(priv
, REG_TX4
, TX4_PD_RAM
);
1124 if (priv
->rev
== TDA19988
)
1125 reg_set(priv
, REG_TX4
, TX4_PD_RAM
);
1126 dev_warn(&priv
->hdmi
->dev
, "failed to read EDID\n");
1132 tda998x_encoder_get_modes(struct tda998x_priv
*priv
,
1133 struct drm_connector
*connector
)
1135 struct edid
*edid
= (struct edid
*)do_get_edid(priv
);
1139 drm_mode_connector_update_edid_property(connector
, edid
);
1140 n
= drm_add_edid_modes(connector
, edid
);
1141 priv
->is_hdmi_sink
= drm_detect_hdmi_monitor(edid
);
1148 static void tda998x_encoder_set_polling(struct tda998x_priv
*priv
,
1149 struct drm_connector
*connector
)
1151 if (priv
->hdmi
->irq
)
1152 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1154 connector
->polled
= DRM_CONNECTOR_POLL_CONNECT
|
1155 DRM_CONNECTOR_POLL_DISCONNECT
;
1159 tda998x_encoder_set_property(struct drm_encoder
*encoder
,
1160 struct drm_connector
*connector
,
1161 struct drm_property
*property
,
1168 static void tda998x_destroy(struct tda998x_priv
*priv
)
1170 /* disable all IRQs and free the IRQ handler */
1171 cec_write(priv
, REG_CEC_RXSHPDINTENA
, 0);
1172 reg_clear(priv
, REG_INT_FLAGS_2
, INT_FLAGS_2_EDID_BLK_RD
);
1173 if (priv
->hdmi
->irq
)
1174 free_irq(priv
->hdmi
->irq
, priv
);
1176 i2c_unregister_device(priv
->cec
);
1179 /* Slave encoder support */
1182 tda998x_encoder_slave_set_config(struct drm_encoder
*encoder
, void *params
)
1184 tda998x_encoder_set_config(to_tda998x_priv(encoder
), params
);
1187 static void tda998x_encoder_slave_destroy(struct drm_encoder
*encoder
)
1189 struct tda998x_priv
*priv
= to_tda998x_priv(encoder
);
1191 tda998x_destroy(priv
);
1192 drm_i2c_encoder_destroy(encoder
);
1196 static void tda998x_encoder_slave_dpms(struct drm_encoder
*encoder
, int mode
)
1198 tda998x_encoder_dpms(to_tda998x_priv(encoder
), mode
);
1201 static int tda998x_encoder_slave_mode_valid(struct drm_encoder
*encoder
,
1202 struct drm_display_mode
*mode
)
1204 return tda998x_encoder_mode_valid(to_tda998x_priv(encoder
), mode
);
1208 tda998x_encoder_slave_mode_set(struct drm_encoder
*encoder
,
1209 struct drm_display_mode
*mode
,
1210 struct drm_display_mode
*adjusted_mode
)
1212 tda998x_encoder_mode_set(to_tda998x_priv(encoder
), mode
, adjusted_mode
);
1215 static enum drm_connector_status
1216 tda998x_encoder_slave_detect(struct drm_encoder
*encoder
,
1217 struct drm_connector
*connector
)
1219 return tda998x_encoder_detect(to_tda998x_priv(encoder
));
1222 static int tda998x_encoder_slave_get_modes(struct drm_encoder
*encoder
,
1223 struct drm_connector
*connector
)
1225 return tda998x_encoder_get_modes(to_tda998x_priv(encoder
), connector
);
1229 tda998x_encoder_slave_create_resources(struct drm_encoder
*encoder
,
1230 struct drm_connector
*connector
)
1232 tda998x_encoder_set_polling(to_tda998x_priv(encoder
), connector
);
1236 static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs
= {
1237 .set_config
= tda998x_encoder_slave_set_config
,
1238 .destroy
= tda998x_encoder_slave_destroy
,
1239 .dpms
= tda998x_encoder_slave_dpms
,
1240 .save
= tda998x_encoder_save
,
1241 .restore
= tda998x_encoder_restore
,
1242 .mode_fixup
= tda998x_encoder_mode_fixup
,
1243 .mode_valid
= tda998x_encoder_slave_mode_valid
,
1244 .mode_set
= tda998x_encoder_slave_mode_set
,
1245 .detect
= tda998x_encoder_slave_detect
,
1246 .get_modes
= tda998x_encoder_slave_get_modes
,
1247 .create_resources
= tda998x_encoder_slave_create_resources
,
1248 .set_property
= tda998x_encoder_set_property
,
1251 /* I2C driver functions */
1253 static int tda998x_create(struct i2c_client
*client
, struct tda998x_priv
*priv
)
1255 struct device_node
*np
= client
->dev
.of_node
;
1257 int rev_lo
, rev_hi
, ret
;
1259 priv
->vip_cntrl_0
= VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1260 priv
->vip_cntrl_1
= VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1261 priv
->vip_cntrl_2
= VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1263 priv
->current_page
= 0xff;
1264 priv
->hdmi
= client
;
1265 priv
->cec
= i2c_new_dummy(client
->adapter
, 0x34);
1269 priv
->dpms
= DRM_MODE_DPMS_OFF
;
1271 /* wake up the device: */
1272 cec_write(priv
, REG_CEC_ENAMODS
,
1273 CEC_ENAMODS_EN_RXSENS
| CEC_ENAMODS_EN_HDMI
);
1275 tda998x_reset(priv
);
1278 rev_lo
= reg_read(priv
, REG_VERSION_LSB
);
1279 rev_hi
= reg_read(priv
, REG_VERSION_MSB
);
1280 if (rev_lo
< 0 || rev_hi
< 0) {
1281 ret
= rev_lo
< 0 ? rev_lo
: rev_hi
;
1285 priv
->rev
= rev_lo
| rev_hi
<< 8;
1287 /* mask off feature bits: */
1288 priv
->rev
&= ~0x30; /* not-hdcp and not-scalar bit */
1290 switch (priv
->rev
) {
1292 dev_info(&client
->dev
, "found TDA9989 n2");
1295 dev_info(&client
->dev
, "found TDA19989");
1298 dev_info(&client
->dev
, "found TDA19989 n2");
1301 dev_info(&client
->dev
, "found TDA19988");
1304 dev_err(&client
->dev
, "found unsupported device: %04x\n",
1309 /* after reset, enable DDC: */
1310 reg_write(priv
, REG_DDC_DISABLE
, 0x00);
1312 /* set clock on DDC channel: */
1313 reg_write(priv
, REG_TX3
, 39);
1315 /* if necessary, disable multi-master: */
1316 if (priv
->rev
== TDA19989
)
1317 reg_set(priv
, REG_I2C_MASTER
, I2C_MASTER_DIS_MM
);
1319 cec_write(priv
, REG_CEC_FRO_IM_CLK_CTRL
,
1320 CEC_FRO_IM_CLK_CTRL_GHOST_DIS
| CEC_FRO_IM_CLK_CTRL_IMCLK_SEL
);
1322 /* initialize the optional IRQ */
1326 /* init read EDID waitqueue */
1327 init_waitqueue_head(&priv
->wq_edid
);
1329 /* clear pending interrupts */
1330 reg_read(priv
, REG_INT_FLAGS_0
);
1331 reg_read(priv
, REG_INT_FLAGS_1
);
1332 reg_read(priv
, REG_INT_FLAGS_2
);
1335 irqd_get_trigger_type(irq_get_irq_data(client
->irq
));
1336 ret
= request_threaded_irq(client
->irq
, NULL
,
1338 irqf_trigger
| IRQF_ONESHOT
,
1341 dev_err(&client
->dev
,
1342 "failed to request IRQ#%u: %d\n",
1347 /* enable HPD irq */
1348 cec_write(priv
, REG_CEC_RXSHPDINTENA
, CEC_RXSHPDLEV_HPD
);
1351 /* enable EDID read irq: */
1352 reg_set(priv
, REG_INT_FLAGS_2
, INT_FLAGS_2_EDID_BLK_RD
);
1355 return 0; /* non-DT */
1357 /* get the optional video properties */
1358 ret
= of_property_read_u32(np
, "video-ports", &video
);
1360 priv
->vip_cntrl_0
= video
>> 16;
1361 priv
->vip_cntrl_1
= video
>> 8;
1362 priv
->vip_cntrl_2
= video
;
1368 /* if encoder_init fails, the encoder slave is never registered,
1372 i2c_unregister_device(priv
->cec
);
1376 static int tda998x_encoder_init(struct i2c_client
*client
,
1377 struct drm_device
*dev
,
1378 struct drm_encoder_slave
*encoder_slave
)
1380 struct tda998x_priv
*priv
;
1383 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
1387 priv
->encoder
= &encoder_slave
->base
;
1389 ret
= tda998x_create(client
, priv
);
1395 encoder_slave
->slave_priv
= priv
;
1396 encoder_slave
->slave_funcs
= &tda998x_encoder_slave_funcs
;
1401 struct tda998x_priv2
{
1402 struct tda998x_priv base
;
1403 struct drm_encoder encoder
;
1404 struct drm_connector connector
;
1407 #define conn_to_tda998x_priv2(x) \
1408 container_of(x, struct tda998x_priv2, connector);
1410 #define enc_to_tda998x_priv2(x) \
1411 container_of(x, struct tda998x_priv2, encoder);
1413 static void tda998x_encoder2_dpms(struct drm_encoder
*encoder
, int mode
)
1415 struct tda998x_priv2
*priv
= enc_to_tda998x_priv2(encoder
);
1417 tda998x_encoder_dpms(&priv
->base
, mode
);
1420 static void tda998x_encoder_prepare(struct drm_encoder
*encoder
)
1422 tda998x_encoder2_dpms(encoder
, DRM_MODE_DPMS_OFF
);
1425 static void tda998x_encoder_commit(struct drm_encoder
*encoder
)
1427 tda998x_encoder2_dpms(encoder
, DRM_MODE_DPMS_ON
);
1430 static void tda998x_encoder2_mode_set(struct drm_encoder
*encoder
,
1431 struct drm_display_mode
*mode
,
1432 struct drm_display_mode
*adjusted_mode
)
1434 struct tda998x_priv2
*priv
= enc_to_tda998x_priv2(encoder
);
1436 tda998x_encoder_mode_set(&priv
->base
, mode
, adjusted_mode
);
1439 static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs
= {
1440 .dpms
= tda998x_encoder2_dpms
,
1441 .save
= tda998x_encoder_save
,
1442 .restore
= tda998x_encoder_restore
,
1443 .mode_fixup
= tda998x_encoder_mode_fixup
,
1444 .prepare
= tda998x_encoder_prepare
,
1445 .commit
= tda998x_encoder_commit
,
1446 .mode_set
= tda998x_encoder2_mode_set
,
1449 static void tda998x_encoder_destroy(struct drm_encoder
*encoder
)
1451 struct tda998x_priv2
*priv
= enc_to_tda998x_priv2(encoder
);
1453 tda998x_destroy(&priv
->base
);
1454 drm_encoder_cleanup(encoder
);
1457 static const struct drm_encoder_funcs tda998x_encoder_funcs
= {
1458 .destroy
= tda998x_encoder_destroy
,
1461 static int tda998x_connector_get_modes(struct drm_connector
*connector
)
1463 struct tda998x_priv2
*priv
= conn_to_tda998x_priv2(connector
);
1465 return tda998x_encoder_get_modes(&priv
->base
, connector
);
1468 static int tda998x_connector_mode_valid(struct drm_connector
*connector
,
1469 struct drm_display_mode
*mode
)
1471 struct tda998x_priv2
*priv
= conn_to_tda998x_priv2(connector
);
1473 return tda998x_encoder_mode_valid(&priv
->base
, mode
);
1476 static struct drm_encoder
*
1477 tda998x_connector_best_encoder(struct drm_connector
*connector
)
1479 struct tda998x_priv2
*priv
= conn_to_tda998x_priv2(connector
);
1481 return &priv
->encoder
;
1485 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs
= {
1486 .get_modes
= tda998x_connector_get_modes
,
1487 .mode_valid
= tda998x_connector_mode_valid
,
1488 .best_encoder
= tda998x_connector_best_encoder
,
1491 static enum drm_connector_status
1492 tda998x_connector_detect(struct drm_connector
*connector
, bool force
)
1494 struct tda998x_priv2
*priv
= conn_to_tda998x_priv2(connector
);
1496 return tda998x_encoder_detect(&priv
->base
);
1499 static void tda998x_connector_destroy(struct drm_connector
*connector
)
1501 drm_sysfs_connector_remove(connector
);
1502 drm_connector_cleanup(connector
);
1505 static const struct drm_connector_funcs tda998x_connector_funcs
= {
1506 .dpms
= drm_helper_connector_dpms
,
1507 .fill_modes
= drm_helper_probe_single_connector_modes
,
1508 .detect
= tda998x_connector_detect
,
1509 .destroy
= tda998x_connector_destroy
,
1512 static int tda998x_bind(struct device
*dev
, struct device
*master
, void *data
)
1514 struct tda998x_encoder_params
*params
= dev
->platform_data
;
1515 struct i2c_client
*client
= to_i2c_client(dev
);
1516 struct drm_device
*drm
= data
;
1517 struct tda998x_priv2
*priv
;
1520 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1524 dev_set_drvdata(dev
, priv
);
1526 priv
->base
.encoder
= &priv
->encoder
;
1527 priv
->connector
.interlace_allowed
= 1;
1528 priv
->encoder
.possible_crtcs
= 1 << 0;
1530 ret
= tda998x_create(client
, &priv
->base
);
1534 if (!dev
->of_node
&& params
)
1535 tda998x_encoder_set_config(&priv
->base
, params
);
1537 tda998x_encoder_set_polling(&priv
->base
, &priv
->connector
);
1539 drm_encoder_helper_add(&priv
->encoder
, &tda998x_encoder_helper_funcs
);
1540 ret
= drm_encoder_init(drm
, &priv
->encoder
, &tda998x_encoder_funcs
,
1541 DRM_MODE_ENCODER_TMDS
);
1545 drm_connector_helper_add(&priv
->connector
,
1546 &tda998x_connector_helper_funcs
);
1547 ret
= drm_connector_init(drm
, &priv
->connector
,
1548 &tda998x_connector_funcs
,
1549 DRM_MODE_CONNECTOR_HDMIA
);
1553 ret
= drm_sysfs_connector_add(&priv
->connector
);
1557 priv
->connector
.encoder
= &priv
->encoder
;
1558 drm_mode_connector_attach_encoder(&priv
->connector
, &priv
->encoder
);
1563 drm_connector_cleanup(&priv
->connector
);
1565 drm_encoder_cleanup(&priv
->encoder
);
1567 tda998x_destroy(&priv
->base
);
1571 static void tda998x_unbind(struct device
*dev
, struct device
*master
,
1574 struct tda998x_priv2
*priv
= dev_get_drvdata(dev
);
1576 drm_connector_cleanup(&priv
->connector
);
1577 drm_encoder_cleanup(&priv
->encoder
);
1578 tda998x_destroy(&priv
->base
);
1581 static const struct component_ops tda998x_ops
= {
1582 .bind
= tda998x_bind
,
1583 .unbind
= tda998x_unbind
,
1587 tda998x_probe(struct i2c_client
*client
, const struct i2c_device_id
*id
)
1589 return component_add(&client
->dev
, &tda998x_ops
);
1592 static int tda998x_remove(struct i2c_client
*client
)
1594 component_del(&client
->dev
, &tda998x_ops
);
1599 static const struct of_device_id tda998x_dt_ids
[] = {
1600 { .compatible
= "nxp,tda998x", },
1603 MODULE_DEVICE_TABLE(of
, tda998x_dt_ids
);
1606 static struct i2c_device_id tda998x_ids
[] = {
1610 MODULE_DEVICE_TABLE(i2c
, tda998x_ids
);
1612 static struct drm_i2c_encoder_driver tda998x_driver
= {
1614 .probe
= tda998x_probe
,
1615 .remove
= tda998x_remove
,
1618 .of_match_table
= of_match_ptr(tda998x_dt_ids
),
1620 .id_table
= tda998x_ids
,
1622 .encoder_init
= tda998x_encoder_init
,
1625 /* Module initialization */
1631 return drm_i2c_encoder_register(THIS_MODULE
, &tda998x_driver
);
1638 drm_i2c_encoder_unregister(&tda998x_driver
);
1641 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1642 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1643 MODULE_LICENSE("GPL");
1645 module_init(tda998x_init
);
1646 module_exit(tda998x_exit
);