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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i830 / i830_dma.c
1 /* i830_dma.c -- DMA support for the I830 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Abraham vd Merwe <abraham@2d3d.co.za>
31 *
32 */
33
34 #include "drmP.h"
35 #include "drm.h"
36 #include "i830_drm.h"
37 #include "i830_drv.h"
38 #include <linux/interrupt.h> /* For task queue support */
39 #include <linux/pagemap.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <asm/uaccess.h>
43
44 #define I830_BUF_FREE 2
45 #define I830_BUF_CLIENT 1
46 #define I830_BUF_HARDWARE 0
47
48 #define I830_BUF_UNMAPPED 0
49 #define I830_BUF_MAPPED 1
50
51 static struct drm_buf *i830_freelist_get(struct drm_device * dev)
52 {
53 struct drm_device_dma *dma = dev->dma;
54 int i;
55 int used;
56
57 /* Linear search might not be the best solution */
58
59 for (i = 0; i < dma->buf_count; i++) {
60 struct drm_buf *buf = dma->buflist[i];
61 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
62 /* In use is already a pointer */
63 used = cmpxchg(buf_priv->in_use, I830_BUF_FREE,
64 I830_BUF_CLIENT);
65 if (used == I830_BUF_FREE) {
66 return buf;
67 }
68 }
69 return NULL;
70 }
71
72 /* This should only be called if the buffer is not sent to the hardware
73 * yet, the hardware updates in use for us once its on the ring buffer.
74 */
75
76 static int i830_freelist_put(struct drm_device * dev, struct drm_buf * buf)
77 {
78 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
79 int used;
80
81 /* In use is already a pointer */
82 used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE);
83 if (used != I830_BUF_CLIENT) {
84 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
85 return -EINVAL;
86 }
87
88 return 0;
89 }
90
91 static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
92 {
93 struct drm_file *priv = filp->private_data;
94 struct drm_device *dev;
95 drm_i830_private_t *dev_priv;
96 struct drm_buf *buf;
97 drm_i830_buf_priv_t *buf_priv;
98
99 lock_kernel();
100 dev = priv->minor->dev;
101 dev_priv = dev->dev_private;
102 buf = dev_priv->mmap_buffer;
103 buf_priv = buf->dev_private;
104
105 vma->vm_flags |= (VM_IO | VM_DONTCOPY);
106 vma->vm_file = filp;
107
108 buf_priv->currently_mapped = I830_BUF_MAPPED;
109 unlock_kernel();
110
111 if (io_remap_pfn_range(vma, vma->vm_start,
112 vma->vm_pgoff,
113 vma->vm_end - vma->vm_start, vma->vm_page_prot))
114 return -EAGAIN;
115 return 0;
116 }
117
118 static const struct file_operations i830_buffer_fops = {
119 .open = drm_open,
120 .release = drm_release,
121 .unlocked_ioctl = drm_ioctl,
122 .mmap = i830_mmap_buffers,
123 .fasync = drm_fasync,
124 };
125
126 static int i830_map_buffer(struct drm_buf * buf, struct drm_file *file_priv)
127 {
128 struct drm_device *dev = file_priv->minor->dev;
129 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
130 drm_i830_private_t *dev_priv = dev->dev_private;
131 const struct file_operations *old_fops;
132 unsigned long virtual;
133 int retcode = 0;
134
135 if (buf_priv->currently_mapped == I830_BUF_MAPPED)
136 return -EINVAL;
137
138 down_write(&current->mm->mmap_sem);
139 old_fops = file_priv->filp->f_op;
140 file_priv->filp->f_op = &i830_buffer_fops;
141 dev_priv->mmap_buffer = buf;
142 virtual = do_mmap(file_priv->filp, 0, buf->total, PROT_READ | PROT_WRITE,
143 MAP_SHARED, buf->bus_address);
144 dev_priv->mmap_buffer = NULL;
145 file_priv->filp->f_op = old_fops;
146 if (IS_ERR((void *)virtual)) { /* ugh */
147 /* Real error */
148 DRM_ERROR("mmap error\n");
149 retcode = PTR_ERR((void *)virtual);
150 buf_priv->virtual = NULL;
151 } else {
152 buf_priv->virtual = (void __user *)virtual;
153 }
154 up_write(&current->mm->mmap_sem);
155
156 return retcode;
157 }
158
159 static int i830_unmap_buffer(struct drm_buf * buf)
160 {
161 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
162 int retcode = 0;
163
164 if (buf_priv->currently_mapped != I830_BUF_MAPPED)
165 return -EINVAL;
166
167 down_write(&current->mm->mmap_sem);
168 retcode = do_munmap(current->mm,
169 (unsigned long)buf_priv->virtual,
170 (size_t) buf->total);
171 up_write(&current->mm->mmap_sem);
172
173 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
174 buf_priv->virtual = NULL;
175
176 return retcode;
177 }
178
179 static int i830_dma_get_buffer(struct drm_device * dev, drm_i830_dma_t * d,
180 struct drm_file *file_priv)
181 {
182 struct drm_buf *buf;
183 drm_i830_buf_priv_t *buf_priv;
184 int retcode = 0;
185
186 buf = i830_freelist_get(dev);
187 if (!buf) {
188 retcode = -ENOMEM;
189 DRM_DEBUG("retcode=%d\n", retcode);
190 return retcode;
191 }
192
193 retcode = i830_map_buffer(buf, file_priv);
194 if (retcode) {
195 i830_freelist_put(dev, buf);
196 DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
197 return retcode;
198 }
199 buf->file_priv = file_priv;
200 buf_priv = buf->dev_private;
201 d->granted = 1;
202 d->request_idx = buf->idx;
203 d->request_size = buf->total;
204 d->virtual = buf_priv->virtual;
205
206 return retcode;
207 }
208
209 static int i830_dma_cleanup(struct drm_device * dev)
210 {
211 struct drm_device_dma *dma = dev->dma;
212
213 /* Make sure interrupts are disabled here because the uninstall ioctl
214 * may not have been called from userspace and after dev_private
215 * is freed, it's too late.
216 */
217 if (dev->irq_enabled)
218 drm_irq_uninstall(dev);
219
220 if (dev->dev_private) {
221 int i;
222 drm_i830_private_t *dev_priv =
223 (drm_i830_private_t *) dev->dev_private;
224
225 if (dev_priv->ring.virtual_start) {
226 drm_core_ioremapfree(&dev_priv->ring.map, dev);
227 }
228 if (dev_priv->hw_status_page) {
229 pci_free_consistent(dev->pdev, PAGE_SIZE,
230 dev_priv->hw_status_page,
231 dev_priv->dma_status_page);
232 /* Need to rewrite hardware status page */
233 I830_WRITE(0x02080, 0x1ffff000);
234 }
235
236 kfree(dev->dev_private);
237 dev->dev_private = NULL;
238
239 for (i = 0; i < dma->buf_count; i++) {
240 struct drm_buf *buf = dma->buflist[i];
241 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
242 if (buf_priv->kernel_virtual && buf->total)
243 drm_core_ioremapfree(&buf_priv->map, dev);
244 }
245 }
246 return 0;
247 }
248
249 int i830_wait_ring(struct drm_device * dev, int n, const char *caller)
250 {
251 drm_i830_private_t *dev_priv = dev->dev_private;
252 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
253 int iters = 0;
254 unsigned long end;
255 unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
256
257 end = jiffies + (HZ * 3);
258 while (ring->space < n) {
259 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
260 ring->space = ring->head - (ring->tail + 8);
261 if (ring->space < 0)
262 ring->space += ring->Size;
263
264 if (ring->head != last_head) {
265 end = jiffies + (HZ * 3);
266 last_head = ring->head;
267 }
268
269 iters++;
270 if (time_before(end, jiffies)) {
271 DRM_ERROR("space: %d wanted %d\n", ring->space, n);
272 DRM_ERROR("lockup\n");
273 goto out_wait_ring;
274 }
275 udelay(1);
276 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
277 }
278
279 out_wait_ring:
280 return iters;
281 }
282
283 static void i830_kernel_lost_context(struct drm_device * dev)
284 {
285 drm_i830_private_t *dev_priv = dev->dev_private;
286 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
287
288 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
289 ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
290 ring->space = ring->head - (ring->tail + 8);
291 if (ring->space < 0)
292 ring->space += ring->Size;
293
294 if (ring->head == ring->tail)
295 dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY;
296 }
297
298 static int i830_freelist_init(struct drm_device * dev, drm_i830_private_t * dev_priv)
299 {
300 struct drm_device_dma *dma = dev->dma;
301 int my_idx = 36;
302 u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
303 int i;
304
305 if (dma->buf_count > 1019) {
306 /* Not enough space in the status page for the freelist */
307 return -EINVAL;
308 }
309
310 for (i = 0; i < dma->buf_count; i++) {
311 struct drm_buf *buf = dma->buflist[i];
312 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
313
314 buf_priv->in_use = hw_status++;
315 buf_priv->my_use_idx = my_idx;
316 my_idx += 4;
317
318 *buf_priv->in_use = I830_BUF_FREE;
319
320 buf_priv->map.offset = buf->bus_address;
321 buf_priv->map.size = buf->total;
322 buf_priv->map.type = _DRM_AGP;
323 buf_priv->map.flags = 0;
324 buf_priv->map.mtrr = 0;
325
326 drm_core_ioremap(&buf_priv->map, dev);
327 buf_priv->kernel_virtual = buf_priv->map.handle;
328 }
329 return 0;
330 }
331
332 static int i830_dma_initialize(struct drm_device * dev,
333 drm_i830_private_t * dev_priv,
334 drm_i830_init_t * init)
335 {
336 struct drm_map_list *r_list;
337
338 memset(dev_priv, 0, sizeof(drm_i830_private_t));
339
340 list_for_each_entry(r_list, &dev->maplist, head) {
341 if (r_list->map &&
342 r_list->map->type == _DRM_SHM &&
343 r_list->map->flags & _DRM_CONTAINS_LOCK) {
344 dev_priv->sarea_map = r_list->map;
345 break;
346 }
347 }
348
349 if (!dev_priv->sarea_map) {
350 dev->dev_private = (void *)dev_priv;
351 i830_dma_cleanup(dev);
352 DRM_ERROR("can not find sarea!\n");
353 return -EINVAL;
354 }
355 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
356 if (!dev_priv->mmio_map) {
357 dev->dev_private = (void *)dev_priv;
358 i830_dma_cleanup(dev);
359 DRM_ERROR("can not find mmio map!\n");
360 return -EINVAL;
361 }
362 dev->agp_buffer_token = init->buffers_offset;
363 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
364 if (!dev->agp_buffer_map) {
365 dev->dev_private = (void *)dev_priv;
366 i830_dma_cleanup(dev);
367 DRM_ERROR("can not find dma buffer map!\n");
368 return -EINVAL;
369 }
370
371 dev_priv->sarea_priv = (drm_i830_sarea_t *)
372 ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
373
374 dev_priv->ring.Start = init->ring_start;
375 dev_priv->ring.End = init->ring_end;
376 dev_priv->ring.Size = init->ring_size;
377
378 dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
379 dev_priv->ring.map.size = init->ring_size;
380 dev_priv->ring.map.type = _DRM_AGP;
381 dev_priv->ring.map.flags = 0;
382 dev_priv->ring.map.mtrr = 0;
383
384 drm_core_ioremap(&dev_priv->ring.map, dev);
385
386 if (dev_priv->ring.map.handle == NULL) {
387 dev->dev_private = (void *)dev_priv;
388 i830_dma_cleanup(dev);
389 DRM_ERROR("can not ioremap virtual address for"
390 " ring buffer\n");
391 return -ENOMEM;
392 }
393
394 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
395
396 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
397
398 dev_priv->w = init->w;
399 dev_priv->h = init->h;
400 dev_priv->pitch = init->pitch;
401 dev_priv->back_offset = init->back_offset;
402 dev_priv->depth_offset = init->depth_offset;
403 dev_priv->front_offset = init->front_offset;
404
405 dev_priv->front_di1 = init->front_offset | init->pitch_bits;
406 dev_priv->back_di1 = init->back_offset | init->pitch_bits;
407 dev_priv->zi1 = init->depth_offset | init->pitch_bits;
408
409 DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1);
410 DRM_DEBUG("back_offset %x\n", dev_priv->back_offset);
411 DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1);
412 DRM_DEBUG("pitch_bits %x\n", init->pitch_bits);
413
414 dev_priv->cpp = init->cpp;
415 /* We are using separate values as placeholders for mechanisms for
416 * private backbuffer/depthbuffer usage.
417 */
418
419 dev_priv->back_pitch = init->back_pitch;
420 dev_priv->depth_pitch = init->depth_pitch;
421 dev_priv->do_boxes = 0;
422 dev_priv->use_mi_batchbuffer_start = 0;
423
424 /* Program Hardware Status Page */
425 dev_priv->hw_status_page =
426 pci_alloc_consistent(dev->pdev, PAGE_SIZE,
427 &dev_priv->dma_status_page);
428 if (!dev_priv->hw_status_page) {
429 dev->dev_private = (void *)dev_priv;
430 i830_dma_cleanup(dev);
431 DRM_ERROR("Can not allocate hardware status page\n");
432 return -ENOMEM;
433 }
434 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
435 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
436
437 I830_WRITE(0x02080, dev_priv->dma_status_page);
438 DRM_DEBUG("Enabled hardware status page\n");
439
440 /* Now we need to init our freelist */
441 if (i830_freelist_init(dev, dev_priv) != 0) {
442 dev->dev_private = (void *)dev_priv;
443 i830_dma_cleanup(dev);
444 DRM_ERROR("Not enough space in the status page for"
445 " the freelist\n");
446 return -ENOMEM;
447 }
448 dev->dev_private = (void *)dev_priv;
449
450 return 0;
451 }
452
453 static int i830_dma_init(struct drm_device *dev, void *data,
454 struct drm_file *file_priv)
455 {
456 drm_i830_private_t *dev_priv;
457 drm_i830_init_t *init = data;
458 int retcode = 0;
459
460 switch (init->func) {
461 case I830_INIT_DMA:
462 dev_priv = kmalloc(sizeof(drm_i830_private_t), GFP_KERNEL);
463 if (dev_priv == NULL)
464 return -ENOMEM;
465 retcode = i830_dma_initialize(dev, dev_priv, init);
466 break;
467 case I830_CLEANUP_DMA:
468 retcode = i830_dma_cleanup(dev);
469 break;
470 default:
471 retcode = -EINVAL;
472 break;
473 }
474
475 return retcode;
476 }
477
478 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
479 #define ST1_ENABLE (1<<16)
480 #define ST1_MASK (0xffff)
481
482 /* Most efficient way to verify state for the i830 is as it is
483 * emitted. Non-conformant state is silently dropped.
484 */
485 static void i830EmitContextVerified(struct drm_device * dev, unsigned int *code)
486 {
487 drm_i830_private_t *dev_priv = dev->dev_private;
488 int i, j = 0;
489 unsigned int tmp;
490 RING_LOCALS;
491
492 BEGIN_LP_RING(I830_CTX_SETUP_SIZE + 4);
493
494 for (i = 0; i < I830_CTXREG_BLENDCOLR0; i++) {
495 tmp = code[i];
496 if ((tmp & (7 << 29)) == CMD_3D &&
497 (tmp & (0x1f << 24)) < (0x1d << 24)) {
498 OUT_RING(tmp);
499 j++;
500 } else {
501 DRM_ERROR("Skipping %d\n", i);
502 }
503 }
504
505 OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD);
506 OUT_RING(code[I830_CTXREG_BLENDCOLR]);
507 j += 2;
508
509 for (i = I830_CTXREG_VF; i < I830_CTXREG_MCSB0; i++) {
510 tmp = code[i];
511 if ((tmp & (7 << 29)) == CMD_3D &&
512 (tmp & (0x1f << 24)) < (0x1d << 24)) {
513 OUT_RING(tmp);
514 j++;
515 } else {
516 DRM_ERROR("Skipping %d\n", i);
517 }
518 }
519
520 OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD);
521 OUT_RING(code[I830_CTXREG_MCSB1]);
522 j += 2;
523
524 if (j & 1)
525 OUT_RING(0);
526
527 ADVANCE_LP_RING();
528 }
529
530 static void i830EmitTexVerified(struct drm_device * dev, unsigned int *code)
531 {
532 drm_i830_private_t *dev_priv = dev->dev_private;
533 int i, j = 0;
534 unsigned int tmp;
535 RING_LOCALS;
536
537 if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO ||
538 (code[I830_TEXREG_MI0] & ~(0xf * LOAD_TEXTURE_MAP0)) ==
539 (STATE3D_LOAD_STATE_IMMEDIATE_2 | 4)) {
540
541 BEGIN_LP_RING(I830_TEX_SETUP_SIZE);
542
543 OUT_RING(code[I830_TEXREG_MI0]); /* TM0LI */
544 OUT_RING(code[I830_TEXREG_MI1]); /* TM0S0 */
545 OUT_RING(code[I830_TEXREG_MI2]); /* TM0S1 */
546 OUT_RING(code[I830_TEXREG_MI3]); /* TM0S2 */
547 OUT_RING(code[I830_TEXREG_MI4]); /* TM0S3 */
548 OUT_RING(code[I830_TEXREG_MI5]); /* TM0S4 */
549
550 for (i = 6; i < I830_TEX_SETUP_SIZE; i++) {
551 tmp = code[i];
552 OUT_RING(tmp);
553 j++;
554 }
555
556 if (j & 1)
557 OUT_RING(0);
558
559 ADVANCE_LP_RING();
560 } else
561 printk("rejected packet %x\n", code[0]);
562 }
563
564 static void i830EmitTexBlendVerified(struct drm_device * dev,
565 unsigned int *code, unsigned int num)
566 {
567 drm_i830_private_t *dev_priv = dev->dev_private;
568 int i, j = 0;
569 unsigned int tmp;
570 RING_LOCALS;
571
572 if (!num)
573 return;
574
575 BEGIN_LP_RING(num + 1);
576
577 for (i = 0; i < num; i++) {
578 tmp = code[i];
579 OUT_RING(tmp);
580 j++;
581 }
582
583 if (j & 1)
584 OUT_RING(0);
585
586 ADVANCE_LP_RING();
587 }
588
589 static void i830EmitTexPalette(struct drm_device * dev,
590 unsigned int *palette, int number, int is_shared)
591 {
592 drm_i830_private_t *dev_priv = dev->dev_private;
593 int i;
594 RING_LOCALS;
595
596 return;
597
598 BEGIN_LP_RING(258);
599
600 if (is_shared == 1) {
601 OUT_RING(CMD_OP_MAP_PALETTE_LOAD |
602 MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH);
603 } else {
604 OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number));
605 }
606 for (i = 0; i < 256; i++) {
607 OUT_RING(palette[i]);
608 }
609 OUT_RING(0);
610 /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop!
611 */
612 }
613
614 /* Need to do some additional checking when setting the dest buffer.
615 */
616 static void i830EmitDestVerified(struct drm_device * dev, unsigned int *code)
617 {
618 drm_i830_private_t *dev_priv = dev->dev_private;
619 unsigned int tmp;
620 RING_LOCALS;
621
622 BEGIN_LP_RING(I830_DEST_SETUP_SIZE + 10);
623
624 tmp = code[I830_DESTREG_CBUFADDR];
625 if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
626 if (((int)outring) & 8) {
627 OUT_RING(0);
628 OUT_RING(0);
629 }
630
631 OUT_RING(CMD_OP_DESTBUFFER_INFO);
632 OUT_RING(BUF_3D_ID_COLOR_BACK |
633 BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) |
634 BUF_3D_USE_FENCE);
635 OUT_RING(tmp);
636 OUT_RING(0);
637
638 OUT_RING(CMD_OP_DESTBUFFER_INFO);
639 OUT_RING(BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE |
640 BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp));
641 OUT_RING(dev_priv->zi1);
642 OUT_RING(0);
643 } else {
644 DRM_ERROR("bad di1 %x (allow %x or %x)\n",
645 tmp, dev_priv->front_di1, dev_priv->back_di1);
646 }
647
648 /* invarient:
649 */
650
651 OUT_RING(GFX_OP_DESTBUFFER_VARS);
652 OUT_RING(code[I830_DESTREG_DV1]);
653
654 OUT_RING(GFX_OP_DRAWRECT_INFO);
655 OUT_RING(code[I830_DESTREG_DR1]);
656 OUT_RING(code[I830_DESTREG_DR2]);
657 OUT_RING(code[I830_DESTREG_DR3]);
658 OUT_RING(code[I830_DESTREG_DR4]);
659
660 /* Need to verify this */
661 tmp = code[I830_DESTREG_SENABLE];
662 if ((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) {
663 OUT_RING(tmp);
664 } else {
665 DRM_ERROR("bad scissor enable\n");
666 OUT_RING(0);
667 }
668
669 OUT_RING(GFX_OP_SCISSOR_RECT);
670 OUT_RING(code[I830_DESTREG_SR1]);
671 OUT_RING(code[I830_DESTREG_SR2]);
672 OUT_RING(0);
673
674 ADVANCE_LP_RING();
675 }
676
677 static void i830EmitStippleVerified(struct drm_device * dev, unsigned int *code)
678 {
679 drm_i830_private_t *dev_priv = dev->dev_private;
680 RING_LOCALS;
681
682 BEGIN_LP_RING(2);
683 OUT_RING(GFX_OP_STIPPLE);
684 OUT_RING(code[1]);
685 ADVANCE_LP_RING();
686 }
687
688 static void i830EmitState(struct drm_device * dev)
689 {
690 drm_i830_private_t *dev_priv = dev->dev_private;
691 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
692 unsigned int dirty = sarea_priv->dirty;
693
694 DRM_DEBUG("%s %x\n", __func__, dirty);
695
696 if (dirty & I830_UPLOAD_BUFFERS) {
697 i830EmitDestVerified(dev, sarea_priv->BufferState);
698 sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS;
699 }
700
701 if (dirty & I830_UPLOAD_CTX) {
702 i830EmitContextVerified(dev, sarea_priv->ContextState);
703 sarea_priv->dirty &= ~I830_UPLOAD_CTX;
704 }
705
706 if (dirty & I830_UPLOAD_TEX0) {
707 i830EmitTexVerified(dev, sarea_priv->TexState[0]);
708 sarea_priv->dirty &= ~I830_UPLOAD_TEX0;
709 }
710
711 if (dirty & I830_UPLOAD_TEX1) {
712 i830EmitTexVerified(dev, sarea_priv->TexState[1]);
713 sarea_priv->dirty &= ~I830_UPLOAD_TEX1;
714 }
715
716 if (dirty & I830_UPLOAD_TEXBLEND0) {
717 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[0],
718 sarea_priv->TexBlendStateWordsUsed[0]);
719 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0;
720 }
721
722 if (dirty & I830_UPLOAD_TEXBLEND1) {
723 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[1],
724 sarea_priv->TexBlendStateWordsUsed[1]);
725 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1;
726 }
727
728 if (dirty & I830_UPLOAD_TEX_PALETTE_SHARED) {
729 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 1);
730 } else {
731 if (dirty & I830_UPLOAD_TEX_PALETTE_N(0)) {
732 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 0);
733 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(0);
734 }
735 if (dirty & I830_UPLOAD_TEX_PALETTE_N(1)) {
736 i830EmitTexPalette(dev, sarea_priv->Palette[1], 1, 0);
737 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(1);
738 }
739
740 /* 1.3:
741 */
742 #if 0
743 if (dirty & I830_UPLOAD_TEX_PALETTE_N(2)) {
744 i830EmitTexPalette(dev, sarea_priv->Palette2[0], 0, 0);
745 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
746 }
747 if (dirty & I830_UPLOAD_TEX_PALETTE_N(3)) {
748 i830EmitTexPalette(dev, sarea_priv->Palette2[1], 1, 0);
749 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
750 }
751 #endif
752 }
753
754 /* 1.3:
755 */
756 if (dirty & I830_UPLOAD_STIPPLE) {
757 i830EmitStippleVerified(dev, sarea_priv->StippleState);
758 sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE;
759 }
760
761 if (dirty & I830_UPLOAD_TEX2) {
762 i830EmitTexVerified(dev, sarea_priv->TexState2);
763 sarea_priv->dirty &= ~I830_UPLOAD_TEX2;
764 }
765
766 if (dirty & I830_UPLOAD_TEX3) {
767 i830EmitTexVerified(dev, sarea_priv->TexState3);
768 sarea_priv->dirty &= ~I830_UPLOAD_TEX3;
769 }
770
771 if (dirty & I830_UPLOAD_TEXBLEND2) {
772 i830EmitTexBlendVerified(dev,
773 sarea_priv->TexBlendState2,
774 sarea_priv->TexBlendStateWordsUsed2);
775
776 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2;
777 }
778
779 if (dirty & I830_UPLOAD_TEXBLEND3) {
780 i830EmitTexBlendVerified(dev,
781 sarea_priv->TexBlendState3,
782 sarea_priv->TexBlendStateWordsUsed3);
783 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3;
784 }
785 }
786
787 /* ================================================================
788 * Performance monitoring functions
789 */
790
791 static void i830_fill_box(struct drm_device * dev,
792 int x, int y, int w, int h, int r, int g, int b)
793 {
794 drm_i830_private_t *dev_priv = dev->dev_private;
795 u32 color;
796 unsigned int BR13, CMD;
797 RING_LOCALS;
798
799 BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1 << 24);
800 CMD = XY_COLOR_BLT_CMD;
801 x += dev_priv->sarea_priv->boxes[0].x1;
802 y += dev_priv->sarea_priv->boxes[0].y1;
803
804 if (dev_priv->cpp == 4) {
805 BR13 |= (1 << 25);
806 CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
807 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
808 } else {
809 color = (((r & 0xf8) << 8) |
810 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
811 }
812
813 BEGIN_LP_RING(6);
814 OUT_RING(CMD);
815 OUT_RING(BR13);
816 OUT_RING((y << 16) | x);
817 OUT_RING(((y + h) << 16) | (x + w));
818
819 if (dev_priv->current_page == 1) {
820 OUT_RING(dev_priv->front_offset);
821 } else {
822 OUT_RING(dev_priv->back_offset);
823 }
824
825 OUT_RING(color);
826 ADVANCE_LP_RING();
827 }
828
829 static void i830_cp_performance_boxes(struct drm_device * dev)
830 {
831 drm_i830_private_t *dev_priv = dev->dev_private;
832
833 /* Purple box for page flipping
834 */
835 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP)
836 i830_fill_box(dev, 4, 4, 8, 8, 255, 0, 255);
837
838 /* Red box if we have to wait for idle at any point
839 */
840 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT)
841 i830_fill_box(dev, 16, 4, 8, 8, 255, 0, 0);
842
843 /* Blue box: lost context?
844 */
845 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT)
846 i830_fill_box(dev, 28, 4, 8, 8, 0, 0, 255);
847
848 /* Yellow box for texture swaps
849 */
850 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD)
851 i830_fill_box(dev, 40, 4, 8, 8, 255, 255, 0);
852
853 /* Green box if hardware never idles (as far as we can tell)
854 */
855 if (!(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY))
856 i830_fill_box(dev, 64, 4, 8, 8, 0, 255, 0);
857
858 /* Draw bars indicating number of buffers allocated
859 * (not a great measure, easily confused)
860 */
861 if (dev_priv->dma_used) {
862 int bar = dev_priv->dma_used / 10240;
863 if (bar > 100)
864 bar = 100;
865 if (bar < 1)
866 bar = 1;
867 i830_fill_box(dev, 4, 16, bar, 4, 196, 128, 128);
868 dev_priv->dma_used = 0;
869 }
870
871 dev_priv->sarea_priv->perf_boxes = 0;
872 }
873
874 static void i830_dma_dispatch_clear(struct drm_device * dev, int flags,
875 unsigned int clear_color,
876 unsigned int clear_zval,
877 unsigned int clear_depthmask)
878 {
879 drm_i830_private_t *dev_priv = dev->dev_private;
880 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
881 int nbox = sarea_priv->nbox;
882 struct drm_clip_rect *pbox = sarea_priv->boxes;
883 int pitch = dev_priv->pitch;
884 int cpp = dev_priv->cpp;
885 int i;
886 unsigned int BR13, CMD, D_CMD;
887 RING_LOCALS;
888
889 if (dev_priv->current_page == 1) {
890 unsigned int tmp = flags;
891
892 flags &= ~(I830_FRONT | I830_BACK);
893 if (tmp & I830_FRONT)
894 flags |= I830_BACK;
895 if (tmp & I830_BACK)
896 flags |= I830_FRONT;
897 }
898
899 i830_kernel_lost_context(dev);
900
901 switch (cpp) {
902 case 2:
903 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
904 D_CMD = CMD = XY_COLOR_BLT_CMD;
905 break;
906 case 4:
907 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24) | (1 << 25);
908 CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA |
909 XY_COLOR_BLT_WRITE_RGB);
910 D_CMD = XY_COLOR_BLT_CMD;
911 if (clear_depthmask & 0x00ffffff)
912 D_CMD |= XY_COLOR_BLT_WRITE_RGB;
913 if (clear_depthmask & 0xff000000)
914 D_CMD |= XY_COLOR_BLT_WRITE_ALPHA;
915 break;
916 default:
917 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
918 D_CMD = CMD = XY_COLOR_BLT_CMD;
919 break;
920 }
921
922 if (nbox > I830_NR_SAREA_CLIPRECTS)
923 nbox = I830_NR_SAREA_CLIPRECTS;
924
925 for (i = 0; i < nbox; i++, pbox++) {
926 if (pbox->x1 > pbox->x2 ||
927 pbox->y1 > pbox->y2 ||
928 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
929 continue;
930
931 if (flags & I830_FRONT) {
932 DRM_DEBUG("clear front\n");
933 BEGIN_LP_RING(6);
934 OUT_RING(CMD);
935 OUT_RING(BR13);
936 OUT_RING((pbox->y1 << 16) | pbox->x1);
937 OUT_RING((pbox->y2 << 16) | pbox->x2);
938 OUT_RING(dev_priv->front_offset);
939 OUT_RING(clear_color);
940 ADVANCE_LP_RING();
941 }
942
943 if (flags & I830_BACK) {
944 DRM_DEBUG("clear back\n");
945 BEGIN_LP_RING(6);
946 OUT_RING(CMD);
947 OUT_RING(BR13);
948 OUT_RING((pbox->y1 << 16) | pbox->x1);
949 OUT_RING((pbox->y2 << 16) | pbox->x2);
950 OUT_RING(dev_priv->back_offset);
951 OUT_RING(clear_color);
952 ADVANCE_LP_RING();
953 }
954
955 if (flags & I830_DEPTH) {
956 DRM_DEBUG("clear depth\n");
957 BEGIN_LP_RING(6);
958 OUT_RING(D_CMD);
959 OUT_RING(BR13);
960 OUT_RING((pbox->y1 << 16) | pbox->x1);
961 OUT_RING((pbox->y2 << 16) | pbox->x2);
962 OUT_RING(dev_priv->depth_offset);
963 OUT_RING(clear_zval);
964 ADVANCE_LP_RING();
965 }
966 }
967 }
968
969 static void i830_dma_dispatch_swap(struct drm_device * dev)
970 {
971 drm_i830_private_t *dev_priv = dev->dev_private;
972 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
973 int nbox = sarea_priv->nbox;
974 struct drm_clip_rect *pbox = sarea_priv->boxes;
975 int pitch = dev_priv->pitch;
976 int cpp = dev_priv->cpp;
977 int i;
978 unsigned int CMD, BR13;
979 RING_LOCALS;
980
981 DRM_DEBUG("swapbuffers\n");
982
983 i830_kernel_lost_context(dev);
984
985 if (dev_priv->do_boxes)
986 i830_cp_performance_boxes(dev);
987
988 switch (cpp) {
989 case 2:
990 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
991 CMD = XY_SRC_COPY_BLT_CMD;
992 break;
993 case 4:
994 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25);
995 CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
996 XY_SRC_COPY_BLT_WRITE_RGB);
997 break;
998 default:
999 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
1000 CMD = XY_SRC_COPY_BLT_CMD;
1001 break;
1002 }
1003
1004 if (nbox > I830_NR_SAREA_CLIPRECTS)
1005 nbox = I830_NR_SAREA_CLIPRECTS;
1006
1007 for (i = 0; i < nbox; i++, pbox++) {
1008 if (pbox->x1 > pbox->x2 ||
1009 pbox->y1 > pbox->y2 ||
1010 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
1011 continue;
1012
1013 DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
1014 pbox->x1, pbox->y1, pbox->x2, pbox->y2);
1015
1016 BEGIN_LP_RING(8);
1017 OUT_RING(CMD);
1018 OUT_RING(BR13);
1019 OUT_RING((pbox->y1 << 16) | pbox->x1);
1020 OUT_RING((pbox->y2 << 16) | pbox->x2);
1021
1022 if (dev_priv->current_page == 0)
1023 OUT_RING(dev_priv->front_offset);
1024 else
1025 OUT_RING(dev_priv->back_offset);
1026
1027 OUT_RING((pbox->y1 << 16) | pbox->x1);
1028 OUT_RING(BR13 & 0xffff);
1029
1030 if (dev_priv->current_page == 0)
1031 OUT_RING(dev_priv->back_offset);
1032 else
1033 OUT_RING(dev_priv->front_offset);
1034
1035 ADVANCE_LP_RING();
1036 }
1037 }
1038
1039 static void i830_dma_dispatch_flip(struct drm_device * dev)
1040 {
1041 drm_i830_private_t *dev_priv = dev->dev_private;
1042 RING_LOCALS;
1043
1044 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1045 __func__,
1046 dev_priv->current_page,
1047 dev_priv->sarea_priv->pf_current_page);
1048
1049 i830_kernel_lost_context(dev);
1050
1051 if (dev_priv->do_boxes) {
1052 dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP;
1053 i830_cp_performance_boxes(dev);
1054 }
1055
1056 BEGIN_LP_RING(2);
1057 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1058 OUT_RING(0);
1059 ADVANCE_LP_RING();
1060
1061 BEGIN_LP_RING(6);
1062 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
1063 OUT_RING(0);
1064 if (dev_priv->current_page == 0) {
1065 OUT_RING(dev_priv->back_offset);
1066 dev_priv->current_page = 1;
1067 } else {
1068 OUT_RING(dev_priv->front_offset);
1069 dev_priv->current_page = 0;
1070 }
1071 OUT_RING(0);
1072 ADVANCE_LP_RING();
1073
1074 BEGIN_LP_RING(2);
1075 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
1076 OUT_RING(0);
1077 ADVANCE_LP_RING();
1078
1079 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1080 }
1081
1082 static void i830_dma_dispatch_vertex(struct drm_device * dev,
1083 struct drm_buf * buf, int discard, int used)
1084 {
1085 drm_i830_private_t *dev_priv = dev->dev_private;
1086 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1087 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
1088 struct drm_clip_rect *box = sarea_priv->boxes;
1089 int nbox = sarea_priv->nbox;
1090 unsigned long address = (unsigned long)buf->bus_address;
1091 unsigned long start = address - dev->agp->base;
1092 int i = 0, u;
1093 RING_LOCALS;
1094
1095 i830_kernel_lost_context(dev);
1096
1097 if (nbox > I830_NR_SAREA_CLIPRECTS)
1098 nbox = I830_NR_SAREA_CLIPRECTS;
1099
1100 if (discard) {
1101 u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1102 I830_BUF_HARDWARE);
1103 if (u != I830_BUF_CLIENT) {
1104 DRM_DEBUG("xxxx 2\n");
1105 }
1106 }
1107
1108 if (used > 4 * 1023)
1109 used = 0;
1110
1111 if (sarea_priv->dirty)
1112 i830EmitState(dev);
1113
1114 DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
1115 address, used, nbox);
1116
1117 dev_priv->counter++;
1118 DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
1119 DRM_DEBUG("i830_dma_dispatch\n");
1120 DRM_DEBUG("start : %lx\n", start);
1121 DRM_DEBUG("used : %d\n", used);
1122 DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
1123
1124 if (buf_priv->currently_mapped == I830_BUF_MAPPED) {
1125 u32 *vp = buf_priv->kernel_virtual;
1126
1127 vp[0] = (GFX_OP_PRIMITIVE |
1128 sarea_priv->vertex_prim | ((used / 4) - 2));
1129
1130 if (dev_priv->use_mi_batchbuffer_start) {
1131 vp[used / 4] = MI_BATCH_BUFFER_END;
1132 used += 4;
1133 }
1134
1135 if (used & 4) {
1136 vp[used / 4] = 0;
1137 used += 4;
1138 }
1139
1140 i830_unmap_buffer(buf);
1141 }
1142
1143 if (used) {
1144 do {
1145 if (i < nbox) {
1146 BEGIN_LP_RING(6);
1147 OUT_RING(GFX_OP_DRAWRECT_INFO);
1148 OUT_RING(sarea_priv->
1149 BufferState[I830_DESTREG_DR1]);
1150 OUT_RING(box[i].x1 | (box[i].y1 << 16));
1151 OUT_RING(box[i].x2 | (box[i].y2 << 16));
1152 OUT_RING(sarea_priv->
1153 BufferState[I830_DESTREG_DR4]);
1154 OUT_RING(0);
1155 ADVANCE_LP_RING();
1156 }
1157
1158 if (dev_priv->use_mi_batchbuffer_start) {
1159 BEGIN_LP_RING(2);
1160 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
1161 OUT_RING(start | MI_BATCH_NON_SECURE);
1162 ADVANCE_LP_RING();
1163 } else {
1164 BEGIN_LP_RING(4);
1165 OUT_RING(MI_BATCH_BUFFER);
1166 OUT_RING(start | MI_BATCH_NON_SECURE);
1167 OUT_RING(start + used - 4);
1168 OUT_RING(0);
1169 ADVANCE_LP_RING();
1170 }
1171
1172 } while (++i < nbox);
1173 }
1174
1175 if (discard) {
1176 dev_priv->counter++;
1177
1178 (void)cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1179 I830_BUF_HARDWARE);
1180
1181 BEGIN_LP_RING(8);
1182 OUT_RING(CMD_STORE_DWORD_IDX);
1183 OUT_RING(20);
1184 OUT_RING(dev_priv->counter);
1185 OUT_RING(CMD_STORE_DWORD_IDX);
1186 OUT_RING(buf_priv->my_use_idx);
1187 OUT_RING(I830_BUF_FREE);
1188 OUT_RING(CMD_REPORT_HEAD);
1189 OUT_RING(0);
1190 ADVANCE_LP_RING();
1191 }
1192 }
1193
1194 static void i830_dma_quiescent(struct drm_device * dev)
1195 {
1196 drm_i830_private_t *dev_priv = dev->dev_private;
1197 RING_LOCALS;
1198
1199 i830_kernel_lost_context(dev);
1200
1201 BEGIN_LP_RING(4);
1202 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1203 OUT_RING(CMD_REPORT_HEAD);
1204 OUT_RING(0);
1205 OUT_RING(0);
1206 ADVANCE_LP_RING();
1207
1208 i830_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
1209 }
1210
1211 static int i830_flush_queue(struct drm_device * dev)
1212 {
1213 drm_i830_private_t *dev_priv = dev->dev_private;
1214 struct drm_device_dma *dma = dev->dma;
1215 int i, ret = 0;
1216 RING_LOCALS;
1217
1218 i830_kernel_lost_context(dev);
1219
1220 BEGIN_LP_RING(2);
1221 OUT_RING(CMD_REPORT_HEAD);
1222 OUT_RING(0);
1223 ADVANCE_LP_RING();
1224
1225 i830_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
1226
1227 for (i = 0; i < dma->buf_count; i++) {
1228 struct drm_buf *buf = dma->buflist[i];
1229 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1230
1231 int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE,
1232 I830_BUF_FREE);
1233
1234 if (used == I830_BUF_HARDWARE)
1235 DRM_DEBUG("reclaimed from HARDWARE\n");
1236 if (used == I830_BUF_CLIENT)
1237 DRM_DEBUG("still on client\n");
1238 }
1239
1240 return ret;
1241 }
1242
1243 /* Must be called with the lock held */
1244 static void i830_reclaim_buffers(struct drm_device * dev, struct drm_file *file_priv)
1245 {
1246 struct drm_device_dma *dma = dev->dma;
1247 int i;
1248
1249 if (!dma)
1250 return;
1251 if (!dev->dev_private)
1252 return;
1253 if (!dma->buflist)
1254 return;
1255
1256 i830_flush_queue(dev);
1257
1258 for (i = 0; i < dma->buf_count; i++) {
1259 struct drm_buf *buf = dma->buflist[i];
1260 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1261
1262 if (buf->file_priv == file_priv && buf_priv) {
1263 int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1264 I830_BUF_FREE);
1265
1266 if (used == I830_BUF_CLIENT)
1267 DRM_DEBUG("reclaimed from client\n");
1268 if (buf_priv->currently_mapped == I830_BUF_MAPPED)
1269 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
1270 }
1271 }
1272 }
1273
1274 static int i830_flush_ioctl(struct drm_device *dev, void *data,
1275 struct drm_file *file_priv)
1276 {
1277 LOCK_TEST_WITH_RETURN(dev, file_priv);
1278
1279 i830_flush_queue(dev);
1280 return 0;
1281 }
1282
1283 static int i830_dma_vertex(struct drm_device *dev, void *data,
1284 struct drm_file *file_priv)
1285 {
1286 struct drm_device_dma *dma = dev->dma;
1287 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1288 u32 *hw_status = dev_priv->hw_status_page;
1289 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1290 dev_priv->sarea_priv;
1291 drm_i830_vertex_t *vertex = data;
1292
1293 LOCK_TEST_WITH_RETURN(dev, file_priv);
1294
1295 DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n",
1296 vertex->idx, vertex->used, vertex->discard);
1297
1298 if (vertex->idx < 0 || vertex->idx > dma->buf_count)
1299 return -EINVAL;
1300
1301 i830_dma_dispatch_vertex(dev,
1302 dma->buflist[vertex->idx],
1303 vertex->discard, vertex->used);
1304
1305 sarea_priv->last_enqueue = dev_priv->counter - 1;
1306 sarea_priv->last_dispatch = (int)hw_status[5];
1307
1308 return 0;
1309 }
1310
1311 static int i830_clear_bufs(struct drm_device *dev, void *data,
1312 struct drm_file *file_priv)
1313 {
1314 drm_i830_clear_t *clear = data;
1315
1316 LOCK_TEST_WITH_RETURN(dev, file_priv);
1317
1318 /* GH: Someone's doing nasty things... */
1319 if (!dev->dev_private) {
1320 return -EINVAL;
1321 }
1322
1323 i830_dma_dispatch_clear(dev, clear->flags,
1324 clear->clear_color,
1325 clear->clear_depth, clear->clear_depthmask);
1326 return 0;
1327 }
1328
1329 static int i830_swap_bufs(struct drm_device *dev, void *data,
1330 struct drm_file *file_priv)
1331 {
1332 DRM_DEBUG("i830_swap_bufs\n");
1333
1334 LOCK_TEST_WITH_RETURN(dev, file_priv);
1335
1336 i830_dma_dispatch_swap(dev);
1337 return 0;
1338 }
1339
1340 /* Not sure why this isn't set all the time:
1341 */
1342 static void i830_do_init_pageflip(struct drm_device * dev)
1343 {
1344 drm_i830_private_t *dev_priv = dev->dev_private;
1345
1346 DRM_DEBUG("%s\n", __func__);
1347 dev_priv->page_flipping = 1;
1348 dev_priv->current_page = 0;
1349 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1350 }
1351
1352 static int i830_do_cleanup_pageflip(struct drm_device * dev)
1353 {
1354 drm_i830_private_t *dev_priv = dev->dev_private;
1355
1356 DRM_DEBUG("%s\n", __func__);
1357 if (dev_priv->current_page != 0)
1358 i830_dma_dispatch_flip(dev);
1359
1360 dev_priv->page_flipping = 0;
1361 return 0;
1362 }
1363
1364 static int i830_flip_bufs(struct drm_device *dev, void *data,
1365 struct drm_file *file_priv)
1366 {
1367 drm_i830_private_t *dev_priv = dev->dev_private;
1368
1369 DRM_DEBUG("%s\n", __func__);
1370
1371 LOCK_TEST_WITH_RETURN(dev, file_priv);
1372
1373 if (!dev_priv->page_flipping)
1374 i830_do_init_pageflip(dev);
1375
1376 i830_dma_dispatch_flip(dev);
1377 return 0;
1378 }
1379
1380 static int i830_getage(struct drm_device *dev, void *data,
1381 struct drm_file *file_priv)
1382 {
1383 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1384 u32 *hw_status = dev_priv->hw_status_page;
1385 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1386 dev_priv->sarea_priv;
1387
1388 sarea_priv->last_dispatch = (int)hw_status[5];
1389 return 0;
1390 }
1391
1392 static int i830_getbuf(struct drm_device *dev, void *data,
1393 struct drm_file *file_priv)
1394 {
1395 int retcode = 0;
1396 drm_i830_dma_t *d = data;
1397 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1398 u32 *hw_status = dev_priv->hw_status_page;
1399 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1400 dev_priv->sarea_priv;
1401
1402 DRM_DEBUG("getbuf\n");
1403
1404 LOCK_TEST_WITH_RETURN(dev, file_priv);
1405
1406 d->granted = 0;
1407
1408 retcode = i830_dma_get_buffer(dev, d, file_priv);
1409
1410 DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n",
1411 task_pid_nr(current), retcode, d->granted);
1412
1413 sarea_priv->last_dispatch = (int)hw_status[5];
1414
1415 return retcode;
1416 }
1417
1418 static int i830_copybuf(struct drm_device *dev, void *data,
1419 struct drm_file *file_priv)
1420 {
1421 /* Never copy - 2.4.x doesn't need it */
1422 return 0;
1423 }
1424
1425 static int i830_docopy(struct drm_device *dev, void *data,
1426 struct drm_file *file_priv)
1427 {
1428 return 0;
1429 }
1430
1431 static int i830_getparam(struct drm_device *dev, void *data,
1432 struct drm_file *file_priv)
1433 {
1434 drm_i830_private_t *dev_priv = dev->dev_private;
1435 drm_i830_getparam_t *param = data;
1436 int value;
1437
1438 if (!dev_priv) {
1439 DRM_ERROR("%s called with no initialization\n", __func__);
1440 return -EINVAL;
1441 }
1442
1443 switch (param->param) {
1444 case I830_PARAM_IRQ_ACTIVE:
1445 value = dev->irq_enabled;
1446 break;
1447 default:
1448 return -EINVAL;
1449 }
1450
1451 if (copy_to_user(param->value, &value, sizeof(int))) {
1452 DRM_ERROR("copy_to_user\n");
1453 return -EFAULT;
1454 }
1455
1456 return 0;
1457 }
1458
1459 static int i830_setparam(struct drm_device *dev, void *data,
1460 struct drm_file *file_priv)
1461 {
1462 drm_i830_private_t *dev_priv = dev->dev_private;
1463 drm_i830_setparam_t *param = data;
1464
1465 if (!dev_priv) {
1466 DRM_ERROR("%s called with no initialization\n", __func__);
1467 return -EINVAL;
1468 }
1469
1470 switch (param->param) {
1471 case I830_SETPARAM_USE_MI_BATCHBUFFER_START:
1472 dev_priv->use_mi_batchbuffer_start = param->value;
1473 break;
1474 default:
1475 return -EINVAL;
1476 }
1477
1478 return 0;
1479 }
1480
1481 int i830_driver_load(struct drm_device *dev, unsigned long flags)
1482 {
1483 /* i830 has 4 more counters */
1484 dev->counters += 4;
1485 dev->types[6] = _DRM_STAT_IRQ;
1486 dev->types[7] = _DRM_STAT_PRIMARY;
1487 dev->types[8] = _DRM_STAT_SECONDARY;
1488 dev->types[9] = _DRM_STAT_DMA;
1489
1490 return 0;
1491 }
1492
1493 void i830_driver_lastclose(struct drm_device * dev)
1494 {
1495 i830_dma_cleanup(dev);
1496 }
1497
1498 void i830_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1499 {
1500 if (dev->dev_private) {
1501 drm_i830_private_t *dev_priv = dev->dev_private;
1502 if (dev_priv->page_flipping) {
1503 i830_do_cleanup_pageflip(dev);
1504 }
1505 }
1506 }
1507
1508 void i830_driver_reclaim_buffers_locked(struct drm_device * dev, struct drm_file *file_priv)
1509 {
1510 i830_reclaim_buffers(dev, file_priv);
1511 }
1512
1513 int i830_driver_dma_quiescent(struct drm_device * dev)
1514 {
1515 i830_dma_quiescent(dev);
1516 return 0;
1517 }
1518
1519 struct drm_ioctl_desc i830_ioctls[] = {
1520 DRM_IOCTL_DEF(DRM_I830_INIT, i830_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1521 DRM_IOCTL_DEF(DRM_I830_VERTEX, i830_dma_vertex, DRM_AUTH),
1522 DRM_IOCTL_DEF(DRM_I830_CLEAR, i830_clear_bufs, DRM_AUTH),
1523 DRM_IOCTL_DEF(DRM_I830_FLUSH, i830_flush_ioctl, DRM_AUTH),
1524 DRM_IOCTL_DEF(DRM_I830_GETAGE, i830_getage, DRM_AUTH),
1525 DRM_IOCTL_DEF(DRM_I830_GETBUF, i830_getbuf, DRM_AUTH),
1526 DRM_IOCTL_DEF(DRM_I830_SWAP, i830_swap_bufs, DRM_AUTH),
1527 DRM_IOCTL_DEF(DRM_I830_COPY, i830_copybuf, DRM_AUTH),
1528 DRM_IOCTL_DEF(DRM_I830_DOCOPY, i830_docopy, DRM_AUTH),
1529 DRM_IOCTL_DEF(DRM_I830_FLIP, i830_flip_bufs, DRM_AUTH),
1530 DRM_IOCTL_DEF(DRM_I830_IRQ_EMIT, i830_irq_emit, DRM_AUTH),
1531 DRM_IOCTL_DEF(DRM_I830_IRQ_WAIT, i830_irq_wait, DRM_AUTH),
1532 DRM_IOCTL_DEF(DRM_I830_GETPARAM, i830_getparam, DRM_AUTH),
1533 DRM_IOCTL_DEF(DRM_I830_SETPARAM, i830_setparam, DRM_AUTH)
1534 };
1535
1536 int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls);
1537
1538 /**
1539 * Determine if the device really is AGP or not.
1540 *
1541 * All Intel graphics chipsets are treated as AGP, even if they are really
1542 * PCI-e.
1543 *
1544 * \param dev The device to be tested.
1545 *
1546 * \returns
1547 * A value of 1 is always retured to indictate every i8xx is AGP.
1548 */
1549 int i830_driver_device_is_agp(struct drm_device * dev)
1550 {
1551 return 1;
1552 }
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