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[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / display / icl_dsi.c
1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Madhav Chauhan <madhav.chauhan@intel.com>
25 * Jani Nikula <jani.nikula@intel.com>
26 */
27
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_mipi_dsi.h>
30
31 #include "intel_atomic.h"
32 #include "intel_combo_phy.h"
33 #include "intel_connector.h"
34 #include "intel_ddi.h"
35 #include "intel_dsi.h"
36 #include "intel_panel.h"
37 #include "intel_vdsc.h"
38
39 static int header_credits_available(struct drm_i915_private *dev_priv,
40 enum transcoder dsi_trans)
41 {
42 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
43 >> FREE_HEADER_CREDIT_SHIFT;
44 }
45
46 static int payload_credits_available(struct drm_i915_private *dev_priv,
47 enum transcoder dsi_trans)
48 {
49 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
50 >> FREE_PLOAD_CREDIT_SHIFT;
51 }
52
53 static void wait_for_header_credits(struct drm_i915_private *dev_priv,
54 enum transcoder dsi_trans)
55 {
56 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
57 MAX_HEADER_CREDIT, 100))
58 drm_err(&dev_priv->drm, "DSI header credits not released\n");
59 }
60
61 static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
62 enum transcoder dsi_trans)
63 {
64 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
65 MAX_PLOAD_CREDIT, 100))
66 drm_err(&dev_priv->drm, "DSI payload credits not released\n");
67 }
68
69 static enum transcoder dsi_port_to_transcoder(enum port port)
70 {
71 if (port == PORT_A)
72 return TRANSCODER_DSI_0;
73 else
74 return TRANSCODER_DSI_1;
75 }
76
77 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
78 {
79 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
80 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
81 struct mipi_dsi_device *dsi;
82 enum port port;
83 enum transcoder dsi_trans;
84 int ret;
85
86 /* wait for header/payload credits to be released */
87 for_each_dsi_port(port, intel_dsi->ports) {
88 dsi_trans = dsi_port_to_transcoder(port);
89 wait_for_header_credits(dev_priv, dsi_trans);
90 wait_for_payload_credits(dev_priv, dsi_trans);
91 }
92
93 /* send nop DCS command */
94 for_each_dsi_port(port, intel_dsi->ports) {
95 dsi = intel_dsi->dsi_hosts[port]->device;
96 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
97 dsi->channel = 0;
98 ret = mipi_dsi_dcs_nop(dsi);
99 if (ret < 0)
100 drm_err(&dev_priv->drm,
101 "error sending DCS NOP command\n");
102 }
103
104 /* wait for header credits to be released */
105 for_each_dsi_port(port, intel_dsi->ports) {
106 dsi_trans = dsi_port_to_transcoder(port);
107 wait_for_header_credits(dev_priv, dsi_trans);
108 }
109
110 /* wait for LP TX in progress bit to be cleared */
111 for_each_dsi_port(port, intel_dsi->ports) {
112 dsi_trans = dsi_port_to_transcoder(port);
113 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
114 LPTX_IN_PROGRESS), 20))
115 drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
116 }
117 }
118
119 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
120 u32 len)
121 {
122 struct intel_dsi *intel_dsi = host->intel_dsi;
123 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
124 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
125 int free_credits;
126 int i, j;
127
128 for (i = 0; i < len; i += 4) {
129 u32 tmp = 0;
130
131 free_credits = payload_credits_available(dev_priv, dsi_trans);
132 if (free_credits < 1) {
133 drm_err(&dev_priv->drm,
134 "Payload credit not available\n");
135 return false;
136 }
137
138 for (j = 0; j < min_t(u32, len - i, 4); j++)
139 tmp |= *data++ << 8 * j;
140
141 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp);
142 }
143
144 return true;
145 }
146
147 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
148 struct mipi_dsi_packet pkt, bool enable_lpdt)
149 {
150 struct intel_dsi *intel_dsi = host->intel_dsi;
151 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
152 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
153 u32 tmp;
154 int free_credits;
155
156 /* check if header credit available */
157 free_credits = header_credits_available(dev_priv, dsi_trans);
158 if (free_credits < 1) {
159 drm_err(&dev_priv->drm,
160 "send pkt header failed, not enough hdr credits\n");
161 return -1;
162 }
163
164 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
165
166 if (pkt.payload)
167 tmp |= PAYLOAD_PRESENT;
168 else
169 tmp &= ~PAYLOAD_PRESENT;
170
171 tmp &= ~VBLANK_FENCE;
172
173 if (enable_lpdt)
174 tmp |= LP_DATA_TRANSFER;
175
176 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
177 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
178 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
179 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
180 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
181 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
182
183 return 0;
184 }
185
186 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
187 struct mipi_dsi_packet pkt)
188 {
189 struct intel_dsi *intel_dsi = host->intel_dsi;
190 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
191
192 /* payload queue can accept *256 bytes*, check limit */
193 if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
194 drm_err(&i915->drm, "payload size exceeds max queue limit\n");
195 return -1;
196 }
197
198 /* load data into command payload queue */
199 if (!add_payld_to_queue(host, pkt.payload,
200 pkt.payload_length)) {
201 drm_err(&i915->drm, "adding payload to queue failed\n");
202 return -1;
203 }
204
205 return 0;
206 }
207
208 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
209 {
210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
211 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
212 enum phy phy;
213 u32 tmp;
214 int lane;
215
216 for_each_dsi_phy(phy, intel_dsi->phys) {
217 /*
218 * Program voltage swing and pre-emphasis level values as per
219 * table in BSPEC under DDI buffer programing
220 */
221 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
222 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
223 tmp |= SCALING_MODE_SEL(0x2);
224 tmp |= TAP2_DISABLE | TAP3_DISABLE;
225 tmp |= RTERM_SELECT(0x6);
226 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
227
228 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
229 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
230 tmp |= SCALING_MODE_SEL(0x2);
231 tmp |= TAP2_DISABLE | TAP3_DISABLE;
232 tmp |= RTERM_SELECT(0x6);
233 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
234
235 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
236 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
237 RCOMP_SCALAR_MASK);
238 tmp |= SWING_SEL_UPPER(0x2);
239 tmp |= SWING_SEL_LOWER(0x2);
240 tmp |= RCOMP_SCALAR(0x98);
241 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
242
243 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
244 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
245 RCOMP_SCALAR_MASK);
246 tmp |= SWING_SEL_UPPER(0x2);
247 tmp |= SWING_SEL_LOWER(0x2);
248 tmp |= RCOMP_SCALAR(0x98);
249 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
250
251 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
252 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
253 CURSOR_COEFF_MASK);
254 tmp |= POST_CURSOR_1(0x0);
255 tmp |= POST_CURSOR_2(0x0);
256 tmp |= CURSOR_COEFF(0x3f);
257 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
258
259 for (lane = 0; lane <= 3; lane++) {
260 /* Bspec: must not use GRP register for write */
261 tmp = intel_de_read(dev_priv,
262 ICL_PORT_TX_DW4_LN(lane, phy));
263 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
264 CURSOR_COEFF_MASK);
265 tmp |= POST_CURSOR_1(0x0);
266 tmp |= POST_CURSOR_2(0x0);
267 tmp |= CURSOR_COEFF(0x3f);
268 intel_de_write(dev_priv,
269 ICL_PORT_TX_DW4_LN(lane, phy), tmp);
270 }
271 }
272 }
273
274 static void configure_dual_link_mode(struct intel_encoder *encoder,
275 const struct intel_crtc_state *pipe_config)
276 {
277 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
278 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
279 u32 dss_ctl1;
280
281 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1);
282 dss_ctl1 |= SPLITTER_ENABLE;
283 dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
284 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
285
286 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
287 const struct drm_display_mode *adjusted_mode =
288 &pipe_config->hw.adjusted_mode;
289 u32 dss_ctl2;
290 u16 hactive = adjusted_mode->crtc_hdisplay;
291 u16 dl_buffer_depth;
292
293 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
294 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
295
296 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
297 drm_err(&dev_priv->drm,
298 "DL buffer depth exceed max value\n");
299
300 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
301 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
302 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2);
303 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
304 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
305 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2);
306 } else {
307 /* Interleave */
308 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
309 }
310
311 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1);
312 }
313
314 /* aka DSI 8X clock */
315 static int afe_clk(struct intel_encoder *encoder,
316 const struct intel_crtc_state *crtc_state)
317 {
318 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
319 int bpp;
320
321 if (crtc_state->dsc.compression_enable)
322 bpp = crtc_state->dsc.compressed_bpp;
323 else
324 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
325
326 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
327 }
328
329 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
330 const struct intel_crtc_state *crtc_state)
331 {
332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
333 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
334 enum port port;
335 int afe_clk_khz;
336 u32 esc_clk_div_m;
337
338 afe_clk_khz = afe_clk(encoder, crtc_state);
339 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
340
341 for_each_dsi_port(port, intel_dsi->ports) {
342 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
343 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
344 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
345 }
346
347 for_each_dsi_port(port, intel_dsi->ports) {
348 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
349 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
350 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
351 }
352 }
353
354 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
355 struct intel_dsi *intel_dsi)
356 {
357 enum port port;
358
359 for_each_dsi_port(port, intel_dsi->ports) {
360 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
361 intel_dsi->io_wakeref[port] =
362 intel_display_power_get(dev_priv,
363 port == PORT_A ?
364 POWER_DOMAIN_PORT_DDI_A_IO :
365 POWER_DOMAIN_PORT_DDI_B_IO);
366 }
367 }
368
369 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
370 {
371 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
372 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
373 enum port port;
374 u32 tmp;
375
376 for_each_dsi_port(port, intel_dsi->ports) {
377 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
378 tmp |= COMBO_PHY_MODE_DSI;
379 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
380 }
381
382 get_dsi_io_power_domains(dev_priv, intel_dsi);
383 }
384
385 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
386 {
387 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
388 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
389 enum phy phy;
390
391 for_each_dsi_phy(phy, intel_dsi->phys)
392 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
393 intel_dsi->lane_count, false);
394 }
395
396 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
397 {
398 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
399 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
400 enum phy phy;
401 u32 tmp;
402 int lane;
403
404 /* Step 4b(i) set loadgen select for transmit and aux lanes */
405 for_each_dsi_phy(phy, intel_dsi->phys) {
406 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy));
407 tmp &= ~LOADGEN_SELECT;
408 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp);
409 for (lane = 0; lane <= 3; lane++) {
410 tmp = intel_de_read(dev_priv,
411 ICL_PORT_TX_DW4_LN(lane, phy));
412 tmp &= ~LOADGEN_SELECT;
413 if (lane != 2)
414 tmp |= LOADGEN_SELECT;
415 intel_de_write(dev_priv,
416 ICL_PORT_TX_DW4_LN(lane, phy), tmp);
417 }
418 }
419
420 /* Step 4b(ii) set latency optimization for transmit and aux lanes */
421 for_each_dsi_phy(phy, intel_dsi->phys) {
422 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy));
423 tmp &= ~FRC_LATENCY_OPTIM_MASK;
424 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
425 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
426 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
427 tmp &= ~FRC_LATENCY_OPTIM_MASK;
428 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
429 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
430
431 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
432 if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
433 tmp = intel_de_read(dev_priv,
434 ICL_PORT_PCS_DW1_AUX(phy));
435 tmp &= ~LATENCY_OPTIM_MASK;
436 tmp |= LATENCY_OPTIM_VAL(0);
437 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
438 tmp);
439
440 tmp = intel_de_read(dev_priv,
441 ICL_PORT_PCS_DW1_LN0(phy));
442 tmp &= ~LATENCY_OPTIM_MASK;
443 tmp |= LATENCY_OPTIM_VAL(0x1);
444 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
445 tmp);
446 }
447 }
448
449 }
450
451 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
452 {
453 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
454 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
455 u32 tmp;
456 enum phy phy;
457
458 /* clear common keeper enable bit */
459 for_each_dsi_phy(phy, intel_dsi->phys) {
460 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
461 tmp &= ~COMMON_KEEPER_EN;
462 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
463 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
464 tmp &= ~COMMON_KEEPER_EN;
465 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp);
466 }
467
468 /*
469 * Set SUS Clock Config bitfield to 11b
470 * Note: loadgen select program is done
471 * as part of lane phy sequence configuration
472 */
473 for_each_dsi_phy(phy, intel_dsi->phys) {
474 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
475 tmp |= SUS_CLOCK_CONFIG;
476 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp);
477 }
478
479 /* Clear training enable to change swing values */
480 for_each_dsi_phy(phy, intel_dsi->phys) {
481 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
482 tmp &= ~TX_TRAINING_EN;
483 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
484 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
485 tmp &= ~TX_TRAINING_EN;
486 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
487 }
488
489 /* Program swing and de-emphasis */
490 dsi_program_swing_and_deemphasis(encoder);
491
492 /* Set training enable to trigger update */
493 for_each_dsi_phy(phy, intel_dsi->phys) {
494 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
495 tmp |= TX_TRAINING_EN;
496 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
497 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
498 tmp |= TX_TRAINING_EN;
499 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
500 }
501 }
502
503 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
504 {
505 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
506 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
507 u32 tmp;
508 enum port port;
509
510 for_each_dsi_port(port, intel_dsi->ports) {
511 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
512 tmp |= DDI_BUF_CTL_ENABLE;
513 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
514
515 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
516 DDI_BUF_IS_IDLE),
517 500))
518 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
519 port_name(port));
520 }
521 }
522
523 static void
524 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
525 const struct intel_crtc_state *crtc_state)
526 {
527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
528 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
529 u32 tmp;
530 enum port port;
531 enum phy phy;
532
533 /* Program T-INIT master registers */
534 for_each_dsi_port(port, intel_dsi->ports) {
535 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port));
536 tmp &= ~MASTER_INIT_TIMER_MASK;
537 tmp |= intel_dsi->init_count;
538 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp);
539 }
540
541 /* Program DPHY clock lanes timings */
542 for_each_dsi_port(port, intel_dsi->ports) {
543 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
544 intel_dsi->dphy_reg);
545
546 /* shadow register inside display core */
547 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
548 intel_dsi->dphy_reg);
549 }
550
551 /* Program DPHY data lanes timings */
552 for_each_dsi_port(port, intel_dsi->ports) {
553 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
554 intel_dsi->dphy_data_lane_reg);
555
556 /* shadow register inside display core */
557 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
558 intel_dsi->dphy_data_lane_reg);
559 }
560
561 /*
562 * If DSI link operating at or below an 800 MHz,
563 * TA_SURE should be override and programmed to
564 * a value '0' inside TA_PARAM_REGISTERS otherwise
565 * leave all fields at HW default values.
566 */
567 if (IS_GEN(dev_priv, 11)) {
568 if (afe_clk(encoder, crtc_state) <= 800000) {
569 for_each_dsi_port(port, intel_dsi->ports) {
570 tmp = intel_de_read(dev_priv,
571 DPHY_TA_TIMING_PARAM(port));
572 tmp &= ~TA_SURE_MASK;
573 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
574 intel_de_write(dev_priv,
575 DPHY_TA_TIMING_PARAM(port),
576 tmp);
577
578 /* shadow register inside display core */
579 tmp = intel_de_read(dev_priv,
580 DSI_TA_TIMING_PARAM(port));
581 tmp &= ~TA_SURE_MASK;
582 tmp |= TA_SURE_OVERRIDE | TA_SURE(0);
583 intel_de_write(dev_priv,
584 DSI_TA_TIMING_PARAM(port), tmp);
585 }
586 }
587 }
588
589 if (IS_ELKHARTLAKE(dev_priv)) {
590 for_each_dsi_phy(phy, intel_dsi->phys) {
591 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
592 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
593 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp);
594 }
595 }
596 }
597
598 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
599 {
600 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
601 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
602 u32 tmp;
603 enum phy phy;
604
605 mutex_lock(&dev_priv->dpll.lock);
606 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
607 for_each_dsi_phy(phy, intel_dsi->phys)
608 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
609
610 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
611 mutex_unlock(&dev_priv->dpll.lock);
612 }
613
614 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
615 {
616 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
617 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
618 u32 tmp;
619 enum phy phy;
620
621 mutex_lock(&dev_priv->dpll.lock);
622 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
623 for_each_dsi_phy(phy, intel_dsi->phys)
624 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
625
626 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
627 mutex_unlock(&dev_priv->dpll.lock);
628 }
629
630 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
631 const struct intel_crtc_state *crtc_state)
632 {
633 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
634 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
635 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
636 enum phy phy;
637 u32 val;
638
639 mutex_lock(&dev_priv->dpll.lock);
640
641 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
642 for_each_dsi_phy(phy, intel_dsi->phys) {
643 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
644 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
645 }
646 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
647
648 for_each_dsi_phy(phy, intel_dsi->phys) {
649 if (INTEL_GEN(dev_priv) >= 12)
650 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
651 else
652 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
653 }
654 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
655
656 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
657
658 mutex_unlock(&dev_priv->dpll.lock);
659 }
660
661 static void
662 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
663 const struct intel_crtc_state *pipe_config)
664 {
665 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
666 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
667 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
668 enum pipe pipe = intel_crtc->pipe;
669 u32 tmp;
670 enum port port;
671 enum transcoder dsi_trans;
672
673 for_each_dsi_port(port, intel_dsi->ports) {
674 dsi_trans = dsi_port_to_transcoder(port);
675 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
676
677 if (intel_dsi->eotp_pkt)
678 tmp &= ~EOTP_DISABLED;
679 else
680 tmp |= EOTP_DISABLED;
681
682 /* enable link calibration if freq > 1.5Gbps */
683 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
684 tmp &= ~LINK_CALIBRATION_MASK;
685 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
686 }
687
688 /* configure continuous clock */
689 tmp &= ~CONTINUOUS_CLK_MASK;
690 if (intel_dsi->clock_stop)
691 tmp |= CLK_ENTER_LP_AFTER_DATA;
692 else
693 tmp |= CLK_HS_CONTINUOUS;
694
695 /* configure buffer threshold limit to minimum */
696 tmp &= ~PIX_BUF_THRESHOLD_MASK;
697 tmp |= PIX_BUF_THRESHOLD_1_4;
698
699 /* set virtual channel to '0' */
700 tmp &= ~PIX_VIRT_CHAN_MASK;
701 tmp |= PIX_VIRT_CHAN(0);
702
703 /* program BGR transmission */
704 if (intel_dsi->bgr_enabled)
705 tmp |= BGR_TRANSMISSION;
706
707 /* select pixel format */
708 tmp &= ~PIX_FMT_MASK;
709 if (pipe_config->dsc.compression_enable) {
710 tmp |= PIX_FMT_COMPRESSED;
711 } else {
712 switch (intel_dsi->pixel_format) {
713 default:
714 MISSING_CASE(intel_dsi->pixel_format);
715 fallthrough;
716 case MIPI_DSI_FMT_RGB565:
717 tmp |= PIX_FMT_RGB565;
718 break;
719 case MIPI_DSI_FMT_RGB666_PACKED:
720 tmp |= PIX_FMT_RGB666_PACKED;
721 break;
722 case MIPI_DSI_FMT_RGB666:
723 tmp |= PIX_FMT_RGB666_LOOSE;
724 break;
725 case MIPI_DSI_FMT_RGB888:
726 tmp |= PIX_FMT_RGB888;
727 break;
728 }
729 }
730
731 if (INTEL_GEN(dev_priv) >= 12) {
732 if (is_vid_mode(intel_dsi))
733 tmp |= BLANKING_PACKET_ENABLE;
734 }
735
736 /* program DSI operation mode */
737 if (is_vid_mode(intel_dsi)) {
738 tmp &= ~OP_MODE_MASK;
739 switch (intel_dsi->video_mode_format) {
740 default:
741 MISSING_CASE(intel_dsi->video_mode_format);
742 fallthrough;
743 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
744 tmp |= VIDEO_MODE_SYNC_EVENT;
745 break;
746 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
747 tmp |= VIDEO_MODE_SYNC_PULSE;
748 break;
749 }
750 } else {
751 /*
752 * FIXME: Retrieve this info from VBT.
753 * As per the spec when dsi transcoder is operating
754 * in TE GATE mode, TE comes from GPIO
755 * which is UTIL PIN for DSI 0.
756 * Also this GPIO would not be used for other
757 * purposes is an assumption.
758 */
759 tmp &= ~OP_MODE_MASK;
760 tmp |= CMD_MODE_TE_GATE;
761 tmp |= TE_SOURCE_GPIO;
762 }
763
764 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
765 }
766
767 /* enable port sync mode if dual link */
768 if (intel_dsi->dual_link) {
769 for_each_dsi_port(port, intel_dsi->ports) {
770 dsi_trans = dsi_port_to_transcoder(port);
771 tmp = intel_de_read(dev_priv,
772 TRANS_DDI_FUNC_CTL2(dsi_trans));
773 tmp |= PORT_SYNC_MODE_ENABLE;
774 intel_de_write(dev_priv,
775 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
776 }
777
778 /* configure stream splitting */
779 configure_dual_link_mode(encoder, pipe_config);
780 }
781
782 for_each_dsi_port(port, intel_dsi->ports) {
783 dsi_trans = dsi_port_to_transcoder(port);
784
785 /* select data lane width */
786 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
787 tmp &= ~DDI_PORT_WIDTH_MASK;
788 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
789
790 /* select input pipe */
791 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
792 switch (pipe) {
793 default:
794 MISSING_CASE(pipe);
795 fallthrough;
796 case PIPE_A:
797 tmp |= TRANS_DDI_EDP_INPUT_A_ON;
798 break;
799 case PIPE_B:
800 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
801 break;
802 case PIPE_C:
803 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
804 break;
805 case PIPE_D:
806 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
807 break;
808 }
809
810 /* enable DDI buffer */
811 tmp |= TRANS_DDI_FUNC_ENABLE;
812 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
813 }
814
815 /* wait for link ready */
816 for_each_dsi_port(port, intel_dsi->ports) {
817 dsi_trans = dsi_port_to_transcoder(port);
818 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
819 LINK_READY), 2500))
820 drm_err(&dev_priv->drm, "DSI link not ready\n");
821 }
822 }
823
824 static void
825 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
826 const struct intel_crtc_state *crtc_state)
827 {
828 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
829 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
830 const struct drm_display_mode *adjusted_mode =
831 &crtc_state->hw.adjusted_mode;
832 enum port port;
833 enum transcoder dsi_trans;
834 /* horizontal timings */
835 u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
836 u16 hback_porch;
837 /* vertical timings */
838 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
839 int mul = 1, div = 1;
840
841 /*
842 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
843 * for slower link speed if DSC is enabled.
844 *
845 * The compression frequency ratio is the ratio between compressed and
846 * non-compressed link speeds, and simplifies down to the ratio between
847 * compressed and non-compressed bpp.
848 */
849 if (crtc_state->dsc.compression_enable) {
850 mul = crtc_state->dsc.compressed_bpp;
851 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
852 }
853
854 hactive = adjusted_mode->crtc_hdisplay;
855
856 if (is_vid_mode(intel_dsi))
857 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
858 else
859 htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
860
861 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
862 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
863 hsync_size = hsync_end - hsync_start;
864 hback_porch = (adjusted_mode->crtc_htotal -
865 adjusted_mode->crtc_hsync_end);
866 vactive = adjusted_mode->crtc_vdisplay;
867
868 if (is_vid_mode(intel_dsi)) {
869 vtotal = adjusted_mode->crtc_vtotal;
870 } else {
871 int bpp, line_time_us, byte_clk_period_ns;
872
873 if (crtc_state->dsc.compression_enable)
874 bpp = crtc_state->dsc.compressed_bpp;
875 else
876 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
877
878 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
879 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
880 vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
881 }
882 vsync_start = adjusted_mode->crtc_vsync_start;
883 vsync_end = adjusted_mode->crtc_vsync_end;
884 vsync_shift = hsync_start - htotal / 2;
885
886 if (intel_dsi->dual_link) {
887 hactive /= 2;
888 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
889 hactive += intel_dsi->pixel_overlap;
890 htotal /= 2;
891 }
892
893 /* minimum hactive as per bspec: 256 pixels */
894 if (adjusted_mode->crtc_hdisplay < 256)
895 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
896
897 /* if RGB666 format, then hactive must be multiple of 4 pixels */
898 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
899 drm_err(&dev_priv->drm,
900 "hactive pixels are not multiple of 4\n");
901
902 /* program TRANS_HTOTAL register */
903 for_each_dsi_port(port, intel_dsi->ports) {
904 dsi_trans = dsi_port_to_transcoder(port);
905 intel_de_write(dev_priv, HTOTAL(dsi_trans),
906 (hactive - 1) | ((htotal - 1) << 16));
907 }
908
909 /* TRANS_HSYNC register to be programmed only for video mode */
910 if (is_vid_mode(intel_dsi)) {
911 if (intel_dsi->video_mode_format ==
912 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
913 /* BSPEC: hsync size should be atleast 16 pixels */
914 if (hsync_size < 16)
915 drm_err(&dev_priv->drm,
916 "hsync size < 16 pixels\n");
917 }
918
919 if (hback_porch < 16)
920 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
921
922 if (intel_dsi->dual_link) {
923 hsync_start /= 2;
924 hsync_end /= 2;
925 }
926
927 for_each_dsi_port(port, intel_dsi->ports) {
928 dsi_trans = dsi_port_to_transcoder(port);
929 intel_de_write(dev_priv, HSYNC(dsi_trans),
930 (hsync_start - 1) | ((hsync_end - 1) << 16));
931 }
932 }
933
934 /* program TRANS_VTOTAL register */
935 for_each_dsi_port(port, intel_dsi->ports) {
936 dsi_trans = dsi_port_to_transcoder(port);
937 /*
938 * FIXME: Programing this by assuming progressive mode, since
939 * non-interlaced info from VBT is not saved inside
940 * struct drm_display_mode.
941 * For interlace mode: program required pixel minus 2
942 */
943 intel_de_write(dev_priv, VTOTAL(dsi_trans),
944 (vactive - 1) | ((vtotal - 1) << 16));
945 }
946
947 if (vsync_end < vsync_start || vsync_end > vtotal)
948 drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
949
950 if (vsync_start < vactive)
951 drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
952
953 /* program TRANS_VSYNC register for video mode only */
954 if (is_vid_mode(intel_dsi)) {
955 for_each_dsi_port(port, intel_dsi->ports) {
956 dsi_trans = dsi_port_to_transcoder(port);
957 intel_de_write(dev_priv, VSYNC(dsi_trans),
958 (vsync_start - 1) | ((vsync_end - 1) << 16));
959 }
960 }
961
962 /*
963 * FIXME: It has to be programmed only for video modes and interlaced
964 * modes. Put the check condition here once interlaced
965 * info available as described above.
966 * program TRANS_VSYNCSHIFT register
967 */
968 if (is_vid_mode(intel_dsi)) {
969 for_each_dsi_port(port, intel_dsi->ports) {
970 dsi_trans = dsi_port_to_transcoder(port);
971 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans),
972 vsync_shift);
973 }
974 }
975
976 /* program TRANS_VBLANK register, should be same as vtotal programmed */
977 if (INTEL_GEN(dev_priv) >= 12) {
978 for_each_dsi_port(port, intel_dsi->ports) {
979 dsi_trans = dsi_port_to_transcoder(port);
980 intel_de_write(dev_priv, VBLANK(dsi_trans),
981 (vactive - 1) | ((vtotal - 1) << 16));
982 }
983 }
984 }
985
986 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
987 {
988 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
989 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
990 enum port port;
991 enum transcoder dsi_trans;
992 u32 tmp;
993
994 for_each_dsi_port(port, intel_dsi->ports) {
995 dsi_trans = dsi_port_to_transcoder(port);
996 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
997 tmp |= PIPECONF_ENABLE;
998 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
999
1000 /* wait for transcoder to be enabled */
1001 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
1002 I965_PIPECONF_ACTIVE, 10))
1003 drm_err(&dev_priv->drm,
1004 "DSI transcoder not enabled\n");
1005 }
1006 }
1007
1008 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1009 const struct intel_crtc_state *crtc_state)
1010 {
1011 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1012 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1013 enum port port;
1014 enum transcoder dsi_trans;
1015 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1016
1017 /*
1018 * escape clock count calculation:
1019 * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1020 * UI (nsec) = (10^6)/Bitrate
1021 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1022 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
1023 */
1024 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1025 mul = 8 * 1000000;
1026 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1027 divisor);
1028 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1029 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1030
1031 for_each_dsi_port(port, intel_dsi->ports) {
1032 dsi_trans = dsi_port_to_transcoder(port);
1033
1034 /* program hst_tx_timeout */
1035 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans));
1036 tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
1037 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
1038 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp);
1039
1040 /* FIXME: DSI_CALIB_TO */
1041
1042 /* program lp_rx_host timeout */
1043 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans));
1044 tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
1045 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
1046 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp);
1047
1048 /* FIXME: DSI_PWAIT_TO */
1049
1050 /* program turn around timeout */
1051 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans));
1052 tmp &= ~TA_TIMEOUT_VALUE_MASK;
1053 tmp |= TA_TIMEOUT_VALUE(ta_timeout);
1054 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp);
1055 }
1056 }
1057
1058 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1059 bool enable)
1060 {
1061 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1062 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1063 u32 tmp;
1064
1065 /*
1066 * used as TE i/p for DSI0,
1067 * for dual link/DSI1 TE is from slave DSI1
1068 * through GPIO.
1069 */
1070 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1071 return;
1072
1073 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1074
1075 if (enable) {
1076 tmp |= UTIL_PIN_DIRECTION_INPUT;
1077 tmp |= UTIL_PIN_ENABLE;
1078 } else {
1079 tmp &= ~UTIL_PIN_ENABLE;
1080 }
1081 intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
1082 }
1083
1084 static void
1085 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1086 const struct intel_crtc_state *crtc_state)
1087 {
1088 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1089
1090 /* step 4a: power up all lanes of the DDI used by DSI */
1091 gen11_dsi_power_up_lanes(encoder);
1092
1093 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1094 gen11_dsi_config_phy_lanes_sequence(encoder);
1095
1096 /* step 4c: configure voltage swing and skew */
1097 gen11_dsi_voltage_swing_program_seq(encoder);
1098
1099 /* enable DDI buffer */
1100 gen11_dsi_enable_ddi_buffer(encoder);
1101
1102 /* setup D-PHY timings */
1103 gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1104
1105 /* Since transcoder is configured to take events from GPIO */
1106 gen11_dsi_config_util_pin(encoder, true);
1107
1108 /* step 4h: setup DSI protocol timeouts */
1109 gen11_dsi_setup_timeouts(encoder, crtc_state);
1110
1111 /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1112 gen11_dsi_configure_transcoder(encoder, crtc_state);
1113
1114 /* Step 4l: Gate DDI clocks */
1115 if (IS_GEN(dev_priv, 11))
1116 gen11_dsi_gate_clocks(encoder);
1117 }
1118
1119 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1120 {
1121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1122 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1123 struct mipi_dsi_device *dsi;
1124 enum port port;
1125 enum transcoder dsi_trans;
1126 u32 tmp;
1127 int ret;
1128
1129 /* set maximum return packet size */
1130 for_each_dsi_port(port, intel_dsi->ports) {
1131 dsi_trans = dsi_port_to_transcoder(port);
1132
1133 /*
1134 * FIXME: This uses the number of DW's currently in the payload
1135 * receive queue. This is probably not what we want here.
1136 */
1137 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1138 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1139 /* multiply "Number Rx Payload DW" by 4 to get max value */
1140 tmp = tmp * 4;
1141 dsi = intel_dsi->dsi_hosts[port]->device;
1142 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1143 if (ret < 0)
1144 drm_err(&dev_priv->drm,
1145 "error setting max return pkt size%d\n", tmp);
1146 }
1147
1148 /* panel power on related mipi dsi vbt sequences */
1149 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1150 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
1151 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1152 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1153 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1154
1155 /* ensure all panel commands dispatched before enabling transcoder */
1156 wait_for_cmds_dispatched_to_panel(encoder);
1157 }
1158
1159 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1160 struct intel_encoder *encoder,
1161 const struct intel_crtc_state *crtc_state,
1162 const struct drm_connector_state *conn_state)
1163 {
1164 /* step2: enable IO power */
1165 gen11_dsi_enable_io_power(encoder);
1166
1167 /* step3: enable DSI PLL */
1168 gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1169 }
1170
1171 static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1172 struct intel_encoder *encoder,
1173 const struct intel_crtc_state *pipe_config,
1174 const struct drm_connector_state *conn_state)
1175 {
1176 /* step3b */
1177 gen11_dsi_map_pll(encoder, pipe_config);
1178
1179 /* step4: enable DSI port and DPHY */
1180 gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1181
1182 /* step5: program and powerup panel */
1183 gen11_dsi_powerup_panel(encoder);
1184
1185 intel_dsc_enable(encoder, pipe_config);
1186
1187 /* step6c: configure transcoder timings */
1188 gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1189 }
1190
1191 static void gen11_dsi_enable(struct intel_atomic_state *state,
1192 struct intel_encoder *encoder,
1193 const struct intel_crtc_state *crtc_state,
1194 const struct drm_connector_state *conn_state)
1195 {
1196 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1197
1198 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
1199
1200 /* step6d: enable dsi transcoder */
1201 gen11_dsi_enable_transcoder(encoder);
1202
1203 /* step7: enable backlight */
1204 intel_panel_enable_backlight(crtc_state, conn_state);
1205 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1206
1207 intel_crtc_vblank_on(crtc_state);
1208 }
1209
1210 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1211 {
1212 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1213 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1214 enum port port;
1215 enum transcoder dsi_trans;
1216 u32 tmp;
1217
1218 for_each_dsi_port(port, intel_dsi->ports) {
1219 dsi_trans = dsi_port_to_transcoder(port);
1220
1221 /* disable transcoder */
1222 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1223 tmp &= ~PIPECONF_ENABLE;
1224 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp);
1225
1226 /* wait for transcoder to be disabled */
1227 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
1228 I965_PIPECONF_ACTIVE, 50))
1229 drm_err(&dev_priv->drm,
1230 "DSI trancoder not disabled\n");
1231 }
1232 }
1233
1234 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1235 {
1236 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1237
1238 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1239 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1240 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1241
1242 /* ensure cmds dispatched to panel */
1243 wait_for_cmds_dispatched_to_panel(encoder);
1244 }
1245
1246 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1247 {
1248 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1249 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1250 enum port port;
1251 enum transcoder dsi_trans;
1252 u32 tmp;
1253
1254 /* disable periodic update mode */
1255 if (is_cmd_mode(intel_dsi)) {
1256 for_each_dsi_port(port, intel_dsi->ports) {
1257 tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
1258 tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
1259 intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
1260 }
1261 }
1262
1263 /* put dsi link in ULPS */
1264 for_each_dsi_port(port, intel_dsi->ports) {
1265 dsi_trans = dsi_port_to_transcoder(port);
1266 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1267 tmp |= LINK_ENTER_ULPS;
1268 tmp &= ~LINK_ULPS_TYPE_LP11;
1269 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
1270
1271 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1272 LINK_IN_ULPS),
1273 10))
1274 drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
1275 }
1276
1277 /* disable ddi function */
1278 for_each_dsi_port(port, intel_dsi->ports) {
1279 dsi_trans = dsi_port_to_transcoder(port);
1280 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1281 tmp &= ~TRANS_DDI_FUNC_ENABLE;
1282 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
1283 }
1284
1285 /* disable port sync mode if dual link */
1286 if (intel_dsi->dual_link) {
1287 for_each_dsi_port(port, intel_dsi->ports) {
1288 dsi_trans = dsi_port_to_transcoder(port);
1289 tmp = intel_de_read(dev_priv,
1290 TRANS_DDI_FUNC_CTL2(dsi_trans));
1291 tmp &= ~PORT_SYNC_MODE_ENABLE;
1292 intel_de_write(dev_priv,
1293 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
1294 }
1295 }
1296 }
1297
1298 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1299 {
1300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1301 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1302 u32 tmp;
1303 enum port port;
1304
1305 gen11_dsi_ungate_clocks(encoder);
1306 for_each_dsi_port(port, intel_dsi->ports) {
1307 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1308 tmp &= ~DDI_BUF_CTL_ENABLE;
1309 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp);
1310
1311 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1312 DDI_BUF_IS_IDLE),
1313 8))
1314 drm_err(&dev_priv->drm,
1315 "DDI port:%c buffer not idle\n",
1316 port_name(port));
1317 }
1318 gen11_dsi_gate_clocks(encoder);
1319 }
1320
1321 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1322 {
1323 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1324 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1325 enum port port;
1326 u32 tmp;
1327
1328 for_each_dsi_port(port, intel_dsi->ports) {
1329 intel_wakeref_t wakeref;
1330
1331 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1332 intel_display_power_put(dev_priv,
1333 port == PORT_A ?
1334 POWER_DOMAIN_PORT_DDI_A_IO :
1335 POWER_DOMAIN_PORT_DDI_B_IO,
1336 wakeref);
1337 }
1338
1339 /* set mode to DDI */
1340 for_each_dsi_port(port, intel_dsi->ports) {
1341 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port));
1342 tmp &= ~COMBO_PHY_MODE_DSI;
1343 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp);
1344 }
1345 }
1346
1347 static void gen11_dsi_disable(struct intel_atomic_state *state,
1348 struct intel_encoder *encoder,
1349 const struct intel_crtc_state *old_crtc_state,
1350 const struct drm_connector_state *old_conn_state)
1351 {
1352 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1353
1354 /* step1: turn off backlight */
1355 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1356 intel_panel_disable_backlight(old_conn_state);
1357
1358 /* step2d,e: disable transcoder and wait */
1359 gen11_dsi_disable_transcoder(encoder);
1360
1361 /* step2f,g: powerdown panel */
1362 gen11_dsi_powerdown_panel(encoder);
1363
1364 /* step2h,i,j: deconfig trancoder */
1365 gen11_dsi_deconfigure_trancoder(encoder);
1366
1367 /* step3: disable port */
1368 gen11_dsi_disable_port(encoder);
1369
1370 gen11_dsi_config_util_pin(encoder, false);
1371
1372 /* step4: disable IO power */
1373 gen11_dsi_disable_io_power(encoder);
1374 }
1375
1376 static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1377 struct intel_encoder *encoder,
1378 const struct intel_crtc_state *old_crtc_state,
1379 const struct drm_connector_state *old_conn_state)
1380 {
1381 intel_crtc_vblank_off(old_crtc_state);
1382
1383 intel_dsc_disable(old_crtc_state);
1384
1385 skl_scaler_disable(old_crtc_state);
1386 }
1387
1388 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1389 struct drm_display_mode *mode)
1390 {
1391 /* FIXME: DSC? */
1392 return intel_dsi_mode_valid(connector, mode);
1393 }
1394
1395 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1396 struct intel_crtc_state *pipe_config)
1397 {
1398 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1399 struct drm_display_mode *adjusted_mode =
1400 &pipe_config->hw.adjusted_mode;
1401
1402 if (pipe_config->dsc.compressed_bpp) {
1403 int div = pipe_config->dsc.compressed_bpp;
1404 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1405
1406 adjusted_mode->crtc_htotal =
1407 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1408 adjusted_mode->crtc_hsync_start =
1409 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1410 adjusted_mode->crtc_hsync_end =
1411 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1412 }
1413
1414 if (intel_dsi->dual_link) {
1415 adjusted_mode->crtc_hdisplay *= 2;
1416 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1417 adjusted_mode->crtc_hdisplay -=
1418 intel_dsi->pixel_overlap;
1419 adjusted_mode->crtc_htotal *= 2;
1420 }
1421 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1422 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1423
1424 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1425 if (intel_dsi->dual_link) {
1426 adjusted_mode->crtc_hsync_start *= 2;
1427 adjusted_mode->crtc_hsync_end *= 2;
1428 }
1429 }
1430 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1431 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1432 }
1433
1434 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1435 {
1436 struct drm_device *dev = intel_dsi->base.base.dev;
1437 struct drm_i915_private *dev_priv = to_i915(dev);
1438 enum transcoder dsi_trans;
1439 u32 val;
1440
1441 if (intel_dsi->ports == BIT(PORT_B))
1442 dsi_trans = TRANSCODER_DSI_1;
1443 else
1444 dsi_trans = TRANSCODER_DSI_0;
1445
1446 val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1447 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1448 }
1449
1450 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1451 struct intel_crtc_state *pipe_config)
1452 {
1453 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1454 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1455 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1456
1457 intel_dsc_get_config(encoder, pipe_config);
1458
1459 /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
1460 pipe_config->port_clock = intel_dpll_get_freq(i915,
1461 pipe_config->shared_dpll);
1462
1463 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1464 if (intel_dsi->dual_link)
1465 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1466
1467 gen11_dsi_get_timings(encoder, pipe_config);
1468 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1469 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1470
1471 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1472 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1473 }
1474
1475 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1476 struct intel_crtc_state *crtc_state)
1477 {
1478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1479 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1480 int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
1481 bool use_dsc;
1482 int ret;
1483
1484 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1485 if (!use_dsc)
1486 return 0;
1487
1488 if (crtc_state->pipe_bpp < 8 * 3)
1489 return -EINVAL;
1490
1491 /* FIXME: split only when necessary */
1492 if (crtc_state->dsc.slice_count > 1)
1493 crtc_state->dsc.dsc_split = true;
1494
1495 vdsc_cfg->convert_rgb = true;
1496
1497 ret = intel_dsc_compute_params(encoder, crtc_state);
1498 if (ret)
1499 return ret;
1500
1501 /* DSI specific sanity checks on the common code */
1502 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
1503 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
1504 drm_WARN_ON(&dev_priv->drm,
1505 vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1506 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
1507 drm_WARN_ON(&dev_priv->drm,
1508 vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1509
1510 ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1511 if (ret)
1512 return ret;
1513
1514 crtc_state->dsc.compression_enable = true;
1515
1516 return 0;
1517 }
1518
1519 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1520 struct intel_crtc_state *pipe_config,
1521 struct drm_connector_state *conn_state)
1522 {
1523 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1524 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1525 base);
1526 struct intel_connector *intel_connector = intel_dsi->attached_connector;
1527 const struct drm_display_mode *fixed_mode =
1528 intel_connector->panel.fixed_mode;
1529 struct drm_display_mode *adjusted_mode =
1530 &pipe_config->hw.adjusted_mode;
1531 int ret;
1532
1533 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1534 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
1535
1536 ret = intel_pch_panel_fitting(pipe_config, conn_state);
1537 if (ret)
1538 return ret;
1539
1540 adjusted_mode->flags = 0;
1541
1542 /* Dual link goes to trancoder DSI'0' */
1543 if (intel_dsi->ports == BIT(PORT_B))
1544 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1545 else
1546 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1547
1548 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1549 pipe_config->pipe_bpp = 24;
1550 else
1551 pipe_config->pipe_bpp = 18;
1552
1553 pipe_config->clock_set = true;
1554
1555 if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1556 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
1557
1558 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1559
1560 /*
1561 * In case of TE GATE cmd mode, we
1562 * receive TE from the slave if
1563 * dual link is enabled
1564 */
1565 if (is_cmd_mode(intel_dsi)) {
1566 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1567 pipe_config->mode_flags |=
1568 I915_MODE_FLAG_DSI_USE_TE1 |
1569 I915_MODE_FLAG_DSI_USE_TE0;
1570 else if (intel_dsi->ports == BIT(PORT_B))
1571 pipe_config->mode_flags |=
1572 I915_MODE_FLAG_DSI_USE_TE1;
1573 else
1574 pipe_config->mode_flags |=
1575 I915_MODE_FLAG_DSI_USE_TE0;
1576 }
1577
1578 return 0;
1579 }
1580
1581 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1582 struct intel_crtc_state *crtc_state)
1583 {
1584 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1585
1586 get_dsi_io_power_domains(i915,
1587 enc_to_intel_dsi(encoder));
1588
1589 if (crtc_state->dsc.compression_enable)
1590 intel_display_power_get(i915,
1591 intel_dsc_power_domain(crtc_state));
1592 }
1593
1594 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1595 enum pipe *pipe)
1596 {
1597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1598 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1599 enum transcoder dsi_trans;
1600 intel_wakeref_t wakeref;
1601 enum port port;
1602 bool ret = false;
1603 u32 tmp;
1604
1605 wakeref = intel_display_power_get_if_enabled(dev_priv,
1606 encoder->power_domain);
1607 if (!wakeref)
1608 return false;
1609
1610 for_each_dsi_port(port, intel_dsi->ports) {
1611 dsi_trans = dsi_port_to_transcoder(port);
1612 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1613 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1614 case TRANS_DDI_EDP_INPUT_A_ON:
1615 *pipe = PIPE_A;
1616 break;
1617 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1618 *pipe = PIPE_B;
1619 break;
1620 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1621 *pipe = PIPE_C;
1622 break;
1623 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1624 *pipe = PIPE_D;
1625 break;
1626 default:
1627 drm_err(&dev_priv->drm, "Invalid PIPE input\n");
1628 goto out;
1629 }
1630
1631 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
1632 ret = tmp & PIPECONF_ENABLE;
1633 }
1634 out:
1635 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1636 return ret;
1637 }
1638
1639 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1640 {
1641 intel_encoder_destroy(encoder);
1642 }
1643
1644 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1645 .destroy = gen11_dsi_encoder_destroy,
1646 };
1647
1648 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1649 .late_register = intel_connector_register,
1650 .early_unregister = intel_connector_unregister,
1651 .destroy = intel_connector_destroy,
1652 .fill_modes = drm_helper_probe_single_connector_modes,
1653 .atomic_get_property = intel_digital_connector_atomic_get_property,
1654 .atomic_set_property = intel_digital_connector_atomic_set_property,
1655 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1656 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1657 };
1658
1659 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1660 .get_modes = intel_dsi_get_modes,
1661 .mode_valid = gen11_dsi_mode_valid,
1662 .atomic_check = intel_digital_connector_atomic_check,
1663 };
1664
1665 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1666 struct mipi_dsi_device *dsi)
1667 {
1668 return 0;
1669 }
1670
1671 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1672 struct mipi_dsi_device *dsi)
1673 {
1674 return 0;
1675 }
1676
1677 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1678 const struct mipi_dsi_msg *msg)
1679 {
1680 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1681 struct mipi_dsi_packet dsi_pkt;
1682 ssize_t ret;
1683 bool enable_lpdt = false;
1684
1685 ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1686 if (ret < 0)
1687 return ret;
1688
1689 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1690 enable_lpdt = true;
1691
1692 /* send packet header */
1693 ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
1694 if (ret < 0)
1695 return ret;
1696
1697 /* only long packet contains payload */
1698 if (mipi_dsi_packet_format_is_long(msg->type)) {
1699 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
1700 if (ret < 0)
1701 return ret;
1702 }
1703
1704 //TODO: add payload receive code if needed
1705
1706 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1707
1708 return ret;
1709 }
1710
1711 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1712 .attach = gen11_dsi_host_attach,
1713 .detach = gen11_dsi_host_detach,
1714 .transfer = gen11_dsi_host_transfer,
1715 };
1716
1717 #define ICL_PREPARE_CNT_MAX 0x7
1718 #define ICL_CLK_ZERO_CNT_MAX 0xf
1719 #define ICL_TRAIL_CNT_MAX 0x7
1720 #define ICL_TCLK_PRE_CNT_MAX 0x3
1721 #define ICL_TCLK_POST_CNT_MAX 0x7
1722 #define ICL_HS_ZERO_CNT_MAX 0xf
1723 #define ICL_EXIT_ZERO_CNT_MAX 0x7
1724
1725 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1726 {
1727 struct drm_device *dev = intel_dsi->base.base.dev;
1728 struct drm_i915_private *dev_priv = to_i915(dev);
1729 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
1730 u32 tlpx_ns;
1731 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1732 u32 ths_prepare_ns, tclk_trail_ns;
1733 u32 hs_zero_cnt;
1734 u32 tclk_pre_cnt, tclk_post_cnt;
1735
1736 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1737
1738 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1739 ths_prepare_ns = max(mipi_config->ths_prepare,
1740 mipi_config->tclk_prepare);
1741
1742 /*
1743 * prepare cnt in escape clocks
1744 * this field represents a hexadecimal value with a precision
1745 * of 1.2 – i.e. the most significant bit is the integer
1746 * and the least significant 2 bits are fraction bits.
1747 * so, the field can represent a range of 0.25 to 1.75
1748 */
1749 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1750 if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1751 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
1752 prepare_cnt);
1753 prepare_cnt = ICL_PREPARE_CNT_MAX;
1754 }
1755
1756 /* clk zero count in escape clocks */
1757 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1758 ths_prepare_ns, tlpx_ns);
1759 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1760 drm_dbg_kms(&dev_priv->drm,
1761 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1762 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1763 }
1764
1765 /* trail cnt in escape clocks*/
1766 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1767 if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1768 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
1769 trail_cnt);
1770 trail_cnt = ICL_TRAIL_CNT_MAX;
1771 }
1772
1773 /* tclk pre count in escape clocks */
1774 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1775 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1776 drm_dbg_kms(&dev_priv->drm,
1777 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1778 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1779 }
1780
1781 /* tclk post count in escape clocks */
1782 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1783 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1784 drm_dbg_kms(&dev_priv->drm,
1785 "tclk_post_cnt out of range (%d)\n",
1786 tclk_post_cnt);
1787 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1788 }
1789
1790 /* hs zero cnt in escape clocks */
1791 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1792 ths_prepare_ns, tlpx_ns);
1793 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1794 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
1795 hs_zero_cnt);
1796 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1797 }
1798
1799 /* hs exit zero cnt in escape clocks */
1800 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1801 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1802 drm_dbg_kms(&dev_priv->drm,
1803 "exit_zero_cnt out of range (%d)\n",
1804 exit_zero_cnt);
1805 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1806 }
1807
1808 /* clock lane dphy timings */
1809 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1810 CLK_PREPARE(prepare_cnt) |
1811 CLK_ZERO_OVERRIDE |
1812 CLK_ZERO(clk_zero_cnt) |
1813 CLK_PRE_OVERRIDE |
1814 CLK_PRE(tclk_pre_cnt) |
1815 CLK_POST_OVERRIDE |
1816 CLK_POST(tclk_post_cnt) |
1817 CLK_TRAIL_OVERRIDE |
1818 CLK_TRAIL(trail_cnt));
1819
1820 /* data lanes dphy timings */
1821 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1822 HS_PREPARE(prepare_cnt) |
1823 HS_ZERO_OVERRIDE |
1824 HS_ZERO(hs_zero_cnt) |
1825 HS_TRAIL_OVERRIDE |
1826 HS_TRAIL(trail_cnt) |
1827 HS_EXIT_OVERRIDE |
1828 HS_EXIT(exit_zero_cnt));
1829
1830 intel_dsi_log_params(intel_dsi);
1831 }
1832
1833 static void icl_dsi_add_properties(struct intel_connector *connector)
1834 {
1835 u32 allowed_scalers;
1836
1837 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
1838 BIT(DRM_MODE_SCALE_FULLSCREEN) |
1839 BIT(DRM_MODE_SCALE_CENTER);
1840
1841 drm_connector_attach_scaling_mode_property(&connector->base,
1842 allowed_scalers);
1843
1844 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1845
1846 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1847 intel_dsi_get_panel_orientation(connector),
1848 connector->panel.fixed_mode->hdisplay,
1849 connector->panel.fixed_mode->vdisplay);
1850 }
1851
1852 void icl_dsi_init(struct drm_i915_private *dev_priv)
1853 {
1854 struct drm_device *dev = &dev_priv->drm;
1855 struct intel_dsi *intel_dsi;
1856 struct intel_encoder *encoder;
1857 struct intel_connector *intel_connector;
1858 struct drm_connector *connector;
1859 struct drm_display_mode *fixed_mode;
1860 enum port port;
1861
1862 if (!intel_bios_is_dsi_present(dev_priv, &port))
1863 return;
1864
1865 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1866 if (!intel_dsi)
1867 return;
1868
1869 intel_connector = intel_connector_alloc();
1870 if (!intel_connector) {
1871 kfree(intel_dsi);
1872 return;
1873 }
1874
1875 encoder = &intel_dsi->base;
1876 intel_dsi->attached_connector = intel_connector;
1877 connector = &intel_connector->base;
1878
1879 /* register DSI encoder with DRM subsystem */
1880 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
1881 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1882
1883 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1884 encoder->pre_enable = gen11_dsi_pre_enable;
1885 encoder->enable = gen11_dsi_enable;
1886 encoder->disable = gen11_dsi_disable;
1887 encoder->post_disable = gen11_dsi_post_disable;
1888 encoder->port = port;
1889 encoder->get_config = gen11_dsi_get_config;
1890 encoder->update_pipe = intel_panel_update_backlight;
1891 encoder->compute_config = gen11_dsi_compute_config;
1892 encoder->get_hw_state = gen11_dsi_get_hw_state;
1893 encoder->type = INTEL_OUTPUT_DSI;
1894 encoder->cloneable = 0;
1895 encoder->pipe_mask = ~0;
1896 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1897 encoder->get_power_domains = gen11_dsi_get_power_domains;
1898
1899 /* register DSI connector with DRM subsystem */
1900 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
1901 DRM_MODE_CONNECTOR_DSI);
1902 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1903 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1904 connector->interlace_allowed = false;
1905 connector->doublescan_allowed = false;
1906 intel_connector->get_hw_state = intel_connector_get_hw_state;
1907
1908 /* attach connector to encoder */
1909 intel_connector_attach_encoder(intel_connector, encoder);
1910
1911 mutex_lock(&dev->mode_config.mutex);
1912 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
1913 mutex_unlock(&dev->mode_config.mutex);
1914
1915 if (!fixed_mode) {
1916 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
1917 goto err;
1918 }
1919
1920 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1921 intel_panel_setup_backlight(connector, INVALID_PIPE);
1922
1923 if (dev_priv->vbt.dsi.config->dual_link)
1924 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1925 else
1926 intel_dsi->ports = BIT(port);
1927
1928 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1929 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1930
1931 for_each_dsi_port(port, intel_dsi->ports) {
1932 struct intel_dsi_host *host;
1933
1934 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
1935 if (!host)
1936 goto err;
1937
1938 intel_dsi->dsi_hosts[port] = host;
1939 }
1940
1941 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1942 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1943 goto err;
1944 }
1945
1946 icl_dphy_param_init(intel_dsi);
1947
1948 icl_dsi_add_properties(intel_connector);
1949 return;
1950
1951 err:
1952 drm_connector_cleanup(connector);
1953 drm_encoder_cleanup(&encoder->base);
1954 kfree(intel_dsi);
1955 kfree(intel_connector);
1956 }
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