2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
25 #include "intel_color.h"
27 #include "intel_display_types.h"
29 #define CTM_COEFF_SIGN (1ULL << 63)
31 #define CTM_COEFF_1_0 (1ULL << 32)
32 #define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
33 #define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
34 #define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
35 #define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
36 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
37 #define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
39 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
41 #define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
42 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
44 #define LEGACY_LUT_LENGTH 256
49 * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0|
50 * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
51 * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2|
53 * ILK/SNB don't have explicit post offsets, and instead
54 * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:
55 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
56 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
57 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
58 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
62 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
63 * format). This macro takes the coefficient we want transformed and the
64 * number of fractional bits.
66 * We only have a 9 bits precision window which slides depending on the value
67 * of the CTM coefficient and we write the value from bit 3. We also round the
70 #define ILK_CSC_COEFF_FP(coeff, fbits) \
71 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
73 #define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
74 #define ILK_CSC_COEFF_1_0 0x7800
76 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
78 /* Nop pre/post offsets */
79 static const u16 ilk_csc_off_zero
[3] = {};
82 static const u16 ilk_csc_coeff_identity
[9] = {
83 ILK_CSC_COEFF_1_0
, 0, 0,
84 0, ILK_CSC_COEFF_1_0
, 0,
85 0, 0, ILK_CSC_COEFF_1_0
,
88 /* Limited range RGB post offsets */
89 static const u16 ilk_csc_postoff_limited_range
[3] = {
90 ILK_CSC_POSTOFF_LIMITED_RANGE
,
91 ILK_CSC_POSTOFF_LIMITED_RANGE
,
92 ILK_CSC_POSTOFF_LIMITED_RANGE
,
95 /* Full range RGB -> limited range RGB matrix */
96 static const u16 ilk_csc_coeff_limited_range
[9] = {
97 ILK_CSC_COEFF_LIMITED_RANGE
, 0, 0,
98 0, ILK_CSC_COEFF_LIMITED_RANGE
, 0,
99 0, 0, ILK_CSC_COEFF_LIMITED_RANGE
,
102 /* BT.709 full range RGB -> limited range YCbCr matrix */
103 static const u16 ilk_csc_coeff_rgb_to_ycbcr
[9] = {
104 0x1e08, 0x9cc0, 0xb528,
105 0x2ba8, 0x09d8, 0x37e8,
106 0xbce8, 0x9ad8, 0x1e08,
109 /* Limited range YCbCr post offsets */
110 static const u16 ilk_csc_postoff_rgb_to_ycbcr
[3] = {
111 0x0800, 0x0100, 0x0800,
114 static bool lut_is_legacy(const struct drm_property_blob
*lut
)
116 return drm_color_lut_size(lut
) == LEGACY_LUT_LENGTH
;
119 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state
*crtc_state
)
121 return !crtc_state
->hw
.degamma_lut
&&
122 !crtc_state
->hw
.ctm
&&
123 crtc_state
->hw
.gamma_lut
&&
124 lut_is_legacy(crtc_state
->hw
.gamma_lut
);
128 * When using limited range, multiply the matrix given by userspace by
129 * the matrix that we would use for the limited range.
131 static u64
*ctm_mult_by_limited(u64
*result
, const u64
*input
)
135 for (i
= 0; i
< 9; i
++) {
136 u64 user_coeff
= input
[i
];
137 u32 limited_coeff
= CTM_COEFF_LIMITED_RANGE
;
138 u32 abs_coeff
= clamp_val(CTM_COEFF_ABS(user_coeff
), 0,
139 CTM_COEFF_4_0
- 1) >> 2;
142 * By scaling every co-efficient with limited range (16-235)
143 * vs full range (0-255) the final o/p will be scaled down to
144 * fit in the limited range supported by the panel.
146 result
[i
] = mul_u32_u32(limited_coeff
, abs_coeff
) >> 30;
147 result
[i
] |= user_coeff
& CTM_COEFF_SIGN
;
153 static void ilk_update_pipe_csc(struct intel_crtc
*crtc
,
156 const u16 postoff
[3])
158 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
159 enum pipe pipe
= crtc
->pipe
;
161 intel_de_write(dev_priv
, PIPE_CSC_PREOFF_HI(pipe
), preoff
[0]);
162 intel_de_write(dev_priv
, PIPE_CSC_PREOFF_ME(pipe
), preoff
[1]);
163 intel_de_write(dev_priv
, PIPE_CSC_PREOFF_LO(pipe
), preoff
[2]);
165 intel_de_write(dev_priv
, PIPE_CSC_COEFF_RY_GY(pipe
),
166 coeff
[0] << 16 | coeff
[1]);
167 intel_de_write(dev_priv
, PIPE_CSC_COEFF_BY(pipe
), coeff
[2] << 16);
169 intel_de_write(dev_priv
, PIPE_CSC_COEFF_RU_GU(pipe
),
170 coeff
[3] << 16 | coeff
[4]);
171 intel_de_write(dev_priv
, PIPE_CSC_COEFF_BU(pipe
), coeff
[5] << 16);
173 intel_de_write(dev_priv
, PIPE_CSC_COEFF_RV_GV(pipe
),
174 coeff
[6] << 16 | coeff
[7]);
175 intel_de_write(dev_priv
, PIPE_CSC_COEFF_BV(pipe
), coeff
[8] << 16);
177 if (DISPLAY_VER(dev_priv
) >= 7) {
178 intel_de_write(dev_priv
, PIPE_CSC_POSTOFF_HI(pipe
),
180 intel_de_write(dev_priv
, PIPE_CSC_POSTOFF_ME(pipe
),
182 intel_de_write(dev_priv
, PIPE_CSC_POSTOFF_LO(pipe
),
187 static void icl_update_output_csc(struct intel_crtc
*crtc
,
190 const u16 postoff
[3])
192 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
193 enum pipe pipe
= crtc
->pipe
;
195 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_PREOFF_HI(pipe
), preoff
[0]);
196 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_PREOFF_ME(pipe
), preoff
[1]);
197 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_PREOFF_LO(pipe
), preoff
[2]);
199 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe
),
200 coeff
[0] << 16 | coeff
[1]);
201 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_COEFF_BY(pipe
),
204 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe
),
205 coeff
[3] << 16 | coeff
[4]);
206 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_COEFF_BU(pipe
),
209 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe
),
210 coeff
[6] << 16 | coeff
[7]);
211 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_COEFF_BV(pipe
),
214 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe
), postoff
[0]);
215 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe
), postoff
[1]);
216 intel_de_write(dev_priv
, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe
), postoff
[2]);
219 static bool ilk_csc_limited_range(const struct intel_crtc_state
*crtc_state
)
221 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
224 * FIXME if there's a gamma LUT after the CSC, we should
225 * do the range compression using the gamma LUT instead.
227 return crtc_state
->limited_color_range
&&
228 (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
229 IS_DISPLAY_VER(dev_priv
, 9, 10));
232 static void ilk_csc_convert_ctm(const struct intel_crtc_state
*crtc_state
,
235 const struct drm_color_ctm
*ctm
= crtc_state
->hw
.ctm
->data
;
240 if (ilk_csc_limited_range(crtc_state
))
241 input
= ctm_mult_by_limited(temp
, ctm
->matrix
);
246 * Convert fixed point S31.32 input to format supported by the
249 for (i
= 0; i
< 9; i
++) {
250 u64 abs_coeff
= ((1ULL << 63) - 1) & input
[i
];
253 * Clamp input value to min/max supported by
256 abs_coeff
= clamp_val(abs_coeff
, 0, CTM_COEFF_4_0
- 1);
261 if (CTM_COEFF_NEGATIVE(input
[i
]))
262 coeffs
[i
] |= 1 << 15;
264 if (abs_coeff
< CTM_COEFF_0_125
)
265 coeffs
[i
] |= (3 << 12) |
266 ILK_CSC_COEFF_FP(abs_coeff
, 12);
267 else if (abs_coeff
< CTM_COEFF_0_25
)
268 coeffs
[i
] |= (2 << 12) |
269 ILK_CSC_COEFF_FP(abs_coeff
, 11);
270 else if (abs_coeff
< CTM_COEFF_0_5
)
271 coeffs
[i
] |= (1 << 12) |
272 ILK_CSC_COEFF_FP(abs_coeff
, 10);
273 else if (abs_coeff
< CTM_COEFF_1_0
)
274 coeffs
[i
] |= ILK_CSC_COEFF_FP(abs_coeff
, 9);
275 else if (abs_coeff
< CTM_COEFF_2_0
)
276 coeffs
[i
] |= (7 << 12) |
277 ILK_CSC_COEFF_FP(abs_coeff
, 8);
279 coeffs
[i
] |= (6 << 12) |
280 ILK_CSC_COEFF_FP(abs_coeff
, 7);
284 static void ilk_load_csc_matrix(const struct intel_crtc_state
*crtc_state
)
286 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
287 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
288 bool limited_color_range
= ilk_csc_limited_range(crtc_state
);
290 if (crtc_state
->hw
.ctm
) {
293 ilk_csc_convert_ctm(crtc_state
, coeff
);
294 ilk_update_pipe_csc(crtc
, ilk_csc_off_zero
, coeff
,
295 limited_color_range
?
296 ilk_csc_postoff_limited_range
:
298 } else if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
) {
299 ilk_update_pipe_csc(crtc
, ilk_csc_off_zero
,
300 ilk_csc_coeff_rgb_to_ycbcr
,
301 ilk_csc_postoff_rgb_to_ycbcr
);
302 } else if (limited_color_range
) {
303 ilk_update_pipe_csc(crtc
, ilk_csc_off_zero
,
304 ilk_csc_coeff_limited_range
,
305 ilk_csc_postoff_limited_range
);
306 } else if (crtc_state
->csc_enable
) {
308 * On GLK both pipe CSC and degamma LUT are controlled
309 * by csc_enable. Hence for the cases where the degama
310 * LUT is needed but CSC is not we need to load an
313 drm_WARN_ON(&dev_priv
->drm
, !IS_GEMINILAKE(dev_priv
));
315 ilk_update_pipe_csc(crtc
, ilk_csc_off_zero
,
316 ilk_csc_coeff_identity
,
320 intel_de_write(dev_priv
, PIPE_CSC_MODE(crtc
->pipe
),
321 crtc_state
->csc_mode
);
324 static void icl_load_csc_matrix(const struct intel_crtc_state
*crtc_state
)
326 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
327 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
329 if (crtc_state
->hw
.ctm
) {
332 ilk_csc_convert_ctm(crtc_state
, coeff
);
333 ilk_update_pipe_csc(crtc
, ilk_csc_off_zero
,
334 coeff
, ilk_csc_off_zero
);
337 if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
) {
338 icl_update_output_csc(crtc
, ilk_csc_off_zero
,
339 ilk_csc_coeff_rgb_to_ycbcr
,
340 ilk_csc_postoff_rgb_to_ycbcr
);
341 } else if (crtc_state
->limited_color_range
) {
342 icl_update_output_csc(crtc
, ilk_csc_off_zero
,
343 ilk_csc_coeff_limited_range
,
344 ilk_csc_postoff_limited_range
);
347 intel_de_write(dev_priv
, PIPE_CSC_MODE(crtc
->pipe
),
348 crtc_state
->csc_mode
);
351 static void chv_load_cgm_csc(struct intel_crtc
*crtc
,
352 const struct drm_property_blob
*blob
)
354 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
355 const struct drm_color_ctm
*ctm
= blob
->data
;
356 enum pipe pipe
= crtc
->pipe
;
360 for (i
= 0; i
< ARRAY_SIZE(coeffs
); i
++) {
361 u64 abs_coeff
= ((1ULL << 63) - 1) & ctm
->matrix
[i
];
363 /* Round coefficient. */
364 abs_coeff
+= 1 << (32 - 13);
365 /* Clamp to hardware limits. */
366 abs_coeff
= clamp_val(abs_coeff
, 0, CTM_COEFF_8_0
- 1);
370 /* Write coefficients in S3.12 format. */
371 if (ctm
->matrix
[i
] & (1ULL << 63))
372 coeffs
[i
] |= 1 << 15;
374 coeffs
[i
] |= ((abs_coeff
>> 32) & 7) << 12;
375 coeffs
[i
] |= (abs_coeff
>> 20) & 0xfff;
378 intel_de_write(dev_priv
, CGM_PIPE_CSC_COEFF01(pipe
),
379 coeffs
[1] << 16 | coeffs
[0]);
380 intel_de_write(dev_priv
, CGM_PIPE_CSC_COEFF23(pipe
),
381 coeffs
[3] << 16 | coeffs
[2]);
382 intel_de_write(dev_priv
, CGM_PIPE_CSC_COEFF45(pipe
),
383 coeffs
[5] << 16 | coeffs
[4]);
384 intel_de_write(dev_priv
, CGM_PIPE_CSC_COEFF67(pipe
),
385 coeffs
[7] << 16 | coeffs
[6]);
386 intel_de_write(dev_priv
, CGM_PIPE_CSC_COEFF8(pipe
),
390 /* convert hw value with given bit_precision to lut property val */
391 static u32
intel_color_lut_pack(u32 val
, int bit_precision
)
393 u32 max
= 0xffff >> (16 - bit_precision
);
395 val
= clamp_val(val
, 0, max
);
397 if (bit_precision
< 16)
398 val
<<= 16 - bit_precision
;
403 static u32
i9xx_lut_8(const struct drm_color_lut
*color
)
405 return drm_color_lut_extract(color
->red
, 8) << 16 |
406 drm_color_lut_extract(color
->green
, 8) << 8 |
407 drm_color_lut_extract(color
->blue
, 8);
410 static void i9xx_lut_8_pack(struct drm_color_lut
*entry
, u32 val
)
412 entry
->red
= intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK
, val
), 8);
413 entry
->green
= intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK
, val
), 8);
414 entry
->blue
= intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK
, val
), 8);
417 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
418 static u32
i965_lut_10p6_ldw(const struct drm_color_lut
*color
)
420 return (color
->red
& 0xff) << 16 |
421 (color
->green
& 0xff) << 8 |
422 (color
->blue
& 0xff);
425 /* i965+ "10.6" interpolated format "odd DW" (high 8 bits) */
426 static u32
i965_lut_10p6_udw(const struct drm_color_lut
*color
)
428 return (color
->red
>> 8) << 16 |
429 (color
->green
>> 8) << 8 |
433 static void i965_lut_10p6_pack(struct drm_color_lut
*entry
, u32 ldw
, u32 udw
)
435 entry
->red
= REG_FIELD_GET(PALETTE_RED_MASK
, udw
) << 8 |
436 REG_FIELD_GET(PALETTE_RED_MASK
, ldw
);
437 entry
->green
= REG_FIELD_GET(PALETTE_GREEN_MASK
, udw
) << 8 |
438 REG_FIELD_GET(PALETTE_GREEN_MASK
, ldw
);
439 entry
->blue
= REG_FIELD_GET(PALETTE_BLUE_MASK
, udw
) << 8 |
440 REG_FIELD_GET(PALETTE_BLUE_MASK
, ldw
);
443 static u16
i965_lut_11p6_max_pack(u32 val
)
445 /* PIPEGCMAX is 11.6, clamp to 10.6 */
446 return clamp_val(val
, 0, 0xffff);
449 static u32
ilk_lut_10(const struct drm_color_lut
*color
)
451 return drm_color_lut_extract(color
->red
, 10) << 20 |
452 drm_color_lut_extract(color
->green
, 10) << 10 |
453 drm_color_lut_extract(color
->blue
, 10);
456 static void ilk_lut_10_pack(struct drm_color_lut
*entry
, u32 val
)
458 entry
->red
= intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK
, val
), 10);
459 entry
->green
= intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK
, val
), 10);
460 entry
->blue
= intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK
, val
), 10);
463 static void icl_lut_multi_seg_pack(struct drm_color_lut
*entry
, u32 ldw
, u32 udw
)
465 entry
->red
= REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK
, udw
) << 6 |
466 REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK
, ldw
);
467 entry
->green
= REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK
, udw
) << 6 |
468 REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK
, ldw
);
469 entry
->blue
= REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK
, udw
) << 6 |
470 REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK
, ldw
);
473 static void i9xx_color_commit(const struct intel_crtc_state
*crtc_state
)
475 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
476 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
477 enum pipe pipe
= crtc
->pipe
;
480 val
= intel_de_read(dev_priv
, PIPECONF(pipe
));
481 val
&= ~PIPECONF_GAMMA_MODE_MASK_I9XX
;
482 val
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
483 intel_de_write(dev_priv
, PIPECONF(pipe
), val
);
486 static void ilk_color_commit(const struct intel_crtc_state
*crtc_state
)
488 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
489 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
490 enum pipe pipe
= crtc
->pipe
;
493 val
= intel_de_read(dev_priv
, PIPECONF(pipe
));
494 val
&= ~PIPECONF_GAMMA_MODE_MASK_ILK
;
495 val
|= PIPECONF_GAMMA_MODE(crtc_state
->gamma_mode
);
496 intel_de_write(dev_priv
, PIPECONF(pipe
), val
);
498 ilk_load_csc_matrix(crtc_state
);
501 static void hsw_color_commit(const struct intel_crtc_state
*crtc_state
)
503 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
504 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
506 intel_de_write(dev_priv
, GAMMA_MODE(crtc
->pipe
),
507 crtc_state
->gamma_mode
);
509 ilk_load_csc_matrix(crtc_state
);
512 static void skl_color_commit(const struct intel_crtc_state
*crtc_state
)
514 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
515 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
516 enum pipe pipe
= crtc
->pipe
;
520 * We don't (yet) allow userspace to control the pipe background color,
521 * so force it to black, but apply pipe gamma and CSC appropriately
522 * so that its handling will match how we program our planes.
524 if (crtc_state
->gamma_enable
)
525 val
|= SKL_BOTTOM_COLOR_GAMMA_ENABLE
;
526 if (crtc_state
->csc_enable
)
527 val
|= SKL_BOTTOM_COLOR_CSC_ENABLE
;
528 intel_de_write(dev_priv
, SKL_BOTTOM_COLOR(pipe
), val
);
530 intel_de_write(dev_priv
, GAMMA_MODE(crtc
->pipe
),
531 crtc_state
->gamma_mode
);
533 if (DISPLAY_VER(dev_priv
) >= 11)
534 icl_load_csc_matrix(crtc_state
);
536 ilk_load_csc_matrix(crtc_state
);
539 static void i9xx_load_lut_8(struct intel_crtc
*crtc
,
540 const struct drm_property_blob
*blob
)
542 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
543 const struct drm_color_lut
*lut
;
544 enum pipe pipe
= crtc
->pipe
;
552 for (i
= 0; i
< 256; i
++)
553 intel_de_write_fw(dev_priv
, PALETTE(pipe
, i
),
554 i9xx_lut_8(&lut
[i
]));
557 static void i9xx_load_luts(const struct intel_crtc_state
*crtc_state
)
559 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
560 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
561 const struct drm_property_blob
*gamma_lut
= crtc_state
->hw
.gamma_lut
;
563 assert_pll_enabled(dev_priv
, crtc
->pipe
);
565 i9xx_load_lut_8(crtc
, gamma_lut
);
568 static void i965_load_lut_10p6(struct intel_crtc
*crtc
,
569 const struct drm_property_blob
*blob
)
571 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
572 const struct drm_color_lut
*lut
= blob
->data
;
573 int i
, lut_size
= drm_color_lut_size(blob
);
574 enum pipe pipe
= crtc
->pipe
;
576 for (i
= 0; i
< lut_size
- 1; i
++) {
577 intel_de_write_fw(dev_priv
, PALETTE(pipe
, 2 * i
+ 0),
578 i965_lut_10p6_ldw(&lut
[i
]));
579 intel_de_write_fw(dev_priv
, PALETTE(pipe
, 2 * i
+ 1),
580 i965_lut_10p6_udw(&lut
[i
]));
583 intel_de_write_fw(dev_priv
, PIPEGCMAX(pipe
, 0), lut
[i
].red
);
584 intel_de_write_fw(dev_priv
, PIPEGCMAX(pipe
, 1), lut
[i
].green
);
585 intel_de_write_fw(dev_priv
, PIPEGCMAX(pipe
, 2), lut
[i
].blue
);
588 static void i965_load_luts(const struct intel_crtc_state
*crtc_state
)
590 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
591 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
592 const struct drm_property_blob
*gamma_lut
= crtc_state
->hw
.gamma_lut
;
594 if (intel_crtc_has_type(crtc_state
, INTEL_OUTPUT_DSI
))
595 assert_dsi_pll_enabled(dev_priv
);
597 assert_pll_enabled(dev_priv
, crtc
->pipe
);
599 if (crtc_state
->gamma_mode
== GAMMA_MODE_MODE_8BIT
)
600 i9xx_load_lut_8(crtc
, gamma_lut
);
602 i965_load_lut_10p6(crtc
, gamma_lut
);
605 static void ilk_load_lut_8(struct intel_crtc
*crtc
,
606 const struct drm_property_blob
*blob
)
608 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
609 const struct drm_color_lut
*lut
;
610 enum pipe pipe
= crtc
->pipe
;
618 for (i
= 0; i
< 256; i
++)
619 intel_de_write_fw(dev_priv
, LGC_PALETTE(pipe
, i
),
620 i9xx_lut_8(&lut
[i
]));
623 static void ilk_load_lut_10(struct intel_crtc
*crtc
,
624 const struct drm_property_blob
*blob
)
626 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
627 const struct drm_color_lut
*lut
= blob
->data
;
628 int i
, lut_size
= drm_color_lut_size(blob
);
629 enum pipe pipe
= crtc
->pipe
;
631 for (i
= 0; i
< lut_size
; i
++)
632 intel_de_write_fw(dev_priv
, PREC_PALETTE(pipe
, i
),
633 ilk_lut_10(&lut
[i
]));
636 static void ilk_load_luts(const struct intel_crtc_state
*crtc_state
)
638 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
639 const struct drm_property_blob
*gamma_lut
= crtc_state
->hw
.gamma_lut
;
641 switch (crtc_state
->gamma_mode
) {
642 case GAMMA_MODE_MODE_8BIT
:
643 ilk_load_lut_8(crtc
, gamma_lut
);
645 case GAMMA_MODE_MODE_10BIT
:
646 ilk_load_lut_10(crtc
, gamma_lut
);
649 MISSING_CASE(crtc_state
->gamma_mode
);
654 static int ivb_lut_10_size(u32 prec_index
)
656 if (prec_index
& PAL_PREC_SPLIT_MODE
)
663 * IVB/HSW Bspec / PAL_PREC_INDEX:
664 * "Restriction : Index auto increment mode is not
665 * supported and must not be enabled."
667 static void ivb_load_lut_10(struct intel_crtc
*crtc
,
668 const struct drm_property_blob
*blob
,
671 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
672 int hw_lut_size
= ivb_lut_10_size(prec_index
);
673 const struct drm_color_lut
*lut
= blob
->data
;
674 int i
, lut_size
= drm_color_lut_size(blob
);
675 enum pipe pipe
= crtc
->pipe
;
677 for (i
= 0; i
< hw_lut_size
; i
++) {
678 /* We discard half the user entries in split gamma mode */
679 const struct drm_color_lut
*entry
=
680 &lut
[i
* (lut_size
- 1) / (hw_lut_size
- 1)];
682 intel_de_write_fw(dev_priv
, PREC_PAL_INDEX(pipe
), prec_index
++);
683 intel_de_write_fw(dev_priv
, PREC_PAL_DATA(pipe
),
688 * Reset the index, otherwise it prevents the legacy palette to be
691 intel_de_write_fw(dev_priv
, PREC_PAL_INDEX(pipe
), 0);
694 /* On BDW+ the index auto increment mode actually works */
695 static void bdw_load_lut_10(struct intel_crtc
*crtc
,
696 const struct drm_property_blob
*blob
,
699 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
700 int hw_lut_size
= ivb_lut_10_size(prec_index
);
701 const struct drm_color_lut
*lut
= blob
->data
;
702 int i
, lut_size
= drm_color_lut_size(blob
);
703 enum pipe pipe
= crtc
->pipe
;
705 intel_de_write_fw(dev_priv
, PREC_PAL_INDEX(pipe
),
706 prec_index
| PAL_PREC_AUTO_INCREMENT
);
708 for (i
= 0; i
< hw_lut_size
; i
++) {
709 /* We discard half the user entries in split gamma mode */
710 const struct drm_color_lut
*entry
=
711 &lut
[i
* (lut_size
- 1) / (hw_lut_size
- 1)];
713 intel_de_write_fw(dev_priv
, PREC_PAL_DATA(pipe
),
718 * Reset the index, otherwise it prevents the legacy palette to be
721 intel_de_write_fw(dev_priv
, PREC_PAL_INDEX(pipe
), 0);
724 static void ivb_load_lut_ext_max(const struct intel_crtc_state
*crtc_state
)
726 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
727 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
728 enum pipe pipe
= crtc
->pipe
;
730 /* Program the max register to clamp values > 1.0. */
731 intel_dsb_reg_write(crtc_state
, PREC_PAL_EXT_GC_MAX(pipe
, 0), 1 << 16);
732 intel_dsb_reg_write(crtc_state
, PREC_PAL_EXT_GC_MAX(pipe
, 1), 1 << 16);
733 intel_dsb_reg_write(crtc_state
, PREC_PAL_EXT_GC_MAX(pipe
, 2), 1 << 16);
736 * Program the gc max 2 register to clamp values > 1.0.
737 * ToDo: Extend the ABI to be able to program values
740 if (DISPLAY_VER(dev_priv
) >= 10) {
741 intel_dsb_reg_write(crtc_state
, PREC_PAL_EXT2_GC_MAX(pipe
, 0),
743 intel_dsb_reg_write(crtc_state
, PREC_PAL_EXT2_GC_MAX(pipe
, 1),
745 intel_dsb_reg_write(crtc_state
, PREC_PAL_EXT2_GC_MAX(pipe
, 2),
750 static void ivb_load_luts(const struct intel_crtc_state
*crtc_state
)
752 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
753 const struct drm_property_blob
*gamma_lut
= crtc_state
->hw
.gamma_lut
;
754 const struct drm_property_blob
*degamma_lut
= crtc_state
->hw
.degamma_lut
;
755 const struct drm_property_blob
*blob
= gamma_lut
?: degamma_lut
;
757 switch (crtc_state
->gamma_mode
) {
758 case GAMMA_MODE_MODE_8BIT
:
759 ilk_load_lut_8(crtc
, blob
);
761 case GAMMA_MODE_MODE_SPLIT
:
762 ivb_load_lut_10(crtc
, degamma_lut
, PAL_PREC_SPLIT_MODE
|
763 PAL_PREC_INDEX_VALUE(0));
764 ivb_load_lut_ext_max(crtc_state
);
765 ivb_load_lut_10(crtc
, gamma_lut
, PAL_PREC_SPLIT_MODE
|
766 PAL_PREC_INDEX_VALUE(512));
768 case GAMMA_MODE_MODE_10BIT
:
769 ivb_load_lut_10(crtc
, blob
,
770 PAL_PREC_INDEX_VALUE(0));
771 ivb_load_lut_ext_max(crtc_state
);
774 MISSING_CASE(crtc_state
->gamma_mode
);
779 static void bdw_load_luts(const struct intel_crtc_state
*crtc_state
)
781 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
782 const struct drm_property_blob
*gamma_lut
= crtc_state
->hw
.gamma_lut
;
783 const struct drm_property_blob
*degamma_lut
= crtc_state
->hw
.degamma_lut
;
784 const struct drm_property_blob
*blob
= gamma_lut
?: degamma_lut
;
786 switch (crtc_state
->gamma_mode
) {
787 case GAMMA_MODE_MODE_8BIT
:
788 ilk_load_lut_8(crtc
, blob
);
790 case GAMMA_MODE_MODE_SPLIT
:
791 bdw_load_lut_10(crtc
, degamma_lut
, PAL_PREC_SPLIT_MODE
|
792 PAL_PREC_INDEX_VALUE(0));
793 ivb_load_lut_ext_max(crtc_state
);
794 bdw_load_lut_10(crtc
, gamma_lut
, PAL_PREC_SPLIT_MODE
|
795 PAL_PREC_INDEX_VALUE(512));
797 case GAMMA_MODE_MODE_10BIT
:
799 bdw_load_lut_10(crtc
, blob
,
800 PAL_PREC_INDEX_VALUE(0));
801 ivb_load_lut_ext_max(crtc_state
);
804 MISSING_CASE(crtc_state
->gamma_mode
);
809 static int glk_degamma_lut_size(struct drm_i915_private
*i915
)
811 if (DISPLAY_VER(i915
) >= 13)
817 static void glk_load_degamma_lut(const struct intel_crtc_state
*crtc_state
)
819 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
820 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
821 enum pipe pipe
= crtc
->pipe
;
822 int i
, lut_size
= INTEL_INFO(dev_priv
)->color
.degamma_lut_size
;
823 const struct drm_color_lut
*lut
= crtc_state
->hw
.degamma_lut
->data
;
826 * When setting the auto-increment bit, the hardware seems to
827 * ignore the index bits, so we need to reset it to index 0
830 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_INDEX(pipe
), 0);
831 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_INDEX(pipe
),
832 PRE_CSC_GAMC_AUTO_INCREMENT
);
834 for (i
= 0; i
< lut_size
; i
++) {
836 * First lut_size entries represent range from 0 to 1.0
837 * 3 additional lut entries will represent extended range
838 * inputs 3.0 and 7.0 respectively, currently clamped
839 * at 1.0. Since the precision is 16bit, the user
840 * value can be directly filled to register.
841 * The pipe degamma table in GLK+ onwards doesn't
842 * support different values per channel, so this just
843 * programs green value which will be equal to Red and
844 * Blue into the lut registers.
845 * ToDo: Extend to max 7.0. Enable 32 bit input value
846 * as compared to just 16 to achieve this.
848 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_DATA(pipe
),
852 /* Clamp values > 1.0. */
853 while (i
++ < glk_degamma_lut_size(dev_priv
))
854 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_DATA(pipe
), 1 << 16);
856 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_INDEX(pipe
), 0);
859 static void glk_load_degamma_lut_linear(const struct intel_crtc_state
*crtc_state
)
861 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
862 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
863 enum pipe pipe
= crtc
->pipe
;
864 int i
, lut_size
= INTEL_INFO(dev_priv
)->color
.degamma_lut_size
;
867 * When setting the auto-increment bit, the hardware seems to
868 * ignore the index bits, so we need to reset it to index 0
871 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_INDEX(pipe
), 0);
872 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_INDEX(pipe
),
873 PRE_CSC_GAMC_AUTO_INCREMENT
);
875 for (i
= 0; i
< lut_size
; i
++) {
876 u32 v
= (i
<< 16) / (lut_size
- 1);
878 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_DATA(pipe
), v
);
881 /* Clamp values > 1.0. */
883 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_DATA(pipe
), 1 << 16);
885 intel_de_write_fw(dev_priv
, PRE_CSC_GAMC_INDEX(pipe
), 0);
888 static void glk_load_luts(const struct intel_crtc_state
*crtc_state
)
890 const struct drm_property_blob
*gamma_lut
= crtc_state
->hw
.gamma_lut
;
891 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
894 * On GLK+ both pipe CSC and degamma LUT are controlled
895 * by csc_enable. Hence for the cases where the CSC is
896 * needed but degamma LUT is not we need to load a
897 * linear degamma LUT. In fact we'll just always load
898 * the degama LUT so that we don't have to reload
899 * it every time the pipe CSC is being enabled.
901 if (crtc_state
->hw
.degamma_lut
)
902 glk_load_degamma_lut(crtc_state
);
904 glk_load_degamma_lut_linear(crtc_state
);
906 switch (crtc_state
->gamma_mode
) {
907 case GAMMA_MODE_MODE_8BIT
:
908 ilk_load_lut_8(crtc
, gamma_lut
);
910 case GAMMA_MODE_MODE_10BIT
:
911 bdw_load_lut_10(crtc
, gamma_lut
, PAL_PREC_INDEX_VALUE(0));
912 ivb_load_lut_ext_max(crtc_state
);
915 MISSING_CASE(crtc_state
->gamma_mode
);
920 /* ilk+ "12.4" interpolated format (high 10 bits) */
921 static u32
ilk_lut_12p4_udw(const struct drm_color_lut
*color
)
923 return (color
->red
>> 6) << 20 | (color
->green
>> 6) << 10 |
927 /* ilk+ "12.4" interpolated format (low 6 bits) */
928 static u32
ilk_lut_12p4_ldw(const struct drm_color_lut
*color
)
930 return (color
->red
& 0x3f) << 24 | (color
->green
& 0x3f) << 14 |
931 (color
->blue
& 0x3f) << 4;
935 icl_load_gcmax(const struct intel_crtc_state
*crtc_state
,
936 const struct drm_color_lut
*color
)
938 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
939 enum pipe pipe
= crtc
->pipe
;
941 /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
942 intel_dsb_reg_write(crtc_state
, PREC_PAL_GC_MAX(pipe
, 0), color
->red
);
943 intel_dsb_reg_write(crtc_state
, PREC_PAL_GC_MAX(pipe
, 1), color
->green
);
944 intel_dsb_reg_write(crtc_state
, PREC_PAL_GC_MAX(pipe
, 2), color
->blue
);
948 icl_program_gamma_superfine_segment(const struct intel_crtc_state
*crtc_state
)
950 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
951 const struct drm_property_blob
*blob
= crtc_state
->hw
.gamma_lut
;
952 const struct drm_color_lut
*lut
= blob
->data
;
953 enum pipe pipe
= crtc
->pipe
;
957 * Program Super Fine segment (let's call it seg1)...
959 * Super Fine segment's step is 1/(8 * 128 * 256) and it has
960 * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
961 * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
963 intel_dsb_reg_write(crtc_state
, PREC_PAL_MULTI_SEG_INDEX(pipe
),
964 PAL_PREC_AUTO_INCREMENT
);
966 for (i
= 0; i
< 9; i
++) {
967 const struct drm_color_lut
*entry
= &lut
[i
];
969 intel_dsb_indexed_reg_write(crtc_state
, PREC_PAL_MULTI_SEG_DATA(pipe
),
970 ilk_lut_12p4_ldw(entry
));
971 intel_dsb_indexed_reg_write(crtc_state
, PREC_PAL_MULTI_SEG_DATA(pipe
),
972 ilk_lut_12p4_udw(entry
));
977 icl_program_gamma_multi_segment(const struct intel_crtc_state
*crtc_state
)
979 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
980 const struct drm_property_blob
*blob
= crtc_state
->hw
.gamma_lut
;
981 const struct drm_color_lut
*lut
= blob
->data
;
982 const struct drm_color_lut
*entry
;
983 enum pipe pipe
= crtc
->pipe
;
987 * Program Fine segment (let's call it seg2)...
989 * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
990 * ... 256/(128 * 256). So in order to program fine segment of LUT we
991 * need to pick every 8th entry in the LUT, and program 256 indexes.
993 * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
994 * seg2[0] being unused by the hardware.
996 intel_dsb_reg_write(crtc_state
, PREC_PAL_INDEX(pipe
),
997 PAL_PREC_AUTO_INCREMENT
);
998 for (i
= 1; i
< 257; i
++) {
1000 intel_dsb_indexed_reg_write(crtc_state
, PREC_PAL_DATA(pipe
),
1001 ilk_lut_12p4_ldw(entry
));
1002 intel_dsb_indexed_reg_write(crtc_state
, PREC_PAL_DATA(pipe
),
1003 ilk_lut_12p4_udw(entry
));
1007 * Program Coarse segment (let's call it seg3)...
1009 * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
1010 * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
1011 * above, we need to pick every (8 * 128)th entry in LUT, and
1012 * program 256 of those.
1014 * Spec is not very clear about if entries seg3[0] and seg3[1] are
1015 * being used or not, but we still need to program these to advance
1018 for (i
= 0; i
< 256; i
++) {
1019 entry
= &lut
[i
* 8 * 128];
1020 intel_dsb_indexed_reg_write(crtc_state
, PREC_PAL_DATA(pipe
),
1021 ilk_lut_12p4_ldw(entry
));
1022 intel_dsb_indexed_reg_write(crtc_state
, PREC_PAL_DATA(pipe
),
1023 ilk_lut_12p4_udw(entry
));
1026 /* The last entry in the LUT is to be programmed in GCMAX */
1027 entry
= &lut
[256 * 8 * 128];
1028 icl_load_gcmax(crtc_state
, entry
);
1029 ivb_load_lut_ext_max(crtc_state
);
1032 static void icl_load_luts(const struct intel_crtc_state
*crtc_state
)
1034 const struct drm_property_blob
*gamma_lut
= crtc_state
->hw
.gamma_lut
;
1035 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1037 if (crtc_state
->hw
.degamma_lut
)
1038 glk_load_degamma_lut(crtc_state
);
1040 switch (crtc_state
->gamma_mode
& GAMMA_MODE_MODE_MASK
) {
1041 case GAMMA_MODE_MODE_8BIT
:
1042 ilk_load_lut_8(crtc
, gamma_lut
);
1044 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED
:
1045 icl_program_gamma_superfine_segment(crtc_state
);
1046 icl_program_gamma_multi_segment(crtc_state
);
1048 case GAMMA_MODE_MODE_10BIT
:
1049 bdw_load_lut_10(crtc
, gamma_lut
, PAL_PREC_INDEX_VALUE(0));
1050 ivb_load_lut_ext_max(crtc_state
);
1053 MISSING_CASE(crtc_state
->gamma_mode
);
1057 intel_dsb_commit(crtc_state
);
1060 static u32
chv_cgm_degamma_ldw(const struct drm_color_lut
*color
)
1062 return drm_color_lut_extract(color
->green
, 14) << 16 |
1063 drm_color_lut_extract(color
->blue
, 14);
1066 static u32
chv_cgm_degamma_udw(const struct drm_color_lut
*color
)
1068 return drm_color_lut_extract(color
->red
, 14);
1071 static void chv_load_cgm_degamma(struct intel_crtc
*crtc
,
1072 const struct drm_property_blob
*blob
)
1074 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1075 const struct drm_color_lut
*lut
= blob
->data
;
1076 int i
, lut_size
= drm_color_lut_size(blob
);
1077 enum pipe pipe
= crtc
->pipe
;
1079 for (i
= 0; i
< lut_size
; i
++) {
1080 intel_de_write_fw(dev_priv
, CGM_PIPE_DEGAMMA(pipe
, i
, 0),
1081 chv_cgm_degamma_ldw(&lut
[i
]));
1082 intel_de_write_fw(dev_priv
, CGM_PIPE_DEGAMMA(pipe
, i
, 1),
1083 chv_cgm_degamma_udw(&lut
[i
]));
1087 static u32
chv_cgm_gamma_ldw(const struct drm_color_lut
*color
)
1089 return drm_color_lut_extract(color
->green
, 10) << 16 |
1090 drm_color_lut_extract(color
->blue
, 10);
1093 static u32
chv_cgm_gamma_udw(const struct drm_color_lut
*color
)
1095 return drm_color_lut_extract(color
->red
, 10);
1098 static void chv_cgm_gamma_pack(struct drm_color_lut
*entry
, u32 ldw
, u32 udw
)
1100 entry
->green
= intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK
, ldw
), 10);
1101 entry
->blue
= intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK
, ldw
), 10);
1102 entry
->red
= intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK
, udw
), 10);
1105 static void chv_load_cgm_gamma(struct intel_crtc
*crtc
,
1106 const struct drm_property_blob
*blob
)
1108 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1109 const struct drm_color_lut
*lut
= blob
->data
;
1110 int i
, lut_size
= drm_color_lut_size(blob
);
1111 enum pipe pipe
= crtc
->pipe
;
1113 for (i
= 0; i
< lut_size
; i
++) {
1114 intel_de_write_fw(dev_priv
, CGM_PIPE_GAMMA(pipe
, i
, 0),
1115 chv_cgm_gamma_ldw(&lut
[i
]));
1116 intel_de_write_fw(dev_priv
, CGM_PIPE_GAMMA(pipe
, i
, 1),
1117 chv_cgm_gamma_udw(&lut
[i
]));
1121 static void chv_load_luts(const struct intel_crtc_state
*crtc_state
)
1123 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1124 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1125 const struct drm_property_blob
*degamma_lut
= crtc_state
->hw
.degamma_lut
;
1126 const struct drm_property_blob
*gamma_lut
= crtc_state
->hw
.gamma_lut
;
1127 const struct drm_property_blob
*ctm
= crtc_state
->hw
.ctm
;
1129 if (crtc_state
->cgm_mode
& CGM_PIPE_MODE_CSC
)
1130 chv_load_cgm_csc(crtc
, ctm
);
1132 if (crtc_state
->cgm_mode
& CGM_PIPE_MODE_DEGAMMA
)
1133 chv_load_cgm_degamma(crtc
, degamma_lut
);
1135 if (crtc_state
->cgm_mode
& CGM_PIPE_MODE_GAMMA
)
1136 chv_load_cgm_gamma(crtc
, gamma_lut
);
1138 i965_load_luts(crtc_state
);
1140 intel_de_write_fw(dev_priv
, CGM_PIPE_MODE(crtc
->pipe
),
1141 crtc_state
->cgm_mode
);
1144 void intel_color_load_luts(const struct intel_crtc_state
*crtc_state
)
1146 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
1148 dev_priv
->display
.load_luts(crtc_state
);
1151 void intel_color_commit(const struct intel_crtc_state
*crtc_state
)
1153 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
1155 dev_priv
->display
.color_commit(crtc_state
);
1158 static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state
)
1160 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
1161 struct intel_atomic_state
*state
=
1162 to_intel_atomic_state(new_crtc_state
->uapi
.state
);
1163 const struct intel_crtc_state
*old_crtc_state
=
1164 intel_atomic_get_old_crtc_state(state
, crtc
);
1166 return !old_crtc_state
->hw
.gamma_lut
&&
1167 !old_crtc_state
->hw
.degamma_lut
;
1170 static bool chv_can_preload_luts(const struct intel_crtc_state
*new_crtc_state
)
1172 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
1173 struct intel_atomic_state
*state
=
1174 to_intel_atomic_state(new_crtc_state
->uapi
.state
);
1175 const struct intel_crtc_state
*old_crtc_state
=
1176 intel_atomic_get_old_crtc_state(state
, crtc
);
1179 * CGM_PIPE_MODE is itself single buffered. We'd have to
1180 * somehow split it out from chv_load_luts() if we wanted
1181 * the ability to preload the CGM LUTs/CSC without tearing.
1183 if (old_crtc_state
->cgm_mode
|| new_crtc_state
->cgm_mode
)
1186 return !old_crtc_state
->hw
.gamma_lut
;
1189 static bool glk_can_preload_luts(const struct intel_crtc_state
*new_crtc_state
)
1191 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
1192 struct intel_atomic_state
*state
=
1193 to_intel_atomic_state(new_crtc_state
->uapi
.state
);
1194 const struct intel_crtc_state
*old_crtc_state
=
1195 intel_atomic_get_old_crtc_state(state
, crtc
);
1198 * The hardware degamma is active whenever the pipe
1199 * CSC is active. Thus even if the old state has no
1200 * software degamma we need to avoid clobbering the
1201 * linear hardware degamma mid scanout.
1203 return !old_crtc_state
->csc_enable
&&
1204 !old_crtc_state
->hw
.gamma_lut
;
1207 int intel_color_check(struct intel_crtc_state
*crtc_state
)
1209 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
1211 return dev_priv
->display
.color_check(crtc_state
);
1214 void intel_color_get_config(struct intel_crtc_state
*crtc_state
)
1216 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
1218 if (dev_priv
->display
.read_luts
)
1219 dev_priv
->display
.read_luts(crtc_state
);
1222 static bool need_plane_update(struct intel_plane
*plane
,
1223 const struct intel_crtc_state
*crtc_state
)
1225 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
1228 * On pre-SKL the pipe gamma enable and pipe csc enable for
1229 * the pipe bottom color are configured via the primary plane.
1230 * We have to reconfigure that even if the plane is inactive.
1232 return crtc_state
->active_planes
& BIT(plane
->id
) ||
1233 (DISPLAY_VER(dev_priv
) < 9 &&
1234 plane
->id
== PLANE_PRIMARY
);
1238 intel_color_add_affected_planes(struct intel_crtc_state
*new_crtc_state
)
1240 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->uapi
.crtc
);
1241 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1242 struct intel_atomic_state
*state
=
1243 to_intel_atomic_state(new_crtc_state
->uapi
.state
);
1244 const struct intel_crtc_state
*old_crtc_state
=
1245 intel_atomic_get_old_crtc_state(state
, crtc
);
1246 struct intel_plane
*plane
;
1248 if (!new_crtc_state
->hw
.active
||
1249 drm_atomic_crtc_needs_modeset(&new_crtc_state
->uapi
))
1252 if (new_crtc_state
->gamma_enable
== old_crtc_state
->gamma_enable
&&
1253 new_crtc_state
->csc_enable
== old_crtc_state
->csc_enable
)
1256 for_each_intel_plane_on_crtc(&dev_priv
->drm
, crtc
, plane
) {
1257 struct intel_plane_state
*plane_state
;
1259 if (!need_plane_update(plane
, new_crtc_state
))
1262 plane_state
= intel_atomic_get_plane_state(state
, plane
);
1263 if (IS_ERR(plane_state
))
1264 return PTR_ERR(plane_state
);
1266 new_crtc_state
->update_planes
|= BIT(plane
->id
);
1272 static int check_lut_size(const struct drm_property_blob
*lut
, int expected
)
1279 len
= drm_color_lut_size(lut
);
1280 if (len
!= expected
) {
1281 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1289 static int check_luts(const struct intel_crtc_state
*crtc_state
)
1291 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
1292 const struct drm_property_blob
*gamma_lut
= crtc_state
->hw
.gamma_lut
;
1293 const struct drm_property_blob
*degamma_lut
= crtc_state
->hw
.degamma_lut
;
1294 int gamma_length
, degamma_length
;
1295 u32 gamma_tests
, degamma_tests
;
1297 /* Always allow legacy gamma LUT with no further checking. */
1298 if (crtc_state_is_legacy_gamma(crtc_state
))
1301 /* C8 relies on its palette being stored in the legacy LUT */
1302 if (crtc_state
->c8_planes
) {
1303 drm_dbg_kms(&dev_priv
->drm
,
1304 "C8 pixelformat requires the legacy LUT\n");
1308 degamma_length
= INTEL_INFO(dev_priv
)->color
.degamma_lut_size
;
1309 gamma_length
= INTEL_INFO(dev_priv
)->color
.gamma_lut_size
;
1310 degamma_tests
= INTEL_INFO(dev_priv
)->color
.degamma_lut_tests
;
1311 gamma_tests
= INTEL_INFO(dev_priv
)->color
.gamma_lut_tests
;
1313 if (check_lut_size(degamma_lut
, degamma_length
) ||
1314 check_lut_size(gamma_lut
, gamma_length
))
1317 if (drm_color_lut_check(degamma_lut
, degamma_tests
) ||
1318 drm_color_lut_check(gamma_lut
, gamma_tests
))
1324 static u32
i9xx_gamma_mode(struct intel_crtc_state
*crtc_state
)
1326 if (!crtc_state
->gamma_enable
||
1327 crtc_state_is_legacy_gamma(crtc_state
))
1328 return GAMMA_MODE_MODE_8BIT
;
1330 return GAMMA_MODE_MODE_10BIT
; /* i965+ only */
1333 static int i9xx_color_check(struct intel_crtc_state
*crtc_state
)
1337 ret
= check_luts(crtc_state
);
1341 crtc_state
->gamma_enable
=
1342 crtc_state
->hw
.gamma_lut
&&
1343 !crtc_state
->c8_planes
;
1345 crtc_state
->gamma_mode
= i9xx_gamma_mode(crtc_state
);
1347 ret
= intel_color_add_affected_planes(crtc_state
);
1351 crtc_state
->preload_luts
= intel_can_preload_luts(crtc_state
);
1356 static u32
chv_cgm_mode(const struct intel_crtc_state
*crtc_state
)
1360 if (crtc_state_is_legacy_gamma(crtc_state
))
1363 if (crtc_state
->hw
.degamma_lut
)
1364 cgm_mode
|= CGM_PIPE_MODE_DEGAMMA
;
1365 if (crtc_state
->hw
.ctm
)
1366 cgm_mode
|= CGM_PIPE_MODE_CSC
;
1367 if (crtc_state
->hw
.gamma_lut
)
1368 cgm_mode
|= CGM_PIPE_MODE_GAMMA
;
1374 * CHV color pipeline:
1375 * u0.10 -> CGM degamma -> u0.14 -> CGM csc -> u0.14 -> CGM gamma ->
1376 * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
1378 * We always bypass the WGC csc and use the CGM csc
1379 * instead since it has degamma and better precision.
1381 static int chv_color_check(struct intel_crtc_state
*crtc_state
)
1385 ret
= check_luts(crtc_state
);
1390 * Pipe gamma will be used only for the legacy LUT.
1391 * Otherwise we bypass it and use the CGM gamma instead.
1393 crtc_state
->gamma_enable
=
1394 crtc_state_is_legacy_gamma(crtc_state
) &&
1395 !crtc_state
->c8_planes
;
1397 crtc_state
->gamma_mode
= GAMMA_MODE_MODE_8BIT
;
1399 crtc_state
->cgm_mode
= chv_cgm_mode(crtc_state
);
1401 ret
= intel_color_add_affected_planes(crtc_state
);
1405 crtc_state
->preload_luts
= chv_can_preload_luts(crtc_state
);
1410 static u32
ilk_gamma_mode(const struct intel_crtc_state
*crtc_state
)
1412 if (!crtc_state
->gamma_enable
||
1413 crtc_state_is_legacy_gamma(crtc_state
))
1414 return GAMMA_MODE_MODE_8BIT
;
1416 return GAMMA_MODE_MODE_10BIT
;
1419 static u32
ilk_csc_mode(const struct intel_crtc_state
*crtc_state
)
1422 * CSC comes after the LUT in RGB->YCbCr mode.
1423 * RGB->YCbCr needs the limited range offsets added to
1424 * the output. RGB limited range output is handled by
1425 * the hw automagically elsewhere.
1427 if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
)
1428 return CSC_BLACK_SCREEN_OFFSET
;
1430 return CSC_MODE_YUV_TO_RGB
|
1431 CSC_POSITION_BEFORE_GAMMA
;
1434 static int ilk_color_check(struct intel_crtc_state
*crtc_state
)
1438 ret
= check_luts(crtc_state
);
1442 crtc_state
->gamma_enable
=
1443 crtc_state
->hw
.gamma_lut
&&
1444 !crtc_state
->c8_planes
;
1447 * We don't expose the ctm on ilk/snb currently, also RGB
1448 * limited range output is handled by the hw automagically.
1450 crtc_state
->csc_enable
=
1451 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
;
1453 crtc_state
->gamma_mode
= ilk_gamma_mode(crtc_state
);
1455 crtc_state
->csc_mode
= ilk_csc_mode(crtc_state
);
1457 ret
= intel_color_add_affected_planes(crtc_state
);
1461 crtc_state
->preload_luts
= intel_can_preload_luts(crtc_state
);
1466 static u32
ivb_gamma_mode(const struct intel_crtc_state
*crtc_state
)
1468 if (!crtc_state
->gamma_enable
||
1469 crtc_state_is_legacy_gamma(crtc_state
))
1470 return GAMMA_MODE_MODE_8BIT
;
1471 else if (crtc_state
->hw
.gamma_lut
&&
1472 crtc_state
->hw
.degamma_lut
)
1473 return GAMMA_MODE_MODE_SPLIT
;
1475 return GAMMA_MODE_MODE_10BIT
;
1478 static u32
ivb_csc_mode(const struct intel_crtc_state
*crtc_state
)
1480 bool limited_color_range
= ilk_csc_limited_range(crtc_state
);
1483 * CSC comes after the LUT in degamma, RGB->YCbCr,
1484 * and RGB full->limited range mode.
1486 if (crtc_state
->hw
.degamma_lut
||
1487 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
||
1488 limited_color_range
)
1491 return CSC_POSITION_BEFORE_GAMMA
;
1494 static int ivb_color_check(struct intel_crtc_state
*crtc_state
)
1496 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
1497 bool limited_color_range
= ilk_csc_limited_range(crtc_state
);
1500 ret
= check_luts(crtc_state
);
1504 if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
&&
1505 crtc_state
->hw
.ctm
) {
1506 drm_dbg_kms(&dev_priv
->drm
,
1507 "YCBCR and CTM together are not possible\n");
1511 crtc_state
->gamma_enable
=
1512 (crtc_state
->hw
.gamma_lut
||
1513 crtc_state
->hw
.degamma_lut
) &&
1514 !crtc_state
->c8_planes
;
1516 crtc_state
->csc_enable
=
1517 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
||
1518 crtc_state
->hw
.ctm
|| limited_color_range
;
1520 crtc_state
->gamma_mode
= ivb_gamma_mode(crtc_state
);
1522 crtc_state
->csc_mode
= ivb_csc_mode(crtc_state
);
1524 ret
= intel_color_add_affected_planes(crtc_state
);
1528 crtc_state
->preload_luts
= intel_can_preload_luts(crtc_state
);
1533 static u32
glk_gamma_mode(const struct intel_crtc_state
*crtc_state
)
1535 if (!crtc_state
->gamma_enable
||
1536 crtc_state_is_legacy_gamma(crtc_state
))
1537 return GAMMA_MODE_MODE_8BIT
;
1539 return GAMMA_MODE_MODE_10BIT
;
1542 static int glk_color_check(struct intel_crtc_state
*crtc_state
)
1544 struct drm_i915_private
*dev_priv
= to_i915(crtc_state
->uapi
.crtc
->dev
);
1547 ret
= check_luts(crtc_state
);
1551 if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
&&
1552 crtc_state
->hw
.ctm
) {
1553 drm_dbg_kms(&dev_priv
->drm
,
1554 "YCBCR and CTM together are not possible\n");
1558 crtc_state
->gamma_enable
=
1559 crtc_state
->hw
.gamma_lut
&&
1560 !crtc_state
->c8_planes
;
1562 /* On GLK+ degamma LUT is controlled by csc_enable */
1563 crtc_state
->csc_enable
=
1564 crtc_state
->hw
.degamma_lut
||
1565 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
||
1566 crtc_state
->hw
.ctm
|| crtc_state
->limited_color_range
;
1568 crtc_state
->gamma_mode
= glk_gamma_mode(crtc_state
);
1570 crtc_state
->csc_mode
= 0;
1572 ret
= intel_color_add_affected_planes(crtc_state
);
1576 crtc_state
->preload_luts
= glk_can_preload_luts(crtc_state
);
1581 static u32
icl_gamma_mode(const struct intel_crtc_state
*crtc_state
)
1583 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1584 struct drm_i915_private
*i915
= to_i915(crtc
->base
.dev
);
1587 if (crtc_state
->hw
.degamma_lut
)
1588 gamma_mode
|= PRE_CSC_GAMMA_ENABLE
;
1590 if (crtc_state
->hw
.gamma_lut
&&
1591 !crtc_state
->c8_planes
)
1592 gamma_mode
|= POST_CSC_GAMMA_ENABLE
;
1594 if (!crtc_state
->hw
.gamma_lut
||
1595 crtc_state_is_legacy_gamma(crtc_state
))
1596 gamma_mode
|= GAMMA_MODE_MODE_8BIT
;
1598 * Enable 10bit gamma for D13
1599 * ToDo: Extend to Logarithmic Gamma once the new UAPI
1600 * is acccepted and implemented by a userspace consumer
1602 else if (DISPLAY_VER(i915
) >= 13)
1603 gamma_mode
|= GAMMA_MODE_MODE_10BIT
;
1605 gamma_mode
|= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED
;
1610 static u32
icl_csc_mode(const struct intel_crtc_state
*crtc_state
)
1614 if (crtc_state
->hw
.ctm
)
1615 csc_mode
|= ICL_CSC_ENABLE
;
1617 if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
||
1618 crtc_state
->limited_color_range
)
1619 csc_mode
|= ICL_OUTPUT_CSC_ENABLE
;
1624 static int icl_color_check(struct intel_crtc_state
*crtc_state
)
1628 ret
= check_luts(crtc_state
);
1632 crtc_state
->gamma_mode
= icl_gamma_mode(crtc_state
);
1634 crtc_state
->csc_mode
= icl_csc_mode(crtc_state
);
1636 crtc_state
->preload_luts
= intel_can_preload_luts(crtc_state
);
1641 static int i9xx_gamma_precision(const struct intel_crtc_state
*crtc_state
)
1643 if (!crtc_state
->gamma_enable
)
1646 switch (crtc_state
->gamma_mode
) {
1647 case GAMMA_MODE_MODE_8BIT
:
1649 case GAMMA_MODE_MODE_10BIT
:
1652 MISSING_CASE(crtc_state
->gamma_mode
);
1657 static int ilk_gamma_precision(const struct intel_crtc_state
*crtc_state
)
1659 if (!crtc_state
->gamma_enable
)
1662 if ((crtc_state
->csc_mode
& CSC_POSITION_BEFORE_GAMMA
) == 0)
1665 switch (crtc_state
->gamma_mode
) {
1666 case GAMMA_MODE_MODE_8BIT
:
1668 case GAMMA_MODE_MODE_10BIT
:
1671 MISSING_CASE(crtc_state
->gamma_mode
);
1676 static int chv_gamma_precision(const struct intel_crtc_state
*crtc_state
)
1678 if (crtc_state
->cgm_mode
& CGM_PIPE_MODE_GAMMA
)
1681 return i9xx_gamma_precision(crtc_state
);
1684 static int glk_gamma_precision(const struct intel_crtc_state
*crtc_state
)
1686 if (!crtc_state
->gamma_enable
)
1689 switch (crtc_state
->gamma_mode
) {
1690 case GAMMA_MODE_MODE_8BIT
:
1692 case GAMMA_MODE_MODE_10BIT
:
1695 MISSING_CASE(crtc_state
->gamma_mode
);
1700 static int icl_gamma_precision(const struct intel_crtc_state
*crtc_state
)
1702 if ((crtc_state
->gamma_mode
& POST_CSC_GAMMA_ENABLE
) == 0)
1705 switch (crtc_state
->gamma_mode
& GAMMA_MODE_MODE_MASK
) {
1706 case GAMMA_MODE_MODE_8BIT
:
1708 case GAMMA_MODE_MODE_10BIT
:
1710 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED
:
1713 MISSING_CASE(crtc_state
->gamma_mode
);
1718 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state
*crtc_state
)
1720 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1721 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1723 if (HAS_GMCH(dev_priv
)) {
1724 if (IS_CHERRYVIEW(dev_priv
))
1725 return chv_gamma_precision(crtc_state
);
1727 return i9xx_gamma_precision(crtc_state
);
1729 if (DISPLAY_VER(dev_priv
) >= 11)
1730 return icl_gamma_precision(crtc_state
);
1731 else if (DISPLAY_VER(dev_priv
) == 10)
1732 return glk_gamma_precision(crtc_state
);
1733 else if (IS_IRONLAKE(dev_priv
))
1734 return ilk_gamma_precision(crtc_state
);
1740 static bool err_check(struct drm_color_lut
*lut1
,
1741 struct drm_color_lut
*lut2
, u32 err
)
1743 return ((abs((long)lut2
->red
- lut1
->red
)) <= err
) &&
1744 ((abs((long)lut2
->blue
- lut1
->blue
)) <= err
) &&
1745 ((abs((long)lut2
->green
- lut1
->green
)) <= err
);
1748 static bool intel_color_lut_entries_equal(struct drm_color_lut
*lut1
,
1749 struct drm_color_lut
*lut2
,
1750 int lut_size
, u32 err
)
1754 for (i
= 0; i
< lut_size
; i
++) {
1755 if (!err_check(&lut1
[i
], &lut2
[i
], err
))
1762 bool intel_color_lut_equal(struct drm_property_blob
*blob1
,
1763 struct drm_property_blob
*blob2
,
1764 u32 gamma_mode
, u32 bit_precision
)
1766 struct drm_color_lut
*lut1
, *lut2
;
1767 int lut_size1
, lut_size2
;
1770 if (!blob1
!= !blob2
)
1776 lut_size1
= drm_color_lut_size(blob1
);
1777 lut_size2
= drm_color_lut_size(blob2
);
1779 /* check sw and hw lut size */
1780 if (lut_size1
!= lut_size2
)
1786 err
= 0xffff >> bit_precision
;
1788 /* check sw and hw lut entry to be equal */
1789 switch (gamma_mode
& GAMMA_MODE_MODE_MASK
) {
1790 case GAMMA_MODE_MODE_8BIT
:
1791 case GAMMA_MODE_MODE_10BIT
:
1792 if (!intel_color_lut_entries_equal(lut1
, lut2
,
1796 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED
:
1797 if (!intel_color_lut_entries_equal(lut1
, lut2
,
1802 MISSING_CASE(gamma_mode
);
1809 static struct drm_property_blob
*i9xx_read_lut_8(struct intel_crtc
*crtc
)
1811 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1812 enum pipe pipe
= crtc
->pipe
;
1813 struct drm_property_blob
*blob
;
1814 struct drm_color_lut
*lut
;
1817 blob
= drm_property_create_blob(&dev_priv
->drm
,
1818 sizeof(struct drm_color_lut
) * LEGACY_LUT_LENGTH
,
1825 for (i
= 0; i
< LEGACY_LUT_LENGTH
; i
++) {
1826 u32 val
= intel_de_read_fw(dev_priv
, PALETTE(pipe
, i
));
1828 i9xx_lut_8_pack(&lut
[i
], val
);
1834 static void i9xx_read_luts(struct intel_crtc_state
*crtc_state
)
1836 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1838 if (!crtc_state
->gamma_enable
)
1841 crtc_state
->hw
.gamma_lut
= i9xx_read_lut_8(crtc
);
1844 static struct drm_property_blob
*i965_read_lut_10p6(struct intel_crtc
*crtc
)
1846 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1847 int i
, lut_size
= INTEL_INFO(dev_priv
)->color
.gamma_lut_size
;
1848 enum pipe pipe
= crtc
->pipe
;
1849 struct drm_property_blob
*blob
;
1850 struct drm_color_lut
*lut
;
1852 blob
= drm_property_create_blob(&dev_priv
->drm
,
1853 sizeof(struct drm_color_lut
) * lut_size
,
1860 for (i
= 0; i
< lut_size
- 1; i
++) {
1861 u32 ldw
= intel_de_read_fw(dev_priv
, PALETTE(pipe
, 2 * i
+ 0));
1862 u32 udw
= intel_de_read_fw(dev_priv
, PALETTE(pipe
, 2 * i
+ 1));
1864 i965_lut_10p6_pack(&lut
[i
], ldw
, udw
);
1867 lut
[i
].red
= i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv
, PIPEGCMAX(pipe
, 0)));
1868 lut
[i
].green
= i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv
, PIPEGCMAX(pipe
, 1)));
1869 lut
[i
].blue
= i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv
, PIPEGCMAX(pipe
, 2)));
1874 static void i965_read_luts(struct intel_crtc_state
*crtc_state
)
1876 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1878 if (!crtc_state
->gamma_enable
)
1881 if (crtc_state
->gamma_mode
== GAMMA_MODE_MODE_8BIT
)
1882 crtc_state
->hw
.gamma_lut
= i9xx_read_lut_8(crtc
);
1884 crtc_state
->hw
.gamma_lut
= i965_read_lut_10p6(crtc
);
1887 static struct drm_property_blob
*chv_read_cgm_gamma(struct intel_crtc
*crtc
)
1889 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1890 int i
, lut_size
= INTEL_INFO(dev_priv
)->color
.gamma_lut_size
;
1891 enum pipe pipe
= crtc
->pipe
;
1892 struct drm_property_blob
*blob
;
1893 struct drm_color_lut
*lut
;
1895 blob
= drm_property_create_blob(&dev_priv
->drm
,
1896 sizeof(struct drm_color_lut
) * lut_size
,
1903 for (i
= 0; i
< lut_size
; i
++) {
1904 u32 ldw
= intel_de_read_fw(dev_priv
, CGM_PIPE_GAMMA(pipe
, i
, 0));
1905 u32 udw
= intel_de_read_fw(dev_priv
, CGM_PIPE_GAMMA(pipe
, i
, 1));
1907 chv_cgm_gamma_pack(&lut
[i
], ldw
, udw
);
1913 static void chv_read_luts(struct intel_crtc_state
*crtc_state
)
1915 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1917 if (crtc_state
->cgm_mode
& CGM_PIPE_MODE_GAMMA
)
1918 crtc_state
->hw
.gamma_lut
= chv_read_cgm_gamma(crtc
);
1920 i965_read_luts(crtc_state
);
1923 static struct drm_property_blob
*ilk_read_lut_8(struct intel_crtc
*crtc
)
1925 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1926 enum pipe pipe
= crtc
->pipe
;
1927 struct drm_property_blob
*blob
;
1928 struct drm_color_lut
*lut
;
1931 blob
= drm_property_create_blob(&dev_priv
->drm
,
1932 sizeof(struct drm_color_lut
) * LEGACY_LUT_LENGTH
,
1939 for (i
= 0; i
< LEGACY_LUT_LENGTH
; i
++) {
1940 u32 val
= intel_de_read_fw(dev_priv
, LGC_PALETTE(pipe
, i
));
1942 i9xx_lut_8_pack(&lut
[i
], val
);
1948 static struct drm_property_blob
*ilk_read_lut_10(struct intel_crtc
*crtc
)
1950 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1951 int i
, lut_size
= INTEL_INFO(dev_priv
)->color
.gamma_lut_size
;
1952 enum pipe pipe
= crtc
->pipe
;
1953 struct drm_property_blob
*blob
;
1954 struct drm_color_lut
*lut
;
1956 blob
= drm_property_create_blob(&dev_priv
->drm
,
1957 sizeof(struct drm_color_lut
) * lut_size
,
1964 for (i
= 0; i
< lut_size
; i
++) {
1965 u32 val
= intel_de_read_fw(dev_priv
, PREC_PALETTE(pipe
, i
));
1967 ilk_lut_10_pack(&lut
[i
], val
);
1973 static void ilk_read_luts(struct intel_crtc_state
*crtc_state
)
1975 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1977 if (!crtc_state
->gamma_enable
)
1980 if ((crtc_state
->csc_mode
& CSC_POSITION_BEFORE_GAMMA
) == 0)
1983 switch (crtc_state
->gamma_mode
) {
1984 case GAMMA_MODE_MODE_8BIT
:
1985 crtc_state
->hw
.gamma_lut
= ilk_read_lut_8(crtc
);
1987 case GAMMA_MODE_MODE_10BIT
:
1988 crtc_state
->hw
.gamma_lut
= ilk_read_lut_10(crtc
);
1991 MISSING_CASE(crtc_state
->gamma_mode
);
1996 /* On BDW+ the index auto increment mode actually works */
1997 static struct drm_property_blob
*bdw_read_lut_10(struct intel_crtc
*crtc
,
2000 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2001 int i
, hw_lut_size
= ivb_lut_10_size(prec_index
);
2002 int lut_size
= INTEL_INFO(dev_priv
)->color
.gamma_lut_size
;
2003 enum pipe pipe
= crtc
->pipe
;
2004 struct drm_property_blob
*blob
;
2005 struct drm_color_lut
*lut
;
2007 drm_WARN_ON(&dev_priv
->drm
, lut_size
!= hw_lut_size
);
2009 blob
= drm_property_create_blob(&dev_priv
->drm
,
2010 sizeof(struct drm_color_lut
) * lut_size
,
2017 intel_de_write_fw(dev_priv
, PREC_PAL_INDEX(pipe
),
2018 prec_index
| PAL_PREC_AUTO_INCREMENT
);
2020 for (i
= 0; i
< lut_size
; i
++) {
2021 u32 val
= intel_de_read_fw(dev_priv
, PREC_PAL_DATA(pipe
));
2023 ilk_lut_10_pack(&lut
[i
], val
);
2026 intel_de_write_fw(dev_priv
, PREC_PAL_INDEX(pipe
), 0);
2031 static void glk_read_luts(struct intel_crtc_state
*crtc_state
)
2033 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2035 if (!crtc_state
->gamma_enable
)
2038 switch (crtc_state
->gamma_mode
) {
2039 case GAMMA_MODE_MODE_8BIT
:
2040 crtc_state
->hw
.gamma_lut
= ilk_read_lut_8(crtc
);
2042 case GAMMA_MODE_MODE_10BIT
:
2043 crtc_state
->hw
.gamma_lut
= bdw_read_lut_10(crtc
, PAL_PREC_INDEX_VALUE(0));
2046 MISSING_CASE(crtc_state
->gamma_mode
);
2051 static struct drm_property_blob
*
2052 icl_read_lut_multi_segment(struct intel_crtc
*crtc
)
2054 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2055 int i
, lut_size
= INTEL_INFO(dev_priv
)->color
.gamma_lut_size
;
2056 enum pipe pipe
= crtc
->pipe
;
2057 struct drm_property_blob
*blob
;
2058 struct drm_color_lut
*lut
;
2060 blob
= drm_property_create_blob(&dev_priv
->drm
,
2061 sizeof(struct drm_color_lut
) * lut_size
,
2068 intel_de_write_fw(dev_priv
, PREC_PAL_MULTI_SEG_INDEX(pipe
),
2069 PAL_PREC_AUTO_INCREMENT
);
2071 for (i
= 0; i
< 9; i
++) {
2072 u32 ldw
= intel_de_read_fw(dev_priv
, PREC_PAL_MULTI_SEG_DATA(pipe
));
2073 u32 udw
= intel_de_read_fw(dev_priv
, PREC_PAL_MULTI_SEG_DATA(pipe
));
2075 icl_lut_multi_seg_pack(&lut
[i
], ldw
, udw
);
2078 intel_de_write_fw(dev_priv
, PREC_PAL_MULTI_SEG_INDEX(pipe
), 0);
2081 * FIXME readouts from PAL_PREC_DATA register aren't giving
2082 * correct values in the case of fine and coarse segments.
2083 * Restricting readouts only for super fine segment as of now.
2089 static void icl_read_luts(struct intel_crtc_state
*crtc_state
)
2091 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
2093 if ((crtc_state
->gamma_mode
& POST_CSC_GAMMA_ENABLE
) == 0)
2096 switch (crtc_state
->gamma_mode
& GAMMA_MODE_MODE_MASK
) {
2097 case GAMMA_MODE_MODE_8BIT
:
2098 crtc_state
->hw
.gamma_lut
= ilk_read_lut_8(crtc
);
2100 case GAMMA_MODE_MODE_10BIT
:
2101 crtc_state
->hw
.gamma_lut
= bdw_read_lut_10(crtc
, PAL_PREC_INDEX_VALUE(0));
2103 case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED
:
2104 crtc_state
->hw
.gamma_lut
= icl_read_lut_multi_segment(crtc
);
2107 MISSING_CASE(crtc_state
->gamma_mode
);
2112 void intel_color_init(struct intel_crtc
*crtc
)
2114 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
2115 bool has_ctm
= INTEL_INFO(dev_priv
)->color
.degamma_lut_size
!= 0;
2117 drm_mode_crtc_set_gamma_size(&crtc
->base
, 256);
2119 if (HAS_GMCH(dev_priv
)) {
2120 if (IS_CHERRYVIEW(dev_priv
)) {
2121 dev_priv
->display
.color_check
= chv_color_check
;
2122 dev_priv
->display
.color_commit
= i9xx_color_commit
;
2123 dev_priv
->display
.load_luts
= chv_load_luts
;
2124 dev_priv
->display
.read_luts
= chv_read_luts
;
2125 } else if (DISPLAY_VER(dev_priv
) >= 4) {
2126 dev_priv
->display
.color_check
= i9xx_color_check
;
2127 dev_priv
->display
.color_commit
= i9xx_color_commit
;
2128 dev_priv
->display
.load_luts
= i965_load_luts
;
2129 dev_priv
->display
.read_luts
= i965_read_luts
;
2131 dev_priv
->display
.color_check
= i9xx_color_check
;
2132 dev_priv
->display
.color_commit
= i9xx_color_commit
;
2133 dev_priv
->display
.load_luts
= i9xx_load_luts
;
2134 dev_priv
->display
.read_luts
= i9xx_read_luts
;
2137 if (DISPLAY_VER(dev_priv
) >= 11)
2138 dev_priv
->display
.color_check
= icl_color_check
;
2139 else if (DISPLAY_VER(dev_priv
) >= 10)
2140 dev_priv
->display
.color_check
= glk_color_check
;
2141 else if (DISPLAY_VER(dev_priv
) >= 7)
2142 dev_priv
->display
.color_check
= ivb_color_check
;
2144 dev_priv
->display
.color_check
= ilk_color_check
;
2146 if (DISPLAY_VER(dev_priv
) >= 9)
2147 dev_priv
->display
.color_commit
= skl_color_commit
;
2148 else if (IS_BROADWELL(dev_priv
) || IS_HASWELL(dev_priv
))
2149 dev_priv
->display
.color_commit
= hsw_color_commit
;
2151 dev_priv
->display
.color_commit
= ilk_color_commit
;
2153 if (DISPLAY_VER(dev_priv
) >= 11) {
2154 dev_priv
->display
.load_luts
= icl_load_luts
;
2155 dev_priv
->display
.read_luts
= icl_read_luts
;
2156 } else if (DISPLAY_VER(dev_priv
) == 10) {
2157 dev_priv
->display
.load_luts
= glk_load_luts
;
2158 dev_priv
->display
.read_luts
= glk_read_luts
;
2159 } else if (DISPLAY_VER(dev_priv
) >= 8) {
2160 dev_priv
->display
.load_luts
= bdw_load_luts
;
2161 } else if (DISPLAY_VER(dev_priv
) >= 7) {
2162 dev_priv
->display
.load_luts
= ivb_load_luts
;
2164 dev_priv
->display
.load_luts
= ilk_load_luts
;
2165 dev_priv
->display
.read_luts
= ilk_read_luts
;
2169 drm_crtc_enable_color_mgmt(&crtc
->base
,
2170 INTEL_INFO(dev_priv
)->color
.degamma_lut_size
,
2172 INTEL_INFO(dev_priv
)->color
.gamma_lut_size
);