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drm/i915/gen9_bc: Introduce HPD pin mappings for TGP PCH + CML combos
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / display / intel_ddi.c
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <drm/drm_scdc_helper.h>
29
30 #include "i915_drv.h"
31 #include "i915_trace.h"
32 #include "intel_audio.h"
33 #include "intel_combo_phy.h"
34 #include "intel_connector.h"
35 #include "intel_ddi.h"
36 #include "intel_display_types.h"
37 #include "intel_dp.h"
38 #include "intel_dp_mst.h"
39 #include "intel_dp_link_training.h"
40 #include "intel_dpio_phy.h"
41 #include "intel_dsi.h"
42 #include "intel_fifo_underrun.h"
43 #include "intel_gmbus.h"
44 #include "intel_hdcp.h"
45 #include "intel_hdmi.h"
46 #include "intel_hotplug.h"
47 #include "intel_lspcon.h"
48 #include "intel_panel.h"
49 #include "intel_psr.h"
50 #include "intel_sprite.h"
51 #include "intel_tc.h"
52 #include "intel_vdsc.h"
53
54 struct ddi_buf_trans {
55 u32 trans1; /* balance leg enable, de-emph level */
56 u32 trans2; /* vref sel, vswing */
57 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
58 };
59
60 static const u8 index_to_dp_signal_levels[] = {
61 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
62 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
63 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
64 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
65 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
66 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
67 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
68 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
69 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
70 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
71 };
72
73 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
74 * them for both DP and FDI transports, allowing those ports to
75 * automatically adapt to HDMI connections as well
76 */
77 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
78 { 0x00FFFFFF, 0x0006000E, 0x0 },
79 { 0x00D75FFF, 0x0005000A, 0x0 },
80 { 0x00C30FFF, 0x00040006, 0x0 },
81 { 0x80AAAFFF, 0x000B0000, 0x0 },
82 { 0x00FFFFFF, 0x0005000A, 0x0 },
83 { 0x00D75FFF, 0x000C0004, 0x0 },
84 { 0x80C30FFF, 0x000B0000, 0x0 },
85 { 0x00FFFFFF, 0x00040006, 0x0 },
86 { 0x80D75FFF, 0x000B0000, 0x0 },
87 };
88
89 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
90 { 0x00FFFFFF, 0x0007000E, 0x0 },
91 { 0x00D75FFF, 0x000F000A, 0x0 },
92 { 0x00C30FFF, 0x00060006, 0x0 },
93 { 0x00AAAFFF, 0x001E0000, 0x0 },
94 { 0x00FFFFFF, 0x000F000A, 0x0 },
95 { 0x00D75FFF, 0x00160004, 0x0 },
96 { 0x00C30FFF, 0x001E0000, 0x0 },
97 { 0x00FFFFFF, 0x00060006, 0x0 },
98 { 0x00D75FFF, 0x001E0000, 0x0 },
99 };
100
101 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
102 /* Idx NT mV d T mV d db */
103 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
104 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
105 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
106 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
107 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
108 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
109 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
110 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
111 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
112 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
113 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
114 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
115 };
116
117 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
118 { 0x00FFFFFF, 0x00000012, 0x0 },
119 { 0x00EBAFFF, 0x00020011, 0x0 },
120 { 0x00C71FFF, 0x0006000F, 0x0 },
121 { 0x00AAAFFF, 0x000E000A, 0x0 },
122 { 0x00FFFFFF, 0x00020011, 0x0 },
123 { 0x00DB6FFF, 0x0005000F, 0x0 },
124 { 0x00BEEFFF, 0x000A000C, 0x0 },
125 { 0x00FFFFFF, 0x0005000F, 0x0 },
126 { 0x00DB6FFF, 0x000A000C, 0x0 },
127 };
128
129 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
130 { 0x00FFFFFF, 0x0007000E, 0x0 },
131 { 0x00D75FFF, 0x000E000A, 0x0 },
132 { 0x00BEFFFF, 0x00140006, 0x0 },
133 { 0x80B2CFFF, 0x001B0002, 0x0 },
134 { 0x00FFFFFF, 0x000E000A, 0x0 },
135 { 0x00DB6FFF, 0x00160005, 0x0 },
136 { 0x80C71FFF, 0x001A0002, 0x0 },
137 { 0x00F7DFFF, 0x00180004, 0x0 },
138 { 0x80D75FFF, 0x001B0002, 0x0 },
139 };
140
141 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
142 { 0x00FFFFFF, 0x0001000E, 0x0 },
143 { 0x00D75FFF, 0x0004000A, 0x0 },
144 { 0x00C30FFF, 0x00070006, 0x0 },
145 { 0x00AAAFFF, 0x000C0000, 0x0 },
146 { 0x00FFFFFF, 0x0004000A, 0x0 },
147 { 0x00D75FFF, 0x00090004, 0x0 },
148 { 0x00C30FFF, 0x000C0000, 0x0 },
149 { 0x00FFFFFF, 0x00070006, 0x0 },
150 { 0x00D75FFF, 0x000C0000, 0x0 },
151 };
152
153 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
154 /* Idx NT mV d T mV df db */
155 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
156 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
157 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
158 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
159 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
160 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
161 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
162 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
163 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
164 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
165 };
166
167 /* Skylake H and S */
168 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
169 { 0x00002016, 0x000000A0, 0x0 },
170 { 0x00005012, 0x0000009B, 0x0 },
171 { 0x00007011, 0x00000088, 0x0 },
172 { 0x80009010, 0x000000C0, 0x1 },
173 { 0x00002016, 0x0000009B, 0x0 },
174 { 0x00005012, 0x00000088, 0x0 },
175 { 0x80007011, 0x000000C0, 0x1 },
176 { 0x00002016, 0x000000DF, 0x0 },
177 { 0x80005012, 0x000000C0, 0x1 },
178 };
179
180 /* Skylake U */
181 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
182 { 0x0000201B, 0x000000A2, 0x0 },
183 { 0x00005012, 0x00000088, 0x0 },
184 { 0x80007011, 0x000000CD, 0x1 },
185 { 0x80009010, 0x000000C0, 0x1 },
186 { 0x0000201B, 0x0000009D, 0x0 },
187 { 0x80005012, 0x000000C0, 0x1 },
188 { 0x80007011, 0x000000C0, 0x1 },
189 { 0x00002016, 0x00000088, 0x0 },
190 { 0x80005012, 0x000000C0, 0x1 },
191 };
192
193 /* Skylake Y */
194 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
195 { 0x00000018, 0x000000A2, 0x0 },
196 { 0x00005012, 0x00000088, 0x0 },
197 { 0x80007011, 0x000000CD, 0x3 },
198 { 0x80009010, 0x000000C0, 0x3 },
199 { 0x00000018, 0x0000009D, 0x0 },
200 { 0x80005012, 0x000000C0, 0x3 },
201 { 0x80007011, 0x000000C0, 0x3 },
202 { 0x00000018, 0x00000088, 0x0 },
203 { 0x80005012, 0x000000C0, 0x3 },
204 };
205
206 /* Kabylake H and S */
207 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
208 { 0x00002016, 0x000000A0, 0x0 },
209 { 0x00005012, 0x0000009B, 0x0 },
210 { 0x00007011, 0x00000088, 0x0 },
211 { 0x80009010, 0x000000C0, 0x1 },
212 { 0x00002016, 0x0000009B, 0x0 },
213 { 0x00005012, 0x00000088, 0x0 },
214 { 0x80007011, 0x000000C0, 0x1 },
215 { 0x00002016, 0x00000097, 0x0 },
216 { 0x80005012, 0x000000C0, 0x1 },
217 };
218
219 /* Kabylake U */
220 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
221 { 0x0000201B, 0x000000A1, 0x0 },
222 { 0x00005012, 0x00000088, 0x0 },
223 { 0x80007011, 0x000000CD, 0x3 },
224 { 0x80009010, 0x000000C0, 0x3 },
225 { 0x0000201B, 0x0000009D, 0x0 },
226 { 0x80005012, 0x000000C0, 0x3 },
227 { 0x80007011, 0x000000C0, 0x3 },
228 { 0x00002016, 0x0000004F, 0x0 },
229 { 0x80005012, 0x000000C0, 0x3 },
230 };
231
232 /* Kabylake Y */
233 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
234 { 0x00001017, 0x000000A1, 0x0 },
235 { 0x00005012, 0x00000088, 0x0 },
236 { 0x80007011, 0x000000CD, 0x3 },
237 { 0x8000800F, 0x000000C0, 0x3 },
238 { 0x00001017, 0x0000009D, 0x0 },
239 { 0x80005012, 0x000000C0, 0x3 },
240 { 0x80007011, 0x000000C0, 0x3 },
241 { 0x00001017, 0x0000004C, 0x0 },
242 { 0x80005012, 0x000000C0, 0x3 },
243 };
244
245 /*
246 * Skylake/Kabylake H and S
247 * eDP 1.4 low vswing translation parameters
248 */
249 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
250 { 0x00000018, 0x000000A8, 0x0 },
251 { 0x00004013, 0x000000A9, 0x0 },
252 { 0x00007011, 0x000000A2, 0x0 },
253 { 0x00009010, 0x0000009C, 0x0 },
254 { 0x00000018, 0x000000A9, 0x0 },
255 { 0x00006013, 0x000000A2, 0x0 },
256 { 0x00007011, 0x000000A6, 0x0 },
257 { 0x00000018, 0x000000AB, 0x0 },
258 { 0x00007013, 0x0000009F, 0x0 },
259 { 0x00000018, 0x000000DF, 0x0 },
260 };
261
262 /*
263 * Skylake/Kabylake U
264 * eDP 1.4 low vswing translation parameters
265 */
266 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
267 { 0x00000018, 0x000000A8, 0x0 },
268 { 0x00004013, 0x000000A9, 0x0 },
269 { 0x00007011, 0x000000A2, 0x0 },
270 { 0x00009010, 0x0000009C, 0x0 },
271 { 0x00000018, 0x000000A9, 0x0 },
272 { 0x00006013, 0x000000A2, 0x0 },
273 { 0x00007011, 0x000000A6, 0x0 },
274 { 0x00002016, 0x000000AB, 0x0 },
275 { 0x00005013, 0x0000009F, 0x0 },
276 { 0x00000018, 0x000000DF, 0x0 },
277 };
278
279 /*
280 * Skylake/Kabylake Y
281 * eDP 1.4 low vswing translation parameters
282 */
283 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
284 { 0x00000018, 0x000000A8, 0x0 },
285 { 0x00004013, 0x000000AB, 0x0 },
286 { 0x00007011, 0x000000A4, 0x0 },
287 { 0x00009010, 0x000000DF, 0x0 },
288 { 0x00000018, 0x000000AA, 0x0 },
289 { 0x00006013, 0x000000A4, 0x0 },
290 { 0x00007011, 0x0000009D, 0x0 },
291 { 0x00000018, 0x000000A0, 0x0 },
292 { 0x00006012, 0x000000DF, 0x0 },
293 { 0x00000018, 0x0000008A, 0x0 },
294 };
295
296 /* Skylake/Kabylake U, H and S */
297 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
298 { 0x00000018, 0x000000AC, 0x0 },
299 { 0x00005012, 0x0000009D, 0x0 },
300 { 0x00007011, 0x00000088, 0x0 },
301 { 0x00000018, 0x000000A1, 0x0 },
302 { 0x00000018, 0x00000098, 0x0 },
303 { 0x00004013, 0x00000088, 0x0 },
304 { 0x80006012, 0x000000CD, 0x1 },
305 { 0x00000018, 0x000000DF, 0x0 },
306 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
307 { 0x80003015, 0x000000C0, 0x1 },
308 { 0x80000018, 0x000000C0, 0x1 },
309 };
310
311 /* Skylake/Kabylake Y */
312 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
313 { 0x00000018, 0x000000A1, 0x0 },
314 { 0x00005012, 0x000000DF, 0x0 },
315 { 0x80007011, 0x000000CB, 0x3 },
316 { 0x00000018, 0x000000A4, 0x0 },
317 { 0x00000018, 0x0000009D, 0x0 },
318 { 0x00004013, 0x00000080, 0x0 },
319 { 0x80006013, 0x000000C0, 0x3 },
320 { 0x00000018, 0x0000008A, 0x0 },
321 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
322 { 0x80003015, 0x000000C0, 0x3 },
323 { 0x80000018, 0x000000C0, 0x3 },
324 };
325
326 struct bxt_ddi_buf_trans {
327 u8 margin; /* swing value */
328 u8 scale; /* scale value */
329 u8 enable; /* scale enable */
330 u8 deemphasis;
331 };
332
333 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
334 /* Idx NT mV diff db */
335 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
336 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
337 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
338 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
339 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
340 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
341 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
342 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
343 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
344 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
345 };
346
347 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
348 /* Idx NT mV diff db */
349 { 26, 0, 0, 128, }, /* 0: 200 0 */
350 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
351 { 48, 0, 0, 96, }, /* 2: 200 4 */
352 { 54, 0, 0, 69, }, /* 3: 200 6 */
353 { 32, 0, 0, 128, }, /* 4: 250 0 */
354 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
355 { 54, 0, 0, 85, }, /* 6: 250 4 */
356 { 43, 0, 0, 128, }, /* 7: 300 0 */
357 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
358 { 48, 0, 0, 128, }, /* 9: 300 0 */
359 };
360
361 /* BSpec has 2 recommended values - entries 0 and 8.
362 * Using the entry with higher vswing.
363 */
364 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
365 /* Idx NT mV diff db */
366 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
367 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
368 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
369 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
370 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
371 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
372 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
373 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
374 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
375 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
376 };
377
378 struct cnl_ddi_buf_trans {
379 u8 dw2_swing_sel;
380 u8 dw7_n_scalar;
381 u8 dw4_cursor_coeff;
382 u8 dw4_post_cursor_2;
383 u8 dw4_post_cursor_1;
384 };
385
386 /* Voltage Swing Programming for VccIO 0.85V for DP */
387 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
388 /* NT mV Trans mV db */
389 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
390 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
391 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
392 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
393 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
394 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
395 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
396 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
397 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
398 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
399 };
400
401 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
402 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
403 /* NT mV Trans mV db */
404 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
405 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
406 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
407 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
408 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
409 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
410 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
411 };
412
413 /* Voltage Swing Programming for VccIO 0.85V for eDP */
414 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
415 /* NT mV Trans mV db */
416 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
417 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
418 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
419 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
420 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
421 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
422 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
423 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
424 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
425 };
426
427 /* Voltage Swing Programming for VccIO 0.95V for DP */
428 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
429 /* NT mV Trans mV db */
430 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
431 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
432 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
433 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
434 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
435 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
436 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
437 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
438 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
439 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
440 };
441
442 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
443 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
444 /* NT mV Trans mV db */
445 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
446 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
447 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
448 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
449 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
450 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
451 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
452 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
453 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
454 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
455 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
456 };
457
458 /* Voltage Swing Programming for VccIO 0.95V for eDP */
459 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
460 /* NT mV Trans mV db */
461 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
462 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
463 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
464 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
465 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
466 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
467 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
468 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
469 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
470 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
471 };
472
473 /* Voltage Swing Programming for VccIO 1.05V for DP */
474 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
475 /* NT mV Trans mV db */
476 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
477 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
478 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
479 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
480 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
481 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
482 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
483 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
484 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
485 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
486 };
487
488 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
489 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
490 /* NT mV Trans mV db */
491 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
492 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
493 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
494 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
495 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
496 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
497 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
498 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
499 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
500 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
501 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
502 };
503
504 /* Voltage Swing Programming for VccIO 1.05V for eDP */
505 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
506 /* NT mV Trans mV db */
507 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
508 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
509 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
510 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
511 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
512 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
513 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
514 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
515 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
516 };
517
518 /* icl_combo_phy_ddi_translations */
519 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
520 /* NT mV Trans mV db */
521 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
522 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
523 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
524 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
525 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
526 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
527 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
528 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
529 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
530 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
531 };
532
533 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
534 /* NT mV Trans mV db */
535 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
536 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
537 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
538 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
539 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
540 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
541 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
542 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
543 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
544 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
545 };
546
547 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
548 /* NT mV Trans mV db */
549 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
550 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
551 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
552 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
553 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
554 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
555 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
556 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
557 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
558 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
559 };
560
561 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
562 /* NT mV Trans mV db */
563 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
564 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
565 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
566 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
567 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
568 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
569 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
570 };
571
572 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
573 /* NT mV Trans mV db */
574 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
575 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
576 { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */
577 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */
578 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
579 { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */
580 { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
581 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
582 { 0x6, 0x7F, 0x38, 0x00, 0x07 }, /* 600 900 3.5 */
583 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
584 };
585
586 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
587 /* NT mV Trans mV db */
588 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
589 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
590 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
591 { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */
592 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
593 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
594 { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
595 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
596 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
597 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
598 };
599
600 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
601 /* NT mV Trans mV db */
602 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
603 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */
604 { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */
605 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */
606 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
607 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */
608 { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */
609 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
610 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
611 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
612 };
613
614 struct icl_mg_phy_ddi_buf_trans {
615 u32 cri_txdeemph_override_11_6;
616 u32 cri_txdeemph_override_5_0;
617 u32 cri_txdeemph_override_17_12;
618 };
619
620 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
621 /* Voltage swing pre-emphasis */
622 { 0x18, 0x00, 0x00 }, /* 0 0 */
623 { 0x1D, 0x00, 0x05 }, /* 0 1 */
624 { 0x24, 0x00, 0x0C }, /* 0 2 */
625 { 0x2B, 0x00, 0x14 }, /* 0 3 */
626 { 0x21, 0x00, 0x00 }, /* 1 0 */
627 { 0x2B, 0x00, 0x08 }, /* 1 1 */
628 { 0x30, 0x00, 0x0F }, /* 1 2 */
629 { 0x31, 0x00, 0x03 }, /* 2 0 */
630 { 0x34, 0x00, 0x0B }, /* 2 1 */
631 { 0x3F, 0x00, 0x00 }, /* 3 0 */
632 };
633
634 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
635 /* Voltage swing pre-emphasis */
636 { 0x18, 0x00, 0x00 }, /* 0 0 */
637 { 0x1D, 0x00, 0x05 }, /* 0 1 */
638 { 0x24, 0x00, 0x0C }, /* 0 2 */
639 { 0x2B, 0x00, 0x14 }, /* 0 3 */
640 { 0x26, 0x00, 0x00 }, /* 1 0 */
641 { 0x2C, 0x00, 0x07 }, /* 1 1 */
642 { 0x33, 0x00, 0x0C }, /* 1 2 */
643 { 0x2E, 0x00, 0x00 }, /* 2 0 */
644 { 0x36, 0x00, 0x09 }, /* 2 1 */
645 { 0x3F, 0x00, 0x00 }, /* 3 0 */
646 };
647
648 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
649 /* HDMI Preset VS Pre-emph */
650 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */
651 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */
652 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */
653 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */
654 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */
655 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */
656 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */
657 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */
658 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */
659 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */
660 };
661
662 struct tgl_dkl_phy_ddi_buf_trans {
663 u32 dkl_vswing_control;
664 u32 dkl_preshoot_control;
665 u32 dkl_de_emphasis_control;
666 };
667
668 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
669 /* VS pre-emp Non-trans mV Pre-emph dB */
670 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
671 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */
672 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
673 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */
674 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
675 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
676 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
677 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
678 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
679 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
680 };
681
682 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = {
683 /* VS pre-emp Non-trans mV Pre-emph dB */
684 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
685 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */
686 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
687 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */
688 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
689 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
690 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
691 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
692 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
693 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
694 };
695
696 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
697 /* HDMI Preset VS Pre-emph */
698 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */
699 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */
700 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */
701 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */
702 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */
703 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */
704 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */
705 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */
706 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */
707 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
708 };
709
710 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
711 /* NT mV Trans mV db */
712 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
713 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
714 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
715 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
716 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
717 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
718 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
719 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
720 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
721 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
722 };
723
724 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
725 /* NT mV Trans mV db */
726 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
727 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
728 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
729 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
730 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
731 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
732 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
733 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
734 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
735 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
736 };
737
738 static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
739 /* NT mV Trans mV db */
740 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
741 { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
742 { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
743 { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
744 { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
745 { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
746 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
747 { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
748 { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
749 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
750 };
751
752 /*
753 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
754 * that DisplayPort specification requires
755 */
756 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
757 /* VS pre-emp */
758 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */
759 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */
760 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */
761 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */
762 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */
763 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */
764 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */
765 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */
766 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */
767 };
768
769 static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
770 {
771 return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
772 }
773
774 static const struct ddi_buf_trans *
775 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
776 {
777 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
778
779 if (dev_priv->vbt.edp.low_vswing) {
780 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
781 return bdw_ddi_translations_edp;
782 } else {
783 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
784 return bdw_ddi_translations_dp;
785 }
786 }
787
788 static const struct ddi_buf_trans *
789 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
790 {
791 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
792
793 if (IS_SKL_ULX(dev_priv)) {
794 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
795 return skl_y_ddi_translations_dp;
796 } else if (IS_SKL_ULT(dev_priv)) {
797 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
798 return skl_u_ddi_translations_dp;
799 } else {
800 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
801 return skl_ddi_translations_dp;
802 }
803 }
804
805 static const struct ddi_buf_trans *
806 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
807 {
808 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
809
810 if (IS_KBL_ULX(dev_priv) ||
811 IS_CFL_ULX(dev_priv) ||
812 IS_CML_ULX(dev_priv)) {
813 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
814 return kbl_y_ddi_translations_dp;
815 } else if (IS_KBL_ULT(dev_priv) ||
816 IS_CFL_ULT(dev_priv) ||
817 IS_CML_ULT(dev_priv)) {
818 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
819 return kbl_u_ddi_translations_dp;
820 } else {
821 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
822 return kbl_ddi_translations_dp;
823 }
824 }
825
826 static const struct ddi_buf_trans *
827 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
828 {
829 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
830
831 if (dev_priv->vbt.edp.low_vswing) {
832 if (IS_SKL_ULX(dev_priv) ||
833 IS_KBL_ULX(dev_priv) ||
834 IS_CFL_ULX(dev_priv) ||
835 IS_CML_ULX(dev_priv)) {
836 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
837 return skl_y_ddi_translations_edp;
838 } else if (IS_SKL_ULT(dev_priv) ||
839 IS_KBL_ULT(dev_priv) ||
840 IS_CFL_ULT(dev_priv) ||
841 IS_CML_ULT(dev_priv)) {
842 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
843 return skl_u_ddi_translations_edp;
844 } else {
845 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
846 return skl_ddi_translations_edp;
847 }
848 }
849
850 if (IS_KABYLAKE(dev_priv) ||
851 IS_COFFEELAKE(dev_priv) ||
852 IS_COMETLAKE(dev_priv))
853 return kbl_get_buf_trans_dp(encoder, n_entries);
854 else
855 return skl_get_buf_trans_dp(encoder, n_entries);
856 }
857
858 static const struct ddi_buf_trans *
859 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
860 {
861 if (IS_SKL_ULX(dev_priv) ||
862 IS_KBL_ULX(dev_priv) ||
863 IS_CFL_ULX(dev_priv) ||
864 IS_CML_ULX(dev_priv)) {
865 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
866 return skl_y_ddi_translations_hdmi;
867 } else {
868 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
869 return skl_ddi_translations_hdmi;
870 }
871 }
872
873 static int skl_buf_trans_num_entries(enum port port, int n_entries)
874 {
875 /* Only DDIA and DDIE can select the 10th register with DP */
876 if (port == PORT_A || port == PORT_E)
877 return min(n_entries, 10);
878 else
879 return min(n_entries, 9);
880 }
881
882 static const struct ddi_buf_trans *
883 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
884 {
885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
886
887 if (IS_KABYLAKE(dev_priv) ||
888 IS_COFFEELAKE(dev_priv) ||
889 IS_COMETLAKE(dev_priv)) {
890 const struct ddi_buf_trans *ddi_translations =
891 kbl_get_buf_trans_dp(encoder, n_entries);
892 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
893 return ddi_translations;
894 } else if (IS_SKYLAKE(dev_priv)) {
895 const struct ddi_buf_trans *ddi_translations =
896 skl_get_buf_trans_dp(encoder, n_entries);
897 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
898 return ddi_translations;
899 } else if (IS_BROADWELL(dev_priv)) {
900 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
901 return bdw_ddi_translations_dp;
902 } else if (IS_HASWELL(dev_priv)) {
903 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
904 return hsw_ddi_translations_dp;
905 }
906
907 *n_entries = 0;
908 return NULL;
909 }
910
911 static const struct ddi_buf_trans *
912 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
913 {
914 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
915
916 if (IS_GEN9_BC(dev_priv)) {
917 const struct ddi_buf_trans *ddi_translations =
918 skl_get_buf_trans_edp(encoder, n_entries);
919 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
920 return ddi_translations;
921 } else if (IS_BROADWELL(dev_priv)) {
922 return bdw_get_buf_trans_edp(encoder, n_entries);
923 } else if (IS_HASWELL(dev_priv)) {
924 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
925 return hsw_ddi_translations_dp;
926 }
927
928 *n_entries = 0;
929 return NULL;
930 }
931
932 static const struct ddi_buf_trans *
933 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
934 int *n_entries)
935 {
936 if (IS_BROADWELL(dev_priv)) {
937 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
938 return bdw_ddi_translations_fdi;
939 } else if (IS_HASWELL(dev_priv)) {
940 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
941 return hsw_ddi_translations_fdi;
942 }
943
944 *n_entries = 0;
945 return NULL;
946 }
947
948 static const struct ddi_buf_trans *
949 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
950 int *n_entries)
951 {
952 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
953
954 if (IS_GEN9_BC(dev_priv)) {
955 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
956 } else if (IS_BROADWELL(dev_priv)) {
957 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
958 return bdw_ddi_translations_hdmi;
959 } else if (IS_HASWELL(dev_priv)) {
960 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
961 return hsw_ddi_translations_hdmi;
962 }
963
964 *n_entries = 0;
965 return NULL;
966 }
967
968 static const struct bxt_ddi_buf_trans *
969 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
970 {
971 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
972 return bxt_ddi_translations_dp;
973 }
974
975 static const struct bxt_ddi_buf_trans *
976 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
977 {
978 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
979
980 if (dev_priv->vbt.edp.low_vswing) {
981 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
982 return bxt_ddi_translations_edp;
983 }
984
985 return bxt_get_buf_trans_dp(encoder, n_entries);
986 }
987
988 static const struct bxt_ddi_buf_trans *
989 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
990 {
991 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
992 return bxt_ddi_translations_hdmi;
993 }
994
995 static const struct cnl_ddi_buf_trans *
996 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
997 {
998 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
999 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1000
1001 if (voltage == VOLTAGE_INFO_0_85V) {
1002 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
1003 return cnl_ddi_translations_hdmi_0_85V;
1004 } else if (voltage == VOLTAGE_INFO_0_95V) {
1005 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
1006 return cnl_ddi_translations_hdmi_0_95V;
1007 } else if (voltage == VOLTAGE_INFO_1_05V) {
1008 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
1009 return cnl_ddi_translations_hdmi_1_05V;
1010 } else {
1011 *n_entries = 1; /* shut up gcc */
1012 MISSING_CASE(voltage);
1013 }
1014 return NULL;
1015 }
1016
1017 static const struct cnl_ddi_buf_trans *
1018 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
1019 {
1020 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1021 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1022
1023 if (voltage == VOLTAGE_INFO_0_85V) {
1024 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
1025 return cnl_ddi_translations_dp_0_85V;
1026 } else if (voltage == VOLTAGE_INFO_0_95V) {
1027 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
1028 return cnl_ddi_translations_dp_0_95V;
1029 } else if (voltage == VOLTAGE_INFO_1_05V) {
1030 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1031 return cnl_ddi_translations_dp_1_05V;
1032 } else {
1033 *n_entries = 1; /* shut up gcc */
1034 MISSING_CASE(voltage);
1035 }
1036 return NULL;
1037 }
1038
1039 static const struct cnl_ddi_buf_trans *
1040 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
1041 {
1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1043 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1044
1045 if (dev_priv->vbt.edp.low_vswing) {
1046 if (voltage == VOLTAGE_INFO_0_85V) {
1047 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1048 return cnl_ddi_translations_edp_0_85V;
1049 } else if (voltage == VOLTAGE_INFO_0_95V) {
1050 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1051 return cnl_ddi_translations_edp_0_95V;
1052 } else if (voltage == VOLTAGE_INFO_1_05V) {
1053 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1054 return cnl_ddi_translations_edp_1_05V;
1055 } else {
1056 *n_entries = 1; /* shut up gcc */
1057 MISSING_CASE(voltage);
1058 }
1059 return NULL;
1060 } else {
1061 return cnl_get_buf_trans_dp(encoder, n_entries);
1062 }
1063 }
1064
1065 static const struct cnl_ddi_buf_trans *
1066 icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1067 const struct intel_crtc_state *crtc_state,
1068 int *n_entries)
1069 {
1070 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1071 return icl_combo_phy_ddi_translations_hdmi;
1072 }
1073
1074 static const struct cnl_ddi_buf_trans *
1075 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1076 const struct intel_crtc_state *crtc_state,
1077 int *n_entries)
1078 {
1079 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1080 return icl_combo_phy_ddi_translations_dp_hbr2;
1081 }
1082
1083 static const struct cnl_ddi_buf_trans *
1084 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1085 const struct intel_crtc_state *crtc_state,
1086 int *n_entries)
1087 {
1088 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1089
1090 if (crtc_state->port_clock > 540000) {
1091 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1092 return icl_combo_phy_ddi_translations_edp_hbr3;
1093 } else if (dev_priv->vbt.edp.low_vswing) {
1094 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1095 return icl_combo_phy_ddi_translations_edp_hbr2;
1096 }
1097
1098 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1099 }
1100
1101 static const struct cnl_ddi_buf_trans *
1102 icl_get_combo_buf_trans(struct intel_encoder *encoder,
1103 const struct intel_crtc_state *crtc_state,
1104 int *n_entries)
1105 {
1106 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1107 return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1108 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1109 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1110 else
1111 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1112 }
1113
1114 static const struct icl_mg_phy_ddi_buf_trans *
1115 icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder,
1116 const struct intel_crtc_state *crtc_state,
1117 int *n_entries)
1118 {
1119 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
1120 return icl_mg_phy_ddi_translations_hdmi;
1121 }
1122
1123 static const struct icl_mg_phy_ddi_buf_trans *
1124 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
1125 const struct intel_crtc_state *crtc_state,
1126 int *n_entries)
1127 {
1128 if (crtc_state->port_clock > 270000) {
1129 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
1130 return icl_mg_phy_ddi_translations_hbr2_hbr3;
1131 } else {
1132 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
1133 return icl_mg_phy_ddi_translations_rbr_hbr;
1134 }
1135 }
1136
1137 static const struct icl_mg_phy_ddi_buf_trans *
1138 icl_get_mg_buf_trans(struct intel_encoder *encoder,
1139 const struct intel_crtc_state *crtc_state,
1140 int *n_entries)
1141 {
1142 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1143 return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries);
1144 else
1145 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
1146 }
1147
1148 static const struct cnl_ddi_buf_trans *
1149 ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1150 const struct intel_crtc_state *crtc_state,
1151 int *n_entries)
1152 {
1153 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1154 return icl_combo_phy_ddi_translations_hdmi;
1155 }
1156
1157 static const struct cnl_ddi_buf_trans *
1158 ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1159 const struct intel_crtc_state *crtc_state,
1160 int *n_entries)
1161 {
1162 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
1163 return ehl_combo_phy_ddi_translations_dp;
1164 }
1165
1166 static const struct cnl_ddi_buf_trans *
1167 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1168 const struct intel_crtc_state *crtc_state,
1169 int *n_entries)
1170 {
1171 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1172
1173 if (dev_priv->vbt.edp.low_vswing) {
1174 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1175 return icl_combo_phy_ddi_translations_edp_hbr2;
1176 }
1177
1178 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1179 }
1180
1181 static const struct cnl_ddi_buf_trans *
1182 ehl_get_combo_buf_trans(struct intel_encoder *encoder,
1183 const struct intel_crtc_state *crtc_state,
1184 int *n_entries)
1185 {
1186 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1187 return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1188 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1189 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1190 else
1191 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1192 }
1193
1194 static const struct cnl_ddi_buf_trans *
1195 jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1196 const struct intel_crtc_state *crtc_state,
1197 int *n_entries)
1198 {
1199 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1200 return icl_combo_phy_ddi_translations_hdmi;
1201 }
1202
1203 static const struct cnl_ddi_buf_trans *
1204 jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1205 const struct intel_crtc_state *crtc_state,
1206 int *n_entries)
1207 {
1208 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1209 return icl_combo_phy_ddi_translations_dp_hbr2;
1210 }
1211
1212 static const struct cnl_ddi_buf_trans *
1213 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1214 const struct intel_crtc_state *crtc_state,
1215 int *n_entries)
1216 {
1217 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1218
1219 if (dev_priv->vbt.edp.low_vswing) {
1220 if (crtc_state->port_clock > 270000) {
1221 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
1222 return jsl_combo_phy_ddi_translations_edp_hbr2;
1223 } else {
1224 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
1225 return jsl_combo_phy_ddi_translations_edp_hbr;
1226 }
1227 }
1228
1229 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1230 }
1231
1232 static const struct cnl_ddi_buf_trans *
1233 jsl_get_combo_buf_trans(struct intel_encoder *encoder,
1234 const struct intel_crtc_state *crtc_state,
1235 int *n_entries)
1236 {
1237 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1238 return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1239 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1240 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1241 else
1242 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1243 }
1244
1245 static const struct cnl_ddi_buf_trans *
1246 tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
1247 const struct intel_crtc_state *crtc_state,
1248 int *n_entries)
1249 {
1250 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1251 return icl_combo_phy_ddi_translations_hdmi;
1252 }
1253
1254 static const struct cnl_ddi_buf_trans *
1255 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1256 const struct intel_crtc_state *crtc_state,
1257 int *n_entries)
1258 {
1259 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1260
1261 if (crtc_state->port_clock > 270000) {
1262 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
1263 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
1264 return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
1265 } else {
1266 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
1267 return tgl_combo_phy_ddi_translations_dp_hbr2;
1268 }
1269 } else {
1270 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
1271 return tgl_combo_phy_ddi_translations_dp_hbr;
1272 }
1273 }
1274
1275 static const struct cnl_ddi_buf_trans *
1276 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1277 const struct intel_crtc_state *crtc_state,
1278 int *n_entries)
1279 {
1280 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1281 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1282
1283 if (crtc_state->port_clock > 540000) {
1284 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1285 return icl_combo_phy_ddi_translations_edp_hbr3;
1286 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
1287 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
1288 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
1289 } else if (dev_priv->vbt.edp.low_vswing) {
1290 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1291 return icl_combo_phy_ddi_translations_edp_hbr2;
1292 }
1293
1294 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1295 }
1296
1297 static const struct cnl_ddi_buf_trans *
1298 tgl_get_combo_buf_trans(struct intel_encoder *encoder,
1299 const struct intel_crtc_state *crtc_state,
1300 int *n_entries)
1301 {
1302 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1303 return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
1304 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1305 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1306 else
1307 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1308 }
1309
1310 static const struct tgl_dkl_phy_ddi_buf_trans *
1311 tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder,
1312 const struct intel_crtc_state *crtc_state,
1313 int *n_entries)
1314 {
1315 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
1316 return tgl_dkl_phy_hdmi_ddi_trans;
1317 }
1318
1319 static const struct tgl_dkl_phy_ddi_buf_trans *
1320 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1321 const struct intel_crtc_state *crtc_state,
1322 int *n_entries)
1323 {
1324 if (crtc_state->port_clock > 270000) {
1325 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
1326 return tgl_dkl_phy_dp_ddi_trans_hbr2;
1327 } else {
1328 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
1329 return tgl_dkl_phy_dp_ddi_trans;
1330 }
1331 }
1332
1333 static const struct tgl_dkl_phy_ddi_buf_trans *
1334 tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
1335 const struct intel_crtc_state *crtc_state,
1336 int *n_entries)
1337 {
1338 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1339 return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
1340 else
1341 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1342 }
1343
1344 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
1345 const struct intel_crtc_state *crtc_state)
1346 {
1347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1348 int n_entries, level, default_entry;
1349 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1350
1351 if (INTEL_GEN(dev_priv) >= 12) {
1352 if (intel_phy_is_combo(dev_priv, phy))
1353 tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1354 else
1355 tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1356 default_entry = n_entries - 1;
1357 } else if (INTEL_GEN(dev_priv) == 11) {
1358 if (intel_phy_is_combo(dev_priv, phy))
1359 icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1360 else
1361 icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
1362 default_entry = n_entries - 1;
1363 } else if (IS_CANNONLAKE(dev_priv)) {
1364 cnl_get_buf_trans_hdmi(encoder, &n_entries);
1365 default_entry = n_entries - 1;
1366 } else if (IS_GEN9_LP(dev_priv)) {
1367 bxt_get_buf_trans_hdmi(encoder, &n_entries);
1368 default_entry = n_entries - 1;
1369 } else if (IS_GEN9_BC(dev_priv)) {
1370 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1371 default_entry = 8;
1372 } else if (IS_BROADWELL(dev_priv)) {
1373 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1374 default_entry = 7;
1375 } else if (IS_HASWELL(dev_priv)) {
1376 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1377 default_entry = 6;
1378 } else {
1379 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1380 return 0;
1381 }
1382
1383 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1384 return 0;
1385
1386 level = intel_bios_hdmi_level_shift(encoder);
1387 if (level < 0)
1388 level = default_entry;
1389
1390 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1391 level = n_entries - 1;
1392
1393 return level;
1394 }
1395
1396 /*
1397 * Starting with Haswell, DDI port buffers must be programmed with correct
1398 * values in advance. This function programs the correct values for
1399 * DP/eDP/FDI use cases.
1400 */
1401 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
1402 const struct intel_crtc_state *crtc_state)
1403 {
1404 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1405 u32 iboost_bit = 0;
1406 int i, n_entries;
1407 enum port port = encoder->port;
1408 const struct ddi_buf_trans *ddi_translations;
1409
1410 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1411 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
1412 &n_entries);
1413 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1414 ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
1415 &n_entries);
1416 else
1417 ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
1418 &n_entries);
1419
1420 /* If we're boosting the current, set bit 31 of trans1 */
1421 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
1422 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1423
1424 for (i = 0; i < n_entries; i++) {
1425 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
1426 ddi_translations[i].trans1 | iboost_bit);
1427 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
1428 ddi_translations[i].trans2);
1429 }
1430 }
1431
1432 /*
1433 * Starting with Haswell, DDI port buffers must be programmed with correct
1434 * values in advance. This function programs the correct values for
1435 * HDMI/DVI use cases.
1436 */
1437 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1438 int level)
1439 {
1440 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1441 u32 iboost_bit = 0;
1442 int n_entries;
1443 enum port port = encoder->port;
1444 const struct ddi_buf_trans *ddi_translations;
1445
1446 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1447
1448 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1449 return;
1450 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1451 level = n_entries - 1;
1452
1453 /* If we're boosting the current, set bit 31 of trans1 */
1454 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
1455 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1456
1457 /* Entry 9 is for HDMI: */
1458 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
1459 ddi_translations[level].trans1 | iboost_bit);
1460 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
1461 ddi_translations[level].trans2);
1462 }
1463
1464 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1465 enum port port)
1466 {
1467 if (IS_BROXTON(dev_priv)) {
1468 udelay(16);
1469 return;
1470 }
1471
1472 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1473 DDI_BUF_IS_IDLE), 8))
1474 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
1475 port_name(port));
1476 }
1477
1478 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
1479 enum port port)
1480 {
1481 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
1482 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
1483 usleep_range(518, 1000);
1484 return;
1485 }
1486
1487 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1488 DDI_BUF_IS_IDLE), 500))
1489 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
1490 port_name(port));
1491 }
1492
1493 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1494 {
1495 switch (pll->info->id) {
1496 case DPLL_ID_WRPLL1:
1497 return PORT_CLK_SEL_WRPLL1;
1498 case DPLL_ID_WRPLL2:
1499 return PORT_CLK_SEL_WRPLL2;
1500 case DPLL_ID_SPLL:
1501 return PORT_CLK_SEL_SPLL;
1502 case DPLL_ID_LCPLL_810:
1503 return PORT_CLK_SEL_LCPLL_810;
1504 case DPLL_ID_LCPLL_1350:
1505 return PORT_CLK_SEL_LCPLL_1350;
1506 case DPLL_ID_LCPLL_2700:
1507 return PORT_CLK_SEL_LCPLL_2700;
1508 default:
1509 MISSING_CASE(pll->info->id);
1510 return PORT_CLK_SEL_NONE;
1511 }
1512 }
1513
1514 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1515 const struct intel_crtc_state *crtc_state)
1516 {
1517 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1518 int clock = crtc_state->port_clock;
1519 const enum intel_dpll_id id = pll->info->id;
1520
1521 switch (id) {
1522 default:
1523 /*
1524 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1525 * here, so do warn if this get passed in
1526 */
1527 MISSING_CASE(id);
1528 return DDI_CLK_SEL_NONE;
1529 case DPLL_ID_ICL_TBTPLL:
1530 switch (clock) {
1531 case 162000:
1532 return DDI_CLK_SEL_TBT_162;
1533 case 270000:
1534 return DDI_CLK_SEL_TBT_270;
1535 case 540000:
1536 return DDI_CLK_SEL_TBT_540;
1537 case 810000:
1538 return DDI_CLK_SEL_TBT_810;
1539 default:
1540 MISSING_CASE(clock);
1541 return DDI_CLK_SEL_NONE;
1542 }
1543 case DPLL_ID_ICL_MGPLL1:
1544 case DPLL_ID_ICL_MGPLL2:
1545 case DPLL_ID_ICL_MGPLL3:
1546 case DPLL_ID_ICL_MGPLL4:
1547 case DPLL_ID_TGL_MGPLL5:
1548 case DPLL_ID_TGL_MGPLL6:
1549 return DDI_CLK_SEL_MG;
1550 }
1551 }
1552
1553 /* Starting with Haswell, different DDI ports can work in FDI mode for
1554 * connection to the PCH-located connectors. For this, it is necessary to train
1555 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1556 *
1557 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1558 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1559 * DDI A (which is used for eDP)
1560 */
1561
1562 void hsw_fdi_link_train(struct intel_encoder *encoder,
1563 const struct intel_crtc_state *crtc_state)
1564 {
1565 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1566 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1567 u32 temp, i, rx_ctl_val, ddi_pll_sel;
1568
1569 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1570
1571 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1572 * mode set "sequence for CRT port" document:
1573 * - TP1 to TP2 time with the default value
1574 * - FDI delay to 90h
1575 *
1576 * WaFDIAutoLinkSetTimingOverrride:hsw
1577 */
1578 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
1579 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1580
1581 /* Enable the PCH Receiver FDI PLL */
1582 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1583 FDI_RX_PLL_ENABLE |
1584 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1585 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1586 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1587 udelay(220);
1588
1589 /* Switch from Rawclk to PCDclk */
1590 rx_ctl_val |= FDI_PCDCLK;
1591 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1592
1593 /* Configure Port Clock Select */
1594 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1595 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1596 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
1597
1598 /* Start the training iterating through available voltages and emphasis,
1599 * testing each value twice. */
1600 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1601 /* Configure DP_TP_CTL with auto-training */
1602 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1603 DP_TP_CTL_FDI_AUTOTRAIN |
1604 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1605 DP_TP_CTL_LINK_TRAIN_PAT1 |
1606 DP_TP_CTL_ENABLE);
1607
1608 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1609 * DDI E does not support port reversal, the functionality is
1610 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1611 * port reversal bit */
1612 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
1613 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
1614 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1615
1616 udelay(600);
1617
1618 /* Program PCH FDI Receiver TU */
1619 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1620
1621 /* Enable PCH FDI Receiver with auto-training */
1622 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1623 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1624 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1625
1626 /* Wait for FDI receiver lane calibration */
1627 udelay(30);
1628
1629 /* Unset FDI_RX_MISC pwrdn lanes */
1630 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1631 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1632 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1633 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1634
1635 /* Wait for FDI auto training time */
1636 udelay(5);
1637
1638 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
1639 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1640 drm_dbg_kms(&dev_priv->drm,
1641 "FDI link training done on step %d\n", i);
1642 break;
1643 }
1644
1645 /*
1646 * Leave things enabled even if we failed to train FDI.
1647 * Results in less fireworks from the state checker.
1648 */
1649 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1650 drm_err(&dev_priv->drm, "FDI link training failed!\n");
1651 break;
1652 }
1653
1654 rx_ctl_val &= ~FDI_RX_ENABLE;
1655 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1656 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1657
1658 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
1659 temp &= ~DDI_BUF_CTL_ENABLE;
1660 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
1661 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1662
1663 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1664 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
1665 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1666 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1667 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
1668 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
1669
1670 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1671
1672 /* Reset FDI_RX_MISC pwrdn lanes */
1673 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1674 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1675 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1676 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1677 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1678 }
1679
1680 /* Enable normal pixel sending for FDI */
1681 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1682 DP_TP_CTL_FDI_AUTOTRAIN |
1683 DP_TP_CTL_LINK_TRAIN_NORMAL |
1684 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1685 DP_TP_CTL_ENABLE);
1686 }
1687
1688 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
1689 const struct intel_crtc_state *crtc_state)
1690 {
1691 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1692 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1693
1694 intel_dp->DP = dig_port->saved_port_bits |
1695 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1696 intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
1697 }
1698
1699 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1700 enum port port)
1701 {
1702 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1703
1704 switch (val) {
1705 case DDI_CLK_SEL_NONE:
1706 return 0;
1707 case DDI_CLK_SEL_TBT_162:
1708 return 162000;
1709 case DDI_CLK_SEL_TBT_270:
1710 return 270000;
1711 case DDI_CLK_SEL_TBT_540:
1712 return 540000;
1713 case DDI_CLK_SEL_TBT_810:
1714 return 810000;
1715 default:
1716 MISSING_CASE(val);
1717 return 0;
1718 }
1719 }
1720
1721 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1722 {
1723 int dotclock;
1724
1725 if (pipe_config->has_pch_encoder)
1726 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1727 &pipe_config->fdi_m_n);
1728 else if (intel_crtc_has_dp_encoder(pipe_config))
1729 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1730 &pipe_config->dp_m_n);
1731 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1732 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1733 else
1734 dotclock = pipe_config->port_clock;
1735
1736 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1737 !intel_crtc_has_dp_encoder(pipe_config))
1738 dotclock *= 2;
1739
1740 if (pipe_config->pixel_multiplier)
1741 dotclock /= pipe_config->pixel_multiplier;
1742
1743 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1744 }
1745
1746 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1747 struct intel_crtc_state *pipe_config)
1748 {
1749 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1750 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1751
1752 if (intel_phy_is_tc(dev_priv, phy) &&
1753 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
1754 DPLL_ID_ICL_TBTPLL)
1755 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
1756 encoder->port);
1757 else
1758 pipe_config->port_clock =
1759 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll,
1760 &pipe_config->dpll_hw_state);
1761
1762 ddi_dotclock_get(pipe_config);
1763 }
1764
1765 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1766 const struct drm_connector_state *conn_state)
1767 {
1768 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1770 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1771 u32 temp;
1772
1773 if (!intel_crtc_has_dp_encoder(crtc_state))
1774 return;
1775
1776 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
1777
1778 temp = DP_MSA_MISC_SYNC_CLOCK;
1779
1780 switch (crtc_state->pipe_bpp) {
1781 case 18:
1782 temp |= DP_MSA_MISC_6_BPC;
1783 break;
1784 case 24:
1785 temp |= DP_MSA_MISC_8_BPC;
1786 break;
1787 case 30:
1788 temp |= DP_MSA_MISC_10_BPC;
1789 break;
1790 case 36:
1791 temp |= DP_MSA_MISC_12_BPC;
1792 break;
1793 default:
1794 MISSING_CASE(crtc_state->pipe_bpp);
1795 break;
1796 }
1797
1798 /* nonsense combination */
1799 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
1800 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1801
1802 if (crtc_state->limited_color_range)
1803 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1804
1805 /*
1806 * As per DP 1.2 spec section 2.3.4.3 while sending
1807 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1808 * colorspace information.
1809 */
1810 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1811 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1812
1813 /*
1814 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1815 * of Color Encoding Format and Content Color Gamut] while sending
1816 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1817 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1818 */
1819 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1820 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1821
1822 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
1823 }
1824
1825 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
1826 {
1827 if (master_transcoder == TRANSCODER_EDP)
1828 return 0;
1829 else
1830 return master_transcoder + 1;
1831 }
1832
1833 /*
1834 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1835 *
1836 * Only intended to be used by intel_ddi_enable_transcoder_func() and
1837 * intel_ddi_config_transcoder_func().
1838 */
1839 static u32
1840 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
1841 const struct intel_crtc_state *crtc_state)
1842 {
1843 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1845 enum pipe pipe = crtc->pipe;
1846 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1847 enum port port = encoder->port;
1848 u32 temp;
1849
1850 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1851 temp = TRANS_DDI_FUNC_ENABLE;
1852 if (INTEL_GEN(dev_priv) >= 12)
1853 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1854 else
1855 temp |= TRANS_DDI_SELECT_PORT(port);
1856
1857 switch (crtc_state->pipe_bpp) {
1858 case 18:
1859 temp |= TRANS_DDI_BPC_6;
1860 break;
1861 case 24:
1862 temp |= TRANS_DDI_BPC_8;
1863 break;
1864 case 30:
1865 temp |= TRANS_DDI_BPC_10;
1866 break;
1867 case 36:
1868 temp |= TRANS_DDI_BPC_12;
1869 break;
1870 default:
1871 BUG();
1872 }
1873
1874 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1875 temp |= TRANS_DDI_PVSYNC;
1876 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1877 temp |= TRANS_DDI_PHSYNC;
1878
1879 if (cpu_transcoder == TRANSCODER_EDP) {
1880 switch (pipe) {
1881 case PIPE_A:
1882 /* On Haswell, can only use the always-on power well for
1883 * eDP when not using the panel fitter, and when not
1884 * using motion blur mitigation (which we don't
1885 * support). */
1886 if (crtc_state->pch_pfit.force_thru)
1887 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1888 else
1889 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1890 break;
1891 case PIPE_B:
1892 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1893 break;
1894 case PIPE_C:
1895 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1896 break;
1897 default:
1898 BUG();
1899 break;
1900 }
1901 }
1902
1903 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1904 if (crtc_state->has_hdmi_sink)
1905 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1906 else
1907 temp |= TRANS_DDI_MODE_SELECT_DVI;
1908
1909 if (crtc_state->hdmi_scrambling)
1910 temp |= TRANS_DDI_HDMI_SCRAMBLING;
1911 if (crtc_state->hdmi_high_tmds_clock_ratio)
1912 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1913 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1914 temp |= TRANS_DDI_MODE_SELECT_FDI;
1915 temp |= (crtc_state->fdi_lanes - 1) << 1;
1916 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1917 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1918 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1919
1920 if (INTEL_GEN(dev_priv) >= 12) {
1921 enum transcoder master;
1922
1923 master = crtc_state->mst_master_transcoder;
1924 drm_WARN_ON(&dev_priv->drm,
1925 master == INVALID_TRANSCODER);
1926 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1927 }
1928 } else {
1929 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1930 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1931 }
1932
1933 if (IS_GEN_RANGE(dev_priv, 8, 10) &&
1934 crtc_state->master_transcoder != INVALID_TRANSCODER) {
1935 u8 master_select =
1936 bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
1937
1938 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
1939 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
1940 }
1941
1942 return temp;
1943 }
1944
1945 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
1946 const struct intel_crtc_state *crtc_state)
1947 {
1948 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1949 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1950 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1951
1952 if (INTEL_GEN(dev_priv) >= 11) {
1953 enum transcoder master_transcoder = crtc_state->master_transcoder;
1954 u32 ctl2 = 0;
1955
1956 if (master_transcoder != INVALID_TRANSCODER) {
1957 u8 master_select =
1958 bdw_trans_port_sync_master_select(master_transcoder);
1959
1960 ctl2 |= PORT_SYNC_MODE_ENABLE |
1961 PORT_SYNC_MODE_MASTER_SELECT(master_select);
1962 }
1963
1964 intel_de_write(dev_priv,
1965 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
1966 }
1967
1968 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
1969 intel_ddi_transcoder_func_reg_val_get(encoder,
1970 crtc_state));
1971 }
1972
1973 /*
1974 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1975 * bit.
1976 */
1977 static void
1978 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
1979 const struct intel_crtc_state *crtc_state)
1980 {
1981 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1982 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1983 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1984 u32 ctl;
1985
1986 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
1987 ctl &= ~TRANS_DDI_FUNC_ENABLE;
1988 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1989 }
1990
1991 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1992 {
1993 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1994 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1995 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1996 u32 ctl;
1997
1998 if (INTEL_GEN(dev_priv) >= 11)
1999 intel_de_write(dev_priv,
2000 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
2001
2002 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
2003
2004 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
2005
2006 ctl &= ~TRANS_DDI_FUNC_ENABLE;
2007
2008 if (IS_GEN_RANGE(dev_priv, 8, 10))
2009 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
2010 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
2011
2012 if (INTEL_GEN(dev_priv) >= 12) {
2013 if (!intel_dp_mst_is_master_trans(crtc_state)) {
2014 ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
2015 TRANS_DDI_MODE_SELECT_MASK);
2016 }
2017 } else {
2018 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
2019 }
2020
2021 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
2022
2023 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
2024 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2025 drm_dbg_kms(&dev_priv->drm,
2026 "Quirk Increase DDI disabled time\n");
2027 /* Quirk time at 100ms for reliable operation */
2028 msleep(100);
2029 }
2030 }
2031
2032 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
2033 enum transcoder cpu_transcoder,
2034 bool enable)
2035 {
2036 struct drm_device *dev = intel_encoder->base.dev;
2037 struct drm_i915_private *dev_priv = to_i915(dev);
2038 intel_wakeref_t wakeref;
2039 int ret = 0;
2040 u32 tmp;
2041
2042 wakeref = intel_display_power_get_if_enabled(dev_priv,
2043 intel_encoder->power_domain);
2044 if (drm_WARN_ON(dev, !wakeref))
2045 return -ENXIO;
2046
2047 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
2048 if (enable)
2049 tmp |= TRANS_DDI_HDCP_SIGNALLING;
2050 else
2051 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
2052 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
2053 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2054 return ret;
2055 }
2056
2057 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
2058 {
2059 struct drm_device *dev = intel_connector->base.dev;
2060 struct drm_i915_private *dev_priv = to_i915(dev);
2061 struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
2062 int type = intel_connector->base.connector_type;
2063 enum port port = encoder->port;
2064 enum transcoder cpu_transcoder;
2065 intel_wakeref_t wakeref;
2066 enum pipe pipe = 0;
2067 u32 tmp;
2068 bool ret;
2069
2070 wakeref = intel_display_power_get_if_enabled(dev_priv,
2071 encoder->power_domain);
2072 if (!wakeref)
2073 return false;
2074
2075 if (!encoder->get_hw_state(encoder, &pipe)) {
2076 ret = false;
2077 goto out;
2078 }
2079
2080 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
2081 cpu_transcoder = TRANSCODER_EDP;
2082 else
2083 cpu_transcoder = (enum transcoder) pipe;
2084
2085 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
2086
2087 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
2088 case TRANS_DDI_MODE_SELECT_HDMI:
2089 case TRANS_DDI_MODE_SELECT_DVI:
2090 ret = type == DRM_MODE_CONNECTOR_HDMIA;
2091 break;
2092
2093 case TRANS_DDI_MODE_SELECT_DP_SST:
2094 ret = type == DRM_MODE_CONNECTOR_eDP ||
2095 type == DRM_MODE_CONNECTOR_DisplayPort;
2096 break;
2097
2098 case TRANS_DDI_MODE_SELECT_DP_MST:
2099 /* if the transcoder is in MST state then
2100 * connector isn't connected */
2101 ret = false;
2102 break;
2103
2104 case TRANS_DDI_MODE_SELECT_FDI:
2105 ret = type == DRM_MODE_CONNECTOR_VGA;
2106 break;
2107
2108 default:
2109 ret = false;
2110 break;
2111 }
2112
2113 out:
2114 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2115
2116 return ret;
2117 }
2118
2119 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2120 u8 *pipe_mask, bool *is_dp_mst)
2121 {
2122 struct drm_device *dev = encoder->base.dev;
2123 struct drm_i915_private *dev_priv = to_i915(dev);
2124 enum port port = encoder->port;
2125 intel_wakeref_t wakeref;
2126 enum pipe p;
2127 u32 tmp;
2128 u8 mst_pipe_mask;
2129
2130 *pipe_mask = 0;
2131 *is_dp_mst = false;
2132
2133 wakeref = intel_display_power_get_if_enabled(dev_priv,
2134 encoder->power_domain);
2135 if (!wakeref)
2136 return;
2137
2138 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2139 if (!(tmp & DDI_BUF_CTL_ENABLE))
2140 goto out;
2141
2142 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
2143 tmp = intel_de_read(dev_priv,
2144 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2145
2146 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2147 default:
2148 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2149 fallthrough;
2150 case TRANS_DDI_EDP_INPUT_A_ON:
2151 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2152 *pipe_mask = BIT(PIPE_A);
2153 break;
2154 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2155 *pipe_mask = BIT(PIPE_B);
2156 break;
2157 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2158 *pipe_mask = BIT(PIPE_C);
2159 break;
2160 }
2161
2162 goto out;
2163 }
2164
2165 mst_pipe_mask = 0;
2166 for_each_pipe(dev_priv, p) {
2167 enum transcoder cpu_transcoder = (enum transcoder)p;
2168 unsigned int port_mask, ddi_select;
2169 intel_wakeref_t trans_wakeref;
2170
2171 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2172 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2173 if (!trans_wakeref)
2174 continue;
2175
2176 if (INTEL_GEN(dev_priv) >= 12) {
2177 port_mask = TGL_TRANS_DDI_PORT_MASK;
2178 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2179 } else {
2180 port_mask = TRANS_DDI_PORT_MASK;
2181 ddi_select = TRANS_DDI_SELECT_PORT(port);
2182 }
2183
2184 tmp = intel_de_read(dev_priv,
2185 TRANS_DDI_FUNC_CTL(cpu_transcoder));
2186 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2187 trans_wakeref);
2188
2189 if ((tmp & port_mask) != ddi_select)
2190 continue;
2191
2192 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2193 TRANS_DDI_MODE_SELECT_DP_MST)
2194 mst_pipe_mask |= BIT(p);
2195
2196 *pipe_mask |= BIT(p);
2197 }
2198
2199 if (!*pipe_mask)
2200 drm_dbg_kms(&dev_priv->drm,
2201 "No pipe for [ENCODER:%d:%s] found\n",
2202 encoder->base.base.id, encoder->base.name);
2203
2204 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2205 drm_dbg_kms(&dev_priv->drm,
2206 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2207 encoder->base.base.id, encoder->base.name,
2208 *pipe_mask);
2209 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2210 }
2211
2212 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2213 drm_dbg_kms(&dev_priv->drm,
2214 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2215 encoder->base.base.id, encoder->base.name,
2216 *pipe_mask, mst_pipe_mask);
2217 else
2218 *is_dp_mst = mst_pipe_mask;
2219
2220 out:
2221 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2222 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
2223 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2224 BXT_PHY_LANE_POWERDOWN_ACK |
2225 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2226 drm_err(&dev_priv->drm,
2227 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
2228 encoder->base.base.id, encoder->base.name, tmp);
2229 }
2230
2231 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2232 }
2233
2234 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2235 enum pipe *pipe)
2236 {
2237 u8 pipe_mask;
2238 bool is_mst;
2239
2240 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2241
2242 if (is_mst || !pipe_mask)
2243 return false;
2244
2245 *pipe = ffs(pipe_mask) - 1;
2246
2247 return true;
2248 }
2249
2250 static enum intel_display_power_domain
2251 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2252 {
2253 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2254 * DC states enabled at the same time, while for driver initiated AUX
2255 * transfers we need the same AUX IOs to be powered but with DC states
2256 * disabled. Accordingly use the AUX power domain here which leaves DC
2257 * states enabled.
2258 * However, for non-A AUX ports the corresponding non-EDP transcoders
2259 * would have already enabled power well 2 and DC_OFF. This means we can
2260 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2261 * specific AUX_IO reference without powering up any extra wells.
2262 * Note that PSR is enabled only on Port A even though this function
2263 * returns the correct domain for other ports too.
2264 */
2265 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2266 intel_aux_power_domain(dig_port);
2267 }
2268
2269 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2270 struct intel_crtc_state *crtc_state)
2271 {
2272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2273 struct intel_digital_port *dig_port;
2274 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2275
2276 /*
2277 * TODO: Add support for MST encoders. Atm, the following should never
2278 * happen since fake-MST encoders don't set their get_power_domains()
2279 * hook.
2280 */
2281 if (drm_WARN_ON(&dev_priv->drm,
2282 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2283 return;
2284
2285 dig_port = enc_to_dig_port(encoder);
2286
2287 if (!intel_phy_is_tc(dev_priv, phy) ||
2288 dig_port->tc_mode != TC_PORT_TBT_ALT)
2289 intel_display_power_get(dev_priv,
2290 dig_port->ddi_io_power_domain);
2291
2292 /*
2293 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2294 * ports.
2295 */
2296 if (intel_crtc_has_dp_encoder(crtc_state) ||
2297 intel_phy_is_tc(dev_priv, phy))
2298 intel_display_power_get(dev_priv,
2299 intel_ddi_main_link_aux_domain(dig_port));
2300 }
2301
2302 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
2303 const struct intel_crtc_state *crtc_state)
2304 {
2305 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2306 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2307 enum port port = encoder->port;
2308 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2309
2310 if (cpu_transcoder != TRANSCODER_EDP) {
2311 if (INTEL_GEN(dev_priv) >= 12)
2312 intel_de_write(dev_priv,
2313 TRANS_CLK_SEL(cpu_transcoder),
2314 TGL_TRANS_CLK_SEL_PORT(port));
2315 else
2316 intel_de_write(dev_priv,
2317 TRANS_CLK_SEL(cpu_transcoder),
2318 TRANS_CLK_SEL_PORT(port));
2319 }
2320 }
2321
2322 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2323 {
2324 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2325 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2326
2327 if (cpu_transcoder != TRANSCODER_EDP) {
2328 if (INTEL_GEN(dev_priv) >= 12)
2329 intel_de_write(dev_priv,
2330 TRANS_CLK_SEL(cpu_transcoder),
2331 TGL_TRANS_CLK_SEL_DISABLED);
2332 else
2333 intel_de_write(dev_priv,
2334 TRANS_CLK_SEL(cpu_transcoder),
2335 TRANS_CLK_SEL_DISABLED);
2336 }
2337 }
2338
2339 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2340 enum port port, u8 iboost)
2341 {
2342 u32 tmp;
2343
2344 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
2345 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2346 if (iboost)
2347 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2348 else
2349 tmp |= BALANCE_LEG_DISABLE(port);
2350 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
2351 }
2352
2353 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2354 const struct intel_crtc_state *crtc_state,
2355 int level)
2356 {
2357 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2359 u8 iboost;
2360
2361 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2362 iboost = intel_bios_hdmi_boost_level(encoder);
2363 else
2364 iboost = intel_bios_dp_boost_level(encoder);
2365
2366 if (iboost == 0) {
2367 const struct ddi_buf_trans *ddi_translations;
2368 int n_entries;
2369
2370 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2371 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
2372 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2373 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);
2374 else
2375 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);
2376
2377 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2378 return;
2379 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2380 level = n_entries - 1;
2381
2382 iboost = ddi_translations[level].i_boost;
2383 }
2384
2385 /* Make sure that the requested I_boost is valid */
2386 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2387 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
2388 return;
2389 }
2390
2391 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
2392
2393 if (encoder->port == PORT_A && dig_port->max_lanes == 4)
2394 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2395 }
2396
2397 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2398 const struct intel_crtc_state *crtc_state,
2399 int level)
2400 {
2401 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2402 const struct bxt_ddi_buf_trans *ddi_translations;
2403 enum port port = encoder->port;
2404 int n_entries;
2405
2406 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2407 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
2408 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2409 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
2410 else
2411 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
2412
2413 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2414 return;
2415 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2416 level = n_entries - 1;
2417
2418 bxt_ddi_phy_set_signal_level(dev_priv, port,
2419 ddi_translations[level].margin,
2420 ddi_translations[level].scale,
2421 ddi_translations[level].enable,
2422 ddi_translations[level].deemphasis);
2423 }
2424
2425 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
2426 const struct intel_crtc_state *crtc_state)
2427 {
2428 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2430 enum port port = encoder->port;
2431 enum phy phy = intel_port_to_phy(dev_priv, port);
2432 int n_entries;
2433
2434 if (INTEL_GEN(dev_priv) >= 12) {
2435 if (intel_phy_is_combo(dev_priv, phy))
2436 tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2437 else
2438 tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
2439 } else if (INTEL_GEN(dev_priv) == 11) {
2440 if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
2441 jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2442 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
2443 ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2444 else if (intel_phy_is_combo(dev_priv, phy))
2445 icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2446 else
2447 icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
2448 } else if (IS_CANNONLAKE(dev_priv)) {
2449 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2450 cnl_get_buf_trans_edp(encoder, &n_entries);
2451 else
2452 cnl_get_buf_trans_dp(encoder, &n_entries);
2453 } else if (IS_GEN9_LP(dev_priv)) {
2454 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2455 bxt_get_buf_trans_edp(encoder, &n_entries);
2456 else
2457 bxt_get_buf_trans_dp(encoder, &n_entries);
2458 } else {
2459 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2460 intel_ddi_get_buf_trans_edp(encoder, &n_entries);
2461 else
2462 intel_ddi_get_buf_trans_dp(encoder, &n_entries);
2463 }
2464
2465 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
2466 n_entries = 1;
2467 if (drm_WARN_ON(&dev_priv->drm,
2468 n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2469 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2470
2471 return index_to_dp_signal_levels[n_entries - 1] &
2472 DP_TRAIN_VOLTAGE_SWING_MASK;
2473 }
2474
2475 /*
2476 * We assume that the full set of pre-emphasis values can be
2477 * used on all DDI platforms. Should that change we need to
2478 * rethink this code.
2479 */
2480 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
2481 {
2482 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2483 }
2484
2485 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2486 const struct intel_crtc_state *crtc_state,
2487 int level)
2488 {
2489 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2490 const struct cnl_ddi_buf_trans *ddi_translations;
2491 enum port port = encoder->port;
2492 int n_entries, ln;
2493 u32 val;
2494
2495 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2496 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
2497 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2498 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
2499 else
2500 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
2501
2502 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2503 return;
2504 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2505 level = n_entries - 1;
2506
2507 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2508 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2509 val &= ~SCALING_MODE_SEL_MASK;
2510 val |= SCALING_MODE_SEL(2);
2511 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2512
2513 /* Program PORT_TX_DW2 */
2514 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
2515 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2516 RCOMP_SCALAR_MASK);
2517 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2518 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2519 /* Rcomp scalar is fixed as 0x98 for every table entry */
2520 val |= RCOMP_SCALAR(0x98);
2521 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
2522
2523 /* Program PORT_TX_DW4 */
2524 /* We cannot write to GRP. It would overrite individual loadgen */
2525 for (ln = 0; ln < 4; ln++) {
2526 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2527 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2528 CURSOR_COEFF_MASK);
2529 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2530 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2531 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2532 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2533 }
2534
2535 /* Program PORT_TX_DW5 */
2536 /* All DW5 values are fixed for every table entry */
2537 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2538 val &= ~RTERM_SELECT_MASK;
2539 val |= RTERM_SELECT(6);
2540 val |= TAP3_DISABLE;
2541 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2542
2543 /* Program PORT_TX_DW7 */
2544 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
2545 val &= ~N_SCALAR_MASK;
2546 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2547 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
2548 }
2549
2550 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2551 const struct intel_crtc_state *crtc_state,
2552 int level)
2553 {
2554 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2555 enum port port = encoder->port;
2556 int width, rate, ln;
2557 u32 val;
2558
2559 width = crtc_state->lane_count;
2560 rate = crtc_state->port_clock;
2561
2562 /*
2563 * 1. If port type is eDP or DP,
2564 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2565 * else clear to 0b.
2566 */
2567 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
2568 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2569 val &= ~COMMON_KEEPER_EN;
2570 else
2571 val |= COMMON_KEEPER_EN;
2572 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
2573
2574 /* 2. Program loadgen select */
2575 /*
2576 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2577 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2578 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2579 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2580 */
2581 for (ln = 0; ln <= 3; ln++) {
2582 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2583 val &= ~LOADGEN_SELECT;
2584
2585 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2586 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2587 val |= LOADGEN_SELECT;
2588 }
2589 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2590 }
2591
2592 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2593 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
2594 val |= SUS_CLOCK_CONFIG;
2595 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
2596
2597 /* 4. Clear training enable to change swing values */
2598 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2599 val &= ~TX_TRAINING_EN;
2600 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2601
2602 /* 5. Program swing and de-emphasis */
2603 cnl_ddi_vswing_program(encoder, crtc_state, level);
2604
2605 /* 6. Set training enable to trigger update */
2606 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2607 val |= TX_TRAINING_EN;
2608 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2609 }
2610
2611 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
2612 const struct intel_crtc_state *crtc_state,
2613 int level)
2614 {
2615 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2616 const struct cnl_ddi_buf_trans *ddi_translations;
2617 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2618 int n_entries, ln;
2619 u32 val;
2620
2621 if (INTEL_GEN(dev_priv) >= 12)
2622 ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2623 else if (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
2624 ddi_translations = jsl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2625 else if (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
2626 ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2627 else
2628 ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
2629 if (!ddi_translations)
2630 return;
2631
2632 if (level >= n_entries) {
2633 drm_dbg_kms(&dev_priv->drm,
2634 "DDI translation not found for level %d. Using %d instead.",
2635 level, n_entries - 1);
2636 level = n_entries - 1;
2637 }
2638
2639 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
2640 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2641
2642 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
2643 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
2644 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
2645 intel_dp->hobl_active ? val : 0);
2646 }
2647
2648 /* Set PORT_TX_DW5 */
2649 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2650 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2651 TAP2_DISABLE | TAP3_DISABLE);
2652 val |= SCALING_MODE_SEL(0x2);
2653 val |= RTERM_SELECT(0x6);
2654 val |= TAP3_DISABLE;
2655 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2656
2657 /* Program PORT_TX_DW2 */
2658 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
2659 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2660 RCOMP_SCALAR_MASK);
2661 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2662 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2663 /* Program Rcomp scalar for every table entry */
2664 val |= RCOMP_SCALAR(0x98);
2665 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
2666
2667 /* Program PORT_TX_DW4 */
2668 /* We cannot write to GRP. It would overwrite individual loadgen. */
2669 for (ln = 0; ln <= 3; ln++) {
2670 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2671 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2672 CURSOR_COEFF_MASK);
2673 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2674 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2675 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2676 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2677 }
2678
2679 /* Program PORT_TX_DW7 */
2680 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
2681 val &= ~N_SCALAR_MASK;
2682 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2683 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
2684 }
2685
2686 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2687 const struct intel_crtc_state *crtc_state,
2688 int level)
2689 {
2690 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2691 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2692 int width, rate, ln;
2693 u32 val;
2694
2695 width = crtc_state->lane_count;
2696 rate = crtc_state->port_clock;
2697
2698 /*
2699 * 1. If port type is eDP or DP,
2700 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2701 * else clear to 0b.
2702 */
2703 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
2704 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2705 val &= ~COMMON_KEEPER_EN;
2706 else
2707 val |= COMMON_KEEPER_EN;
2708 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
2709
2710 /* 2. Program loadgen select */
2711 /*
2712 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2713 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2714 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2715 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2716 */
2717 for (ln = 0; ln <= 3; ln++) {
2718 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2719 val &= ~LOADGEN_SELECT;
2720
2721 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2722 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2723 val |= LOADGEN_SELECT;
2724 }
2725 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2726 }
2727
2728 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2729 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
2730 val |= SUS_CLOCK_CONFIG;
2731 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
2732
2733 /* 4. Clear training enable to change swing values */
2734 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2735 val &= ~TX_TRAINING_EN;
2736 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2737
2738 /* 5. Program swing and de-emphasis */
2739 icl_ddi_combo_vswing_program(encoder, crtc_state, level);
2740
2741 /* 6. Set training enable to trigger update */
2742 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2743 val |= TX_TRAINING_EN;
2744 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2745 }
2746
2747 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2748 const struct intel_crtc_state *crtc_state,
2749 int level)
2750 {
2751 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2752 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2753 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2754 int n_entries, ln;
2755 u32 val;
2756
2757 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
2758 return;
2759
2760 ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
2761 if (level >= n_entries) {
2762 drm_dbg_kms(&dev_priv->drm,
2763 "DDI translation not found for level %d. Using %d instead.",
2764 level, n_entries - 1);
2765 level = n_entries - 1;
2766 }
2767
2768 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2769 for (ln = 0; ln < 2; ln++) {
2770 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
2771 val &= ~CRI_USE_FS32;
2772 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
2773
2774 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
2775 val &= ~CRI_USE_FS32;
2776 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
2777 }
2778
2779 /* Program MG_TX_SWINGCTRL with values from vswing table */
2780 for (ln = 0; ln < 2; ln++) {
2781 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
2782 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2783 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2784 ddi_translations[level].cri_txdeemph_override_17_12);
2785 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
2786
2787 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
2788 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2789 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2790 ddi_translations[level].cri_txdeemph_override_17_12);
2791 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
2792 }
2793
2794 /* Program MG_TX_DRVCTRL with values from vswing table */
2795 for (ln = 0; ln < 2; ln++) {
2796 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
2797 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2798 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2799 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2800 ddi_translations[level].cri_txdeemph_override_5_0) |
2801 CRI_TXDEEMPH_OVERRIDE_11_6(
2802 ddi_translations[level].cri_txdeemph_override_11_6) |
2803 CRI_TXDEEMPH_OVERRIDE_EN;
2804 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
2805
2806 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
2807 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2808 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2809 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2810 ddi_translations[level].cri_txdeemph_override_5_0) |
2811 CRI_TXDEEMPH_OVERRIDE_11_6(
2812 ddi_translations[level].cri_txdeemph_override_11_6) |
2813 CRI_TXDEEMPH_OVERRIDE_EN;
2814 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
2815
2816 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2817 }
2818
2819 /*
2820 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2821 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2822 * values from table for which TX1 and TX2 enabled.
2823 */
2824 for (ln = 0; ln < 2; ln++) {
2825 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
2826 if (crtc_state->port_clock < 300000)
2827 val |= CFG_LOW_RATE_LKREN_EN;
2828 else
2829 val &= ~CFG_LOW_RATE_LKREN_EN;
2830 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
2831 }
2832
2833 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2834 for (ln = 0; ln < 2; ln++) {
2835 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
2836 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2837 if (crtc_state->port_clock <= 500000) {
2838 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2839 } else {
2840 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2841 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2842 }
2843 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
2844
2845 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
2846 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2847 if (crtc_state->port_clock <= 500000) {
2848 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2849 } else {
2850 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2851 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2852 }
2853 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
2854 }
2855
2856 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2857 for (ln = 0; ln < 2; ln++) {
2858 val = intel_de_read(dev_priv,
2859 MG_TX1_PISO_READLOAD(ln, tc_port));
2860 val |= CRI_CALCINIT;
2861 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
2862 val);
2863
2864 val = intel_de_read(dev_priv,
2865 MG_TX2_PISO_READLOAD(ln, tc_port));
2866 val |= CRI_CALCINIT;
2867 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
2868 val);
2869 }
2870 }
2871
2872 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2873 const struct intel_crtc_state *crtc_state,
2874 int level)
2875 {
2876 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2877 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2878
2879 if (intel_phy_is_combo(dev_priv, phy))
2880 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2881 else
2882 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2883 }
2884
2885 static void
2886 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2887 const struct intel_crtc_state *crtc_state,
2888 int level)
2889 {
2890 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2891 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2892 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2893 u32 val, dpcnt_mask, dpcnt_val;
2894 int n_entries, ln;
2895
2896 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
2897 return;
2898
2899 ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
2900
2901 if (level >= n_entries)
2902 level = n_entries - 1;
2903
2904 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2905 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2906 DKL_TX_VSWING_CONTROL_MASK);
2907 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2908 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2909 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2910
2911 for (ln = 0; ln < 2; ln++) {
2912 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2913 HIP_INDEX_VAL(tc_port, ln));
2914
2915 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
2916
2917 /* All the registers are RMW */
2918 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
2919 val &= ~dpcnt_mask;
2920 val |= dpcnt_val;
2921 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
2922
2923 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
2924 val &= ~dpcnt_mask;
2925 val |= dpcnt_val;
2926 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
2927
2928 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
2929 val &= ~DKL_TX_DP20BITMODE;
2930 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
2931 }
2932 }
2933
2934 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2935 const struct intel_crtc_state *crtc_state,
2936 int level)
2937 {
2938 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2939 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2940
2941 if (intel_phy_is_combo(dev_priv, phy))
2942 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2943 else
2944 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
2945 }
2946
2947 static int translate_signal_level(struct intel_dp *intel_dp,
2948 u8 signal_levels)
2949 {
2950 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2951 int i;
2952
2953 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2954 if (index_to_dp_signal_levels[i] == signal_levels)
2955 return i;
2956 }
2957
2958 drm_WARN(&i915->drm, 1,
2959 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2960 signal_levels);
2961
2962 return 0;
2963 }
2964
2965 static int intel_ddi_dp_level(struct intel_dp *intel_dp)
2966 {
2967 u8 train_set = intel_dp->train_set[0];
2968 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2969 DP_TRAIN_PRE_EMPHASIS_MASK);
2970
2971 return translate_signal_level(intel_dp, signal_levels);
2972 }
2973
2974 static void
2975 tgl_set_signal_levels(struct intel_dp *intel_dp,
2976 const struct intel_crtc_state *crtc_state)
2977 {
2978 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2979 int level = intel_ddi_dp_level(intel_dp);
2980
2981 tgl_ddi_vswing_sequence(encoder, crtc_state, level);
2982 }
2983
2984 static void
2985 icl_set_signal_levels(struct intel_dp *intel_dp,
2986 const struct intel_crtc_state *crtc_state)
2987 {
2988 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2989 int level = intel_ddi_dp_level(intel_dp);
2990
2991 icl_ddi_vswing_sequence(encoder, crtc_state, level);
2992 }
2993
2994 static void
2995 cnl_set_signal_levels(struct intel_dp *intel_dp,
2996 const struct intel_crtc_state *crtc_state)
2997 {
2998 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2999 int level = intel_ddi_dp_level(intel_dp);
3000
3001 cnl_ddi_vswing_sequence(encoder, crtc_state, level);
3002 }
3003
3004 static void
3005 bxt_set_signal_levels(struct intel_dp *intel_dp,
3006 const struct intel_crtc_state *crtc_state)
3007 {
3008 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3009 int level = intel_ddi_dp_level(intel_dp);
3010
3011 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3012 }
3013
3014 static void
3015 hsw_set_signal_levels(struct intel_dp *intel_dp,
3016 const struct intel_crtc_state *crtc_state)
3017 {
3018 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3020 int level = intel_ddi_dp_level(intel_dp);
3021 enum port port = encoder->port;
3022 u32 signal_levels;
3023
3024 signal_levels = DDI_BUF_TRANS_SELECT(level);
3025
3026 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
3027 signal_levels);
3028
3029 intel_dp->DP &= ~DDI_BUF_EMP_MASK;
3030 intel_dp->DP |= signal_levels;
3031
3032 if (IS_GEN9_BC(dev_priv))
3033 skl_ddi_set_iboost(encoder, crtc_state, level);
3034
3035 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3036 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3037 }
3038
3039 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
3040 enum phy phy)
3041 {
3042 if (IS_ROCKETLAKE(dev_priv)) {
3043 return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3044 } else if (intel_phy_is_combo(dev_priv, phy)) {
3045 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3046 } else if (intel_phy_is_tc(dev_priv, phy)) {
3047 enum tc_port tc_port = intel_port_to_tc(dev_priv,
3048 (enum port)phy);
3049
3050 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
3051 }
3052
3053 return 0;
3054 }
3055
3056 static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
3057 const struct intel_crtc_state *crtc_state)
3058 {
3059 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3060 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3061 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3062 u32 val;
3063
3064 /*
3065 * If we fail this, something went very wrong: first 2 PLLs should be
3066 * used by first 2 phys and last 2 PLLs by last phys
3067 */
3068 if (drm_WARN_ON(&dev_priv->drm,
3069 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
3070 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
3071 return;
3072
3073 mutex_lock(&dev_priv->dpll.lock);
3074
3075 val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
3076 drm_WARN_ON(&dev_priv->drm,
3077 (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
3078
3079 val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
3080 val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
3081 intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
3082 intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
3083
3084 val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3085 intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
3086
3087 mutex_unlock(&dev_priv->dpll.lock);
3088 }
3089
3090 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
3091 const struct intel_crtc_state *crtc_state)
3092 {
3093 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3094 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3095 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3096 u32 val;
3097
3098 mutex_lock(&dev_priv->dpll.lock);
3099
3100 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
3101 drm_WARN_ON(&dev_priv->drm,
3102 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
3103
3104 if (intel_phy_is_combo(dev_priv, phy)) {
3105 u32 mask, sel;
3106
3107 if (IS_ROCKETLAKE(dev_priv)) {
3108 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
3109 sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
3110 } else {
3111 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
3112 sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
3113 }
3114
3115 /*
3116 * Even though this register references DDIs, note that we
3117 * want to pass the PHY rather than the port (DDI). For
3118 * ICL, port=phy in all cases so it doesn't matter, but for
3119 * EHL the bspec notes the following:
3120 *
3121 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
3122 * Clock Select chooses the PLL for both DDIA and DDID and
3123 * drives port A in all cases."
3124 */
3125 val &= ~mask;
3126 val |= sel;
3127 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
3128 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
3129 }
3130
3131 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3132 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
3133
3134 mutex_unlock(&dev_priv->dpll.lock);
3135 }
3136
3137 static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
3138 {
3139 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3140 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3141
3142 mutex_lock(&dev_priv->dpll.lock);
3143
3144 intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
3145 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
3146
3147 mutex_unlock(&dev_priv->dpll.lock);
3148 }
3149
3150 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
3151 {
3152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3153 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3154 u32 val;
3155
3156 mutex_lock(&dev_priv->dpll.lock);
3157
3158 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
3159 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3160 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
3161
3162 mutex_unlock(&dev_priv->dpll.lock);
3163 }
3164
3165 static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
3166 u32 port_mask, bool ddi_clk_needed)
3167 {
3168 enum port port;
3169 u32 val;
3170
3171 for_each_port_masked(port, port_mask) {
3172 enum phy phy = intel_port_to_phy(dev_priv, port);
3173 bool ddi_clk_off;
3174
3175 val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
3176 ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3177
3178 if (ddi_clk_needed == !ddi_clk_off)
3179 continue;
3180
3181 /*
3182 * Punt on the case now where clock is gated, but it would
3183 * be needed by the port. Something else is really broken then.
3184 */
3185 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
3186 continue;
3187
3188 drm_notice(&dev_priv->drm,
3189 "PHY %c is disabled with an ungated DDI clock, gate it\n",
3190 phy_name(phy));
3191 val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
3192 intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
3193 }
3194 }
3195
3196 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
3197 u32 port_mask, bool ddi_clk_needed)
3198 {
3199 enum port port;
3200 u32 val;
3201
3202 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
3203 for_each_port_masked(port, port_mask) {
3204 enum phy phy = intel_port_to_phy(dev_priv, port);
3205 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
3206 phy);
3207
3208 if (ddi_clk_needed == !ddi_clk_off)
3209 continue;
3210
3211 /*
3212 * Punt on the case now where clock is gated, but it would
3213 * be needed by the port. Something else is really broken then.
3214 */
3215 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
3216 continue;
3217
3218 drm_notice(&dev_priv->drm,
3219 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
3220 phy_name(phy));
3221 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3222 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
3223 }
3224 }
3225
3226 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
3227 {
3228 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3229 u32 port_mask;
3230 bool ddi_clk_needed;
3231
3232 /*
3233 * In case of DP MST, we sanitize the primary encoder only, not the
3234 * virtual ones.
3235 */
3236 if (encoder->type == INTEL_OUTPUT_DP_MST)
3237 return;
3238
3239 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
3240 u8 pipe_mask;
3241 bool is_mst;
3242
3243 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
3244 /*
3245 * In the unlikely case that BIOS enables DP in MST mode, just
3246 * warn since our MST HW readout is incomplete.
3247 */
3248 if (drm_WARN_ON(&dev_priv->drm, is_mst))
3249 return;
3250 }
3251
3252 port_mask = BIT(encoder->port);
3253 ddi_clk_needed = encoder->base.crtc;
3254
3255 if (encoder->type == INTEL_OUTPUT_DSI) {
3256 struct intel_encoder *other_encoder;
3257
3258 port_mask = intel_dsi_encoder_ports(encoder);
3259 /*
3260 * Sanity check that we haven't incorrectly registered another
3261 * encoder using any of the ports of this DSI encoder.
3262 */
3263 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3264 if (other_encoder == encoder)
3265 continue;
3266
3267 if (drm_WARN_ON(&dev_priv->drm,
3268 port_mask & BIT(other_encoder->port)))
3269 return;
3270 }
3271 /*
3272 * For DSI we keep the ddi clocks gated
3273 * except during enable/disable sequence.
3274 */
3275 ddi_clk_needed = false;
3276 }
3277
3278 if (IS_DG1(dev_priv))
3279 dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
3280 else
3281 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
3282 }
3283
3284 static void intel_ddi_clk_select(struct intel_encoder *encoder,
3285 const struct intel_crtc_state *crtc_state)
3286 {
3287 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3288 enum port port = encoder->port;
3289 enum phy phy = intel_port_to_phy(dev_priv, port);
3290 u32 val;
3291 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3292
3293 if (drm_WARN_ON(&dev_priv->drm, !pll))
3294 return;
3295
3296 mutex_lock(&dev_priv->dpll.lock);
3297
3298 if (INTEL_GEN(dev_priv) >= 11) {
3299 if (!intel_phy_is_combo(dev_priv, phy))
3300 intel_de_write(dev_priv, DDI_CLK_SEL(port),
3301 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3302 else if (IS_JSL_EHL(dev_priv) && port >= PORT_C)
3303 /*
3304 * MG does not exist but the programming is required
3305 * to ungate DDIC and DDID
3306 */
3307 intel_de_write(dev_priv, DDI_CLK_SEL(port),
3308 DDI_CLK_SEL_MG);
3309 } else if (IS_CANNONLAKE(dev_priv)) {
3310 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3311 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3312 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3313 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3314 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3315
3316 /*
3317 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3318 * This step and the step before must be done with separate
3319 * register writes.
3320 */
3321 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3322 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3323 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3324 } else if (IS_GEN9_BC(dev_priv)) {
3325 /* DDI -> PLL mapping */
3326 val = intel_de_read(dev_priv, DPLL_CTRL2);
3327
3328 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3329 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3330 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3331 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3332
3333 intel_de_write(dev_priv, DPLL_CTRL2, val);
3334
3335 } else if (INTEL_GEN(dev_priv) < 9) {
3336 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3337 hsw_pll_to_ddi_pll_sel(pll));
3338 }
3339
3340 mutex_unlock(&dev_priv->dpll.lock);
3341 }
3342
3343 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3344 {
3345 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3346 enum port port = encoder->port;
3347 enum phy phy = intel_port_to_phy(dev_priv, port);
3348
3349 if (INTEL_GEN(dev_priv) >= 11) {
3350 if (!intel_phy_is_combo(dev_priv, phy) ||
3351 (IS_JSL_EHL(dev_priv) && port >= PORT_C))
3352 intel_de_write(dev_priv, DDI_CLK_SEL(port),
3353 DDI_CLK_SEL_NONE);
3354 } else if (IS_CANNONLAKE(dev_priv)) {
3355 intel_de_write(dev_priv, DPCLKA_CFGCR0,
3356 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3357 } else if (IS_GEN9_BC(dev_priv)) {
3358 intel_de_write(dev_priv, DPLL_CTRL2,
3359 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
3360 } else if (INTEL_GEN(dev_priv) < 9) {
3361 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3362 PORT_CLK_SEL_NONE);
3363 }
3364 }
3365
3366 static void
3367 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
3368 const struct intel_crtc_state *crtc_state)
3369 {
3370 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3371 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
3372 u32 ln0, ln1, pin_assignment;
3373 u8 width;
3374
3375 if (dig_port->tc_mode == TC_PORT_TBT_ALT)
3376 return;
3377
3378 if (INTEL_GEN(dev_priv) >= 12) {
3379 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3380 HIP_INDEX_VAL(tc_port, 0x0));
3381 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3382 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3383 HIP_INDEX_VAL(tc_port, 0x1));
3384 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3385 } else {
3386 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
3387 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
3388 }
3389
3390 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3391 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3392
3393 /* DPPATC */
3394 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
3395 width = crtc_state->lane_count;
3396
3397 switch (pin_assignment) {
3398 case 0x0:
3399 drm_WARN_ON(&dev_priv->drm,
3400 dig_port->tc_mode != TC_PORT_LEGACY);
3401 if (width == 1) {
3402 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3403 } else {
3404 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3405 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3406 }
3407 break;
3408 case 0x1:
3409 if (width == 4) {
3410 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3411 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3412 }
3413 break;
3414 case 0x2:
3415 if (width == 2) {
3416 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3417 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3418 }
3419 break;
3420 case 0x3:
3421 case 0x5:
3422 if (width == 1) {
3423 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3424 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3425 } else {
3426 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3427 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3428 }
3429 break;
3430 case 0x4:
3431 case 0x6:
3432 if (width == 1) {
3433 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3434 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3435 } else {
3436 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3437 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3438 }
3439 break;
3440 default:
3441 MISSING_CASE(pin_assignment);
3442 }
3443
3444 if (INTEL_GEN(dev_priv) >= 12) {
3445 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3446 HIP_INDEX_VAL(tc_port, 0x0));
3447 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
3448 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3449 HIP_INDEX_VAL(tc_port, 0x1));
3450 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
3451 } else {
3452 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
3453 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
3454 }
3455 }
3456
3457 static enum transcoder
3458 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
3459 {
3460 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
3461 return crtc_state->mst_master_transcoder;
3462 else
3463 return crtc_state->cpu_transcoder;
3464 }
3465
3466 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
3467 const struct intel_crtc_state *crtc_state)
3468 {
3469 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3470
3471 if (INTEL_GEN(dev_priv) >= 12)
3472 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
3473 else
3474 return DP_TP_CTL(encoder->port);
3475 }
3476
3477 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
3478 const struct intel_crtc_state *crtc_state)
3479 {
3480 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3481
3482 if (INTEL_GEN(dev_priv) >= 12)
3483 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
3484 else
3485 return DP_TP_STATUS(encoder->port);
3486 }
3487
3488 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3489 const struct intel_crtc_state *crtc_state)
3490 {
3491 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3492
3493 if (!crtc_state->fec_enable)
3494 return;
3495
3496 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3497 drm_dbg_kms(&i915->drm,
3498 "Failed to set FEC_READY in the sink\n");
3499 }
3500
3501 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3502 const struct intel_crtc_state *crtc_state)
3503 {
3504 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3505 struct intel_dp *intel_dp;
3506 u32 val;
3507
3508 if (!crtc_state->fec_enable)
3509 return;
3510
3511 intel_dp = enc_to_intel_dp(encoder);
3512 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3513 val |= DP_TP_CTL_FEC_ENABLE;
3514 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3515
3516 if (intel_de_wait_for_set(dev_priv,
3517 dp_tp_status_reg(encoder, crtc_state),
3518 DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3519 drm_err(&dev_priv->drm,
3520 "Timed out waiting for FEC Enable Status\n");
3521 }
3522
3523 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3524 const struct intel_crtc_state *crtc_state)
3525 {
3526 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3527 struct intel_dp *intel_dp;
3528 u32 val;
3529
3530 if (!crtc_state->fec_enable)
3531 return;
3532
3533 intel_dp = enc_to_intel_dp(encoder);
3534 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3535 val &= ~DP_TP_CTL_FEC_ENABLE;
3536 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3537 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3538 }
3539
3540 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
3541 const struct intel_crtc_state *crtc_state)
3542 {
3543 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3544 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3545 enum phy phy = intel_port_to_phy(i915, encoder->port);
3546
3547 if (intel_phy_is_combo(i915, phy)) {
3548 bool lane_reversal =
3549 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3550
3551 intel_combo_phy_power_up_lanes(i915, phy, false,
3552 crtc_state->lane_count,
3553 lane_reversal);
3554 }
3555 }
3556
3557 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
3558 struct intel_encoder *encoder,
3559 const struct intel_crtc_state *crtc_state,
3560 const struct drm_connector_state *conn_state)
3561 {
3562 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3564 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3565 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3566 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3567 int level = intel_ddi_dp_level(intel_dp);
3568
3569 intel_dp_set_link_params(intel_dp,
3570 crtc_state->port_clock,
3571 crtc_state->lane_count);
3572
3573 /*
3574 * 1. Enable Power Wells
3575 *
3576 * This was handled at the beginning of intel_atomic_commit_tail(),
3577 * before we called down into this function.
3578 */
3579
3580 /* 2. Enable Panel Power if PPS is required */
3581 intel_edp_panel_on(intel_dp);
3582
3583 /*
3584 * 3. For non-TBT Type-C ports, set FIA lane count
3585 * (DFLEXDPSP.DPX4TXLATC)
3586 *
3587 * This was done before tgl_ddi_pre_enable_dp by
3588 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3589 */
3590
3591 /*
3592 * 4. Enable the port PLL.
3593 *
3594 * The PLL enabling itself was already done before this function by
3595 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
3596 * configure the PLL to port mapping here.
3597 */
3598 intel_ddi_clk_select(encoder, crtc_state);
3599
3600 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3601 if (!intel_phy_is_tc(dev_priv, phy) ||
3602 dig_port->tc_mode != TC_PORT_TBT_ALT)
3603 intel_display_power_get(dev_priv,
3604 dig_port->ddi_io_power_domain);
3605
3606 /* 6. Program DP_MODE */
3607 icl_program_mg_dp_mode(dig_port, crtc_state);
3608
3609 /*
3610 * 7. The rest of the below are substeps under the bspec's "Enable and
3611 * Train Display Port" step. Note that steps that are specific to
3612 * MST will be handled by intel_mst_pre_enable_dp() before/after it
3613 * calls into this function. Also intel_mst_pre_enable_dp() only calls
3614 * us when active_mst_links==0, so any steps designated for "single
3615 * stream or multi-stream master transcoder" can just be performed
3616 * unconditionally here.
3617 */
3618
3619 /*
3620 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3621 * Transcoder.
3622 */
3623 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3624
3625 /*
3626 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3627 * Transport Select
3628 */
3629 intel_ddi_config_transcoder_func(encoder, crtc_state);
3630
3631 /*
3632 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3633 * selected
3634 *
3635 * This will be handled by the intel_dp_start_link_train() farther
3636 * down this function.
3637 */
3638
3639 /* 7.e Configure voltage swing and related IO settings */
3640 tgl_ddi_vswing_sequence(encoder, crtc_state, level);
3641
3642 /*
3643 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3644 * the used lanes of the DDI.
3645 */
3646 intel_ddi_power_up_lanes(encoder, crtc_state);
3647
3648 /*
3649 * 7.g Configure and enable DDI_BUF_CTL
3650 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3651 * after 500 us.
3652 *
3653 * We only configure what the register value will be here. Actual
3654 * enabling happens during link training farther down.
3655 */
3656 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
3657
3658 if (!is_mst)
3659 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
3660
3661 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3662 /*
3663 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3664 * in the FEC_CONFIGURATION register to 1 before initiating link
3665 * training
3666 */
3667 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3668
3669 /*
3670 * 7.i Follow DisplayPort specification training sequence (see notes for
3671 * failure handling)
3672 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3673 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3674 * (timeout after 800 us)
3675 */
3676 intel_dp_start_link_train(intel_dp, crtc_state);
3677
3678 /* 7.k Set DP_TP_CTL link training to Normal */
3679 if (!is_trans_port_sync_mode(crtc_state))
3680 intel_dp_stop_link_train(intel_dp, crtc_state);
3681
3682 /* 7.l Configure and enable FEC if needed */
3683 intel_ddi_enable_fec(encoder, crtc_state);
3684 if (!crtc_state->bigjoiner)
3685 intel_dsc_enable(encoder, crtc_state);
3686 }
3687
3688 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
3689 struct intel_encoder *encoder,
3690 const struct intel_crtc_state *crtc_state,
3691 const struct drm_connector_state *conn_state)
3692 {
3693 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3694 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3695 enum port port = encoder->port;
3696 enum phy phy = intel_port_to_phy(dev_priv, port);
3697 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3698 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3699 int level = intel_ddi_dp_level(intel_dp);
3700
3701 if (INTEL_GEN(dev_priv) < 11)
3702 drm_WARN_ON(&dev_priv->drm,
3703 is_mst && (port == PORT_A || port == PORT_E));
3704 else
3705 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
3706
3707 intel_dp_set_link_params(intel_dp,
3708 crtc_state->port_clock,
3709 crtc_state->lane_count);
3710
3711 intel_edp_panel_on(intel_dp);
3712
3713 intel_ddi_clk_select(encoder, crtc_state);
3714
3715 if (!intel_phy_is_tc(dev_priv, phy) ||
3716 dig_port->tc_mode != TC_PORT_TBT_ALT)
3717 intel_display_power_get(dev_priv,
3718 dig_port->ddi_io_power_domain);
3719
3720 icl_program_mg_dp_mode(dig_port, crtc_state);
3721
3722 if (INTEL_GEN(dev_priv) >= 11)
3723 icl_ddi_vswing_sequence(encoder, crtc_state, level);
3724 else if (IS_CANNONLAKE(dev_priv))
3725 cnl_ddi_vswing_sequence(encoder, crtc_state, level);
3726 else if (IS_GEN9_LP(dev_priv))
3727 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3728 else
3729 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3730
3731 intel_ddi_power_up_lanes(encoder, crtc_state);
3732
3733 intel_ddi_init_dp_buf_reg(encoder, crtc_state);
3734 if (!is_mst)
3735 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
3736 intel_dp_configure_protocol_converter(intel_dp, crtc_state);
3737 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3738 true);
3739 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3740 intel_dp_start_link_train(intel_dp, crtc_state);
3741 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3742 !is_trans_port_sync_mode(crtc_state))
3743 intel_dp_stop_link_train(intel_dp, crtc_state);
3744
3745 intel_ddi_enable_fec(encoder, crtc_state);
3746
3747 if (!is_mst)
3748 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3749
3750 if (!crtc_state->bigjoiner)
3751 intel_dsc_enable(encoder, crtc_state);
3752 }
3753
3754 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
3755 struct intel_encoder *encoder,
3756 const struct intel_crtc_state *crtc_state,
3757 const struct drm_connector_state *conn_state)
3758 {
3759 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3760
3761 if (INTEL_GEN(dev_priv) >= 12)
3762 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3763 else
3764 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3765
3766 /* MST will call a setting of MSA after an allocating of Virtual Channel
3767 * from MST encoder pre_enable callback.
3768 */
3769 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3770 intel_ddi_set_dp_msa(crtc_state, conn_state);
3771
3772 intel_dp_set_m_n(crtc_state, M1_N1);
3773 }
3774 }
3775
3776 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
3777 struct intel_encoder *encoder,
3778 const struct intel_crtc_state *crtc_state,
3779 const struct drm_connector_state *conn_state)
3780 {
3781 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3782 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3783 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3784 int level = intel_ddi_hdmi_level(encoder, crtc_state);
3785
3786 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3787 intel_ddi_clk_select(encoder, crtc_state);
3788
3789 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3790
3791 icl_program_mg_dp_mode(dig_port, crtc_state);
3792
3793 if (INTEL_GEN(dev_priv) >= 12)
3794 tgl_ddi_vswing_sequence(encoder, crtc_state, level);
3795 else if (INTEL_GEN(dev_priv) == 11)
3796 icl_ddi_vswing_sequence(encoder, crtc_state, level);
3797 else if (IS_CANNONLAKE(dev_priv))
3798 cnl_ddi_vswing_sequence(encoder, crtc_state, level);
3799 else if (IS_GEN9_LP(dev_priv))
3800 bxt_ddi_vswing_sequence(encoder, crtc_state, level);
3801 else
3802 intel_prepare_hdmi_ddi_buffers(encoder, level);
3803
3804 if (IS_GEN9_BC(dev_priv))
3805 skl_ddi_set_iboost(encoder, crtc_state, level);
3806
3807 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3808
3809 dig_port->set_infoframes(encoder,
3810 crtc_state->has_infoframe,
3811 crtc_state, conn_state);
3812 }
3813
3814 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3815 struct intel_encoder *encoder,
3816 const struct intel_crtc_state *crtc_state,
3817 const struct drm_connector_state *conn_state)
3818 {
3819 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3820 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3821 enum pipe pipe = crtc->pipe;
3822
3823 /*
3824 * When called from DP MST code:
3825 * - conn_state will be NULL
3826 * - encoder will be the main encoder (ie. mst->primary)
3827 * - the main connector associated with this port
3828 * won't be active or linked to a crtc
3829 * - crtc_state will be the state of the first stream to
3830 * be activated on this port, and it may not be the same
3831 * stream that will be deactivated last, but each stream
3832 * should have a state that is identical when it comes to
3833 * the DP link parameteres
3834 */
3835
3836 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
3837
3838 if (IS_DG1(dev_priv))
3839 dg1_map_plls_to_ports(encoder, crtc_state);
3840 else if (INTEL_GEN(dev_priv) >= 11)
3841 icl_map_plls_to_ports(encoder, crtc_state);
3842
3843 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3844
3845 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3846 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3847 conn_state);
3848 } else {
3849 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3850
3851 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3852 conn_state);
3853
3854 /* FIXME precompute everything properly */
3855 /* FIXME how do we turn infoframes off again? */
3856 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3857 dig_port->set_infoframes(encoder,
3858 crtc_state->has_infoframe,
3859 crtc_state, conn_state);
3860 }
3861 }
3862
3863 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3864 const struct intel_crtc_state *crtc_state)
3865 {
3866 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3867 enum port port = encoder->port;
3868 bool wait = false;
3869 u32 val;
3870
3871 val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3872 if (val & DDI_BUF_CTL_ENABLE) {
3873 val &= ~DDI_BUF_CTL_ENABLE;
3874 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3875 wait = true;
3876 }
3877
3878 if (intel_crtc_has_dp_encoder(crtc_state)) {
3879 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3880 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3881 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3882 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3883 }
3884
3885 /* Disable FEC in DP Sink */
3886 intel_ddi_disable_fec_state(encoder, crtc_state);
3887
3888 if (wait)
3889 intel_wait_ddi_buf_idle(dev_priv, port);
3890 }
3891
3892 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3893 struct intel_encoder *encoder,
3894 const struct intel_crtc_state *old_crtc_state,
3895 const struct drm_connector_state *old_conn_state)
3896 {
3897 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3898 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3899 struct intel_dp *intel_dp = &dig_port->dp;
3900 bool is_mst = intel_crtc_has_type(old_crtc_state,
3901 INTEL_OUTPUT_DP_MST);
3902 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3903
3904 if (!is_mst)
3905 intel_dp_set_infoframes(encoder, false,
3906 old_crtc_state, old_conn_state);
3907
3908 /*
3909 * Power down sink before disabling the port, otherwise we end
3910 * up getting interrupts from the sink on detecting link loss.
3911 */
3912 intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3913
3914 if (INTEL_GEN(dev_priv) >= 12) {
3915 if (is_mst) {
3916 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3917 u32 val;
3918
3919 val = intel_de_read(dev_priv,
3920 TRANS_DDI_FUNC_CTL(cpu_transcoder));
3921 val &= ~(TGL_TRANS_DDI_PORT_MASK |
3922 TRANS_DDI_MODE_SELECT_MASK);
3923 intel_de_write(dev_priv,
3924 TRANS_DDI_FUNC_CTL(cpu_transcoder),
3925 val);
3926 }
3927 } else {
3928 if (!is_mst)
3929 intel_ddi_disable_pipe_clock(old_crtc_state);
3930 }
3931
3932 intel_disable_ddi_buf(encoder, old_crtc_state);
3933
3934 /*
3935 * From TGL spec: "If single stream or multi-stream master transcoder:
3936 * Configure Transcoder Clock select to direct no clock to the
3937 * transcoder"
3938 */
3939 if (INTEL_GEN(dev_priv) >= 12)
3940 intel_ddi_disable_pipe_clock(old_crtc_state);
3941
3942 intel_edp_panel_vdd_on(intel_dp);
3943 intel_edp_panel_off(intel_dp);
3944
3945 if (!intel_phy_is_tc(dev_priv, phy) ||
3946 dig_port->tc_mode != TC_PORT_TBT_ALT)
3947 intel_display_power_put_unchecked(dev_priv,
3948 dig_port->ddi_io_power_domain);
3949
3950 intel_ddi_clk_disable(encoder);
3951 }
3952
3953 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3954 struct intel_encoder *encoder,
3955 const struct intel_crtc_state *old_crtc_state,
3956 const struct drm_connector_state *old_conn_state)
3957 {
3958 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3959 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3960 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3961
3962 dig_port->set_infoframes(encoder, false,
3963 old_crtc_state, old_conn_state);
3964
3965 intel_ddi_disable_pipe_clock(old_crtc_state);
3966
3967 intel_disable_ddi_buf(encoder, old_crtc_state);
3968
3969 intel_display_power_put_unchecked(dev_priv,
3970 dig_port->ddi_io_power_domain);
3971
3972 intel_ddi_clk_disable(encoder);
3973
3974 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3975 }
3976
3977 static void intel_ddi_post_disable(struct intel_atomic_state *state,
3978 struct intel_encoder *encoder,
3979 const struct intel_crtc_state *old_crtc_state,
3980 const struct drm_connector_state *old_conn_state)
3981 {
3982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3983 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3984 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3985 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3986
3987 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
3988 intel_crtc_vblank_off(old_crtc_state);
3989
3990 intel_disable_pipe(old_crtc_state);
3991
3992 intel_ddi_disable_transcoder_func(old_crtc_state);
3993
3994 intel_dsc_disable(old_crtc_state);
3995
3996 if (INTEL_GEN(dev_priv) >= 9)
3997 skl_scaler_disable(old_crtc_state);
3998 else
3999 ilk_pfit_disable(old_crtc_state);
4000 }
4001
4002 if (old_crtc_state->bigjoiner_linked_crtc) {
4003 struct intel_atomic_state *state =
4004 to_intel_atomic_state(old_crtc_state->uapi.state);
4005 struct intel_crtc *slave =
4006 old_crtc_state->bigjoiner_linked_crtc;
4007 const struct intel_crtc_state *old_slave_crtc_state =
4008 intel_atomic_get_old_crtc_state(state, slave);
4009
4010 intel_crtc_vblank_off(old_slave_crtc_state);
4011 trace_intel_pipe_disable(slave);
4012
4013 intel_dsc_disable(old_slave_crtc_state);
4014 skl_scaler_disable(old_slave_crtc_state);
4015 }
4016
4017 /*
4018 * When called from DP MST code:
4019 * - old_conn_state will be NULL
4020 * - encoder will be the main encoder (ie. mst->primary)
4021 * - the main connector associated with this port
4022 * won't be active or linked to a crtc
4023 * - old_crtc_state will be the state of the last stream to
4024 * be deactivated on this port, and it may not be the same
4025 * stream that was activated last, but each stream
4026 * should have a state that is identical when it comes to
4027 * the DP link parameteres
4028 */
4029
4030 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4031 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
4032 old_conn_state);
4033 else
4034 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
4035 old_conn_state);
4036
4037 if (IS_DG1(dev_priv))
4038 dg1_unmap_plls_to_ports(encoder);
4039 else if (INTEL_GEN(dev_priv) >= 11)
4040 icl_unmap_plls_to_ports(encoder);
4041
4042 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
4043 intel_display_power_put_unchecked(dev_priv,
4044 intel_ddi_main_link_aux_domain(dig_port));
4045
4046 if (is_tc_port)
4047 intel_tc_port_put_link(dig_port);
4048 }
4049
4050 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
4051 struct intel_encoder *encoder,
4052 const struct intel_crtc_state *old_crtc_state,
4053 const struct drm_connector_state *old_conn_state)
4054 {
4055 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4056 u32 val;
4057
4058 /*
4059 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
4060 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
4061 * step 13 is the correct place for it. Step 18 is where it was
4062 * originally before the BUN.
4063 */
4064 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
4065 val &= ~FDI_RX_ENABLE;
4066 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
4067
4068 intel_disable_ddi_buf(encoder, old_crtc_state);
4069 intel_ddi_clk_disable(encoder);
4070
4071 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
4072 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
4073 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
4074 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
4075
4076 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
4077 val &= ~FDI_PCDCLK;
4078 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
4079
4080 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
4081 val &= ~FDI_RX_PLL_ENABLE;
4082 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
4083 }
4084
4085 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
4086 struct intel_encoder *encoder,
4087 const struct intel_crtc_state *crtc_state)
4088 {
4089 const struct drm_connector_state *conn_state;
4090 struct drm_connector *conn;
4091 int i;
4092
4093 if (!crtc_state->sync_mode_slaves_mask)
4094 return;
4095
4096 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
4097 struct intel_encoder *slave_encoder =
4098 to_intel_encoder(conn_state->best_encoder);
4099 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
4100 const struct intel_crtc_state *slave_crtc_state;
4101
4102 if (!slave_crtc)
4103 continue;
4104
4105 slave_crtc_state =
4106 intel_atomic_get_new_crtc_state(state, slave_crtc);
4107
4108 if (slave_crtc_state->master_transcoder !=
4109 crtc_state->cpu_transcoder)
4110 continue;
4111
4112 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
4113 slave_crtc_state);
4114 }
4115
4116 usleep_range(200, 400);
4117
4118 intel_dp_stop_link_train(enc_to_intel_dp(encoder),
4119 crtc_state);
4120 }
4121
4122 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
4123 struct intel_encoder *encoder,
4124 const struct intel_crtc_state *crtc_state,
4125 const struct drm_connector_state *conn_state)
4126 {
4127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4128 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4129 enum port port = encoder->port;
4130
4131 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
4132 intel_dp_stop_link_train(intel_dp, crtc_state);
4133
4134 intel_edp_backlight_on(crtc_state, conn_state);
4135 intel_psr_enable(intel_dp, crtc_state, conn_state);
4136 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
4137 intel_edp_drrs_enable(intel_dp, crtc_state);
4138
4139 if (crtc_state->has_audio)
4140 intel_audio_codec_enable(encoder, crtc_state, conn_state);
4141
4142 trans_port_sync_stop_link_train(state, encoder, crtc_state);
4143 }
4144
4145 static i915_reg_t
4146 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
4147 enum port port)
4148 {
4149 static const enum transcoder trans[] = {
4150 [PORT_A] = TRANSCODER_EDP,
4151 [PORT_B] = TRANSCODER_A,
4152 [PORT_C] = TRANSCODER_B,
4153 [PORT_D] = TRANSCODER_C,
4154 [PORT_E] = TRANSCODER_A,
4155 };
4156
4157 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
4158
4159 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
4160 port = PORT_A;
4161
4162 return CHICKEN_TRANS(trans[port]);
4163 }
4164
4165 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
4166 struct intel_encoder *encoder,
4167 const struct intel_crtc_state *crtc_state,
4168 const struct drm_connector_state *conn_state)
4169 {
4170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4171 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4172 struct drm_connector *connector = conn_state->connector;
4173 enum port port = encoder->port;
4174
4175 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4176 crtc_state->hdmi_high_tmds_clock_ratio,
4177 crtc_state->hdmi_scrambling))
4178 drm_dbg_kms(&dev_priv->drm,
4179 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
4180 connector->base.id, connector->name);
4181
4182 /* Display WA #1143: skl,kbl,cfl */
4183 if (IS_GEN9_BC(dev_priv)) {
4184 /*
4185 * For some reason these chicken bits have been
4186 * stuffed into a transcoder register, event though
4187 * the bits affect a specific DDI port rather than
4188 * a specific transcoder.
4189 */
4190 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
4191 u32 val;
4192
4193 val = intel_de_read(dev_priv, reg);
4194
4195 if (port == PORT_E)
4196 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
4197 DDIE_TRAINING_OVERRIDE_VALUE;
4198 else
4199 val |= DDI_TRAINING_OVERRIDE_ENABLE |
4200 DDI_TRAINING_OVERRIDE_VALUE;
4201
4202 intel_de_write(dev_priv, reg, val);
4203 intel_de_posting_read(dev_priv, reg);
4204
4205 udelay(1);
4206
4207 if (port == PORT_E)
4208 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
4209 DDIE_TRAINING_OVERRIDE_VALUE);
4210 else
4211 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
4212 DDI_TRAINING_OVERRIDE_VALUE);
4213
4214 intel_de_write(dev_priv, reg, val);
4215 }
4216
4217 intel_ddi_power_up_lanes(encoder, crtc_state);
4218
4219 /* In HDMI/DVI mode, the port width, and swing/emphasis values
4220 * are ignored so nothing special needs to be done besides
4221 * enabling the port.
4222 */
4223 intel_de_write(dev_priv, DDI_BUF_CTL(port),
4224 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
4225
4226 if (crtc_state->has_audio)
4227 intel_audio_codec_enable(encoder, crtc_state, conn_state);
4228 }
4229
4230 static void intel_enable_ddi(struct intel_atomic_state *state,
4231 struct intel_encoder *encoder,
4232 const struct intel_crtc_state *crtc_state,
4233 const struct drm_connector_state *conn_state)
4234 {
4235 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
4236
4237 if (!crtc_state->bigjoiner_slave)
4238 intel_ddi_enable_transcoder_func(encoder, crtc_state);
4239
4240 intel_enable_pipe(crtc_state);
4241
4242 intel_crtc_vblank_on(crtc_state);
4243
4244 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4245 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
4246 else
4247 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
4248
4249 /* Enable hdcp if it's desired */
4250 if (conn_state->content_protection ==
4251 DRM_MODE_CONTENT_PROTECTION_DESIRED)
4252 intel_hdcp_enable(to_intel_connector(conn_state->connector),
4253 crtc_state->cpu_transcoder,
4254 (u8)conn_state->hdcp_content_type);
4255 }
4256
4257 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
4258 struct intel_encoder *encoder,
4259 const struct intel_crtc_state *old_crtc_state,
4260 const struct drm_connector_state *old_conn_state)
4261 {
4262 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4263
4264 intel_dp->link_trained = false;
4265
4266 if (old_crtc_state->has_audio)
4267 intel_audio_codec_disable(encoder,
4268 old_crtc_state, old_conn_state);
4269
4270 intel_edp_drrs_disable(intel_dp, old_crtc_state);
4271 intel_psr_disable(intel_dp, old_crtc_state);
4272 intel_edp_backlight_off(old_conn_state);
4273 /* Disable the decompression in DP Sink */
4274 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
4275 false);
4276 }
4277
4278 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
4279 struct intel_encoder *encoder,
4280 const struct intel_crtc_state *old_crtc_state,
4281 const struct drm_connector_state *old_conn_state)
4282 {
4283 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4284 struct drm_connector *connector = old_conn_state->connector;
4285
4286 if (old_crtc_state->has_audio)
4287 intel_audio_codec_disable(encoder,
4288 old_crtc_state, old_conn_state);
4289
4290 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4291 false, false))
4292 drm_dbg_kms(&i915->drm,
4293 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
4294 connector->base.id, connector->name);
4295 }
4296
4297 static void intel_disable_ddi(struct intel_atomic_state *state,
4298 struct intel_encoder *encoder,
4299 const struct intel_crtc_state *old_crtc_state,
4300 const struct drm_connector_state *old_conn_state)
4301 {
4302 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
4303
4304 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4305 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
4306 old_conn_state);
4307 else
4308 intel_disable_ddi_dp(state, encoder, old_crtc_state,
4309 old_conn_state);
4310 }
4311
4312 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
4313 struct intel_encoder *encoder,
4314 const struct intel_crtc_state *crtc_state,
4315 const struct drm_connector_state *conn_state)
4316 {
4317 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4318
4319 intel_ddi_set_dp_msa(crtc_state, conn_state);
4320
4321 intel_psr_update(intel_dp, crtc_state, conn_state);
4322 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
4323 intel_edp_drrs_update(intel_dp, crtc_state);
4324
4325 intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
4326 }
4327
4328 void intel_ddi_update_pipe(struct intel_atomic_state *state,
4329 struct intel_encoder *encoder,
4330 const struct intel_crtc_state *crtc_state,
4331 const struct drm_connector_state *conn_state)
4332 {
4333
4334 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
4335 !intel_encoder_is_mst(encoder))
4336 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
4337 conn_state);
4338
4339 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
4340 }
4341
4342 static void
4343 intel_ddi_update_prepare(struct intel_atomic_state *state,
4344 struct intel_encoder *encoder,
4345 struct intel_crtc *crtc)
4346 {
4347 struct intel_crtc_state *crtc_state =
4348 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4349 int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4350
4351 drm_WARN_ON(state->base.dev, crtc && crtc->active);
4352
4353 intel_tc_port_get_link(enc_to_dig_port(encoder),
4354 required_lanes);
4355 if (crtc_state && crtc_state->hw.active)
4356 intel_update_active_dpll(state, crtc, encoder);
4357 }
4358
4359 static void
4360 intel_ddi_update_complete(struct intel_atomic_state *state,
4361 struct intel_encoder *encoder,
4362 struct intel_crtc *crtc)
4363 {
4364 intel_tc_port_put_link(enc_to_dig_port(encoder));
4365 }
4366
4367 static void
4368 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
4369 struct intel_encoder *encoder,
4370 const struct intel_crtc_state *crtc_state,
4371 const struct drm_connector_state *conn_state)
4372 {
4373 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4374 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4375 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4376 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4377
4378 if (is_tc_port)
4379 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4380
4381 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4382 intel_display_power_get(dev_priv,
4383 intel_ddi_main_link_aux_domain(dig_port));
4384
4385 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4386 /*
4387 * Program the lane count for static/dynamic connections on
4388 * Type-C ports. Skip this step for TBT.
4389 */
4390 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4391 else if (IS_GEN9_LP(dev_priv))
4392 bxt_ddi_phy_set_lane_optim_mask(encoder,
4393 crtc_state->lane_lat_optim_mask);
4394 }
4395
4396 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
4397 const struct intel_crtc_state *crtc_state)
4398 {
4399 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4401 enum port port = encoder->port;
4402 u32 dp_tp_ctl, ddi_buf_ctl;
4403 bool wait = false;
4404
4405 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4406
4407 if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
4408 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
4409 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
4410 intel_de_write(dev_priv, DDI_BUF_CTL(port),
4411 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
4412 wait = true;
4413 }
4414
4415 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4416 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
4417 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
4418 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4419
4420 if (wait)
4421 intel_wait_ddi_buf_idle(dev_priv, port);
4422 }
4423
4424 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
4425 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
4426 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
4427 } else {
4428 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
4429 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4430 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4431 }
4432 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
4433 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4434
4435 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4436 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
4437 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
4438
4439 intel_wait_ddi_buf_active(dev_priv, port);
4440 }
4441
4442 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
4443 const struct intel_crtc_state *crtc_state,
4444 u8 dp_train_pat)
4445 {
4446 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4448 u32 temp;
4449
4450 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4451
4452 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4453 switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
4454 case DP_TRAINING_PATTERN_DISABLE:
4455 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
4456 break;
4457 case DP_TRAINING_PATTERN_1:
4458 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
4459 break;
4460 case DP_TRAINING_PATTERN_2:
4461 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
4462 break;
4463 case DP_TRAINING_PATTERN_3:
4464 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
4465 break;
4466 case DP_TRAINING_PATTERN_4:
4467 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
4468 break;
4469 }
4470
4471 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
4472 }
4473
4474 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
4475 const struct intel_crtc_state *crtc_state)
4476 {
4477 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4479 enum port port = encoder->port;
4480 u32 val;
4481
4482 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
4483 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4484 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4485 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
4486
4487 /*
4488 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4489 * reason we need to set idle transmission mode is to work around a HW
4490 * issue where we enable the pipe while not in idle link-training mode.
4491 * In this case there is requirement to wait for a minimum number of
4492 * idle patterns to be sent.
4493 */
4494 if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4495 return;
4496
4497 if (intel_de_wait_for_set(dev_priv,
4498 dp_tp_status_reg(encoder, crtc_state),
4499 DP_TP_STATUS_IDLE_DONE, 1))
4500 drm_err(&dev_priv->drm,
4501 "Timed out waiting for DP idle patterns\n");
4502 }
4503
4504 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4505 enum transcoder cpu_transcoder)
4506 {
4507 if (cpu_transcoder == TRANSCODER_EDP)
4508 return false;
4509
4510 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4511 return false;
4512
4513 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
4514 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4515 }
4516
4517 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4518 struct intel_crtc_state *crtc_state)
4519 {
4520 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
4521 crtc_state->min_voltage_level = 2;
4522 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
4523 crtc_state->min_voltage_level = 3;
4524 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4525 crtc_state->min_voltage_level = 1;
4526 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4527 crtc_state->min_voltage_level = 2;
4528 }
4529
4530 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
4531 enum transcoder cpu_transcoder)
4532 {
4533 u32 master_select;
4534
4535 if (INTEL_GEN(dev_priv) >= 11) {
4536 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
4537
4538 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
4539 return INVALID_TRANSCODER;
4540
4541 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
4542 } else {
4543 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4544
4545 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
4546 return INVALID_TRANSCODER;
4547
4548 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
4549 }
4550
4551 if (master_select == 0)
4552 return TRANSCODER_EDP;
4553 else
4554 return master_select - 1;
4555 }
4556
4557 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
4558 {
4559 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4560 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
4561 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
4562 enum transcoder cpu_transcoder;
4563
4564 crtc_state->master_transcoder =
4565 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
4566
4567 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
4568 enum intel_display_power_domain power_domain;
4569 intel_wakeref_t trans_wakeref;
4570
4571 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
4572 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
4573 power_domain);
4574
4575 if (!trans_wakeref)
4576 continue;
4577
4578 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
4579 crtc_state->cpu_transcoder)
4580 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
4581
4582 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
4583 }
4584
4585 drm_WARN_ON(&dev_priv->drm,
4586 crtc_state->master_transcoder != INVALID_TRANSCODER &&
4587 crtc_state->sync_mode_slaves_mask);
4588 }
4589
4590 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
4591 struct intel_crtc_state *pipe_config)
4592 {
4593 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4594 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4595 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4596 u32 temp, flags = 0;
4597
4598 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4599 if (temp & TRANS_DDI_PHSYNC)
4600 flags |= DRM_MODE_FLAG_PHSYNC;
4601 else
4602 flags |= DRM_MODE_FLAG_NHSYNC;
4603 if (temp & TRANS_DDI_PVSYNC)
4604 flags |= DRM_MODE_FLAG_PVSYNC;
4605 else
4606 flags |= DRM_MODE_FLAG_NVSYNC;
4607
4608 pipe_config->hw.adjusted_mode.flags |= flags;
4609
4610 switch (temp & TRANS_DDI_BPC_MASK) {
4611 case TRANS_DDI_BPC_6:
4612 pipe_config->pipe_bpp = 18;
4613 break;
4614 case TRANS_DDI_BPC_8:
4615 pipe_config->pipe_bpp = 24;
4616 break;
4617 case TRANS_DDI_BPC_10:
4618 pipe_config->pipe_bpp = 30;
4619 break;
4620 case TRANS_DDI_BPC_12:
4621 pipe_config->pipe_bpp = 36;
4622 break;
4623 default:
4624 break;
4625 }
4626
4627 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4628 case TRANS_DDI_MODE_SELECT_HDMI:
4629 pipe_config->has_hdmi_sink = true;
4630
4631 pipe_config->infoframes.enable |=
4632 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4633
4634 if (pipe_config->infoframes.enable)
4635 pipe_config->has_infoframe = true;
4636
4637 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4638 pipe_config->hdmi_scrambling = true;
4639 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4640 pipe_config->hdmi_high_tmds_clock_ratio = true;
4641 fallthrough;
4642 case TRANS_DDI_MODE_SELECT_DVI:
4643 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4644 pipe_config->lane_count = 4;
4645 break;
4646 case TRANS_DDI_MODE_SELECT_FDI:
4647 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4648 break;
4649 case TRANS_DDI_MODE_SELECT_DP_SST:
4650 if (encoder->type == INTEL_OUTPUT_EDP)
4651 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4652 else
4653 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4654 pipe_config->lane_count =
4655 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4656 intel_dp_get_m_n(intel_crtc, pipe_config);
4657
4658 if (INTEL_GEN(dev_priv) >= 11) {
4659 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
4660
4661 pipe_config->fec_enable =
4662 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4663
4664 drm_dbg_kms(&dev_priv->drm,
4665 "[ENCODER:%d:%s] Fec status: %u\n",
4666 encoder->base.base.id, encoder->base.name,
4667 pipe_config->fec_enable);
4668 }
4669
4670 pipe_config->infoframes.enable |=
4671 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4672
4673 break;
4674 case TRANS_DDI_MODE_SELECT_DP_MST:
4675 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4676 pipe_config->lane_count =
4677 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4678
4679 if (INTEL_GEN(dev_priv) >= 12)
4680 pipe_config->mst_master_transcoder =
4681 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
4682
4683 intel_dp_get_m_n(intel_crtc, pipe_config);
4684
4685 pipe_config->infoframes.enable |=
4686 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4687 break;
4688 default:
4689 break;
4690 }
4691 }
4692
4693 void intel_ddi_get_config(struct intel_encoder *encoder,
4694 struct intel_crtc_state *pipe_config)
4695 {
4696 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4697 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4698
4699 /* XXX: DSI transcoder paranoia */
4700 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
4701 return;
4702
4703 if (pipe_config->bigjoiner_slave) {
4704 /* read out pipe settings from master */
4705 enum transcoder save = pipe_config->cpu_transcoder;
4706
4707 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */
4708 WARN_ON(pipe_config->output_types);
4709 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe;
4710 intel_ddi_read_func_ctl(encoder, pipe_config);
4711 pipe_config->cpu_transcoder = save;
4712 } else {
4713 intel_ddi_read_func_ctl(encoder, pipe_config);
4714 }
4715
4716 pipe_config->has_audio =
4717 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4718
4719 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4720 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4721 /*
4722 * This is a big fat ugly hack.
4723 *
4724 * Some machines in UEFI boot mode provide us a VBT that has 18
4725 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4726 * unknown we fail to light up. Yet the same BIOS boots up with
4727 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4728 * max, not what it tells us to use.
4729 *
4730 * Note: This will still be broken if the eDP panel is not lit
4731 * up by the BIOS, and thus we can't get the mode at module
4732 * load.
4733 */
4734 drm_dbg_kms(&dev_priv->drm,
4735 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4736 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4737 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4738 }
4739
4740 if (!pipe_config->bigjoiner_slave)
4741 intel_ddi_clock_get(encoder, pipe_config);
4742
4743 if (IS_GEN9_LP(dev_priv))
4744 pipe_config->lane_lat_optim_mask =
4745 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4746
4747 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4748
4749 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4750
4751 intel_read_infoframe(encoder, pipe_config,
4752 HDMI_INFOFRAME_TYPE_AVI,
4753 &pipe_config->infoframes.avi);
4754 intel_read_infoframe(encoder, pipe_config,
4755 HDMI_INFOFRAME_TYPE_SPD,
4756 &pipe_config->infoframes.spd);
4757 intel_read_infoframe(encoder, pipe_config,
4758 HDMI_INFOFRAME_TYPE_VENDOR,
4759 &pipe_config->infoframes.hdmi);
4760 intel_read_infoframe(encoder, pipe_config,
4761 HDMI_INFOFRAME_TYPE_DRM,
4762 &pipe_config->infoframes.drm);
4763
4764 if (INTEL_GEN(dev_priv) >= 8)
4765 bdw_get_trans_port_sync_config(pipe_config);
4766
4767 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
4768 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
4769 }
4770
4771 static void intel_ddi_sync_state(struct intel_encoder *encoder,
4772 const struct intel_crtc_state *crtc_state)
4773 {
4774 if (intel_crtc_has_dp_encoder(crtc_state))
4775 intel_dp_sync_state(encoder, crtc_state);
4776 }
4777
4778 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
4779 struct intel_crtc_state *crtc_state)
4780 {
4781 if (intel_crtc_has_dp_encoder(crtc_state))
4782 return intel_dp_initial_fastset_check(encoder, crtc_state);
4783
4784 return true;
4785 }
4786
4787 static enum intel_output_type
4788 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4789 struct intel_crtc_state *crtc_state,
4790 struct drm_connector_state *conn_state)
4791 {
4792 switch (conn_state->connector->connector_type) {
4793 case DRM_MODE_CONNECTOR_HDMIA:
4794 return INTEL_OUTPUT_HDMI;
4795 case DRM_MODE_CONNECTOR_eDP:
4796 return INTEL_OUTPUT_EDP;
4797 case DRM_MODE_CONNECTOR_DisplayPort:
4798 return INTEL_OUTPUT_DP;
4799 default:
4800 MISSING_CASE(conn_state->connector->connector_type);
4801 return INTEL_OUTPUT_UNUSED;
4802 }
4803 }
4804
4805 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4806 struct intel_crtc_state *pipe_config,
4807 struct drm_connector_state *conn_state)
4808 {
4809 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4810 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4811 enum port port = encoder->port;
4812 int ret;
4813
4814 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4815 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4816
4817 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4818 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4819 } else {
4820 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4821 }
4822
4823 if (ret)
4824 return ret;
4825
4826 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4827 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4828 pipe_config->pch_pfit.force_thru =
4829 pipe_config->pch_pfit.enabled ||
4830 pipe_config->crc_enabled;
4831
4832 if (IS_GEN9_LP(dev_priv))
4833 pipe_config->lane_lat_optim_mask =
4834 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4835
4836 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4837
4838 return 0;
4839 }
4840
4841 static bool mode_equal(const struct drm_display_mode *mode1,
4842 const struct drm_display_mode *mode2)
4843 {
4844 return drm_mode_match(mode1, mode2,
4845 DRM_MODE_MATCH_TIMINGS |
4846 DRM_MODE_MATCH_FLAGS |
4847 DRM_MODE_MATCH_3D_FLAGS) &&
4848 mode1->clock == mode2->clock; /* we want an exact match */
4849 }
4850
4851 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4852 const struct intel_link_m_n *m_n_2)
4853 {
4854 return m_n_1->tu == m_n_2->tu &&
4855 m_n_1->gmch_m == m_n_2->gmch_m &&
4856 m_n_1->gmch_n == m_n_2->gmch_n &&
4857 m_n_1->link_m == m_n_2->link_m &&
4858 m_n_1->link_n == m_n_2->link_n;
4859 }
4860
4861 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4862 const struct intel_crtc_state *crtc_state2)
4863 {
4864 return crtc_state1->hw.active && crtc_state2->hw.active &&
4865 crtc_state1->output_types == crtc_state2->output_types &&
4866 crtc_state1->output_format == crtc_state2->output_format &&
4867 crtc_state1->lane_count == crtc_state2->lane_count &&
4868 crtc_state1->port_clock == crtc_state2->port_clock &&
4869 mode_equal(&crtc_state1->hw.adjusted_mode,
4870 &crtc_state2->hw.adjusted_mode) &&
4871 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4872 }
4873
4874 static u8
4875 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4876 int tile_group_id)
4877 {
4878 struct drm_connector *connector;
4879 const struct drm_connector_state *conn_state;
4880 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4881 struct intel_atomic_state *state =
4882 to_intel_atomic_state(ref_crtc_state->uapi.state);
4883 u8 transcoders = 0;
4884 int i;
4885
4886 /*
4887 * We don't enable port sync on BDW due to missing w/as and
4888 * due to not having adjusted the modeset sequence appropriately.
4889 */
4890 if (INTEL_GEN(dev_priv) < 9)
4891 return 0;
4892
4893 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4894 return 0;
4895
4896 for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4897 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4898 const struct intel_crtc_state *crtc_state;
4899
4900 if (!crtc)
4901 continue;
4902
4903 if (!connector->has_tile ||
4904 connector->tile_group->id !=
4905 tile_group_id)
4906 continue;
4907 crtc_state = intel_atomic_get_new_crtc_state(state,
4908 crtc);
4909 if (!crtcs_port_sync_compatible(ref_crtc_state,
4910 crtc_state))
4911 continue;
4912 transcoders |= BIT(crtc_state->cpu_transcoder);
4913 }
4914
4915 return transcoders;
4916 }
4917
4918 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4919 struct intel_crtc_state *crtc_state,
4920 struct drm_connector_state *conn_state)
4921 {
4922 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4923 struct drm_connector *connector = conn_state->connector;
4924 u8 port_sync_transcoders = 0;
4925
4926 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4927 encoder->base.base.id, encoder->base.name,
4928 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4929
4930 if (connector->has_tile)
4931 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4932 connector->tile_group->id);
4933
4934 /*
4935 * EDP Transcoders cannot be ensalved
4936 * make them a master always when present
4937 */
4938 if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4939 crtc_state->master_transcoder = TRANSCODER_EDP;
4940 else
4941 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4942
4943 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4944 crtc_state->master_transcoder = INVALID_TRANSCODER;
4945 crtc_state->sync_mode_slaves_mask =
4946 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4947 }
4948
4949 return 0;
4950 }
4951
4952 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4953 {
4954 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4955
4956 intel_dp_encoder_flush_work(encoder);
4957
4958 drm_encoder_cleanup(encoder);
4959 kfree(dig_port);
4960 }
4961
4962 static const struct drm_encoder_funcs intel_ddi_funcs = {
4963 .reset = intel_dp_encoder_reset,
4964 .destroy = intel_ddi_encoder_destroy,
4965 };
4966
4967 static struct intel_connector *
4968 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4969 {
4970 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4971 struct intel_connector *connector;
4972 enum port port = dig_port->base.port;
4973
4974 connector = intel_connector_alloc();
4975 if (!connector)
4976 return NULL;
4977
4978 dig_port->dp.output_reg = DDI_BUF_CTL(port);
4979 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4980 dig_port->dp.set_link_train = intel_ddi_set_link_train;
4981 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4982
4983 if (INTEL_GEN(dev_priv) >= 12)
4984 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
4985 else if (INTEL_GEN(dev_priv) >= 11)
4986 dig_port->dp.set_signal_levels = icl_set_signal_levels;
4987 else if (IS_CANNONLAKE(dev_priv))
4988 dig_port->dp.set_signal_levels = cnl_set_signal_levels;
4989 else if (IS_GEN9_LP(dev_priv))
4990 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
4991 else
4992 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
4993
4994 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4995 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4996
4997 if (!intel_dp_init_connector(dig_port, connector)) {
4998 kfree(connector);
4999 return NULL;
5000 }
5001
5002 return connector;
5003 }
5004
5005 static int modeset_pipe(struct drm_crtc *crtc,
5006 struct drm_modeset_acquire_ctx *ctx)
5007 {
5008 struct drm_atomic_state *state;
5009 struct drm_crtc_state *crtc_state;
5010 int ret;
5011
5012 state = drm_atomic_state_alloc(crtc->dev);
5013 if (!state)
5014 return -ENOMEM;
5015
5016 state->acquire_ctx = ctx;
5017
5018 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5019 if (IS_ERR(crtc_state)) {
5020 ret = PTR_ERR(crtc_state);
5021 goto out;
5022 }
5023
5024 crtc_state->connectors_changed = true;
5025
5026 ret = drm_atomic_commit(state);
5027 out:
5028 drm_atomic_state_put(state);
5029
5030 return ret;
5031 }
5032
5033 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
5034 struct drm_modeset_acquire_ctx *ctx)
5035 {
5036 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5037 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
5038 struct intel_connector *connector = hdmi->attached_connector;
5039 struct i2c_adapter *adapter =
5040 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
5041 struct drm_connector_state *conn_state;
5042 struct intel_crtc_state *crtc_state;
5043 struct intel_crtc *crtc;
5044 u8 config;
5045 int ret;
5046
5047 if (!connector || connector->base.status != connector_status_connected)
5048 return 0;
5049
5050 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5051 ctx);
5052 if (ret)
5053 return ret;
5054
5055 conn_state = connector->base.state;
5056
5057 crtc = to_intel_crtc(conn_state->crtc);
5058 if (!crtc)
5059 return 0;
5060
5061 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5062 if (ret)
5063 return ret;
5064
5065 crtc_state = to_intel_crtc_state(crtc->base.state);
5066
5067 drm_WARN_ON(&dev_priv->drm,
5068 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
5069
5070 if (!crtc_state->hw.active)
5071 return 0;
5072
5073 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
5074 !crtc_state->hdmi_scrambling)
5075 return 0;
5076
5077 if (conn_state->commit &&
5078 !try_wait_for_completion(&conn_state->commit->hw_done))
5079 return 0;
5080
5081 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
5082 if (ret < 0) {
5083 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
5084 ret);
5085 return 0;
5086 }
5087
5088 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
5089 crtc_state->hdmi_high_tmds_clock_ratio &&
5090 !!(config & SCDC_SCRAMBLING_ENABLE) ==
5091 crtc_state->hdmi_scrambling)
5092 return 0;
5093
5094 /*
5095 * HDMI 2.0 says that one should not send scrambled data
5096 * prior to configuring the sink scrambling, and that
5097 * TMDS clock/data transmission should be suspended when
5098 * changing the TMDS clock rate in the sink. So let's
5099 * just do a full modeset here, even though some sinks
5100 * would be perfectly happy if were to just reconfigure
5101 * the SCDC settings on the fly.
5102 */
5103 return modeset_pipe(&crtc->base, ctx);
5104 }
5105
5106 static enum intel_hotplug_state
5107 intel_ddi_hotplug(struct intel_encoder *encoder,
5108 struct intel_connector *connector)
5109 {
5110 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
5111 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5112 enum phy phy = intel_port_to_phy(i915, encoder->port);
5113 bool is_tc = intel_phy_is_tc(i915, phy);
5114 struct drm_modeset_acquire_ctx ctx;
5115 enum intel_hotplug_state state;
5116 int ret;
5117
5118 state = intel_encoder_hotplug(encoder, connector);
5119
5120 drm_modeset_acquire_init(&ctx, 0);
5121
5122 for (;;) {
5123 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
5124 ret = intel_hdmi_reset_link(encoder, &ctx);
5125 else
5126 ret = intel_dp_retrain_link(encoder, &ctx);
5127
5128 if (ret == -EDEADLK) {
5129 drm_modeset_backoff(&ctx);
5130 continue;
5131 }
5132
5133 break;
5134 }
5135
5136 drm_modeset_drop_locks(&ctx);
5137 drm_modeset_acquire_fini(&ctx);
5138 drm_WARN(encoder->base.dev, ret,
5139 "Acquiring modeset locks failed with %i\n", ret);
5140
5141 /*
5142 * Unpowered type-c dongles can take some time to boot and be
5143 * responsible, so here giving some time to those dongles to power up
5144 * and then retrying the probe.
5145 *
5146 * On many platforms the HDMI live state signal is known to be
5147 * unreliable, so we can't use it to detect if a sink is connected or
5148 * not. Instead we detect if it's connected based on whether we can
5149 * read the EDID or not. That in turn has a problem during disconnect,
5150 * since the HPD interrupt may be raised before the DDC lines get
5151 * disconnected (due to how the required length of DDC vs. HPD
5152 * connector pins are specified) and so we'll still be able to get a
5153 * valid EDID. To solve this schedule another detection cycle if this
5154 * time around we didn't detect any change in the sink's connection
5155 * status.
5156 *
5157 * Type-c connectors which get their HPD signal deasserted then
5158 * reasserted, without unplugging/replugging the sink from the
5159 * connector, introduce a delay until the AUX channel communication
5160 * becomes functional. Retry the detection for 5 seconds on type-c
5161 * connectors to account for this delay.
5162 */
5163 if (state == INTEL_HOTPLUG_UNCHANGED &&
5164 connector->hotplug_retries < (is_tc ? 5 : 1) &&
5165 !dig_port->dp.is_mst)
5166 state = INTEL_HOTPLUG_RETRY;
5167
5168 return state;
5169 }
5170
5171 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
5172 {
5173 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5174 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
5175
5176 return intel_de_read(dev_priv, SDEISR) & bit;
5177 }
5178
5179 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
5180 {
5181 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5182 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
5183
5184 return intel_de_read(dev_priv, DEISR) & bit;
5185 }
5186
5187 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5188 {
5189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5190 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
5191
5192 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
5193 }
5194
5195 static struct intel_connector *
5196 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
5197 {
5198 struct intel_connector *connector;
5199 enum port port = dig_port->base.port;
5200
5201 connector = intel_connector_alloc();
5202 if (!connector)
5203 return NULL;
5204
5205 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
5206 intel_hdmi_init_connector(dig_port, connector);
5207
5208 return connector;
5209 }
5210
5211 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
5212 {
5213 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
5214
5215 if (dig_port->base.port != PORT_A)
5216 return false;
5217
5218 if (dig_port->saved_port_bits & DDI_A_4_LANES)
5219 return false;
5220
5221 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
5222 * supported configuration
5223 */
5224 if (IS_GEN9_LP(dev_priv))
5225 return true;
5226
5227 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
5228 * one who does also have a full A/E split called
5229 * DDI_F what makes DDI_E useless. However for this
5230 * case let's trust VBT info.
5231 */
5232 if (IS_CANNONLAKE(dev_priv) &&
5233 !intel_bios_is_port_present(dev_priv, PORT_E))
5234 return true;
5235
5236 return false;
5237 }
5238
5239 static int
5240 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
5241 {
5242 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
5243 enum port port = dig_port->base.port;
5244 int max_lanes = 4;
5245
5246 if (INTEL_GEN(dev_priv) >= 11)
5247 return max_lanes;
5248
5249 if (port == PORT_A || port == PORT_E) {
5250 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
5251 max_lanes = port == PORT_A ? 4 : 0;
5252 else
5253 /* Both A and E share 2 lanes */
5254 max_lanes = 2;
5255 }
5256
5257 /*
5258 * Some BIOS might fail to set this bit on port A if eDP
5259 * wasn't lit up at boot. Force this bit set when needed
5260 * so we use the proper lane count for our calculations.
5261 */
5262 if (intel_ddi_a_force_4_lanes(dig_port)) {
5263 drm_dbg_kms(&dev_priv->drm,
5264 "Forcing DDI_A_4_LANES for port A\n");
5265 dig_port->saved_port_bits |= DDI_A_4_LANES;
5266 max_lanes = 4;
5267 }
5268
5269 return max_lanes;
5270 }
5271
5272 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
5273 {
5274 return i915->hti_state & HDPORT_ENABLED &&
5275 (i915->hti_state & HDPORT_PHY_USED_DP(phy) ||
5276 i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
5277 }
5278
5279 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
5280 enum port port)
5281 {
5282 if (port >= PORT_TC1)
5283 return HPD_PORT_C + port - PORT_TC1;
5284 else
5285 return HPD_PORT_A + port - PORT_A;
5286 }
5287
5288 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
5289 enum port port)
5290 {
5291 if (IS_GEN9_BC(dev_priv) && port >= PORT_C)
5292 return HPD_PORT_TC1 + port - PORT_C;
5293 else if (port >= PORT_TC1)
5294 return HPD_PORT_TC1 + port - PORT_TC1;
5295 else
5296 return HPD_PORT_A + port - PORT_A;
5297 }
5298
5299 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
5300 enum port port)
5301 {
5302 if (HAS_PCH_TGP(dev_priv))
5303 return tgl_hpd_pin(dev_priv, port);
5304
5305 if (port >= PORT_TC1)
5306 return HPD_PORT_C + port - PORT_TC1;
5307 else
5308 return HPD_PORT_A + port - PORT_A;
5309 }
5310
5311 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
5312 enum port port)
5313 {
5314 if (port >= PORT_C)
5315 return HPD_PORT_TC1 + port - PORT_C;
5316 else
5317 return HPD_PORT_A + port - PORT_A;
5318 }
5319
5320 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
5321 enum port port)
5322 {
5323 if (port == PORT_D)
5324 return HPD_PORT_A;
5325
5326 if (HAS_PCH_MCC(dev_priv))
5327 return icl_hpd_pin(dev_priv, port);
5328
5329 return HPD_PORT_A + port - PORT_A;
5330 }
5331
5332 static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
5333 enum port port)
5334 {
5335 if (port == PORT_F)
5336 return HPD_PORT_E;
5337
5338 return HPD_PORT_A + port - PORT_A;
5339 }
5340
5341 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
5342 {
5343 if (HAS_PCH_TGP(dev_priv))
5344 return icl_hpd_pin(dev_priv, port);
5345
5346 return HPD_PORT_A + port - PORT_A;
5347 }
5348
5349 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
5350 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
5351
5352 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
5353 {
5354 struct intel_digital_port *dig_port;
5355 struct intel_encoder *encoder;
5356 bool init_hdmi, init_dp;
5357 enum phy phy = intel_port_to_phy(dev_priv, port);
5358
5359 /*
5360 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
5361 * have taken over some of the PHYs and made them unavailable to the
5362 * driver. In that case we should skip initializing the corresponding
5363 * outputs.
5364 */
5365 if (hti_uses_phy(dev_priv, phy)) {
5366 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
5367 port_name(port), phy_name(phy));
5368 return;
5369 }
5370
5371 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
5372 intel_bios_port_supports_hdmi(dev_priv, port);
5373 init_dp = intel_bios_port_supports_dp(dev_priv, port);
5374
5375 if (intel_bios_is_lspcon_present(dev_priv, port)) {
5376 /*
5377 * Lspcon device needs to be driven with DP connector
5378 * with special detection sequence. So make sure DP
5379 * is initialized before lspcon.
5380 */
5381 init_dp = true;
5382 init_hdmi = false;
5383 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
5384 port_name(port));
5385 }
5386
5387 if (!init_dp && !init_hdmi) {
5388 drm_dbg_kms(&dev_priv->drm,
5389 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
5390 port_name(port));
5391 return;
5392 }
5393
5394 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
5395 if (!dig_port)
5396 return;
5397
5398 encoder = &dig_port->base;
5399
5400 if (INTEL_GEN(dev_priv) >= 12) {
5401 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5402
5403 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5404 DRM_MODE_ENCODER_TMDS,
5405 "DDI %s%c/PHY %s%c",
5406 port >= PORT_TC1 ? "TC" : "",
5407 port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
5408 tc_port != TC_PORT_NONE ? "TC" : "",
5409 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5410 } else if (INTEL_GEN(dev_priv) >= 11) {
5411 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5412
5413 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5414 DRM_MODE_ENCODER_TMDS,
5415 "DDI %c%s/PHY %s%c",
5416 port_name(port),
5417 port >= PORT_C ? " (TC)" : "",
5418 tc_port != TC_PORT_NONE ? "TC" : "",
5419 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5420 } else {
5421 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5422 DRM_MODE_ENCODER_TMDS,
5423 "DDI %c/PHY %c", port_name(port), phy_name(phy));
5424 }
5425
5426 mutex_init(&dig_port->hdcp_mutex);
5427 dig_port->num_hdcp_streams = 0;
5428
5429 encoder->hotplug = intel_ddi_hotplug;
5430 encoder->compute_output_type = intel_ddi_compute_output_type;
5431 encoder->compute_config = intel_ddi_compute_config;
5432 encoder->compute_config_late = intel_ddi_compute_config_late;
5433 encoder->enable = intel_enable_ddi;
5434 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
5435 encoder->pre_enable = intel_ddi_pre_enable;
5436 encoder->disable = intel_disable_ddi;
5437 encoder->post_disable = intel_ddi_post_disable;
5438 encoder->update_pipe = intel_ddi_update_pipe;
5439 encoder->get_hw_state = intel_ddi_get_hw_state;
5440 encoder->get_config = intel_ddi_get_config;
5441 encoder->sync_state = intel_ddi_sync_state;
5442 encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
5443 encoder->suspend = intel_dp_encoder_suspend;
5444 encoder->shutdown = intel_dp_encoder_shutdown;
5445 encoder->get_power_domains = intel_ddi_get_power_domains;
5446
5447 encoder->type = INTEL_OUTPUT_DDI;
5448 encoder->power_domain = intel_port_to_power_domain(port);
5449 encoder->port = port;
5450 encoder->cloneable = 0;
5451 encoder->pipe_mask = ~0;
5452
5453 if (IS_DG1(dev_priv))
5454 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
5455 else if (IS_ROCKETLAKE(dev_priv))
5456 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
5457 else if (INTEL_GEN(dev_priv) >= 12 || (IS_GEN9_BC(dev_priv) &&
5458 HAS_PCH_TGP(dev_priv)))
5459 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
5460 else if (IS_JSL_EHL(dev_priv))
5461 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
5462 else if (IS_GEN(dev_priv, 11))
5463 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
5464 else if (IS_GEN(dev_priv, 10))
5465 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
5466 else if (IS_GEN(dev_priv, 9))
5467 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
5468 else
5469 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
5470
5471 if (INTEL_GEN(dev_priv) >= 11)
5472 dig_port->saved_port_bits =
5473 intel_de_read(dev_priv, DDI_BUF_CTL(port))
5474 & DDI_BUF_PORT_REVERSAL;
5475 else
5476 dig_port->saved_port_bits =
5477 intel_de_read(dev_priv, DDI_BUF_CTL(port))
5478 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
5479
5480 if (intel_bios_is_lane_reversal_needed(dev_priv, port))
5481 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
5482
5483 dig_port->dp.output_reg = INVALID_MMIO_REG;
5484 dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5485 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
5486
5487 if (intel_phy_is_tc(dev_priv, phy)) {
5488 bool is_legacy =
5489 !intel_bios_port_supports_typec_usb(dev_priv, port) &&
5490 !intel_bios_port_supports_tbt(dev_priv, port);
5491
5492 intel_tc_port_init(dig_port, is_legacy);
5493
5494 encoder->update_prepare = intel_ddi_update_prepare;
5495 encoder->update_complete = intel_ddi_update_complete;
5496 }
5497
5498 drm_WARN_ON(&dev_priv->drm, port > PORT_I);
5499 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
5500 port - PORT_A;
5501
5502 if (init_dp) {
5503 if (!intel_ddi_init_dp_connector(dig_port))
5504 goto err;
5505
5506 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5507 }
5508
5509 /* In theory we don't need the encoder->type check, but leave it just in
5510 * case we have some really bad VBTs... */
5511 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5512 if (!intel_ddi_init_hdmi_connector(dig_port))
5513 goto err;
5514 }
5515
5516 if (INTEL_GEN(dev_priv) >= 11) {
5517 if (intel_phy_is_tc(dev_priv, phy))
5518 dig_port->connected = intel_tc_port_connected;
5519 else
5520 dig_port->connected = lpt_digital_port_connected;
5521 } else if (INTEL_GEN(dev_priv) >= 8) {
5522 if (port == PORT_A || IS_GEN9_LP(dev_priv))
5523 dig_port->connected = bdw_digital_port_connected;
5524 else
5525 dig_port->connected = lpt_digital_port_connected;
5526 } else {
5527 if (port == PORT_A)
5528 dig_port->connected = hsw_digital_port_connected;
5529 else
5530 dig_port->connected = lpt_digital_port_connected;
5531 }
5532
5533 intel_infoframe_init(dig_port);
5534
5535 return;
5536
5537 err:
5538 drm_encoder_cleanup(&encoder->base);
5539 kfree(dig_port);
5540 }
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