2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_rect.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/i915_mei_hdcp_interface.h>
44 #include <media/cec-notifier.h>
50 struct __intel_global_objs_state
;
53 * Display related stuff
56 /* these are outputs from the chip - integrated only
57 external chips are via DVO or SDVO output */
58 enum intel_output_type
{
59 INTEL_OUTPUT_UNUSED
= 0,
60 INTEL_OUTPUT_ANALOG
= 1,
62 INTEL_OUTPUT_SDVO
= 3,
63 INTEL_OUTPUT_LVDS
= 4,
64 INTEL_OUTPUT_TVOUT
= 5,
65 INTEL_OUTPUT_HDMI
= 6,
69 INTEL_OUTPUT_DDI
= 10,
70 INTEL_OUTPUT_DP_MST
= 11,
73 enum hdmi_force_audio
{
74 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
75 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
76 HDMI_AUDIO_AUTO
, /* trust EDID */
77 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
80 /* "Broadcast RGB" property */
81 enum intel_broadcast_rgb
{
82 INTEL_BROADCAST_RGB_AUTO
,
83 INTEL_BROADCAST_RGB_FULL
,
84 INTEL_BROADCAST_RGB_LIMITED
,
87 struct intel_framebuffer
{
88 struct drm_framebuffer base
;
89 struct intel_frontbuffer
*frontbuffer
;
90 struct intel_rotation_info rot_info
;
92 /* for each plane in the normal GTT view */
96 /* for each plane in the rotated GTT view for no-CCS formats */
99 unsigned int pitch
; /* pixels */
104 struct drm_fb_helper helper
;
105 struct intel_framebuffer
*fb
;
106 struct i915_vma
*vma
;
107 unsigned long vma_flags
;
108 async_cookie_t cookie
;
111 /* Whether or not fbdev hpd processing is temporarily suspended */
112 bool hpd_suspended
: 1;
113 /* Set when a hotplug was received while HPD processing was
116 bool hpd_waiting
: 1;
118 /* Protects hpd_suspended */
119 struct mutex hpd_lock
;
122 enum intel_hotplug_state
{
123 INTEL_HOTPLUG_UNCHANGED
,
124 INTEL_HOTPLUG_CHANGED
,
128 struct intel_encoder
{
129 struct drm_encoder base
;
131 enum intel_output_type type
;
135 enum intel_hotplug_state (*hotplug
)(struct intel_encoder
*encoder
,
136 struct intel_connector
*connector
);
137 enum intel_output_type (*compute_output_type
)(struct intel_encoder
*,
138 struct intel_crtc_state
*,
139 struct drm_connector_state
*);
140 int (*compute_config
)(struct intel_encoder
*,
141 struct intel_crtc_state
*,
142 struct drm_connector_state
*);
143 int (*compute_config_late
)(struct intel_encoder
*,
144 struct intel_crtc_state
*,
145 struct drm_connector_state
*);
146 void (*update_prepare
)(struct intel_atomic_state
*,
147 struct intel_encoder
*,
148 struct intel_crtc
*);
149 void (*pre_pll_enable
)(struct intel_atomic_state
*,
150 struct intel_encoder
*,
151 const struct intel_crtc_state
*,
152 const struct drm_connector_state
*);
153 void (*pre_enable
)(struct intel_atomic_state
*,
154 struct intel_encoder
*,
155 const struct intel_crtc_state
*,
156 const struct drm_connector_state
*);
157 void (*enable
)(struct intel_atomic_state
*,
158 struct intel_encoder
*,
159 const struct intel_crtc_state
*,
160 const struct drm_connector_state
*);
161 void (*update_complete
)(struct intel_atomic_state
*,
162 struct intel_encoder
*,
163 struct intel_crtc
*);
164 void (*disable
)(struct intel_atomic_state
*,
165 struct intel_encoder
*,
166 const struct intel_crtc_state
*,
167 const struct drm_connector_state
*);
168 void (*post_disable
)(struct intel_atomic_state
*,
169 struct intel_encoder
*,
170 const struct intel_crtc_state
*,
171 const struct drm_connector_state
*);
172 void (*post_pll_disable
)(struct intel_atomic_state
*,
173 struct intel_encoder
*,
174 const struct intel_crtc_state
*,
175 const struct drm_connector_state
*);
176 void (*update_pipe
)(struct intel_atomic_state
*,
177 struct intel_encoder
*,
178 const struct intel_crtc_state
*,
179 const struct drm_connector_state
*);
180 /* Read out the current hw state of this connector, returning true if
181 * the encoder is active. If the encoder is enabled it also set the pipe
182 * it is connected to in the pipe parameter. */
183 bool (*get_hw_state
)(struct intel_encoder
*, enum pipe
*pipe
);
184 /* Reconstructs the equivalent mode flags for the current hardware
185 * state. This must be called _after_ display->get_pipe_config has
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
187 * be set correctly before calling this function. */
188 void (*get_config
)(struct intel_encoder
*,
189 struct intel_crtc_state
*pipe_config
);
192 * Optional hook called during init/resume to sync any state
193 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
195 void (*sync_state
)(struct intel_encoder
*encoder
,
196 const struct intel_crtc_state
*crtc_state
);
199 * Optional hook, returning true if this encoder allows a fastset
200 * during the initial commit, false otherwise.
202 bool (*initial_fastset_check
)(struct intel_encoder
*encoder
,
203 struct intel_crtc_state
*crtc_state
);
206 * Acquires the power domains needed for an active encoder during
207 * hardware state readout.
209 void (*get_power_domains
)(struct intel_encoder
*encoder
,
210 struct intel_crtc_state
*crtc_state
);
212 * Called during system suspend after all pending requests for the
213 * encoder are flushed (for example for DP AUX transactions) and
214 * device interrupts are disabled.
216 void (*suspend
)(struct intel_encoder
*);
217 enum hpd_pin hpd_pin
;
218 enum intel_display_power_domain power_domain
;
219 /* for communication with audio component; protected by av_mutex */
220 const struct drm_connector
*audio_connector
;
224 struct drm_display_mode
*fixed_mode
;
225 struct drm_display_mode
*downclock_mode
;
234 bool combination_mode
; /* gen 2/4 only */
236 bool alternate_pwm_increment
; /* lpt+ */
239 bool util_pin_active_low
; /* bxt+ */
240 u8 controller
; /* bxt+ only */
241 struct pwm_device
*pwm
;
242 struct pwm_state pwm_state
;
247 struct backlight_device
*device
;
249 /* Connector and platform specific backlight functions */
250 int (*setup
)(struct intel_connector
*connector
, enum pipe pipe
);
251 u32 (*get
)(struct intel_connector
*connector
);
252 void (*set
)(const struct drm_connector_state
*conn_state
, u32 level
);
253 void (*disable
)(const struct drm_connector_state
*conn_state
);
254 void (*enable
)(const struct intel_crtc_state
*crtc_state
,
255 const struct drm_connector_state
*conn_state
);
256 u32 (*hz_to_pwm
)(struct intel_connector
*connector
, u32 hz
);
257 void (*power
)(struct intel_connector
*, bool enable
);
261 struct intel_digital_port
;
263 enum check_link_response
{
264 HDCP_LINK_PROTECTED
= 0,
265 HDCP_TOPOLOGY_CHANGE
,
266 HDCP_LINK_INTEGRITY_FAILURE
,
271 * This structure serves as a translation layer between the generic HDCP code
272 * and the bus-specific code. What that means is that HDCP over HDMI differs
273 * from HDCP over DP, so to account for these differences, we need to
274 * communicate with the receiver through this shim.
276 * For completeness, the 2 buses differ in the following ways:
278 * HDCP registers on the receiver are set via DP AUX for DP, and
279 * they are set via DDC for HDMI.
280 * - Receiver register offsets
281 * The offsets of the registers are different for DP vs. HDMI
282 * - Receiver register masks/offsets
283 * For instance, the ready bit for the KSV fifo is in a different
284 * place on DP vs HDMI
285 * - Receiver register names
286 * Seriously. In the DP spec, the 16-bit register containing
287 * downstream information is called BINFO, on HDMI it's called
288 * BSTATUS. To confuse matters further, DP has a BSTATUS register
289 * with a completely different definition.
291 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
292 * be read 3 keys at a time
294 * Since Aksv is hidden in hardware, there's different procedures
295 * to send it over DP AUX vs DDC
297 struct intel_hdcp_shim
{
298 /* Outputs the transmitter's An and Aksv values to the receiver. */
299 int (*write_an_aksv
)(struct intel_digital_port
*dig_port
, u8
*an
);
301 /* Reads the receiver's key selection vector */
302 int (*read_bksv
)(struct intel_digital_port
*dig_port
, u8
*bksv
);
305 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
306 * definitions are the same in the respective specs, but the names are
307 * different. Call it BSTATUS since that's the name the HDMI spec
308 * uses and it was there first.
310 int (*read_bstatus
)(struct intel_digital_port
*dig_port
,
313 /* Determines whether a repeater is present downstream */
314 int (*repeater_present
)(struct intel_digital_port
*dig_port
,
315 bool *repeater_present
);
317 /* Reads the receiver's Ri' value */
318 int (*read_ri_prime
)(struct intel_digital_port
*dig_port
, u8
*ri
);
320 /* Determines if the receiver's KSV FIFO is ready for consumption */
321 int (*read_ksv_ready
)(struct intel_digital_port
*dig_port
,
324 /* Reads the ksv fifo for num_downstream devices */
325 int (*read_ksv_fifo
)(struct intel_digital_port
*dig_port
,
326 int num_downstream
, u8
*ksv_fifo
);
328 /* Reads a 32-bit part of V' from the receiver */
329 int (*read_v_prime_part
)(struct intel_digital_port
*dig_port
,
332 /* Enables HDCP signalling on the port */
333 int (*toggle_signalling
)(struct intel_digital_port
*dig_port
,
334 enum transcoder cpu_transcoder
,
337 /* Ensures the link is still protected */
338 bool (*check_link
)(struct intel_digital_port
*dig_port
,
339 struct intel_connector
*connector
);
341 /* Detects panel's hdcp capability. This is optional for HDMI. */
342 int (*hdcp_capable
)(struct intel_digital_port
*dig_port
,
345 /* HDCP adaptation(DP/HDMI) required on the port */
346 enum hdcp_wired_protocol protocol
;
348 /* Detects whether sink is HDCP2.2 capable */
349 int (*hdcp_2_2_capable
)(struct intel_digital_port
*dig_port
,
352 /* Write HDCP2.2 messages */
353 int (*write_2_2_msg
)(struct intel_digital_port
*dig_port
,
354 void *buf
, size_t size
);
356 /* Read HDCP2.2 messages */
357 int (*read_2_2_msg
)(struct intel_digital_port
*dig_port
,
358 u8 msg_id
, void *buf
, size_t size
);
361 * Implementation of DP HDCP2.2 Errata for the communication of stream
362 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
363 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
365 int (*config_stream_type
)(struct intel_digital_port
*dig_port
,
366 bool is_repeater
, u8 type
);
368 /* HDCP2.2 Link Integrity Check */
369 int (*check_2_2_link
)(struct intel_digital_port
*dig_port
);
373 const struct intel_hdcp_shim
*shim
;
374 /* Mutex for hdcp state of the connector */
377 struct delayed_work check_work
;
378 struct work_struct prop_work
;
380 /* HDCP1.4 Encryption status */
383 /* HDCP2.2 related definitions */
384 /* Flag indicates whether this connector supports HDCP2.2 or not. */
385 bool hdcp2_supported
;
387 /* HDCP2.2 Encryption status */
388 bool hdcp2_encrypted
;
391 * Content Stream Type defined by content owner. TYPE0(0x0) content can
392 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
393 * content can flow only through a link protected by HDCP2.2.
396 struct hdcp_port_data port_data
;
402 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
403 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
404 * When it rolls over re-auth has to be triggered.
409 * Count of RepeaterAuth_Stream_Manage msg propagated.
410 * Initialized to 0 on AKE_INIT. Incremented after every successful
411 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
412 * over re-Auth has to be triggered.
417 * Work queue to signal the CP_IRQ. Used for the waiters to read the
418 * available information from HDCP DP sink.
420 wait_queue_head_t cp_irq_queue
;
421 atomic_t cp_irq_count
;
422 int cp_irq_count_cached
;
425 * HDCP register access for gen12+ need the transcoder associated.
426 * Transcoder attached to the connector could be changed at modeset.
427 * Hence caching the transcoder here.
429 enum transcoder cpu_transcoder
;
432 struct intel_connector
{
433 struct drm_connector base
;
435 * The fixed encoder this connector is connected to.
437 struct intel_encoder
*encoder
;
439 /* ACPI device id for ACPI and driver cooperation */
442 /* Reads out the current hw, returning true if the connector is enabled
443 * and active (i.e. dpms ON state). */
444 bool (*get_hw_state
)(struct intel_connector
*);
446 /* Panel info for eDP and LVDS */
447 struct intel_panel panel
;
449 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
451 struct edid
*detect_edid
;
453 /* Number of times hotplug detection was tried after an HPD interrupt */
456 /* since POLL and HPD connectors may use the same HPD line keep the native
457 state of connector->polled in case hotplug storm detection changes it */
460 struct drm_dp_mst_port
*port
;
462 struct intel_dp
*mst_port
;
464 /* Work struct to schedule a uevent on link train failure */
465 struct work_struct modeset_retry_work
;
467 struct intel_hdcp hdcp
;
470 struct intel_digital_connector_state
{
471 struct drm_connector_state base
;
473 enum hdmi_force_audio force_audio
;
477 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
491 struct intel_atomic_state
{
492 struct drm_atomic_state base
;
494 intel_wakeref_t wakeref
;
496 struct __intel_global_objs_state
*global_objs
;
499 bool dpll_set
, modeset
;
501 struct intel_shared_dpll_state shared_dpll
[I915_NUM_PLLS
];
504 * Current watermarks can't be trusted during hardware readout, so
505 * don't bother calculating intermediate watermarks.
507 bool skip_intermediate_wm
;
509 bool rps_interactive
;
511 struct i915_sw_fence commit_ready
;
513 struct llist_node freed
;
516 struct intel_plane_state
{
517 struct drm_plane_state uapi
;
520 * actual hardware state, the state we program to the hardware.
521 * The following members are used to verify the hardware state:
522 * During initial hw readout, they need to be copied from uapi.
525 struct drm_crtc
*crtc
;
526 struct drm_framebuffer
*fb
;
529 uint16_t pixel_blend_mode
;
530 unsigned int rotation
;
531 enum drm_color_encoding color_encoding
;
532 enum drm_color_range color_range
;
535 struct i915_ggtt_view view
;
536 struct i915_vma
*vma
;
538 #define PLANE_HAS_FENCE BIT(0)
544 * bytes for 0/180 degree rotation
545 * pixels for 90/270 degree rotation
551 /* plane control register */
554 /* plane color control register */
557 /* chroma upsampler control register */
562 * = -1 : not using a scaler
563 * >= 0 : using a scalers
565 * plane requiring a scaler:
566 * - During check_plane, its bit is set in
567 * crtc_state->scaler_state.scaler_users by calling helper function
568 * update_scaler_plane.
569 * - scaler_id indicates the scaler it got assigned.
571 * plane doesn't require a scaler:
572 * - this can happen when scaling is no more required or plane simply
574 * - During check_plane, corresponding bit is reset in
575 * crtc_state->scaler_state.scaler_users by calling helper function
576 * update_scaler_plane.
581 * planar_linked_plane:
583 * ICL planar formats require 2 planes that are updated as pairs.
584 * This member is used to make sure the other plane is also updated
585 * when required, and for update_slave() to find the correct
586 * plane_state to pass as argument.
588 struct intel_plane
*planar_linked_plane
;
592 * If set don't update use the linked plane's state for updating
593 * this plane during atomic commit with the update_slave() callback.
595 * It's also used by the watermark code to ignore wm calculations on
596 * this plane. They're calculated by the linked plane's wm code.
600 struct drm_intel_sprite_colorkey ckey
;
603 struct intel_initial_plane_config
{
604 struct intel_framebuffer
*fb
;
605 struct i915_vma
*vma
;
612 struct intel_scaler
{
617 struct intel_crtc_scaler_state
{
618 #define SKL_NUM_SCALERS 2
619 struct intel_scaler scalers
[SKL_NUM_SCALERS
];
622 * scaler_users: keeps track of users requesting scalers on this crtc.
624 * If a bit is set, a user is using a scaler.
625 * Here user can be a plane or crtc as defined below:
626 * bits 0-30 - plane (bit position is index from drm_plane_index)
629 * Instead of creating a new index to cover planes and crtc, using
630 * existing drm_plane_index for planes which is well less than 31
631 * planes and bit 31 for crtc. This should be fine to cover all
634 * intel_atomic_setup_scalers will setup available scalers to users
635 * requesting scalers. It will gracefully fail if request exceeds
638 #define SKL_CRTC_INDEX 31
639 unsigned scaler_users
;
641 /* scaler used by crtc for panel fitting purpose */
645 /* {crtc,crtc_state}->mode_flags */
646 /* Flag to get scanline using frame time stamps */
647 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
648 /* Flag to use the scanline counter instead of the pixel counter */
649 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
651 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
652 * is operating in command mode.
653 * Flag to use TE from DSI0 instead of VBI in command mode
655 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
656 /* Flag to use TE from DSI1 instead of VBI in command mode */
657 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
658 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
659 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
661 struct intel_wm_level
{
669 struct intel_pipe_wm
{
670 struct intel_wm_level wm
[5];
673 bool sprites_enabled
;
677 struct skl_wm_level
{
685 struct skl_plane_wm
{
686 struct skl_wm_level wm
[8];
687 struct skl_wm_level uv_wm
[8];
688 struct skl_wm_level trans_wm
;
689 struct skl_wm_level sagv_wm0
;
694 struct skl_plane_wm planes
[I915_MAX_PLANES
];
701 VLV_WM_LEVEL_DDR_DVFS
,
705 struct vlv_wm_state
{
706 struct g4x_pipe_wm wm
[NUM_VLV_WM_LEVELS
];
707 struct g4x_sr_wm sr
[NUM_VLV_WM_LEVELS
];
712 struct vlv_fifo_state
{
713 u16 plane
[I915_MAX_PLANES
];
723 struct g4x_wm_state
{
724 struct g4x_pipe_wm wm
;
726 struct g4x_sr_wm hpll
;
732 struct intel_crtc_wm_state
{
736 * Intermediate watermarks; these can be
737 * programmed immediately since they satisfy
738 * both the current configuration we're
739 * switching away from and the new
740 * configuration we're switching to.
742 struct intel_pipe_wm intermediate
;
745 * Optimal watermarks, programmed post-vblank
746 * when this state is committed.
748 struct intel_pipe_wm optimal
;
752 /* gen9+ only needs 1-step wm programming */
753 struct skl_pipe_wm optimal
;
754 struct skl_ddb_entry ddb
;
755 struct skl_ddb_entry plane_ddb_y
[I915_MAX_PLANES
];
756 struct skl_ddb_entry plane_ddb_uv
[I915_MAX_PLANES
];
760 /* "raw" watermarks (not inverted) */
761 struct g4x_pipe_wm raw
[NUM_VLV_WM_LEVELS
];
762 /* intermediate watermarks (inverted) */
763 struct vlv_wm_state intermediate
;
764 /* optimal watermarks (inverted) */
765 struct vlv_wm_state optimal
;
766 /* display FIFO split */
767 struct vlv_fifo_state fifo_state
;
771 /* "raw" watermarks */
772 struct g4x_pipe_wm raw
[NUM_G4X_WM_LEVELS
];
773 /* intermediate watermarks */
774 struct g4x_wm_state intermediate
;
775 /* optimal watermarks */
776 struct g4x_wm_state optimal
;
781 * Platforms with two-step watermark programming will need to
782 * update watermark programming post-vblank to switch from the
783 * safe intermediate watermarks to the optimal final
786 bool need_postvbl_update
;
789 enum intel_output_format
{
790 INTEL_OUTPUT_FORMAT_INVALID
,
791 INTEL_OUTPUT_FORMAT_RGB
,
792 INTEL_OUTPUT_FORMAT_YCBCR420
,
793 INTEL_OUTPUT_FORMAT_YCBCR444
,
796 struct intel_crtc_state
{
798 * uapi (drm) state. This is the software state shown to userspace.
799 * In particular, the following members are used for bookkeeping:
807 struct drm_crtc_state uapi
;
810 * actual hardware state, the state we program to the hardware.
811 * The following members are used to verify the hardware state:
814 * - mode / adjusted_mode
815 * - color property blobs.
817 * During initial hw readout, they need to be copied to uapi.
821 struct drm_property_blob
*degamma_lut
, *gamma_lut
, *ctm
;
822 struct drm_display_mode mode
, adjusted_mode
;
826 * quirks - bitfield with hw state readout quirks
828 * For various reasons the hw state readout code might not be able to
829 * completely faithfully read out the current state. These cases are
830 * tracked with quirk flags so that fastboot and state checker can act
833 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
834 unsigned long quirks
;
836 unsigned fb_bits
; /* framebuffers to flip */
837 bool update_pipe
; /* can a fast modeset be performed? */
839 bool update_wm_pre
, update_wm_post
; /* watermarks are updated */
840 bool fifo_changed
; /* FIFO split is changed */
842 bool inherited
; /* state inherited from BIOS? */
844 /* Pipe source size (ie. panel fitter input size)
845 * All planes will be positioned inside this space,
846 * and get clipped at the edges. */
847 int pipe_src_w
, pipe_src_h
;
850 * Pipe pixel rate, adjusted for
851 * panel fitter/pipe scaler downscaling.
853 unsigned int pixel_rate
;
855 /* Whether to set up the PCH/FDI. Note that we never allow sharing
856 * between pch encoders and cpu encoders. */
857 bool has_pch_encoder
;
859 /* Are we sending infoframes on the attached port */
862 /* CPU Transcoder for the pipe. Currently this can only differ from the
863 * pipe on Haswell and later (where we have a special eDP transcoder)
864 * and Broxton (where we have special DSI transcoders). */
865 enum transcoder cpu_transcoder
;
868 * Use reduced/limited/broadcast rbg range, compressing from the full
869 * range fed into the crtcs.
871 bool limited_color_range
;
873 /* Bitmask of encoder types (enum intel_output_type)
874 * driven by the pipe.
876 unsigned int output_types
;
878 /* Whether we should send NULL infoframes. Required for audio. */
881 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
882 * has_dp_encoder is set. */
886 * Enable dithering, used when the selected pipe bpp doesn't match the
892 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
893 * compliance video pattern tests.
894 * Disable dither only if it is a compliance test request for
897 bool dither_force_disable
;
899 /* Controls for the clock computation, to override various stages. */
902 /* SDVO TV has a bunch of special case. To make multifunction encoders
903 * work correctly, we need to track this at runtime.*/
907 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
908 * required. This is set in the 2nd loop of calling encoder's
909 * ->compute_config if the first pick doesn't work out.
913 /* Settings for the intel dpll used on pretty much everything but
917 /* Selected dpll when shared or NULL. */
918 struct intel_shared_dpll
*shared_dpll
;
920 /* Actual register state of the dpll, for shared dpll cross-checking. */
921 struct intel_dpll_hw_state dpll_hw_state
;
924 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
925 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
927 struct icl_port_dpll
{
928 struct intel_shared_dpll
*pll
;
929 struct intel_dpll_hw_state hw_state
;
930 } icl_port_dplls
[ICL_PORT_DPLL_COUNT
];
932 /* DSI PLL registers */
938 struct intel_link_m_n dp_m_n
;
940 /* m2_n2 for eDP downclock */
941 struct intel_link_m_n dp_m2_n2
;
946 bool enable_psr2_sel_fetch
;
950 * Frequence the dpll for the port should run at. Differs from the
951 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
952 * already multiplied by pixel_multiplier.
956 /* Used by SDVO (and if we ever fix it, HDMI). */
957 unsigned pixel_multiplier
;
959 /* I915_MODE_FLAG_* */
965 * Used by platforms having DP/HDMI PHY with programmable lane
966 * latency optimization.
968 u8 lane_lat_optim_mask
;
970 /* minimum acceptable voltage level */
971 u8 min_voltage_level
;
973 /* Panel fitter controls for gen2-gen4 + VLV */
977 u32 lvds_border_bits
;
980 /* Panel fitter placement and size for Ironlake+ */
987 /* FDI configuration, only valid if has_pch_encoder is set. */
989 struct intel_link_m_n fdi_m_n
;
1001 struct intel_crtc_scaler_state scaler_state
;
1003 /* w/a for waiting 2 vblanks during crtc enable */
1004 enum pipe hsw_workaround_pipe
;
1006 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1009 struct intel_crtc_wm_state wm
;
1011 int min_cdclk
[I915_MAX_PLANES
];
1013 u32 data_rate
[I915_MAX_PLANES
];
1015 /* Gamma mode programmed on the pipe */
1019 /* CSC mode programmed on the pipe */
1026 /* bitmask of visible planes (enum plane_id) */
1031 /* bitmask of planes that will be updated during the commit */
1037 union hdmi_infoframe avi
;
1038 union hdmi_infoframe spd
;
1039 union hdmi_infoframe hdmi
;
1040 union hdmi_infoframe drm
;
1041 struct drm_dp_vsc_sdp vsc
;
1044 /* HDMI scrambling status */
1045 bool hdmi_scrambling
;
1047 /* HDMI High TMDS char rate ratio */
1048 bool hdmi_high_tmds_clock_ratio
;
1050 /* Output format RGB/YCBCR etc */
1051 enum intel_output_format output_format
;
1053 /* Output down scaling is done in LSPCON device */
1054 bool lspcon_downsampling
;
1056 /* enable pipe gamma? */
1059 /* enable pipe csc? */
1062 /* Display Stream compression state */
1064 bool compression_enable
;
1068 struct drm_dsc_config config
;
1071 /* HSW+ linetime watermarks */
1075 /* Forward Error correction State */
1078 /* Pointer to master transcoder in case of tiled displays */
1079 enum transcoder master_transcoder
;
1081 /* Bitmask to indicate slaves attached */
1082 u8 sync_mode_slaves_mask
;
1084 /* Only valid on TGL+ */
1085 enum transcoder mst_master_transcoder
;
1087 /* For DSB related info */
1088 struct intel_dsb
*dsb
;
1090 u32 psr2_man_track_ctl
;
1093 enum intel_pipe_crc_source
{
1094 INTEL_PIPE_CRC_SOURCE_NONE
,
1095 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1096 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1097 INTEL_PIPE_CRC_SOURCE_PLANE3
,
1098 INTEL_PIPE_CRC_SOURCE_PLANE4
,
1099 INTEL_PIPE_CRC_SOURCE_PLANE5
,
1100 INTEL_PIPE_CRC_SOURCE_PLANE6
,
1101 INTEL_PIPE_CRC_SOURCE_PLANE7
,
1102 INTEL_PIPE_CRC_SOURCE_PIPE
,
1103 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1104 INTEL_PIPE_CRC_SOURCE_TV
,
1105 INTEL_PIPE_CRC_SOURCE_DP_B
,
1106 INTEL_PIPE_CRC_SOURCE_DP_C
,
1107 INTEL_PIPE_CRC_SOURCE_DP_D
,
1108 INTEL_PIPE_CRC_SOURCE_AUTO
,
1109 INTEL_PIPE_CRC_SOURCE_MAX
,
1112 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1113 struct intel_pipe_crc
{
1116 enum intel_pipe_crc_source source
;
1120 struct drm_crtc base
;
1123 * Whether the crtc and the connected output pipeline is active. Implies
1124 * that crtc->enabled is set, i.e. the current mode configuration has
1125 * some outputs connected to this crtc.
1130 /* I915_MODE_FLAG_* */
1133 unsigned long long enabled_power_domains
;
1134 struct intel_overlay
*overlay
;
1136 struct intel_crtc_state
*config
;
1138 /* Access to these should be protected by dev_priv->irq_lock. */
1139 bool cpu_fifo_underrun_disabled
;
1140 bool pch_fifo_underrun_disabled
;
1142 /* per-pipe watermark state */
1144 /* watermarks currently being used */
1146 struct intel_pipe_wm ilk
;
1147 struct vlv_wm_state vlv
;
1148 struct g4x_wm_state g4x
;
1152 int scanline_offset
;
1155 unsigned start_vbl_count
;
1156 ktime_t start_vbl_time
;
1157 int min_vbl
, max_vbl
;
1161 /* scalers available on this crtc */
1164 #ifdef CONFIG_DEBUG_FS
1165 struct intel_pipe_crc pipe_crc
;
1169 struct intel_plane
{
1170 struct drm_plane base
;
1171 enum i9xx_plane_id i9xx_plane
;
1176 u32 frontbuffer_bit
;
1179 u32 base
, cntl
, size
;
1183 * NOTE: Do not place new plane state fields here (e.g., when adding
1184 * new plane properties). New runtime state should now be placed in
1185 * the intel_plane_state structure and accessed via plane_state.
1188 unsigned int (*max_stride
)(struct intel_plane
*plane
,
1189 u32 pixel_format
, u64 modifier
,
1190 unsigned int rotation
);
1191 void (*update_plane
)(struct intel_plane
*plane
,
1192 const struct intel_crtc_state
*crtc_state
,
1193 const struct intel_plane_state
*plane_state
);
1194 void (*disable_plane
)(struct intel_plane
*plane
,
1195 const struct intel_crtc_state
*crtc_state
);
1196 bool (*get_hw_state
)(struct intel_plane
*plane
, enum pipe
*pipe
);
1197 int (*check_plane
)(struct intel_crtc_state
*crtc_state
,
1198 struct intel_plane_state
*plane_state
);
1199 int (*min_cdclk
)(const struct intel_crtc_state
*crtc_state
,
1200 const struct intel_plane_state
*plane_state
);
1201 void (*async_flip
)(struct intel_plane
*plane
,
1202 const struct intel_crtc_state
*crtc_state
,
1203 const struct intel_plane_state
*plane_state
);
1206 struct intel_watermark_params
{
1214 struct cxsr_latency
{
1215 bool is_desktop
: 1;
1220 u16 display_hpll_disable
;
1222 u16 cursor_hpll_disable
;
1225 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1226 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1227 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1228 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1229 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1230 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1231 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1232 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1233 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1236 i915_reg_t hdmi_reg
;
1239 enum drm_dp_dual_mode_type type
;
1244 struct intel_connector
*attached_connector
;
1245 struct cec_notifier
*cec_notifier
;
1248 struct intel_dp_mst_encoder
;
1250 * enum link_m_n_set:
1251 * When platform provides two set of M_N registers for dp, we can
1252 * program them and switch between them incase of DRRS.
1253 * But When only one such register is provided, we have to program the
1254 * required divider value on that registers itself based on the DRRS state.
1256 * M1_N1 : Program dp_m_n on M1_N1 registers
1257 * dp_m2_n2 on M2_N2 registers (If supported)
1259 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1260 * M2_N2 registers are not supported
1264 /* Sets the m1_n1 and m2_n2 */
1269 struct intel_dp_compliance_data
{
1272 u16 hdisplay
, vdisplay
;
1274 struct drm_dp_phy_test_params phytest
;
1277 struct intel_dp_compliance
{
1278 unsigned long test_type
;
1279 struct intel_dp_compliance_data test_data
;
1286 i915_reg_t output_reg
;
1294 bool reset_link_params
;
1295 u8 dpcd
[DP_RECEIVER_CAP_SIZE
];
1296 u8 psr_dpcd
[EDP_PSR_RECEIVER_CAP_SIZE
];
1297 u8 downstream_ports
[DP_MAX_DOWNSTREAM_PORTS
];
1298 u8 edp_dpcd
[EDP_DISPLAY_CTL_CAP_SIZE
];
1299 u8 dsc_dpcd
[DP_DSC_RECEIVER_CAP_SIZE
];
1302 int num_source_rates
;
1303 const int *source_rates
;
1304 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1306 int sink_rates
[DP_MAX_SUPPORTED_RATES
];
1307 bool use_rate_select
;
1308 /* intersection of source and sink rates */
1309 int num_common_rates
;
1310 int common_rates
[DP_MAX_SUPPORTED_RATES
];
1311 /* Max lane count for the current link */
1312 int max_link_lane_count
;
1313 /* Max rate for the current link */
1315 /* sink or branch descriptor */
1316 struct drm_dp_desc desc
;
1318 struct drm_dp_aux aux
;
1319 u32 aux_busy_last_status
;
1321 int panel_power_up_delay
;
1322 int panel_power_down_delay
;
1323 int panel_power_cycle_delay
;
1324 int backlight_on_delay
;
1325 int backlight_off_delay
;
1326 struct delayed_work panel_vdd_work
;
1327 bool want_panel_vdd
;
1328 unsigned long last_power_on
;
1329 unsigned long last_backlight_off
;
1330 ktime_t panel_power_off_time
;
1332 struct notifier_block edp_notifier
;
1335 * Pipe whose power sequencer is currently locked into
1336 * this port. Only relevant on VLV/CHV.
1340 * Pipe currently driving the port. Used for preventing
1341 * the use of the PPS for any pipe currentrly driving
1342 * external DP as that will mess things up on VLV.
1344 enum pipe active_pipe
;
1346 * Set if the sequencer may be reset due to a power transition,
1347 * requiring a reinitialization. Only relevant on BXT.
1350 struct edp_power_seq pps_delays
;
1352 bool can_mst
; /* this port supports mst */
1354 int active_mst_links
;
1356 /* connector directly attached - won't be use for modeset in mst world */
1357 struct intel_connector
*attached_connector
;
1359 /* mst connector list */
1360 struct intel_dp_mst_encoder
*mst_encoders
[I915_MAX_PIPES
];
1361 struct drm_dp_mst_topology_mgr mst_mgr
;
1363 u32 (*get_aux_clock_divider
)(struct intel_dp
*dp
, int index
);
1365 * This function returns the value we have to program the AUX_CTL
1366 * register with to kick off an AUX transaction.
1368 u32 (*get_aux_send_ctl
)(struct intel_dp
*dp
, int send_bytes
,
1369 u32 aux_clock_divider
);
1371 i915_reg_t (*aux_ch_ctl_reg
)(struct intel_dp
*dp
);
1372 i915_reg_t (*aux_ch_data_reg
)(struct intel_dp
*dp
, int index
);
1374 /* This is called before a link training is starterd */
1375 void (*prepare_link_retrain
)(struct intel_dp
*intel_dp
,
1376 const struct intel_crtc_state
*crtc_state
);
1377 void (*set_link_train
)(struct intel_dp
*intel_dp
,
1378 const struct intel_crtc_state
*crtc_state
,
1380 void (*set_idle_link_train
)(struct intel_dp
*intel_dp
,
1381 const struct intel_crtc_state
*crtc_state
);
1382 void (*set_signal_levels
)(struct intel_dp
*intel_dp
,
1383 const struct intel_crtc_state
*crtc_state
);
1385 u8 (*preemph_max
)(struct intel_dp
*intel_dp
);
1386 u8 (*voltage_max
)(struct intel_dp
*intel_dp
,
1387 const struct intel_crtc_state
*crtc_state
);
1389 /* Displayport compliance testing */
1390 struct intel_dp_compliance compliance
;
1392 /* Downstream facing port caps */
1394 int min_tmds_clock
, max_tmds_clock
;
1397 bool ycbcr_444_to_420
;
1400 /* Display stream compression testing */
1407 enum lspcon_vendor
{
1409 LSPCON_VENDOR_PARADE
1412 struct intel_lspcon
{
1414 enum drm_lspcon_mode mode
;
1415 enum lspcon_vendor vendor
;
1418 struct intel_digital_port
{
1419 struct intel_encoder base
;
1420 u32 saved_port_bits
;
1422 struct intel_hdmi hdmi
;
1423 struct intel_lspcon lspcon
;
1424 enum irqreturn (*hpd_pulse
)(struct intel_digital_port
*, bool);
1425 bool release_cl2_override
;
1427 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1429 enum intel_display_power_domain ddi_io_power_domain
;
1430 struct mutex tc_lock
; /* protects the TypeC port mode */
1431 intel_wakeref_t tc_lock_wakeref
;
1432 int tc_link_refcount
;
1433 bool tc_legacy_port
:1;
1434 char tc_port_name
[8];
1435 enum tc_port_mode tc_mode
;
1436 enum phy_fia tc_phy_fia
;
1439 /* protects num_hdcp_streams reference count */
1440 struct mutex hdcp_mutex
;
1441 /* the number of pipes using HDCP signalling out of this port */
1442 unsigned int num_hdcp_streams
;
1444 void (*write_infoframe
)(struct intel_encoder
*encoder
,
1445 const struct intel_crtc_state
*crtc_state
,
1447 const void *frame
, ssize_t len
);
1448 void (*read_infoframe
)(struct intel_encoder
*encoder
,
1449 const struct intel_crtc_state
*crtc_state
,
1451 void *frame
, ssize_t len
);
1452 void (*set_infoframes
)(struct intel_encoder
*encoder
,
1454 const struct intel_crtc_state
*crtc_state
,
1455 const struct drm_connector_state
*conn_state
);
1456 u32 (*infoframes_enabled
)(struct intel_encoder
*encoder
,
1457 const struct intel_crtc_state
*pipe_config
);
1458 bool (*connected
)(struct intel_encoder
*encoder
);
1461 struct intel_dp_mst_encoder
{
1462 struct intel_encoder base
;
1464 struct intel_digital_port
*primary
;
1465 struct intel_connector
*connector
;
1468 static inline enum dpio_channel
1469 vlv_dig_port_to_channel(struct intel_digital_port
*dig_port
)
1471 switch (dig_port
->base
.port
) {
1482 static inline enum dpio_phy
1483 vlv_dig_port_to_phy(struct intel_digital_port
*dig_port
)
1485 switch (dig_port
->base
.port
) {
1496 static inline enum dpio_channel
1497 vlv_pipe_to_channel(enum pipe pipe
)
1510 static inline struct intel_crtc
*
1511 intel_get_first_crtc(struct drm_i915_private
*dev_priv
)
1513 return to_intel_crtc(drm_crtc_from_index(&dev_priv
->drm
, 0));
1516 static inline struct intel_crtc
*
1517 intel_get_crtc_for_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1519 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
1520 drm_WARN_ON(&dev_priv
->drm
,
1521 !(INTEL_INFO(dev_priv
)->pipe_mask
& BIT(pipe
)));
1522 return dev_priv
->pipe_to_crtc_mapping
[pipe
];
1525 static inline struct intel_crtc
*
1526 intel_get_crtc_for_plane(struct drm_i915_private
*dev_priv
, enum i9xx_plane_id plane
)
1528 return dev_priv
->plane_to_crtc_mapping
[plane
];
1531 struct intel_load_detect_pipe
{
1532 struct drm_atomic_state
*restore_state
;
1535 static inline struct intel_encoder
*
1536 intel_attached_encoder(struct intel_connector
*connector
)
1538 return connector
->encoder
;
1541 static inline bool intel_encoder_is_dig_port(struct intel_encoder
*encoder
)
1543 switch (encoder
->type
) {
1544 case INTEL_OUTPUT_DDI
:
1545 case INTEL_OUTPUT_DP
:
1546 case INTEL_OUTPUT_EDP
:
1547 case INTEL_OUTPUT_HDMI
:
1554 static inline bool intel_encoder_is_mst(struct intel_encoder
*encoder
)
1556 return encoder
->type
== INTEL_OUTPUT_DP_MST
;
1559 static inline struct intel_dp_mst_encoder
*
1560 enc_to_mst(struct intel_encoder
*encoder
)
1562 return container_of(&encoder
->base
, struct intel_dp_mst_encoder
,
1566 static inline struct intel_digital_port
*
1567 enc_to_dig_port(struct intel_encoder
*encoder
)
1569 struct intel_encoder
*intel_encoder
= encoder
;
1571 if (intel_encoder_is_dig_port(intel_encoder
))
1572 return container_of(&encoder
->base
, struct intel_digital_port
,
1574 else if (intel_encoder_is_mst(intel_encoder
))
1575 return enc_to_mst(encoder
)->primary
;
1580 static inline struct intel_digital_port
*
1581 intel_attached_dig_port(struct intel_connector
*connector
)
1583 return enc_to_dig_port(intel_attached_encoder(connector
));
1586 static inline struct intel_dp
*enc_to_intel_dp(struct intel_encoder
*encoder
)
1588 return &enc_to_dig_port(encoder
)->dp
;
1591 static inline struct intel_dp
*intel_attached_dp(struct intel_connector
*connector
)
1593 return enc_to_intel_dp(intel_attached_encoder(connector
));
1596 static inline bool intel_encoder_is_dp(struct intel_encoder
*encoder
)
1598 switch (encoder
->type
) {
1599 case INTEL_OUTPUT_DP
:
1600 case INTEL_OUTPUT_EDP
:
1602 case INTEL_OUTPUT_DDI
:
1603 /* Skip pure HDMI/DVI DDI encoders */
1604 return i915_mmio_reg_valid(enc_to_intel_dp(encoder
)->output_reg
);
1610 static inline struct intel_lspcon
*
1611 enc_to_intel_lspcon(struct intel_encoder
*encoder
)
1613 return &enc_to_dig_port(encoder
)->lspcon
;
1616 static inline struct intel_digital_port
*
1617 dp_to_dig_port(struct intel_dp
*intel_dp
)
1619 return container_of(intel_dp
, struct intel_digital_port
, dp
);
1622 static inline struct intel_lspcon
*
1623 dp_to_lspcon(struct intel_dp
*intel_dp
)
1625 return &dp_to_dig_port(intel_dp
)->lspcon
;
1628 static inline struct drm_i915_private
*
1629 dp_to_i915(struct intel_dp
*intel_dp
)
1631 return to_i915(dp_to_dig_port(intel_dp
)->base
.base
.dev
);
1634 static inline struct intel_digital_port
*
1635 hdmi_to_dig_port(struct intel_hdmi
*intel_hdmi
)
1637 return container_of(intel_hdmi
, struct intel_digital_port
, hdmi
);
1640 static inline struct intel_plane_state
*
1641 intel_atomic_get_plane_state(struct intel_atomic_state
*state
,
1642 struct intel_plane
*plane
)
1644 struct drm_plane_state
*ret
=
1645 drm_atomic_get_plane_state(&state
->base
, &plane
->base
);
1648 return ERR_CAST(ret
);
1650 return to_intel_plane_state(ret
);
1653 static inline struct intel_plane_state
*
1654 intel_atomic_get_old_plane_state(struct intel_atomic_state
*state
,
1655 struct intel_plane
*plane
)
1657 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state
->base
,
1661 static inline struct intel_plane_state
*
1662 intel_atomic_get_new_plane_state(struct intel_atomic_state
*state
,
1663 struct intel_plane
*plane
)
1665 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state
->base
,
1669 static inline struct intel_crtc_state
*
1670 intel_atomic_get_old_crtc_state(struct intel_atomic_state
*state
,
1671 struct intel_crtc
*crtc
)
1673 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state
->base
,
1677 static inline struct intel_crtc_state
*
1678 intel_atomic_get_new_crtc_state(struct intel_atomic_state
*state
,
1679 struct intel_crtc
*crtc
)
1681 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state
->base
,
1685 static inline struct intel_digital_connector_state
*
1686 intel_atomic_get_new_connector_state(struct intel_atomic_state
*state
,
1687 struct intel_connector
*connector
)
1689 return to_intel_digital_connector_state(
1690 drm_atomic_get_new_connector_state(&state
->base
,
1694 static inline struct intel_digital_connector_state
*
1695 intel_atomic_get_old_connector_state(struct intel_atomic_state
*state
,
1696 struct intel_connector
*connector
)
1698 return to_intel_digital_connector_state(
1699 drm_atomic_get_old_connector_state(&state
->base
,
1703 /* intel_display.c */
1705 intel_crtc_has_type(const struct intel_crtc_state
*crtc_state
,
1706 enum intel_output_type type
)
1708 return crtc_state
->output_types
& (1 << type
);
1711 intel_crtc_has_dp_encoder(const struct intel_crtc_state
*crtc_state
)
1713 return crtc_state
->output_types
&
1714 ((1 << INTEL_OUTPUT_DP
) |
1715 (1 << INTEL_OUTPUT_DP_MST
) |
1716 (1 << INTEL_OUTPUT_EDP
));
1720 intel_wait_for_vblank(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1722 struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1724 drm_crtc_wait_one_vblank(&crtc
->base
);
1728 intel_wait_for_vblank_if_active(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1730 const struct intel_crtc
*crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
1733 intel_wait_for_vblank(dev_priv
, pipe
);
1736 static inline u32
intel_plane_ggtt_offset(const struct intel_plane_state
*state
)
1738 return i915_ggtt_offset(state
->vma
);
1741 #endif /* __INTEL_DISPLAY_TYPES_H__ */