2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <drm/intel_lpe_audio.h>
41 #include "i915_debugfs.h"
43 #include "intel_atomic.h"
44 #include "intel_audio.h"
45 #include "intel_connector.h"
46 #include "intel_ddi.h"
47 #include "intel_display_types.h"
49 #include "intel_dpio_phy.h"
50 #include "intel_fifo_underrun.h"
51 #include "intel_gmbus.h"
52 #include "intel_hdcp.h"
53 #include "intel_hdmi.h"
54 #include "intel_hotplug.h"
55 #include "intel_lspcon.h"
56 #include "intel_panel.h"
57 #include "intel_sdvo.h"
58 #include "intel_sideband.h"
60 static struct drm_device
*intel_hdmi_to_dev(struct intel_hdmi
*intel_hdmi
)
62 return hdmi_to_dig_port(intel_hdmi
)->base
.base
.dev
;
66 assert_hdmi_port_disabled(struct intel_hdmi
*intel_hdmi
)
68 struct drm_device
*dev
= intel_hdmi_to_dev(intel_hdmi
);
69 struct drm_i915_private
*dev_priv
= to_i915(dev
);
72 enabled_bits
= HAS_DDI(dev_priv
) ? DDI_BUF_CTL_ENABLE
: SDVO_ENABLE
;
75 intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
) & enabled_bits
,
76 "HDMI port enabled, expecting disabled\n");
80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private
*dev_priv
,
81 enum transcoder cpu_transcoder
)
83 drm_WARN(&dev_priv
->drm
,
84 intel_de_read(dev_priv
, TRANS_DDI_FUNC_CTL(cpu_transcoder
)) &
85 TRANS_DDI_FUNC_ENABLE
,
86 "HDMI transcoder function enabled, expecting disabled\n");
89 struct intel_hdmi
*enc_to_intel_hdmi(struct intel_encoder
*encoder
)
91 struct intel_digital_port
*dig_port
=
92 container_of(&encoder
->base
, struct intel_digital_port
,
94 return &dig_port
->hdmi
;
97 static struct intel_hdmi
*intel_attached_hdmi(struct intel_connector
*connector
)
99 return enc_to_intel_hdmi(intel_attached_encoder(connector
));
102 static u32
g4x_infoframe_index(unsigned int type
)
105 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
106 return VIDEO_DIP_SELECT_GAMUT
;
107 case HDMI_INFOFRAME_TYPE_AVI
:
108 return VIDEO_DIP_SELECT_AVI
;
109 case HDMI_INFOFRAME_TYPE_SPD
:
110 return VIDEO_DIP_SELECT_SPD
;
111 case HDMI_INFOFRAME_TYPE_VENDOR
:
112 return VIDEO_DIP_SELECT_VENDOR
;
119 static u32
g4x_infoframe_enable(unsigned int type
)
122 case HDMI_PACKET_TYPE_GENERAL_CONTROL
:
123 return VIDEO_DIP_ENABLE_GCP
;
124 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
125 return VIDEO_DIP_ENABLE_GAMUT
;
128 case HDMI_INFOFRAME_TYPE_AVI
:
129 return VIDEO_DIP_ENABLE_AVI
;
130 case HDMI_INFOFRAME_TYPE_SPD
:
131 return VIDEO_DIP_ENABLE_SPD
;
132 case HDMI_INFOFRAME_TYPE_VENDOR
:
133 return VIDEO_DIP_ENABLE_VENDOR
;
134 case HDMI_INFOFRAME_TYPE_DRM
:
142 static u32
hsw_infoframe_enable(unsigned int type
)
145 case HDMI_PACKET_TYPE_GENERAL_CONTROL
:
146 return VIDEO_DIP_ENABLE_GCP_HSW
;
147 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
148 return VIDEO_DIP_ENABLE_GMP_HSW
;
150 return VIDEO_DIP_ENABLE_VSC_HSW
;
152 return VDIP_ENABLE_PPS
;
153 case HDMI_INFOFRAME_TYPE_AVI
:
154 return VIDEO_DIP_ENABLE_AVI_HSW
;
155 case HDMI_INFOFRAME_TYPE_SPD
:
156 return VIDEO_DIP_ENABLE_SPD_HSW
;
157 case HDMI_INFOFRAME_TYPE_VENDOR
:
158 return VIDEO_DIP_ENABLE_VS_HSW
;
159 case HDMI_INFOFRAME_TYPE_DRM
:
160 return VIDEO_DIP_ENABLE_DRM_GLK
;
168 hsw_dip_data_reg(struct drm_i915_private
*dev_priv
,
169 enum transcoder cpu_transcoder
,
174 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
175 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder
, i
);
177 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder
, i
);
179 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder
, i
);
180 case HDMI_INFOFRAME_TYPE_AVI
:
181 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder
, i
);
182 case HDMI_INFOFRAME_TYPE_SPD
:
183 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder
, i
);
184 case HDMI_INFOFRAME_TYPE_VENDOR
:
185 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder
, i
);
186 case HDMI_INFOFRAME_TYPE_DRM
:
187 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder
, i
);
190 return INVALID_MMIO_REG
;
194 static int hsw_dip_data_size(struct drm_i915_private
*dev_priv
,
199 return VIDEO_DIP_VSC_DATA_SIZE
;
201 return VIDEO_DIP_PPS_DATA_SIZE
;
202 case HDMI_PACKET_TYPE_GAMUT_METADATA
:
203 if (INTEL_GEN(dev_priv
) >= 11)
204 return VIDEO_DIP_GMP_DATA_SIZE
;
206 return VIDEO_DIP_DATA_SIZE
;
208 return VIDEO_DIP_DATA_SIZE
;
212 static void g4x_write_infoframe(struct intel_encoder
*encoder
,
213 const struct intel_crtc_state
*crtc_state
,
215 const void *frame
, ssize_t len
)
217 const u32
*data
= frame
;
218 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
219 u32 val
= intel_de_read(dev_priv
, VIDEO_DIP_CTL
);
222 drm_WARN(&dev_priv
->drm
, !(val
& VIDEO_DIP_ENABLE
),
223 "Writing DIP with CTL reg disabled\n");
225 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
226 val
|= g4x_infoframe_index(type
);
228 val
&= ~g4x_infoframe_enable(type
);
230 intel_de_write(dev_priv
, VIDEO_DIP_CTL
, val
);
232 for (i
= 0; i
< len
; i
+= 4) {
233 intel_de_write(dev_priv
, VIDEO_DIP_DATA
, *data
);
236 /* Write every possible data byte to force correct ECC calculation. */
237 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
238 intel_de_write(dev_priv
, VIDEO_DIP_DATA
, 0);
240 val
|= g4x_infoframe_enable(type
);
241 val
&= ~VIDEO_DIP_FREQ_MASK
;
242 val
|= VIDEO_DIP_FREQ_VSYNC
;
244 intel_de_write(dev_priv
, VIDEO_DIP_CTL
, val
);
245 intel_de_posting_read(dev_priv
, VIDEO_DIP_CTL
);
248 static void g4x_read_infoframe(struct intel_encoder
*encoder
,
249 const struct intel_crtc_state
*crtc_state
,
251 void *frame
, ssize_t len
)
253 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
254 u32 val
, *data
= frame
;
257 val
= intel_de_read(dev_priv
, VIDEO_DIP_CTL
);
259 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
260 val
|= g4x_infoframe_index(type
);
262 intel_de_write(dev_priv
, VIDEO_DIP_CTL
, val
);
264 for (i
= 0; i
< len
; i
+= 4)
265 *data
++ = intel_de_read(dev_priv
, VIDEO_DIP_DATA
);
268 static u32
g4x_infoframes_enabled(struct intel_encoder
*encoder
,
269 const struct intel_crtc_state
*pipe_config
)
271 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
272 u32 val
= intel_de_read(dev_priv
, VIDEO_DIP_CTL
);
274 if ((val
& VIDEO_DIP_ENABLE
) == 0)
277 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(encoder
->port
))
280 return val
& (VIDEO_DIP_ENABLE_AVI
|
281 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
284 static void ibx_write_infoframe(struct intel_encoder
*encoder
,
285 const struct intel_crtc_state
*crtc_state
,
287 const void *frame
, ssize_t len
)
289 const u32
*data
= frame
;
290 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
291 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
292 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
293 u32 val
= intel_de_read(dev_priv
, reg
);
296 drm_WARN(&dev_priv
->drm
, !(val
& VIDEO_DIP_ENABLE
),
297 "Writing DIP with CTL reg disabled\n");
299 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
300 val
|= g4x_infoframe_index(type
);
302 val
&= ~g4x_infoframe_enable(type
);
304 intel_de_write(dev_priv
, reg
, val
);
306 for (i
= 0; i
< len
; i
+= 4) {
307 intel_de_write(dev_priv
, TVIDEO_DIP_DATA(intel_crtc
->pipe
),
311 /* Write every possible data byte to force correct ECC calculation. */
312 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
313 intel_de_write(dev_priv
, TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
315 val
|= g4x_infoframe_enable(type
);
316 val
&= ~VIDEO_DIP_FREQ_MASK
;
317 val
|= VIDEO_DIP_FREQ_VSYNC
;
319 intel_de_write(dev_priv
, reg
, val
);
320 intel_de_posting_read(dev_priv
, reg
);
323 static void ibx_read_infoframe(struct intel_encoder
*encoder
,
324 const struct intel_crtc_state
*crtc_state
,
326 void *frame
, ssize_t len
)
328 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
329 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
330 u32 val
, *data
= frame
;
333 val
= intel_de_read(dev_priv
, TVIDEO_DIP_CTL(crtc
->pipe
));
335 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
336 val
|= g4x_infoframe_index(type
);
338 intel_de_write(dev_priv
, TVIDEO_DIP_CTL(crtc
->pipe
), val
);
340 for (i
= 0; i
< len
; i
+= 4)
341 *data
++ = intel_de_read(dev_priv
, TVIDEO_DIP_DATA(crtc
->pipe
));
344 static u32
ibx_infoframes_enabled(struct intel_encoder
*encoder
,
345 const struct intel_crtc_state
*pipe_config
)
347 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
348 enum pipe pipe
= to_intel_crtc(pipe_config
->uapi
.crtc
)->pipe
;
349 i915_reg_t reg
= TVIDEO_DIP_CTL(pipe
);
350 u32 val
= intel_de_read(dev_priv
, reg
);
352 if ((val
& VIDEO_DIP_ENABLE
) == 0)
355 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(encoder
->port
))
358 return val
& (VIDEO_DIP_ENABLE_AVI
|
359 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
360 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
363 static void cpt_write_infoframe(struct intel_encoder
*encoder
,
364 const struct intel_crtc_state
*crtc_state
,
366 const void *frame
, ssize_t len
)
368 const u32
*data
= frame
;
369 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
370 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
371 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
372 u32 val
= intel_de_read(dev_priv
, reg
);
375 drm_WARN(&dev_priv
->drm
, !(val
& VIDEO_DIP_ENABLE
),
376 "Writing DIP with CTL reg disabled\n");
378 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
379 val
|= g4x_infoframe_index(type
);
381 /* The DIP control register spec says that we need to update the AVI
382 * infoframe without clearing its enable bit */
383 if (type
!= HDMI_INFOFRAME_TYPE_AVI
)
384 val
&= ~g4x_infoframe_enable(type
);
386 intel_de_write(dev_priv
, reg
, val
);
388 for (i
= 0; i
< len
; i
+= 4) {
389 intel_de_write(dev_priv
, TVIDEO_DIP_DATA(intel_crtc
->pipe
),
393 /* Write every possible data byte to force correct ECC calculation. */
394 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
395 intel_de_write(dev_priv
, TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
397 val
|= g4x_infoframe_enable(type
);
398 val
&= ~VIDEO_DIP_FREQ_MASK
;
399 val
|= VIDEO_DIP_FREQ_VSYNC
;
401 intel_de_write(dev_priv
, reg
, val
);
402 intel_de_posting_read(dev_priv
, reg
);
405 static void cpt_read_infoframe(struct intel_encoder
*encoder
,
406 const struct intel_crtc_state
*crtc_state
,
408 void *frame
, ssize_t len
)
410 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
411 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
412 u32 val
, *data
= frame
;
415 val
= intel_de_read(dev_priv
, TVIDEO_DIP_CTL(crtc
->pipe
));
417 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
418 val
|= g4x_infoframe_index(type
);
420 intel_de_write(dev_priv
, TVIDEO_DIP_CTL(crtc
->pipe
), val
);
422 for (i
= 0; i
< len
; i
+= 4)
423 *data
++ = intel_de_read(dev_priv
, TVIDEO_DIP_DATA(crtc
->pipe
));
426 static u32
cpt_infoframes_enabled(struct intel_encoder
*encoder
,
427 const struct intel_crtc_state
*pipe_config
)
429 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
430 enum pipe pipe
= to_intel_crtc(pipe_config
->uapi
.crtc
)->pipe
;
431 u32 val
= intel_de_read(dev_priv
, TVIDEO_DIP_CTL(pipe
));
433 if ((val
& VIDEO_DIP_ENABLE
) == 0)
436 return val
& (VIDEO_DIP_ENABLE_AVI
|
437 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
438 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
441 static void vlv_write_infoframe(struct intel_encoder
*encoder
,
442 const struct intel_crtc_state
*crtc_state
,
444 const void *frame
, ssize_t len
)
446 const u32
*data
= frame
;
447 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
448 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
449 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
450 u32 val
= intel_de_read(dev_priv
, reg
);
453 drm_WARN(&dev_priv
->drm
, !(val
& VIDEO_DIP_ENABLE
),
454 "Writing DIP with CTL reg disabled\n");
456 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
457 val
|= g4x_infoframe_index(type
);
459 val
&= ~g4x_infoframe_enable(type
);
461 intel_de_write(dev_priv
, reg
, val
);
463 for (i
= 0; i
< len
; i
+= 4) {
464 intel_de_write(dev_priv
,
465 VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
468 /* Write every possible data byte to force correct ECC calculation. */
469 for (; i
< VIDEO_DIP_DATA_SIZE
; i
+= 4)
470 intel_de_write(dev_priv
,
471 VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), 0);
473 val
|= g4x_infoframe_enable(type
);
474 val
&= ~VIDEO_DIP_FREQ_MASK
;
475 val
|= VIDEO_DIP_FREQ_VSYNC
;
477 intel_de_write(dev_priv
, reg
, val
);
478 intel_de_posting_read(dev_priv
, reg
);
481 static void vlv_read_infoframe(struct intel_encoder
*encoder
,
482 const struct intel_crtc_state
*crtc_state
,
484 void *frame
, ssize_t len
)
486 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
487 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
488 u32 val
, *data
= frame
;
491 val
= intel_de_read(dev_priv
, VLV_TVIDEO_DIP_CTL(crtc
->pipe
));
493 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
494 val
|= g4x_infoframe_index(type
);
496 intel_de_write(dev_priv
, VLV_TVIDEO_DIP_CTL(crtc
->pipe
), val
);
498 for (i
= 0; i
< len
; i
+= 4)
499 *data
++ = intel_de_read(dev_priv
,
500 VLV_TVIDEO_DIP_DATA(crtc
->pipe
));
503 static u32
vlv_infoframes_enabled(struct intel_encoder
*encoder
,
504 const struct intel_crtc_state
*pipe_config
)
506 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
507 enum pipe pipe
= to_intel_crtc(pipe_config
->uapi
.crtc
)->pipe
;
508 u32 val
= intel_de_read(dev_priv
, VLV_TVIDEO_DIP_CTL(pipe
));
510 if ((val
& VIDEO_DIP_ENABLE
) == 0)
513 if ((val
& VIDEO_DIP_PORT_MASK
) != VIDEO_DIP_PORT(encoder
->port
))
516 return val
& (VIDEO_DIP_ENABLE_AVI
|
517 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
518 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
521 static void hsw_write_infoframe(struct intel_encoder
*encoder
,
522 const struct intel_crtc_state
*crtc_state
,
524 const void *frame
, ssize_t len
)
526 const u32
*data
= frame
;
527 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
528 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
529 i915_reg_t ctl_reg
= HSW_TVIDEO_DIP_CTL(cpu_transcoder
);
532 u32 val
= intel_de_read(dev_priv
, ctl_reg
);
534 data_size
= hsw_dip_data_size(dev_priv
, type
);
536 drm_WARN_ON(&dev_priv
->drm
, len
> data_size
);
538 val
&= ~hsw_infoframe_enable(type
);
539 intel_de_write(dev_priv
, ctl_reg
, val
);
541 for (i
= 0; i
< len
; i
+= 4) {
542 intel_de_write(dev_priv
,
543 hsw_dip_data_reg(dev_priv
, cpu_transcoder
, type
, i
>> 2),
547 /* Write every possible data byte to force correct ECC calculation. */
548 for (; i
< data_size
; i
+= 4)
549 intel_de_write(dev_priv
,
550 hsw_dip_data_reg(dev_priv
, cpu_transcoder
, type
, i
>> 2),
553 val
|= hsw_infoframe_enable(type
);
554 intel_de_write(dev_priv
, ctl_reg
, val
);
555 intel_de_posting_read(dev_priv
, ctl_reg
);
558 static void hsw_read_infoframe(struct intel_encoder
*encoder
,
559 const struct intel_crtc_state
*crtc_state
,
561 void *frame
, ssize_t len
)
563 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
564 enum transcoder cpu_transcoder
= crtc_state
->cpu_transcoder
;
565 u32 val
, *data
= frame
;
568 val
= intel_de_read(dev_priv
, HSW_TVIDEO_DIP_CTL(cpu_transcoder
));
570 for (i
= 0; i
< len
; i
+= 4)
571 *data
++ = intel_de_read(dev_priv
,
572 hsw_dip_data_reg(dev_priv
, cpu_transcoder
, type
, i
>> 2));
575 static u32
hsw_infoframes_enabled(struct intel_encoder
*encoder
,
576 const struct intel_crtc_state
*pipe_config
)
578 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
579 u32 val
= intel_de_read(dev_priv
,
580 HSW_TVIDEO_DIP_CTL(pipe_config
->cpu_transcoder
));
583 mask
= (VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
584 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
585 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
);
587 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
588 mask
|= VIDEO_DIP_ENABLE_DRM_GLK
;
593 static const u8 infoframe_type_to_idx
[] = {
594 HDMI_PACKET_TYPE_GENERAL_CONTROL
,
595 HDMI_PACKET_TYPE_GAMUT_METADATA
,
597 HDMI_INFOFRAME_TYPE_AVI
,
598 HDMI_INFOFRAME_TYPE_SPD
,
599 HDMI_INFOFRAME_TYPE_VENDOR
,
600 HDMI_INFOFRAME_TYPE_DRM
,
603 u32
intel_hdmi_infoframe_enable(unsigned int type
)
607 for (i
= 0; i
< ARRAY_SIZE(infoframe_type_to_idx
); i
++) {
608 if (infoframe_type_to_idx
[i
] == type
)
615 u32
intel_hdmi_infoframes_enabled(struct intel_encoder
*encoder
,
616 const struct intel_crtc_state
*crtc_state
)
618 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
619 struct intel_digital_port
*dig_port
= enc_to_dig_port(encoder
);
623 val
= dig_port
->infoframes_enabled(encoder
, crtc_state
);
625 /* map from hardware bits to dip idx */
626 for (i
= 0; i
< ARRAY_SIZE(infoframe_type_to_idx
); i
++) {
627 unsigned int type
= infoframe_type_to_idx
[i
];
629 if (HAS_DDI(dev_priv
)) {
630 if (val
& hsw_infoframe_enable(type
))
633 if (val
& g4x_infoframe_enable(type
))
642 * The data we write to the DIP data buffer registers is 1 byte bigger than the
643 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
644 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
645 * used for both technologies.
647 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
648 * DW1: DB3 | DB2 | DB1 | DB0
649 * DW2: DB7 | DB6 | DB5 | DB4
652 * (HB is Header Byte, DB is Data Byte)
654 * The hdmi pack() functions don't know about that hardware specific hole so we
655 * trick them by giving an offset into the buffer and moving back the header
658 static void intel_write_infoframe(struct intel_encoder
*encoder
,
659 const struct intel_crtc_state
*crtc_state
,
660 enum hdmi_infoframe_type type
,
661 const union hdmi_infoframe
*frame
)
663 struct intel_digital_port
*dig_port
= enc_to_dig_port(encoder
);
664 u8 buffer
[VIDEO_DIP_DATA_SIZE
];
667 if ((crtc_state
->infoframes
.enable
&
668 intel_hdmi_infoframe_enable(type
)) == 0)
671 if (drm_WARN_ON(encoder
->base
.dev
, frame
->any
.type
!= type
))
674 /* see comment above for the reason for this offset */
675 len
= hdmi_infoframe_pack_only(frame
, buffer
+ 1, sizeof(buffer
) - 1);
676 if (drm_WARN_ON(encoder
->base
.dev
, len
< 0))
679 /* Insert the 'hole' (see big comment above) at position 3 */
680 memmove(&buffer
[0], &buffer
[1], 3);
684 dig_port
->write_infoframe(encoder
, crtc_state
, type
, buffer
, len
);
687 void intel_read_infoframe(struct intel_encoder
*encoder
,
688 const struct intel_crtc_state
*crtc_state
,
689 enum hdmi_infoframe_type type
,
690 union hdmi_infoframe
*frame
)
692 struct intel_digital_port
*dig_port
= enc_to_dig_port(encoder
);
693 u8 buffer
[VIDEO_DIP_DATA_SIZE
];
696 if ((crtc_state
->infoframes
.enable
&
697 intel_hdmi_infoframe_enable(type
)) == 0)
700 dig_port
->read_infoframe(encoder
, crtc_state
,
701 type
, buffer
, sizeof(buffer
));
703 /* Fill the 'hole' (see big comment above) at position 3 */
704 memmove(&buffer
[1], &buffer
[0], 3);
706 /* see comment above for the reason for this offset */
707 ret
= hdmi_infoframe_unpack(frame
, buffer
+ 1, sizeof(buffer
) - 1);
709 drm_dbg_kms(encoder
->base
.dev
,
710 "Failed to unpack infoframe type 0x%02x\n", type
);
714 if (frame
->any
.type
!= type
)
715 drm_dbg_kms(encoder
->base
.dev
,
716 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
717 frame
->any
.type
, type
);
721 intel_hdmi_compute_avi_infoframe(struct intel_encoder
*encoder
,
722 struct intel_crtc_state
*crtc_state
,
723 struct drm_connector_state
*conn_state
)
725 struct hdmi_avi_infoframe
*frame
= &crtc_state
->infoframes
.avi
.avi
;
726 const struct drm_display_mode
*adjusted_mode
=
727 &crtc_state
->hw
.adjusted_mode
;
728 struct drm_connector
*connector
= conn_state
->connector
;
731 if (!crtc_state
->has_infoframe
)
734 crtc_state
->infoframes
.enable
|=
735 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI
);
737 ret
= drm_hdmi_avi_infoframe_from_display_mode(frame
, connector
,
742 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
743 frame
->colorspace
= HDMI_COLORSPACE_YUV420
;
744 else if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR444
)
745 frame
->colorspace
= HDMI_COLORSPACE_YUV444
;
747 frame
->colorspace
= HDMI_COLORSPACE_RGB
;
749 drm_hdmi_avi_infoframe_colorspace(frame
, conn_state
);
751 /* nonsense combination */
752 drm_WARN_ON(encoder
->base
.dev
, crtc_state
->limited_color_range
&&
753 crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
);
755 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_RGB
) {
756 drm_hdmi_avi_infoframe_quant_range(frame
, connector
,
758 crtc_state
->limited_color_range
?
759 HDMI_QUANTIZATION_RANGE_LIMITED
:
760 HDMI_QUANTIZATION_RANGE_FULL
);
762 frame
->quantization_range
= HDMI_QUANTIZATION_RANGE_DEFAULT
;
763 frame
->ycc_quantization_range
= HDMI_YCC_QUANTIZATION_RANGE_LIMITED
;
766 drm_hdmi_avi_infoframe_content_type(frame
, conn_state
);
768 /* TODO: handle pixel repetition for YCBCR420 outputs */
770 ret
= hdmi_avi_infoframe_check(frame
);
771 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
778 intel_hdmi_compute_spd_infoframe(struct intel_encoder
*encoder
,
779 struct intel_crtc_state
*crtc_state
,
780 struct drm_connector_state
*conn_state
)
782 struct hdmi_spd_infoframe
*frame
= &crtc_state
->infoframes
.spd
.spd
;
785 if (!crtc_state
->has_infoframe
)
788 crtc_state
->infoframes
.enable
|=
789 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD
);
791 ret
= hdmi_spd_infoframe_init(frame
, "Intel", "Integrated gfx");
792 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
795 frame
->sdi
= HDMI_SPD_SDI_PC
;
797 ret
= hdmi_spd_infoframe_check(frame
);
798 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
805 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder
*encoder
,
806 struct intel_crtc_state
*crtc_state
,
807 struct drm_connector_state
*conn_state
)
809 struct hdmi_vendor_infoframe
*frame
=
810 &crtc_state
->infoframes
.hdmi
.vendor
.hdmi
;
811 const struct drm_display_info
*info
=
812 &conn_state
->connector
->display_info
;
815 if (!crtc_state
->has_infoframe
|| !info
->has_hdmi_infoframe
)
818 crtc_state
->infoframes
.enable
|=
819 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR
);
821 ret
= drm_hdmi_vendor_infoframe_from_display_mode(frame
,
822 conn_state
->connector
,
823 &crtc_state
->hw
.adjusted_mode
);
824 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
827 ret
= hdmi_vendor_infoframe_check(frame
);
828 if (drm_WARN_ON(encoder
->base
.dev
, ret
))
835 intel_hdmi_compute_drm_infoframe(struct intel_encoder
*encoder
,
836 struct intel_crtc_state
*crtc_state
,
837 struct drm_connector_state
*conn_state
)
839 struct hdmi_drm_infoframe
*frame
= &crtc_state
->infoframes
.drm
.drm
;
840 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
843 if (!(INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
)))
846 if (!crtc_state
->has_infoframe
)
849 if (!conn_state
->hdr_output_metadata
)
852 crtc_state
->infoframes
.enable
|=
853 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM
);
855 ret
= drm_hdmi_infoframe_set_hdr_metadata(frame
, conn_state
);
857 drm_dbg_kms(&dev_priv
->drm
,
858 "couldn't set HDR metadata in infoframe\n");
862 ret
= hdmi_drm_infoframe_check(frame
);
863 if (drm_WARN_ON(&dev_priv
->drm
, ret
))
869 static void g4x_set_infoframes(struct intel_encoder
*encoder
,
871 const struct intel_crtc_state
*crtc_state
,
872 const struct drm_connector_state
*conn_state
)
874 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
875 struct intel_digital_port
*dig_port
= enc_to_dig_port(encoder
);
876 struct intel_hdmi
*intel_hdmi
= &dig_port
->hdmi
;
877 i915_reg_t reg
= VIDEO_DIP_CTL
;
878 u32 val
= intel_de_read(dev_priv
, reg
);
879 u32 port
= VIDEO_DIP_PORT(encoder
->port
);
881 assert_hdmi_port_disabled(intel_hdmi
);
883 /* If the registers were not initialized yet, they might be zeroes,
884 * which means we're selecting the AVI DIP and we're setting its
885 * frequency to once. This seems to really confuse the HW and make
886 * things stop working (the register spec says the AVI always needs to
887 * be sent every VSync). So here we avoid writing to the register more
888 * than we need and also explicitly select the AVI DIP and explicitly
889 * set its frequency to every VSync. Avoiding to write it twice seems to
890 * be enough to solve the problem, but being defensive shouldn't hurt us
892 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
895 if (!(val
& VIDEO_DIP_ENABLE
))
897 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
898 drm_dbg_kms(&dev_priv
->drm
,
899 "video DIP still enabled on port %c\n",
900 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
903 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
904 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
905 intel_de_write(dev_priv
, reg
, val
);
906 intel_de_posting_read(dev_priv
, reg
);
910 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
911 if (val
& VIDEO_DIP_ENABLE
) {
912 drm_dbg_kms(&dev_priv
->drm
,
913 "video DIP already enabled on port %c\n",
914 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
917 val
&= ~VIDEO_DIP_PORT_MASK
;
921 val
|= VIDEO_DIP_ENABLE
;
922 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
923 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_SPD
);
925 intel_de_write(dev_priv
, reg
, val
);
926 intel_de_posting_read(dev_priv
, reg
);
928 intel_write_infoframe(encoder
, crtc_state
,
929 HDMI_INFOFRAME_TYPE_AVI
,
930 &crtc_state
->infoframes
.avi
);
931 intel_write_infoframe(encoder
, crtc_state
,
932 HDMI_INFOFRAME_TYPE_SPD
,
933 &crtc_state
->infoframes
.spd
);
934 intel_write_infoframe(encoder
, crtc_state
,
935 HDMI_INFOFRAME_TYPE_VENDOR
,
936 &crtc_state
->infoframes
.hdmi
);
940 * Determine if default_phase=1 can be indicated in the GCP infoframe.
942 * From HDMI specification 1.4a:
943 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
944 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
945 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
946 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
949 static bool gcp_default_phase_possible(int pipe_bpp
,
950 const struct drm_display_mode
*mode
)
952 unsigned int pixels_per_group
;
956 /* 4 pixels in 5 clocks */
957 pixels_per_group
= 4;
960 /* 2 pixels in 3 clocks */
961 pixels_per_group
= 2;
964 /* 1 pixel in 2 clocks */
965 pixels_per_group
= 1;
968 /* phase information not relevant for 8bpc */
972 return mode
->crtc_hdisplay
% pixels_per_group
== 0 &&
973 mode
->crtc_htotal
% pixels_per_group
== 0 &&
974 mode
->crtc_hblank_start
% pixels_per_group
== 0 &&
975 mode
->crtc_hblank_end
% pixels_per_group
== 0 &&
976 mode
->crtc_hsync_start
% pixels_per_group
== 0 &&
977 mode
->crtc_hsync_end
% pixels_per_group
== 0 &&
978 ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) == 0 ||
979 mode
->crtc_htotal
/2 % pixels_per_group
== 0);
982 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder
*encoder
,
983 const struct intel_crtc_state
*crtc_state
,
984 const struct drm_connector_state
*conn_state
)
986 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
987 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
990 if ((crtc_state
->infoframes
.enable
&
991 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
)) == 0)
994 if (HAS_DDI(dev_priv
))
995 reg
= HSW_TVIDEO_DIP_GCP(crtc_state
->cpu_transcoder
);
996 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
997 reg
= VLV_TVIDEO_DIP_GCP(crtc
->pipe
);
998 else if (HAS_PCH_SPLIT(dev_priv
))
999 reg
= TVIDEO_DIP_GCP(crtc
->pipe
);
1003 intel_de_write(dev_priv
, reg
, crtc_state
->infoframes
.gcp
);
1008 void intel_hdmi_read_gcp_infoframe(struct intel_encoder
*encoder
,
1009 struct intel_crtc_state
*crtc_state
)
1011 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1012 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1015 if ((crtc_state
->infoframes
.enable
&
1016 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
)) == 0)
1019 if (HAS_DDI(dev_priv
))
1020 reg
= HSW_TVIDEO_DIP_GCP(crtc_state
->cpu_transcoder
);
1021 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1022 reg
= VLV_TVIDEO_DIP_GCP(crtc
->pipe
);
1023 else if (HAS_PCH_SPLIT(dev_priv
))
1024 reg
= TVIDEO_DIP_GCP(crtc
->pipe
);
1028 crtc_state
->infoframes
.gcp
= intel_de_read(dev_priv
, reg
);
1031 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder
*encoder
,
1032 struct intel_crtc_state
*crtc_state
,
1033 struct drm_connector_state
*conn_state
)
1035 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1037 if (IS_G4X(dev_priv
) || !crtc_state
->has_infoframe
)
1040 crtc_state
->infoframes
.enable
|=
1041 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL
);
1043 /* Indicate color indication for deep color mode */
1044 if (crtc_state
->pipe_bpp
> 24)
1045 crtc_state
->infoframes
.gcp
|= GCP_COLOR_INDICATION
;
1047 /* Enable default_phase whenever the display mode is suitably aligned */
1048 if (gcp_default_phase_possible(crtc_state
->pipe_bpp
,
1049 &crtc_state
->hw
.adjusted_mode
))
1050 crtc_state
->infoframes
.gcp
|= GCP_DEFAULT_PHASE_ENABLE
;
1053 static void ibx_set_infoframes(struct intel_encoder
*encoder
,
1055 const struct intel_crtc_state
*crtc_state
,
1056 const struct drm_connector_state
*conn_state
)
1058 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1059 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1060 struct intel_digital_port
*dig_port
= enc_to_dig_port(encoder
);
1061 struct intel_hdmi
*intel_hdmi
= &dig_port
->hdmi
;
1062 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
1063 u32 val
= intel_de_read(dev_priv
, reg
);
1064 u32 port
= VIDEO_DIP_PORT(encoder
->port
);
1066 assert_hdmi_port_disabled(intel_hdmi
);
1068 /* See the big comment in g4x_set_infoframes() */
1069 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
1072 if (!(val
& VIDEO_DIP_ENABLE
))
1074 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
1075 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1076 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1077 intel_de_write(dev_priv
, reg
, val
);
1078 intel_de_posting_read(dev_priv
, reg
);
1082 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
1083 drm_WARN(&dev_priv
->drm
, val
& VIDEO_DIP_ENABLE
,
1084 "DIP already enabled on port %c\n",
1085 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
1086 val
&= ~VIDEO_DIP_PORT_MASK
;
1090 val
|= VIDEO_DIP_ENABLE
;
1091 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
1092 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1093 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1095 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1096 val
|= VIDEO_DIP_ENABLE_GCP
;
1098 intel_de_write(dev_priv
, reg
, val
);
1099 intel_de_posting_read(dev_priv
, reg
);
1101 intel_write_infoframe(encoder
, crtc_state
,
1102 HDMI_INFOFRAME_TYPE_AVI
,
1103 &crtc_state
->infoframes
.avi
);
1104 intel_write_infoframe(encoder
, crtc_state
,
1105 HDMI_INFOFRAME_TYPE_SPD
,
1106 &crtc_state
->infoframes
.spd
);
1107 intel_write_infoframe(encoder
, crtc_state
,
1108 HDMI_INFOFRAME_TYPE_VENDOR
,
1109 &crtc_state
->infoframes
.hdmi
);
1112 static void cpt_set_infoframes(struct intel_encoder
*encoder
,
1114 const struct intel_crtc_state
*crtc_state
,
1115 const struct drm_connector_state
*conn_state
)
1117 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1118 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1119 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1120 i915_reg_t reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
1121 u32 val
= intel_de_read(dev_priv
, reg
);
1123 assert_hdmi_port_disabled(intel_hdmi
);
1125 /* See the big comment in g4x_set_infoframes() */
1126 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
1129 if (!(val
& VIDEO_DIP_ENABLE
))
1131 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
1132 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1133 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1134 intel_de_write(dev_priv
, reg
, val
);
1135 intel_de_posting_read(dev_priv
, reg
);
1139 /* Set both together, unset both together: see the spec. */
1140 val
|= VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
;
1141 val
&= ~(VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1142 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1144 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1145 val
|= VIDEO_DIP_ENABLE_GCP
;
1147 intel_de_write(dev_priv
, reg
, val
);
1148 intel_de_posting_read(dev_priv
, reg
);
1150 intel_write_infoframe(encoder
, crtc_state
,
1151 HDMI_INFOFRAME_TYPE_AVI
,
1152 &crtc_state
->infoframes
.avi
);
1153 intel_write_infoframe(encoder
, crtc_state
,
1154 HDMI_INFOFRAME_TYPE_SPD
,
1155 &crtc_state
->infoframes
.spd
);
1156 intel_write_infoframe(encoder
, crtc_state
,
1157 HDMI_INFOFRAME_TYPE_VENDOR
,
1158 &crtc_state
->infoframes
.hdmi
);
1161 static void vlv_set_infoframes(struct intel_encoder
*encoder
,
1163 const struct intel_crtc_state
*crtc_state
,
1164 const struct drm_connector_state
*conn_state
)
1166 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1167 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1168 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1169 i915_reg_t reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
1170 u32 val
= intel_de_read(dev_priv
, reg
);
1171 u32 port
= VIDEO_DIP_PORT(encoder
->port
);
1173 assert_hdmi_port_disabled(intel_hdmi
);
1175 /* See the big comment in g4x_set_infoframes() */
1176 val
|= VIDEO_DIP_SELECT_AVI
| VIDEO_DIP_FREQ_VSYNC
;
1179 if (!(val
& VIDEO_DIP_ENABLE
))
1181 val
&= ~(VIDEO_DIP_ENABLE
| VIDEO_DIP_ENABLE_AVI
|
1182 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1183 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1184 intel_de_write(dev_priv
, reg
, val
);
1185 intel_de_posting_read(dev_priv
, reg
);
1189 if (port
!= (val
& VIDEO_DIP_PORT_MASK
)) {
1190 drm_WARN(&dev_priv
->drm
, val
& VIDEO_DIP_ENABLE
,
1191 "DIP already enabled on port %c\n",
1192 (val
& VIDEO_DIP_PORT_MASK
) >> 29);
1193 val
&= ~VIDEO_DIP_PORT_MASK
;
1197 val
|= VIDEO_DIP_ENABLE
;
1198 val
&= ~(VIDEO_DIP_ENABLE_AVI
|
1199 VIDEO_DIP_ENABLE_VENDOR
| VIDEO_DIP_ENABLE_GAMUT
|
1200 VIDEO_DIP_ENABLE_SPD
| VIDEO_DIP_ENABLE_GCP
);
1202 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1203 val
|= VIDEO_DIP_ENABLE_GCP
;
1205 intel_de_write(dev_priv
, reg
, val
);
1206 intel_de_posting_read(dev_priv
, reg
);
1208 intel_write_infoframe(encoder
, crtc_state
,
1209 HDMI_INFOFRAME_TYPE_AVI
,
1210 &crtc_state
->infoframes
.avi
);
1211 intel_write_infoframe(encoder
, crtc_state
,
1212 HDMI_INFOFRAME_TYPE_SPD
,
1213 &crtc_state
->infoframes
.spd
);
1214 intel_write_infoframe(encoder
, crtc_state
,
1215 HDMI_INFOFRAME_TYPE_VENDOR
,
1216 &crtc_state
->infoframes
.hdmi
);
1219 static void hsw_set_infoframes(struct intel_encoder
*encoder
,
1221 const struct intel_crtc_state
*crtc_state
,
1222 const struct drm_connector_state
*conn_state
)
1224 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1225 i915_reg_t reg
= HSW_TVIDEO_DIP_CTL(crtc_state
->cpu_transcoder
);
1226 u32 val
= intel_de_read(dev_priv
, reg
);
1228 assert_hdmi_transcoder_func_disabled(dev_priv
,
1229 crtc_state
->cpu_transcoder
);
1231 val
&= ~(VIDEO_DIP_ENABLE_VSC_HSW
| VIDEO_DIP_ENABLE_AVI_HSW
|
1232 VIDEO_DIP_ENABLE_GCP_HSW
| VIDEO_DIP_ENABLE_VS_HSW
|
1233 VIDEO_DIP_ENABLE_GMP_HSW
| VIDEO_DIP_ENABLE_SPD_HSW
|
1234 VIDEO_DIP_ENABLE_DRM_GLK
);
1237 intel_de_write(dev_priv
, reg
, val
);
1238 intel_de_posting_read(dev_priv
, reg
);
1242 if (intel_hdmi_set_gcp_infoframe(encoder
, crtc_state
, conn_state
))
1243 val
|= VIDEO_DIP_ENABLE_GCP_HSW
;
1245 intel_de_write(dev_priv
, reg
, val
);
1246 intel_de_posting_read(dev_priv
, reg
);
1248 intel_write_infoframe(encoder
, crtc_state
,
1249 HDMI_INFOFRAME_TYPE_AVI
,
1250 &crtc_state
->infoframes
.avi
);
1251 intel_write_infoframe(encoder
, crtc_state
,
1252 HDMI_INFOFRAME_TYPE_SPD
,
1253 &crtc_state
->infoframes
.spd
);
1254 intel_write_infoframe(encoder
, crtc_state
,
1255 HDMI_INFOFRAME_TYPE_VENDOR
,
1256 &crtc_state
->infoframes
.hdmi
);
1257 intel_write_infoframe(encoder
, crtc_state
,
1258 HDMI_INFOFRAME_TYPE_DRM
,
1259 &crtc_state
->infoframes
.drm
);
1262 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi
*hdmi
, bool enable
)
1264 struct drm_i915_private
*dev_priv
= to_i915(intel_hdmi_to_dev(hdmi
));
1265 struct i2c_adapter
*adapter
=
1266 intel_gmbus_get_adapter(dev_priv
, hdmi
->ddc_bus
);
1268 if (hdmi
->dp_dual_mode
.type
< DRM_DP_DUAL_MODE_TYPE2_DVI
)
1271 if (dev_priv
->bypass_tmds_oe
) {
1272 drm_dbg_kms(&dev_priv
->drm
, "Bypassing TMDS_OE setting\n");
1276 drm_dbg_kms(&dev_priv
->drm
, "%s DP dual mode adaptor TMDS output\n",
1277 enable
? "Enabling" : "Disabling");
1279 drm_dp_dual_mode_set_tmds_output(hdmi
->dp_dual_mode
.type
,
1283 static int intel_hdmi_hdcp_read(struct intel_digital_port
*dig_port
,
1284 unsigned int offset
, void *buffer
, size_t size
)
1286 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1287 struct intel_hdmi
*hdmi
= &dig_port
->hdmi
;
1288 struct i2c_adapter
*adapter
= intel_gmbus_get_adapter(i915
,
1291 u8 start
= offset
& 0xff;
1292 struct i2c_msg msgs
[] = {
1294 .addr
= DRM_HDCP_DDC_ADDR
,
1300 .addr
= DRM_HDCP_DDC_ADDR
,
1306 ret
= i2c_transfer(adapter
, msgs
, ARRAY_SIZE(msgs
));
1307 if (ret
== ARRAY_SIZE(msgs
))
1309 return ret
>= 0 ? -EIO
: ret
;
1312 static int intel_hdmi_hdcp_write(struct intel_digital_port
*dig_port
,
1313 unsigned int offset
, void *buffer
, size_t size
)
1315 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1316 struct intel_hdmi
*hdmi
= &dig_port
->hdmi
;
1317 struct i2c_adapter
*adapter
= intel_gmbus_get_adapter(i915
,
1323 write_buf
= kzalloc(size
+ 1, GFP_KERNEL
);
1327 write_buf
[0] = offset
& 0xff;
1328 memcpy(&write_buf
[1], buffer
, size
);
1330 msg
.addr
= DRM_HDCP_DDC_ADDR
;
1333 msg
.buf
= write_buf
;
1335 ret
= i2c_transfer(adapter
, &msg
, 1);
1346 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port
*dig_port
,
1349 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1350 struct intel_hdmi
*hdmi
= &dig_port
->hdmi
;
1351 struct i2c_adapter
*adapter
= intel_gmbus_get_adapter(i915
,
1355 ret
= intel_hdmi_hdcp_write(dig_port
, DRM_HDCP_DDC_AN
, an
,
1358 drm_dbg_kms(&i915
->drm
, "Write An over DDC failed (%d)\n",
1363 ret
= intel_gmbus_output_aksv(adapter
);
1365 drm_dbg_kms(&i915
->drm
, "Failed to output aksv (%d)\n", ret
);
1371 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port
*dig_port
,
1374 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1377 ret
= intel_hdmi_hdcp_read(dig_port
, DRM_HDCP_DDC_BKSV
, bksv
,
1380 drm_dbg_kms(&i915
->drm
, "Read Bksv over DDC failed (%d)\n",
1386 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port
*dig_port
,
1389 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1392 ret
= intel_hdmi_hdcp_read(dig_port
, DRM_HDCP_DDC_BSTATUS
,
1393 bstatus
, DRM_HDCP_BSTATUS_LEN
);
1395 drm_dbg_kms(&i915
->drm
, "Read bstatus over DDC failed (%d)\n",
1401 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port
*dig_port
,
1402 bool *repeater_present
)
1404 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1408 ret
= intel_hdmi_hdcp_read(dig_port
, DRM_HDCP_DDC_BCAPS
, &val
, 1);
1410 drm_dbg_kms(&i915
->drm
, "Read bcaps over DDC failed (%d)\n",
1414 *repeater_present
= val
& DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT
;
1419 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port
*dig_port
,
1422 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1425 ret
= intel_hdmi_hdcp_read(dig_port
, DRM_HDCP_DDC_RI_PRIME
,
1426 ri_prime
, DRM_HDCP_RI_LEN
);
1428 drm_dbg_kms(&i915
->drm
, "Read Ri' over DDC failed (%d)\n",
1434 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port
*dig_port
,
1437 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1441 ret
= intel_hdmi_hdcp_read(dig_port
, DRM_HDCP_DDC_BCAPS
, &val
, 1);
1443 drm_dbg_kms(&i915
->drm
, "Read bcaps over DDC failed (%d)\n",
1447 *ksv_ready
= val
& DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY
;
1452 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port
*dig_port
,
1453 int num_downstream
, u8
*ksv_fifo
)
1455 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1457 ret
= intel_hdmi_hdcp_read(dig_port
, DRM_HDCP_DDC_KSV_FIFO
,
1458 ksv_fifo
, num_downstream
* DRM_HDCP_KSV_LEN
);
1460 drm_dbg_kms(&i915
->drm
,
1461 "Read ksv fifo over DDC failed (%d)\n", ret
);
1468 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port
*dig_port
,
1471 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1474 if (i
>= DRM_HDCP_V_PRIME_NUM_PARTS
)
1477 ret
= intel_hdmi_hdcp_read(dig_port
, DRM_HDCP_DDC_V_PRIME(i
),
1478 part
, DRM_HDCP_V_PRIME_PART_LEN
);
1480 drm_dbg_kms(&i915
->drm
, "Read V'[%d] over DDC failed (%d)\n",
1485 static int kbl_repositioning_enc_en_signal(struct intel_connector
*connector
,
1486 enum transcoder cpu_transcoder
)
1488 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
1489 struct intel_digital_port
*dig_port
= intel_attached_dig_port(connector
);
1490 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
1491 struct intel_crtc
*intel_crtc
= container_of(crtc
,
1492 struct intel_crtc
, base
);
1497 scanline
= intel_de_read(dev_priv
, PIPEDSL(intel_crtc
->pipe
));
1498 if (scanline
> 100 && scanline
< 200)
1500 usleep_range(25, 50);
1503 ret
= intel_ddi_toggle_hdcp_signalling(&dig_port
->base
, cpu_transcoder
,
1506 drm_err(&dev_priv
->drm
,
1507 "Disable HDCP signalling failed (%d)\n", ret
);
1510 ret
= intel_ddi_toggle_hdcp_signalling(&dig_port
->base
, cpu_transcoder
,
1513 drm_err(&dev_priv
->drm
,
1514 "Enable HDCP signalling failed (%d)\n", ret
);
1522 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port
*dig_port
,
1523 enum transcoder cpu_transcoder
,
1526 struct intel_hdmi
*hdmi
= &dig_port
->hdmi
;
1527 struct intel_connector
*connector
= hdmi
->attached_connector
;
1528 struct drm_i915_private
*dev_priv
= to_i915(connector
->base
.dev
);
1532 usleep_range(6, 60); /* Bspec says >= 6us */
1534 ret
= intel_ddi_toggle_hdcp_signalling(&dig_port
->base
, cpu_transcoder
,
1537 drm_err(&dev_priv
->drm
, "%s HDCP signalling failed (%d)\n",
1538 enable
? "Enable" : "Disable", ret
);
1543 * WA: To fix incorrect positioning of the window of
1544 * opportunity and enc_en signalling in KABYLAKE.
1546 if (IS_KABYLAKE(dev_priv
) && enable
)
1547 return kbl_repositioning_enc_en_signal(connector
,
1554 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port
*dig_port
,
1555 struct intel_connector
*connector
)
1557 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1558 enum port port
= dig_port
->base
.port
;
1559 enum transcoder cpu_transcoder
= connector
->hdcp
.cpu_transcoder
;
1563 u8 shim
[DRM_HDCP_RI_LEN
];
1566 ret
= intel_hdmi_hdcp_read_ri_prime(dig_port
, ri
.shim
);
1570 intel_de_write(i915
, HDCP_RPRIME(i915
, cpu_transcoder
, port
), ri
.reg
);
1572 /* Wait for Ri prime match */
1573 if (wait_for((intel_de_read(i915
, HDCP_STATUS(i915
, cpu_transcoder
, port
)) &
1574 (HDCP_STATUS_RI_MATCH
| HDCP_STATUS_ENC
)) ==
1575 (HDCP_STATUS_RI_MATCH
| HDCP_STATUS_ENC
), 1)) {
1576 drm_dbg_kms(&i915
->drm
, "Ri' mismatch detected (%x)\n",
1577 intel_de_read(i915
, HDCP_STATUS(i915
, cpu_transcoder
,
1585 bool intel_hdmi_hdcp_check_link(struct intel_digital_port
*dig_port
,
1586 struct intel_connector
*connector
)
1588 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1591 for (retry
= 0; retry
< 3; retry
++)
1592 if (intel_hdmi_hdcp_check_link_once(dig_port
, connector
))
1595 drm_err(&i915
->drm
, "Link check failed\n");
1599 struct hdcp2_hdmi_msg_timeout
{
1604 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout
[] = {
1605 { HDCP_2_2_AKE_SEND_CERT
, HDCP_2_2_CERT_TIMEOUT_MS
, },
1606 { HDCP_2_2_AKE_SEND_PAIRING_INFO
, HDCP_2_2_PAIRING_TIMEOUT_MS
, },
1607 { HDCP_2_2_LC_SEND_LPRIME
, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS
, },
1608 { HDCP_2_2_REP_SEND_RECVID_LIST
, HDCP_2_2_RECVID_LIST_TIMEOUT_MS
, },
1609 { HDCP_2_2_REP_STREAM_READY
, HDCP_2_2_STREAM_READY_TIMEOUT_MS
, },
1613 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port
*dig_port
,
1616 return intel_hdmi_hdcp_read(dig_port
,
1617 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET
,
1619 HDCP_2_2_HDMI_RXSTATUS_LEN
);
1622 static int get_hdcp2_msg_timeout(u8 msg_id
, bool is_paired
)
1626 if (msg_id
== HDCP_2_2_AKE_SEND_HPRIME
) {
1628 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS
;
1630 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS
;
1633 for (i
= 0; i
< ARRAY_SIZE(hdcp2_msg_timeout
); i
++) {
1634 if (hdcp2_msg_timeout
[i
].msg_id
== msg_id
)
1635 return hdcp2_msg_timeout
[i
].timeout
;
1642 hdcp2_detect_msg_availability(struct intel_digital_port
*dig_port
,
1643 u8 msg_id
, bool *msg_ready
,
1646 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1647 u8 rx_status
[HDCP_2_2_HDMI_RXSTATUS_LEN
];
1650 ret
= intel_hdmi_hdcp2_read_rx_status(dig_port
, rx_status
);
1652 drm_dbg_kms(&i915
->drm
, "rx_status read failed. Err %d\n",
1657 *msg_sz
= ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status
[1]) << 8) |
1660 if (msg_id
== HDCP_2_2_REP_SEND_RECVID_LIST
)
1661 *msg_ready
= (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status
[1]) &&
1664 *msg_ready
= *msg_sz
;
1670 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port
*dig_port
,
1671 u8 msg_id
, bool paired
)
1673 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1674 bool msg_ready
= false;
1678 timeout
= get_hdcp2_msg_timeout(msg_id
, paired
);
1682 ret
= __wait_for(ret
= hdcp2_detect_msg_availability(dig_port
,
1685 !ret
&& msg_ready
&& msg_sz
, timeout
* 1000,
1688 drm_dbg_kms(&i915
->drm
, "msg_id: %d, ret: %d, timeout: %d\n",
1689 msg_id
, ret
, timeout
);
1691 return ret
? ret
: msg_sz
;
1695 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port
*dig_port
,
1696 void *buf
, size_t size
)
1698 unsigned int offset
;
1700 offset
= HDCP_2_2_HDMI_REG_WR_MSG_OFFSET
;
1701 return intel_hdmi_hdcp_write(dig_port
, offset
, buf
, size
);
1705 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port
*dig_port
,
1706 u8 msg_id
, void *buf
, size_t size
)
1708 struct drm_i915_private
*i915
= to_i915(dig_port
->base
.base
.dev
);
1709 struct intel_hdmi
*hdmi
= &dig_port
->hdmi
;
1710 struct intel_hdcp
*hdcp
= &hdmi
->attached_connector
->hdcp
;
1711 unsigned int offset
;
1714 ret
= intel_hdmi_hdcp2_wait_for_msg(dig_port
, msg_id
,
1720 * Available msg size should be equal to or lesser than the
1724 drm_dbg_kms(&i915
->drm
,
1725 "msg_sz(%zd) is more than exp size(%zu)\n",
1730 offset
= HDCP_2_2_HDMI_REG_RD_MSG_OFFSET
;
1731 ret
= intel_hdmi_hdcp_read(dig_port
, offset
, buf
, ret
);
1733 drm_dbg_kms(&i915
->drm
, "Failed to read msg_id: %d(%zd)\n",
1740 int intel_hdmi_hdcp2_check_link(struct intel_digital_port
*dig_port
)
1742 u8 rx_status
[HDCP_2_2_HDMI_RXSTATUS_LEN
];
1745 ret
= intel_hdmi_hdcp2_read_rx_status(dig_port
, rx_status
);
1750 * Re-auth request and Link Integrity Failures are represented by
1751 * same bit. i.e reauth_req.
1753 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status
[1]))
1754 ret
= HDCP_REAUTH_REQUEST
;
1755 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status
[1]))
1756 ret
= HDCP_TOPOLOGY_CHANGE
;
1762 int intel_hdmi_hdcp2_capable(struct intel_digital_port
*dig_port
,
1769 ret
= intel_hdmi_hdcp_read(dig_port
, HDCP_2_2_HDMI_REG_VER_OFFSET
,
1770 &hdcp2_version
, sizeof(hdcp2_version
));
1771 if (!ret
&& hdcp2_version
& HDCP_2_2_HDMI_SUPPORT_MASK
)
1777 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim
= {
1778 .write_an_aksv
= intel_hdmi_hdcp_write_an_aksv
,
1779 .read_bksv
= intel_hdmi_hdcp_read_bksv
,
1780 .read_bstatus
= intel_hdmi_hdcp_read_bstatus
,
1781 .repeater_present
= intel_hdmi_hdcp_repeater_present
,
1782 .read_ri_prime
= intel_hdmi_hdcp_read_ri_prime
,
1783 .read_ksv_ready
= intel_hdmi_hdcp_read_ksv_ready
,
1784 .read_ksv_fifo
= intel_hdmi_hdcp_read_ksv_fifo
,
1785 .read_v_prime_part
= intel_hdmi_hdcp_read_v_prime_part
,
1786 .toggle_signalling
= intel_hdmi_hdcp_toggle_signalling
,
1787 .check_link
= intel_hdmi_hdcp_check_link
,
1788 .write_2_2_msg
= intel_hdmi_hdcp2_write_msg
,
1789 .read_2_2_msg
= intel_hdmi_hdcp2_read_msg
,
1790 .check_2_2_link
= intel_hdmi_hdcp2_check_link
,
1791 .hdcp_2_2_capable
= intel_hdmi_hdcp2_capable
,
1792 .protocol
= HDCP_PROTOCOL_HDMI
,
1795 static void intel_hdmi_prepare(struct intel_encoder
*encoder
,
1796 const struct intel_crtc_state
*crtc_state
)
1798 struct drm_device
*dev
= encoder
->base
.dev
;
1799 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1800 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->uapi
.crtc
);
1801 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1802 const struct drm_display_mode
*adjusted_mode
= &crtc_state
->hw
.adjusted_mode
;
1805 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, true);
1807 hdmi_val
= SDVO_ENCODING_HDMI
;
1808 if (!HAS_PCH_SPLIT(dev_priv
) && crtc_state
->limited_color_range
)
1809 hdmi_val
|= HDMI_COLOR_RANGE_16_235
;
1810 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
1811 hdmi_val
|= SDVO_VSYNC_ACTIVE_HIGH
;
1812 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
1813 hdmi_val
|= SDVO_HSYNC_ACTIVE_HIGH
;
1815 if (crtc_state
->pipe_bpp
> 24)
1816 hdmi_val
|= HDMI_COLOR_FORMAT_12bpc
;
1818 hdmi_val
|= SDVO_COLOR_FORMAT_8bpc
;
1820 if (crtc_state
->has_hdmi_sink
)
1821 hdmi_val
|= HDMI_MODE_SELECT_HDMI
;
1823 if (HAS_PCH_CPT(dev_priv
))
1824 hdmi_val
|= SDVO_PIPE_SEL_CPT(crtc
->pipe
);
1825 else if (IS_CHERRYVIEW(dev_priv
))
1826 hdmi_val
|= SDVO_PIPE_SEL_CHV(crtc
->pipe
);
1828 hdmi_val
|= SDVO_PIPE_SEL(crtc
->pipe
);
1830 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, hdmi_val
);
1831 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1834 static bool intel_hdmi_get_hw_state(struct intel_encoder
*encoder
,
1837 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1838 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1839 intel_wakeref_t wakeref
;
1842 wakeref
= intel_display_power_get_if_enabled(dev_priv
,
1843 encoder
->power_domain
);
1847 ret
= intel_sdvo_port_enabled(dev_priv
, intel_hdmi
->hdmi_reg
, pipe
);
1849 intel_display_power_put(dev_priv
, encoder
->power_domain
, wakeref
);
1854 static void intel_hdmi_get_config(struct intel_encoder
*encoder
,
1855 struct intel_crtc_state
*pipe_config
)
1857 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1858 struct drm_device
*dev
= encoder
->base
.dev
;
1859 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1863 pipe_config
->output_types
|= BIT(INTEL_OUTPUT_HDMI
);
1865 tmp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1867 if (tmp
& SDVO_HSYNC_ACTIVE_HIGH
)
1868 flags
|= DRM_MODE_FLAG_PHSYNC
;
1870 flags
|= DRM_MODE_FLAG_NHSYNC
;
1872 if (tmp
& SDVO_VSYNC_ACTIVE_HIGH
)
1873 flags
|= DRM_MODE_FLAG_PVSYNC
;
1875 flags
|= DRM_MODE_FLAG_NVSYNC
;
1877 if (tmp
& HDMI_MODE_SELECT_HDMI
)
1878 pipe_config
->has_hdmi_sink
= true;
1880 pipe_config
->infoframes
.enable
|=
1881 intel_hdmi_infoframes_enabled(encoder
, pipe_config
);
1883 if (pipe_config
->infoframes
.enable
)
1884 pipe_config
->has_infoframe
= true;
1886 if (tmp
& HDMI_AUDIO_ENABLE
)
1887 pipe_config
->has_audio
= true;
1889 if (!HAS_PCH_SPLIT(dev_priv
) &&
1890 tmp
& HDMI_COLOR_RANGE_16_235
)
1891 pipe_config
->limited_color_range
= true;
1893 pipe_config
->hw
.adjusted_mode
.flags
|= flags
;
1895 if ((tmp
& SDVO_COLOR_FORMAT_MASK
) == HDMI_COLOR_FORMAT_12bpc
)
1896 dotclock
= pipe_config
->port_clock
* 2 / 3;
1898 dotclock
= pipe_config
->port_clock
;
1900 if (pipe_config
->pixel_multiplier
)
1901 dotclock
/= pipe_config
->pixel_multiplier
;
1903 pipe_config
->hw
.adjusted_mode
.crtc_clock
= dotclock
;
1905 pipe_config
->lane_count
= 4;
1907 intel_hdmi_read_gcp_infoframe(encoder
, pipe_config
);
1909 intel_read_infoframe(encoder
, pipe_config
,
1910 HDMI_INFOFRAME_TYPE_AVI
,
1911 &pipe_config
->infoframes
.avi
);
1912 intel_read_infoframe(encoder
, pipe_config
,
1913 HDMI_INFOFRAME_TYPE_SPD
,
1914 &pipe_config
->infoframes
.spd
);
1915 intel_read_infoframe(encoder
, pipe_config
,
1916 HDMI_INFOFRAME_TYPE_VENDOR
,
1917 &pipe_config
->infoframes
.hdmi
);
1920 static void intel_enable_hdmi_audio(struct intel_encoder
*encoder
,
1921 const struct intel_crtc_state
*pipe_config
,
1922 const struct drm_connector_state
*conn_state
)
1924 struct drm_i915_private
*i915
= to_i915(encoder
->base
.dev
);
1925 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->uapi
.crtc
);
1927 drm_WARN_ON(&i915
->drm
, !pipe_config
->has_hdmi_sink
);
1928 drm_dbg_kms(&i915
->drm
, "Enabling HDMI audio on pipe %c\n",
1929 pipe_name(crtc
->pipe
));
1930 intel_audio_codec_enable(encoder
, pipe_config
, conn_state
);
1933 static void g4x_enable_hdmi(struct intel_atomic_state
*state
,
1934 struct intel_encoder
*encoder
,
1935 const struct intel_crtc_state
*pipe_config
,
1936 const struct drm_connector_state
*conn_state
)
1938 struct drm_device
*dev
= encoder
->base
.dev
;
1939 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1940 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1943 temp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1945 temp
|= SDVO_ENABLE
;
1946 if (pipe_config
->has_audio
)
1947 temp
|= HDMI_AUDIO_ENABLE
;
1949 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1950 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1952 if (pipe_config
->has_audio
)
1953 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
1956 static void ibx_enable_hdmi(struct intel_atomic_state
*state
,
1957 struct intel_encoder
*encoder
,
1958 const struct intel_crtc_state
*pipe_config
,
1959 const struct drm_connector_state
*conn_state
)
1961 struct drm_device
*dev
= encoder
->base
.dev
;
1962 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1963 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1966 temp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1968 temp
|= SDVO_ENABLE
;
1969 if (pipe_config
->has_audio
)
1970 temp
|= HDMI_AUDIO_ENABLE
;
1973 * HW workaround, need to write this twice for issue
1974 * that may result in first write getting masked.
1976 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1977 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1978 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1979 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1982 * HW workaround, need to toggle enable bit off and on
1983 * for 12bpc with pixel repeat.
1985 * FIXME: BSpec says this should be done at the end of
1986 * of the modeset sequence, so not sure if this isn't too soon.
1988 if (pipe_config
->pipe_bpp
> 24 &&
1989 pipe_config
->pixel_multiplier
> 1) {
1990 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
,
1991 temp
& ~SDVO_ENABLE
);
1992 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
1995 * HW workaround, need to write this twice for issue
1996 * that may result in first write getting masked.
1998 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
1999 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2000 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2001 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2004 if (pipe_config
->has_audio
)
2005 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
2008 static void cpt_enable_hdmi(struct intel_atomic_state
*state
,
2009 struct intel_encoder
*encoder
,
2010 const struct intel_crtc_state
*pipe_config
,
2011 const struct drm_connector_state
*conn_state
)
2013 struct drm_device
*dev
= encoder
->base
.dev
;
2014 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2015 struct intel_crtc
*crtc
= to_intel_crtc(pipe_config
->uapi
.crtc
);
2016 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2017 enum pipe pipe
= crtc
->pipe
;
2020 temp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2022 temp
|= SDVO_ENABLE
;
2023 if (pipe_config
->has_audio
)
2024 temp
|= HDMI_AUDIO_ENABLE
;
2027 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
2029 * The procedure for 12bpc is as follows:
2030 * 1. disable HDMI clock gating
2031 * 2. enable HDMI with 8bpc
2032 * 3. enable HDMI with 12bpc
2033 * 4. enable HDMI clock gating
2036 if (pipe_config
->pipe_bpp
> 24) {
2037 intel_de_write(dev_priv
, TRANS_CHICKEN1(pipe
),
2038 intel_de_read(dev_priv
, TRANS_CHICKEN1(pipe
)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
2040 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
2041 temp
|= SDVO_COLOR_FORMAT_8bpc
;
2044 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2045 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2047 if (pipe_config
->pipe_bpp
> 24) {
2048 temp
&= ~SDVO_COLOR_FORMAT_MASK
;
2049 temp
|= HDMI_COLOR_FORMAT_12bpc
;
2051 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2052 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2054 intel_de_write(dev_priv
, TRANS_CHICKEN1(pipe
),
2055 intel_de_read(dev_priv
, TRANS_CHICKEN1(pipe
)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
);
2058 if (pipe_config
->has_audio
)
2059 intel_enable_hdmi_audio(encoder
, pipe_config
, conn_state
);
2062 static void vlv_enable_hdmi(struct intel_atomic_state
*state
,
2063 struct intel_encoder
*encoder
,
2064 const struct intel_crtc_state
*pipe_config
,
2065 const struct drm_connector_state
*conn_state
)
2069 static void intel_disable_hdmi(struct intel_atomic_state
*state
,
2070 struct intel_encoder
*encoder
,
2071 const struct intel_crtc_state
*old_crtc_state
,
2072 const struct drm_connector_state
*old_conn_state
)
2074 struct drm_device
*dev
= encoder
->base
.dev
;
2075 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2076 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2077 struct intel_digital_port
*dig_port
=
2078 hdmi_to_dig_port(intel_hdmi
);
2079 struct intel_crtc
*crtc
= to_intel_crtc(old_crtc_state
->uapi
.crtc
);
2082 temp
= intel_de_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2084 temp
&= ~(SDVO_ENABLE
| HDMI_AUDIO_ENABLE
);
2085 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2086 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2089 * HW workaround for IBX, we need to move the port
2090 * to transcoder A after disabling it to allow the
2091 * matching DP port to be enabled on transcoder A.
2093 if (HAS_PCH_IBX(dev_priv
) && crtc
->pipe
== PIPE_B
) {
2095 * We get CPU/PCH FIFO underruns on the other pipe when
2096 * doing the workaround. Sweep them under the rug.
2098 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
2099 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, false);
2101 temp
&= ~SDVO_PIPE_SEL_MASK
;
2102 temp
|= SDVO_ENABLE
| SDVO_PIPE_SEL(PIPE_A
);
2104 * HW workaround, need to write this twice for issue
2105 * that may result in first write getting masked.
2107 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2108 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2109 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2110 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2112 temp
&= ~SDVO_ENABLE
;
2113 intel_de_write(dev_priv
, intel_hdmi
->hdmi_reg
, temp
);
2114 intel_de_posting_read(dev_priv
, intel_hdmi
->hdmi_reg
);
2116 intel_wait_for_vblank_if_active(dev_priv
, PIPE_A
);
2117 intel_set_cpu_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
2118 intel_set_pch_fifo_underrun_reporting(dev_priv
, PIPE_A
, true);
2121 dig_port
->set_infoframes(encoder
,
2123 old_crtc_state
, old_conn_state
);
2125 intel_dp_dual_mode_set_tmds_output(intel_hdmi
, false);
2128 static void g4x_disable_hdmi(struct intel_atomic_state
*state
,
2129 struct intel_encoder
*encoder
,
2130 const struct intel_crtc_state
*old_crtc_state
,
2131 const struct drm_connector_state
*old_conn_state
)
2133 if (old_crtc_state
->has_audio
)
2134 intel_audio_codec_disable(encoder
,
2135 old_crtc_state
, old_conn_state
);
2137 intel_disable_hdmi(state
, encoder
, old_crtc_state
, old_conn_state
);
2140 static void pch_disable_hdmi(struct intel_atomic_state
*state
,
2141 struct intel_encoder
*encoder
,
2142 const struct intel_crtc_state
*old_crtc_state
,
2143 const struct drm_connector_state
*old_conn_state
)
2145 if (old_crtc_state
->has_audio
)
2146 intel_audio_codec_disable(encoder
,
2147 old_crtc_state
, old_conn_state
);
2150 static void pch_post_disable_hdmi(struct intel_atomic_state
*state
,
2151 struct intel_encoder
*encoder
,
2152 const struct intel_crtc_state
*old_crtc_state
,
2153 const struct drm_connector_state
*old_conn_state
)
2155 intel_disable_hdmi(state
, encoder
, old_crtc_state
, old_conn_state
);
2158 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder
*encoder
)
2160 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2161 int max_tmds_clock
, vbt_max_tmds_clock
;
2163 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
2164 max_tmds_clock
= 594000;
2165 else if (INTEL_GEN(dev_priv
) >= 8 || IS_HASWELL(dev_priv
))
2166 max_tmds_clock
= 300000;
2167 else if (INTEL_GEN(dev_priv
) >= 5)
2168 max_tmds_clock
= 225000;
2170 max_tmds_clock
= 165000;
2172 vbt_max_tmds_clock
= intel_bios_max_tmds_clock(encoder
);
2173 if (vbt_max_tmds_clock
)
2174 max_tmds_clock
= min(max_tmds_clock
, vbt_max_tmds_clock
);
2176 return max_tmds_clock
;
2179 static bool intel_has_hdmi_sink(struct intel_hdmi
*hdmi
,
2180 const struct drm_connector_state
*conn_state
)
2182 return hdmi
->has_hdmi_sink
&&
2183 READ_ONCE(to_intel_digital_connector_state(conn_state
)->force_audio
) != HDMI_AUDIO_OFF_DVI
;
2186 static int hdmi_port_clock_limit(struct intel_hdmi
*hdmi
,
2187 bool respect_downstream_limits
,
2190 struct intel_encoder
*encoder
= &hdmi_to_dig_port(hdmi
)->base
;
2191 int max_tmds_clock
= intel_hdmi_source_max_tmds_clock(encoder
);
2193 if (respect_downstream_limits
) {
2194 struct intel_connector
*connector
= hdmi
->attached_connector
;
2195 const struct drm_display_info
*info
= &connector
->base
.display_info
;
2197 if (hdmi
->dp_dual_mode
.max_tmds_clock
)
2198 max_tmds_clock
= min(max_tmds_clock
,
2199 hdmi
->dp_dual_mode
.max_tmds_clock
);
2201 if (info
->max_tmds_clock
)
2202 max_tmds_clock
= min(max_tmds_clock
,
2203 info
->max_tmds_clock
);
2204 else if (!has_hdmi_sink
)
2205 max_tmds_clock
= min(max_tmds_clock
, 165000);
2208 return max_tmds_clock
;
2211 static enum drm_mode_status
2212 hdmi_port_clock_valid(struct intel_hdmi
*hdmi
,
2213 int clock
, bool respect_downstream_limits
,
2216 struct drm_i915_private
*dev_priv
= to_i915(intel_hdmi_to_dev(hdmi
));
2219 return MODE_CLOCK_LOW
;
2220 if (clock
> hdmi_port_clock_limit(hdmi
, respect_downstream_limits
,
2222 return MODE_CLOCK_HIGH
;
2224 /* GLK DPLL can't generate 446-480 MHz */
2225 if (IS_GEMINILAKE(dev_priv
) && clock
> 446666 && clock
< 480000)
2226 return MODE_CLOCK_RANGE
;
2228 /* BXT/GLK DPLL can't generate 223-240 MHz */
2229 if (IS_GEN9_LP(dev_priv
) && clock
> 223333 && clock
< 240000)
2230 return MODE_CLOCK_RANGE
;
2232 /* CHV DPLL can't generate 216-240 MHz */
2233 if (IS_CHERRYVIEW(dev_priv
) && clock
> 216000 && clock
< 240000)
2234 return MODE_CLOCK_RANGE
;
2239 static int intel_hdmi_port_clock(int clock
, int bpc
)
2242 * Need to adjust the port link by:
2246 return clock
* bpc
/ 8;
2249 static enum drm_mode_status
2250 intel_hdmi_mode_clock_valid(struct intel_hdmi
*hdmi
, int clock
, bool has_hdmi_sink
)
2252 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
2253 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2254 enum drm_mode_status status
;
2256 /* check if we can do 8bpc */
2257 status
= hdmi_port_clock_valid(hdmi
, intel_hdmi_port_clock(clock
, 8),
2258 true, has_hdmi_sink
);
2260 if (has_hdmi_sink
) {
2261 /* if we can't do 8bpc we may still be able to do 12bpc */
2262 if (status
!= MODE_OK
&& !HAS_GMCH(dev_priv
))
2263 status
= hdmi_port_clock_valid(hdmi
, intel_hdmi_port_clock(clock
, 12),
2264 true, has_hdmi_sink
);
2266 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2267 if (status
!= MODE_OK
&& INTEL_GEN(dev_priv
) >= 11)
2268 status
= hdmi_port_clock_valid(hdmi
, intel_hdmi_port_clock(clock
, 10),
2269 true, has_hdmi_sink
);
2275 static enum drm_mode_status
2276 intel_hdmi_mode_valid(struct drm_connector
*connector
,
2277 struct drm_display_mode
*mode
)
2279 struct intel_hdmi
*hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2280 struct drm_device
*dev
= intel_hdmi_to_dev(hdmi
);
2281 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2282 enum drm_mode_status status
;
2283 int clock
= mode
->clock
;
2284 int max_dotclk
= to_i915(connector
->dev
)->max_dotclk_freq
;
2285 bool has_hdmi_sink
= intel_has_hdmi_sink(hdmi
, connector
->state
);
2287 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
2288 return MODE_NO_DBLESCAN
;
2290 if ((mode
->flags
& DRM_MODE_FLAG_3D_MASK
) == DRM_MODE_FLAG_3D_FRAME_PACKING
)
2293 if (clock
> max_dotclk
)
2294 return MODE_CLOCK_HIGH
;
2296 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
) {
2298 return MODE_CLOCK_LOW
;
2302 if (drm_mode_is_420_only(&connector
->display_info
, mode
))
2305 status
= intel_hdmi_mode_clock_valid(hdmi
, clock
, has_hdmi_sink
);
2306 if (status
!= MODE_OK
)
2309 return intel_mode_valid_max_plane_size(dev_priv
, mode
, false);
2312 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state
*crtc_state
,
2313 int bpc
, bool has_hdmi_sink
, bool ycbcr420_output
)
2315 struct drm_atomic_state
*state
= crtc_state
->uapi
.state
;
2316 struct drm_connector_state
*connector_state
;
2317 struct drm_connector
*connector
;
2320 if (crtc_state
->pipe_bpp
< bpc
* 3)
2326 for_each_new_connector_in_state(state
, connector
, connector_state
, i
) {
2327 const struct drm_display_info
*info
= &connector
->display_info
;
2329 if (connector_state
->crtc
!= crtc_state
->uapi
.crtc
)
2332 if (ycbcr420_output
) {
2333 const struct drm_hdmi_info
*hdmi
= &info
->hdmi
;
2335 if (bpc
== 12 && !(hdmi
->y420_dc_modes
&
2336 DRM_EDID_YCBCR420_DC_36
))
2338 else if (bpc
== 10 && !(hdmi
->y420_dc_modes
&
2339 DRM_EDID_YCBCR420_DC_30
))
2342 if (bpc
== 12 && !(info
->edid_hdmi_dc_modes
&
2343 DRM_EDID_HDMI_DC_36
))
2345 else if (bpc
== 10 && !(info
->edid_hdmi_dc_modes
&
2346 DRM_EDID_HDMI_DC_30
))
2354 static bool hdmi_deep_color_possible(const struct intel_crtc_state
*crtc_state
,
2357 struct drm_i915_private
*dev_priv
=
2358 to_i915(crtc_state
->uapi
.crtc
->dev
);
2359 const struct drm_display_mode
*adjusted_mode
=
2360 &crtc_state
->hw
.adjusted_mode
;
2362 if (HAS_GMCH(dev_priv
))
2365 if (bpc
== 10 && INTEL_GEN(dev_priv
) < 11)
2369 * HDMI deep color affects the clocks, so it's only possible
2370 * when not cloning with other encoder types.
2372 if (crtc_state
->output_types
!= BIT(INTEL_OUTPUT_HDMI
))
2375 /* Display Wa_1405510057:icl,ehl */
2376 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
&&
2377 bpc
== 10 && IS_GEN(dev_priv
, 11) &&
2378 (adjusted_mode
->crtc_hblank_end
-
2379 adjusted_mode
->crtc_hblank_start
) % 8 == 2)
2382 return intel_hdmi_deep_color_possible(crtc_state
, bpc
,
2383 crtc_state
->has_hdmi_sink
,
2384 crtc_state
->output_format
==
2385 INTEL_OUTPUT_FORMAT_YCBCR420
);
2389 intel_hdmi_ycbcr420_config(struct intel_crtc_state
*crtc_state
,
2390 const struct drm_connector_state
*conn_state
)
2392 struct drm_connector
*connector
= conn_state
->connector
;
2393 struct drm_i915_private
*i915
= to_i915(connector
->dev
);
2394 const struct drm_display_mode
*adjusted_mode
=
2395 &crtc_state
->hw
.adjusted_mode
;
2397 if (!drm_mode_is_420_only(&connector
->display_info
, adjusted_mode
))
2400 if (!connector
->ycbcr_420_allowed
) {
2402 "Platform doesn't support YCBCR420 output\n");
2406 crtc_state
->output_format
= INTEL_OUTPUT_FORMAT_YCBCR420
;
2408 return intel_pch_panel_fitting(crtc_state
, conn_state
);
2411 static int intel_hdmi_compute_bpc(struct intel_encoder
*encoder
,
2412 struct intel_crtc_state
*crtc_state
,
2415 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2418 for (bpc
= 12; bpc
>= 10; bpc
-= 2) {
2419 if (hdmi_deep_color_possible(crtc_state
, bpc
) &&
2420 hdmi_port_clock_valid(intel_hdmi
,
2421 intel_hdmi_port_clock(clock
, bpc
),
2422 true, crtc_state
->has_hdmi_sink
) == MODE_OK
)
2429 static int intel_hdmi_compute_clock(struct intel_encoder
*encoder
,
2430 struct intel_crtc_state
*crtc_state
)
2432 struct drm_i915_private
*i915
= to_i915(encoder
->base
.dev
);
2433 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2434 const struct drm_display_mode
*adjusted_mode
=
2435 &crtc_state
->hw
.adjusted_mode
;
2436 int bpc
, clock
= adjusted_mode
->crtc_clock
;
2438 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
2441 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2442 if (crtc_state
->output_format
== INTEL_OUTPUT_FORMAT_YCBCR420
)
2445 bpc
= intel_hdmi_compute_bpc(encoder
, crtc_state
, clock
);
2447 crtc_state
->port_clock
= intel_hdmi_port_clock(clock
, bpc
);
2450 * pipe_bpp could already be below 8bpc due to
2451 * FDI bandwidth constraints. We shouldn't bump it
2452 * back up to 8bpc in that case.
2454 if (crtc_state
->pipe_bpp
> bpc
* 3)
2455 crtc_state
->pipe_bpp
= bpc
* 3;
2457 drm_dbg_kms(&i915
->drm
,
2458 "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2459 bpc
, crtc_state
->pipe_bpp
);
2461 if (hdmi_port_clock_valid(intel_hdmi
, crtc_state
->port_clock
,
2462 false, crtc_state
->has_hdmi_sink
) != MODE_OK
) {
2463 drm_dbg_kms(&i915
->drm
,
2464 "unsupported HDMI clock (%d kHz), rejecting mode\n",
2465 crtc_state
->port_clock
);
2472 bool intel_hdmi_limited_color_range(const struct intel_crtc_state
*crtc_state
,
2473 const struct drm_connector_state
*conn_state
)
2475 const struct intel_digital_connector_state
*intel_conn_state
=
2476 to_intel_digital_connector_state(conn_state
);
2477 const struct drm_display_mode
*adjusted_mode
=
2478 &crtc_state
->hw
.adjusted_mode
;
2481 * Our YCbCr output is always limited range.
2482 * crtc_state->limited_color_range only applies to RGB,
2483 * and it must never be set for YCbCr or we risk setting
2484 * some conflicting bits in PIPECONF which will mess up
2485 * the colors on the monitor.
2487 if (crtc_state
->output_format
!= INTEL_OUTPUT_FORMAT_RGB
)
2490 if (intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_AUTO
) {
2491 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2492 return crtc_state
->has_hdmi_sink
&&
2493 drm_default_rgb_quant_range(adjusted_mode
) ==
2494 HDMI_QUANTIZATION_RANGE_LIMITED
;
2496 return intel_conn_state
->broadcast_rgb
== INTEL_BROADCAST_RGB_LIMITED
;
2500 static bool intel_hdmi_has_audio(struct intel_encoder
*encoder
,
2501 const struct intel_crtc_state
*crtc_state
,
2502 const struct drm_connector_state
*conn_state
)
2504 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2505 const struct intel_digital_connector_state
*intel_conn_state
=
2506 to_intel_digital_connector_state(conn_state
);
2508 if (!crtc_state
->has_hdmi_sink
)
2511 if (intel_conn_state
->force_audio
== HDMI_AUDIO_AUTO
)
2512 return intel_hdmi
->has_audio
;
2514 return intel_conn_state
->force_audio
== HDMI_AUDIO_ON
;
2517 int intel_hdmi_compute_config(struct intel_encoder
*encoder
,
2518 struct intel_crtc_state
*pipe_config
,
2519 struct drm_connector_state
*conn_state
)
2521 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
2522 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2523 struct drm_display_mode
*adjusted_mode
= &pipe_config
->hw
.adjusted_mode
;
2524 struct drm_connector
*connector
= conn_state
->connector
;
2525 struct drm_scdc
*scdc
= &connector
->display_info
.hdmi
.scdc
;
2528 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
2531 pipe_config
->output_format
= INTEL_OUTPUT_FORMAT_RGB
;
2532 pipe_config
->has_hdmi_sink
= intel_has_hdmi_sink(intel_hdmi
,
2535 if (pipe_config
->has_hdmi_sink
)
2536 pipe_config
->has_infoframe
= true;
2538 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
2539 pipe_config
->pixel_multiplier
= 2;
2541 ret
= intel_hdmi_ycbcr420_config(pipe_config
, conn_state
);
2545 pipe_config
->limited_color_range
=
2546 intel_hdmi_limited_color_range(pipe_config
, conn_state
);
2548 if (HAS_PCH_SPLIT(dev_priv
) && !HAS_DDI(dev_priv
))
2549 pipe_config
->has_pch_encoder
= true;
2551 pipe_config
->has_audio
=
2552 intel_hdmi_has_audio(encoder
, pipe_config
, conn_state
);
2554 ret
= intel_hdmi_compute_clock(encoder
, pipe_config
);
2558 if (conn_state
->picture_aspect_ratio
)
2559 adjusted_mode
->picture_aspect_ratio
=
2560 conn_state
->picture_aspect_ratio
;
2562 pipe_config
->lane_count
= 4;
2564 if (scdc
->scrambling
.supported
&& (INTEL_GEN(dev_priv
) >= 10 ||
2565 IS_GEMINILAKE(dev_priv
))) {
2566 if (scdc
->scrambling
.low_rates
)
2567 pipe_config
->hdmi_scrambling
= true;
2569 if (pipe_config
->port_clock
> 340000) {
2570 pipe_config
->hdmi_scrambling
= true;
2571 pipe_config
->hdmi_high_tmds_clock_ratio
= true;
2575 intel_hdmi_compute_gcp_infoframe(encoder
, pipe_config
,
2578 if (!intel_hdmi_compute_avi_infoframe(encoder
, pipe_config
, conn_state
)) {
2579 drm_dbg_kms(&dev_priv
->drm
, "bad AVI infoframe\n");
2583 if (!intel_hdmi_compute_spd_infoframe(encoder
, pipe_config
, conn_state
)) {
2584 drm_dbg_kms(&dev_priv
->drm
, "bad SPD infoframe\n");
2588 if (!intel_hdmi_compute_hdmi_infoframe(encoder
, pipe_config
, conn_state
)) {
2589 drm_dbg_kms(&dev_priv
->drm
, "bad HDMI infoframe\n");
2593 if (!intel_hdmi_compute_drm_infoframe(encoder
, pipe_config
, conn_state
)) {
2594 drm_dbg_kms(&dev_priv
->drm
, "bad DRM infoframe\n");
2602 intel_hdmi_unset_edid(struct drm_connector
*connector
)
2604 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2606 intel_hdmi
->has_hdmi_sink
= false;
2607 intel_hdmi
->has_audio
= false;
2609 intel_hdmi
->dp_dual_mode
.type
= DRM_DP_DUAL_MODE_NONE
;
2610 intel_hdmi
->dp_dual_mode
.max_tmds_clock
= 0;
2612 kfree(to_intel_connector(connector
)->detect_edid
);
2613 to_intel_connector(connector
)->detect_edid
= NULL
;
2617 intel_hdmi_dp_dual_mode_detect(struct drm_connector
*connector
, bool has_edid
)
2619 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2620 struct intel_hdmi
*hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2621 enum port port
= hdmi_to_dig_port(hdmi
)->base
.port
;
2622 struct i2c_adapter
*adapter
=
2623 intel_gmbus_get_adapter(dev_priv
, hdmi
->ddc_bus
);
2624 enum drm_dp_dual_mode_type type
= drm_dp_dual_mode_detect(adapter
);
2627 * Type 1 DVI adaptors are not required to implement any
2628 * registers, so we can't always detect their presence.
2629 * Ideally we should be able to check the state of the
2630 * CONFIG1 pin, but no such luck on our hardware.
2632 * The only method left to us is to check the VBT to see
2633 * if the port is a dual mode capable DP port. But let's
2634 * only do that when we sucesfully read the EDID, to avoid
2635 * confusing log messages about DP dual mode adaptors when
2636 * there's nothing connected to the port.
2638 if (type
== DRM_DP_DUAL_MODE_UNKNOWN
) {
2639 /* An overridden EDID imply that we want this port for testing.
2640 * Make sure not to set limits for that port.
2642 if (has_edid
&& !connector
->override_edid
&&
2643 intel_bios_is_port_dp_dual_mode(dev_priv
, port
)) {
2644 drm_dbg_kms(&dev_priv
->drm
,
2645 "Assuming DP dual mode adaptor presence based on VBT\n");
2646 type
= DRM_DP_DUAL_MODE_TYPE1_DVI
;
2648 type
= DRM_DP_DUAL_MODE_NONE
;
2652 if (type
== DRM_DP_DUAL_MODE_NONE
)
2655 hdmi
->dp_dual_mode
.type
= type
;
2656 hdmi
->dp_dual_mode
.max_tmds_clock
=
2657 drm_dp_dual_mode_max_tmds_clock(type
, adapter
);
2659 drm_dbg_kms(&dev_priv
->drm
,
2660 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2661 drm_dp_get_dual_mode_type_name(type
),
2662 hdmi
->dp_dual_mode
.max_tmds_clock
);
2666 intel_hdmi_set_edid(struct drm_connector
*connector
)
2668 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2669 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2670 intel_wakeref_t wakeref
;
2672 bool connected
= false;
2673 struct i2c_adapter
*i2c
;
2675 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
2677 i2c
= intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
2679 edid
= drm_get_edid(connector
, i2c
);
2681 if (!edid
&& !intel_gmbus_is_forced_bit(i2c
)) {
2682 drm_dbg_kms(&dev_priv
->drm
,
2683 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2684 intel_gmbus_force_bit(i2c
, true);
2685 edid
= drm_get_edid(connector
, i2c
);
2686 intel_gmbus_force_bit(i2c
, false);
2689 intel_hdmi_dp_dual_mode_detect(connector
, edid
!= NULL
);
2691 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
, wakeref
);
2693 to_intel_connector(connector
)->detect_edid
= edid
;
2694 if (edid
&& edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
2695 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
2696 intel_hdmi
->has_hdmi_sink
= drm_detect_hdmi_monitor(edid
);
2701 cec_notifier_set_phys_addr_from_edid(intel_hdmi
->cec_notifier
, edid
);
2706 static enum drm_connector_status
2707 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
2709 enum drm_connector_status status
= connector_status_disconnected
;
2710 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2711 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2712 struct intel_encoder
*encoder
= &hdmi_to_dig_port(intel_hdmi
)->base
;
2713 intel_wakeref_t wakeref
;
2715 drm_dbg_kms(&dev_priv
->drm
, "[CONNECTOR:%d:%s]\n",
2716 connector
->base
.id
, connector
->name
);
2718 if (!INTEL_DISPLAY_ENABLED(dev_priv
))
2719 return connector_status_disconnected
;
2721 wakeref
= intel_display_power_get(dev_priv
, POWER_DOMAIN_GMBUS
);
2723 if (INTEL_GEN(dev_priv
) >= 11 &&
2724 !intel_digital_port_connected(encoder
))
2727 intel_hdmi_unset_edid(connector
);
2729 if (intel_hdmi_set_edid(connector
))
2730 status
= connector_status_connected
;
2733 intel_display_power_put(dev_priv
, POWER_DOMAIN_GMBUS
, wakeref
);
2735 if (status
!= connector_status_connected
)
2736 cec_notifier_phys_addr_invalidate(intel_hdmi
->cec_notifier
);
2739 * Make sure the refs for power wells enabled during detect are
2740 * dropped to avoid a new detect cycle triggered by HPD polling.
2742 intel_display_power_flush_work(dev_priv
);
2748 intel_hdmi_force(struct drm_connector
*connector
)
2750 struct drm_i915_private
*i915
= to_i915(connector
->dev
);
2752 drm_dbg_kms(&i915
->drm
, "[CONNECTOR:%d:%s]\n",
2753 connector
->base
.id
, connector
->name
);
2755 intel_hdmi_unset_edid(connector
);
2757 if (connector
->status
!= connector_status_connected
)
2760 intel_hdmi_set_edid(connector
);
2763 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
2767 edid
= to_intel_connector(connector
)->detect_edid
;
2771 return intel_connector_update_modes(connector
, edid
);
2774 static void intel_hdmi_pre_enable(struct intel_atomic_state
*state
,
2775 struct intel_encoder
*encoder
,
2776 const struct intel_crtc_state
*pipe_config
,
2777 const struct drm_connector_state
*conn_state
)
2779 struct intel_digital_port
*dig_port
=
2780 enc_to_dig_port(encoder
);
2782 intel_hdmi_prepare(encoder
, pipe_config
);
2784 dig_port
->set_infoframes(encoder
,
2785 pipe_config
->has_infoframe
,
2786 pipe_config
, conn_state
);
2789 static void vlv_hdmi_pre_enable(struct intel_atomic_state
*state
,
2790 struct intel_encoder
*encoder
,
2791 const struct intel_crtc_state
*pipe_config
,
2792 const struct drm_connector_state
*conn_state
)
2794 struct intel_digital_port
*dig_port
= enc_to_dig_port(encoder
);
2795 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
2797 vlv_phy_pre_encoder_enable(encoder
, pipe_config
);
2800 vlv_set_phy_signal_level(encoder
, pipe_config
,
2801 0x2b245f5f, 0x00002000,
2802 0x5578b83a, 0x2b247878);
2804 dig_port
->set_infoframes(encoder
,
2805 pipe_config
->has_infoframe
,
2806 pipe_config
, conn_state
);
2808 g4x_enable_hdmi(state
, encoder
, pipe_config
, conn_state
);
2810 vlv_wait_port_ready(dev_priv
, dig_port
, 0x0);
2813 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state
*state
,
2814 struct intel_encoder
*encoder
,
2815 const struct intel_crtc_state
*pipe_config
,
2816 const struct drm_connector_state
*conn_state
)
2818 intel_hdmi_prepare(encoder
, pipe_config
);
2820 vlv_phy_pre_pll_enable(encoder
, pipe_config
);
2823 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state
*state
,
2824 struct intel_encoder
*encoder
,
2825 const struct intel_crtc_state
*pipe_config
,
2826 const struct drm_connector_state
*conn_state
)
2828 intel_hdmi_prepare(encoder
, pipe_config
);
2830 chv_phy_pre_pll_enable(encoder
, pipe_config
);
2833 static void chv_hdmi_post_pll_disable(struct intel_atomic_state
*state
,
2834 struct intel_encoder
*encoder
,
2835 const struct intel_crtc_state
*old_crtc_state
,
2836 const struct drm_connector_state
*old_conn_state
)
2838 chv_phy_post_pll_disable(encoder
, old_crtc_state
);
2841 static void vlv_hdmi_post_disable(struct intel_atomic_state
*state
,
2842 struct intel_encoder
*encoder
,
2843 const struct intel_crtc_state
*old_crtc_state
,
2844 const struct drm_connector_state
*old_conn_state
)
2846 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2847 vlv_phy_reset_lanes(encoder
, old_crtc_state
);
2850 static void chv_hdmi_post_disable(struct intel_atomic_state
*state
,
2851 struct intel_encoder
*encoder
,
2852 const struct intel_crtc_state
*old_crtc_state
,
2853 const struct drm_connector_state
*old_conn_state
)
2855 struct drm_device
*dev
= encoder
->base
.dev
;
2856 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2858 vlv_dpio_get(dev_priv
);
2860 /* Assert data lane reset */
2861 chv_data_lane_soft_reset(encoder
, old_crtc_state
, true);
2863 vlv_dpio_put(dev_priv
);
2866 static void chv_hdmi_pre_enable(struct intel_atomic_state
*state
,
2867 struct intel_encoder
*encoder
,
2868 const struct intel_crtc_state
*pipe_config
,
2869 const struct drm_connector_state
*conn_state
)
2871 struct intel_digital_port
*dig_port
= enc_to_dig_port(encoder
);
2872 struct drm_device
*dev
= encoder
->base
.dev
;
2873 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2875 chv_phy_pre_encoder_enable(encoder
, pipe_config
);
2877 /* FIXME: Program the support xxx V-dB */
2879 chv_set_phy_signal_level(encoder
, pipe_config
, 128, 102, false);
2881 dig_port
->set_infoframes(encoder
,
2882 pipe_config
->has_infoframe
,
2883 pipe_config
, conn_state
);
2885 g4x_enable_hdmi(state
, encoder
, pipe_config
, conn_state
);
2887 vlv_wait_port_ready(dev_priv
, dig_port
, 0x0);
2889 /* Second common lane will stay alive on its own now */
2890 chv_phy_release_cl2_override(encoder
);
2893 static struct i2c_adapter
*
2894 intel_hdmi_get_i2c_adapter(struct drm_connector
*connector
)
2896 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2897 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(to_intel_connector(connector
));
2899 return intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
2902 static void intel_hdmi_create_i2c_symlink(struct drm_connector
*connector
)
2904 struct drm_i915_private
*i915
= to_i915(connector
->dev
);
2905 struct i2c_adapter
*adapter
= intel_hdmi_get_i2c_adapter(connector
);
2906 struct kobject
*i2c_kobj
= &adapter
->dev
.kobj
;
2907 struct kobject
*connector_kobj
= &connector
->kdev
->kobj
;
2910 ret
= sysfs_create_link(connector_kobj
, i2c_kobj
, i2c_kobj
->name
);
2912 drm_err(&i915
->drm
, "Failed to create i2c symlink (%d)\n", ret
);
2915 static void intel_hdmi_remove_i2c_symlink(struct drm_connector
*connector
)
2917 struct i2c_adapter
*adapter
= intel_hdmi_get_i2c_adapter(connector
);
2918 struct kobject
*i2c_kobj
= &adapter
->dev
.kobj
;
2919 struct kobject
*connector_kobj
= &connector
->kdev
->kobj
;
2921 sysfs_remove_link(connector_kobj
, i2c_kobj
->name
);
2925 intel_hdmi_connector_register(struct drm_connector
*connector
)
2929 ret
= intel_connector_register(connector
);
2933 intel_hdmi_create_i2c_symlink(connector
);
2938 static void intel_hdmi_connector_unregister(struct drm_connector
*connector
)
2940 struct cec_notifier
*n
= intel_attached_hdmi(to_intel_connector(connector
))->cec_notifier
;
2942 cec_notifier_conn_unregister(n
);
2944 intel_hdmi_remove_i2c_symlink(connector
);
2945 intel_connector_unregister(connector
);
2948 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
2949 .detect
= intel_hdmi_detect
,
2950 .force
= intel_hdmi_force
,
2951 .fill_modes
= drm_helper_probe_single_connector_modes
,
2952 .atomic_get_property
= intel_digital_connector_atomic_get_property
,
2953 .atomic_set_property
= intel_digital_connector_atomic_set_property
,
2954 .late_register
= intel_hdmi_connector_register
,
2955 .early_unregister
= intel_hdmi_connector_unregister
,
2956 .destroy
= intel_connector_destroy
,
2957 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
2958 .atomic_duplicate_state
= intel_digital_connector_duplicate_state
,
2961 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
2962 .get_modes
= intel_hdmi_get_modes
,
2963 .mode_valid
= intel_hdmi_mode_valid
,
2964 .atomic_check
= intel_digital_connector_atomic_check
,
2967 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
2968 .destroy
= intel_encoder_destroy
,
2972 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
2974 struct drm_i915_private
*dev_priv
= to_i915(connector
->dev
);
2975 struct intel_digital_port
*dig_port
=
2976 hdmi_to_dig_port(intel_hdmi
);
2978 intel_attach_force_audio_property(connector
);
2979 intel_attach_broadcast_rgb_property(connector
);
2980 intel_attach_aspect_ratio_property(connector
);
2983 * Attach Colorspace property for Non LSPCON based device
2984 * ToDo: This needs to be extended for LSPCON implementation
2985 * as well. Will be implemented separately.
2987 if (!dig_port
->lspcon
.active
)
2988 intel_attach_colorspace_property(connector
);
2990 drm_connector_attach_content_type_property(connector
);
2992 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
2993 drm_object_attach_property(&connector
->base
,
2994 connector
->dev
->mode_config
.hdr_output_metadata_property
, 0);
2996 if (!HAS_GMCH(dev_priv
))
2997 drm_connector_attach_max_bpc_property(connector
, 8, 12);
3001 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
3002 * @encoder: intel_encoder
3003 * @connector: drm_connector
3004 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
3005 * or reset the high tmds clock ratio for scrambling
3006 * @scrambling: bool to Indicate if the function needs to set or reset
3009 * This function handles scrambling on HDMI 2.0 capable sinks.
3010 * If required clock rate is > 340 Mhz && scrambling is supported by sink
3011 * it enables scrambling. This should be called before enabling the HDMI
3012 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
3013 * detect a scrambled clock within 100 ms.
3016 * True on success, false on failure.
3018 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder
*encoder
,
3019 struct drm_connector
*connector
,
3020 bool high_tmds_clock_ratio
,
3023 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3024 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
3025 struct drm_scrambling
*sink_scrambling
=
3026 &connector
->display_info
.hdmi
.scdc
.scrambling
;
3027 struct i2c_adapter
*adapter
=
3028 intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
3030 if (!sink_scrambling
->supported
)
3033 drm_dbg_kms(&dev_priv
->drm
,
3034 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
3035 connector
->base
.id
, connector
->name
,
3036 yesno(scrambling
), high_tmds_clock_ratio
? 40 : 10);
3038 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
3039 return drm_scdc_set_high_tmds_clock_ratio(adapter
,
3040 high_tmds_clock_ratio
) &&
3041 drm_scdc_set_scrambling(adapter
, scrambling
);
3044 static u8
chv_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
3050 ddc_pin
= GMBUS_PIN_DPB
;
3053 ddc_pin
= GMBUS_PIN_DPC
;
3056 ddc_pin
= GMBUS_PIN_DPD_CHV
;
3060 ddc_pin
= GMBUS_PIN_DPB
;
3066 static u8
bxt_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
3072 ddc_pin
= GMBUS_PIN_1_BXT
;
3075 ddc_pin
= GMBUS_PIN_2_BXT
;
3079 ddc_pin
= GMBUS_PIN_1_BXT
;
3085 static u8
cnp_port_to_ddc_pin(struct drm_i915_private
*dev_priv
,
3092 ddc_pin
= GMBUS_PIN_1_BXT
;
3095 ddc_pin
= GMBUS_PIN_2_BXT
;
3098 ddc_pin
= GMBUS_PIN_4_CNP
;
3101 ddc_pin
= GMBUS_PIN_3_BXT
;
3105 ddc_pin
= GMBUS_PIN_1_BXT
;
3111 static u8
icl_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
3113 enum phy phy
= intel_port_to_phy(dev_priv
, port
);
3115 if (intel_phy_is_combo(dev_priv
, phy
))
3116 return GMBUS_PIN_1_BXT
+ port
;
3117 else if (intel_phy_is_tc(dev_priv
, phy
))
3118 return GMBUS_PIN_9_TC1_ICP
+ intel_port_to_tc(dev_priv
, port
);
3120 drm_WARN(&dev_priv
->drm
, 1, "Unknown port:%c\n", port_name(port
));
3121 return GMBUS_PIN_2_BXT
;
3124 static u8
mcc_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
3126 enum phy phy
= intel_port_to_phy(dev_priv
, port
);
3131 ddc_pin
= GMBUS_PIN_1_BXT
;
3134 ddc_pin
= GMBUS_PIN_2_BXT
;
3137 ddc_pin
= GMBUS_PIN_9_TC1_ICP
;
3141 ddc_pin
= GMBUS_PIN_1_BXT
;
3147 static u8
rkl_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
3149 enum phy phy
= intel_port_to_phy(dev_priv
, port
);
3151 WARN_ON(port
== PORT_C
);
3154 * Pin mapping for RKL depends on which PCH is present. With TGP, the
3155 * final two outputs use type-c pins, even though they're actually
3156 * combo outputs. With CMP, the traditional DDI A-D pins are used for
3159 if (INTEL_PCH_TYPE(dev_priv
) >= PCH_TGP
&& phy
>= PHY_C
)
3160 return GMBUS_PIN_9_TC1_ICP
+ phy
- PHY_C
;
3162 return GMBUS_PIN_1_BXT
+ phy
;
3165 static u8
gen9bc_port_to_ddc_pin(struct drm_i915_private
*i915
, enum port port
)
3167 enum phy phy
= intel_port_to_phy(i915
, port
);
3169 drm_WARN_ON(&i915
->drm
, port
== PORT_A
);
3172 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP,
3173 * final two outputs use type-c pins, even though they're actually
3174 * combo outputs. With CMP, the traditional DDI A-D pins are used for
3177 if (INTEL_PCH_TYPE(i915
) >= PCH_TGP
&& phy
>= PHY_C
)
3178 return GMBUS_PIN_9_TC1_ICP
+ phy
- PHY_C
;
3180 return GMBUS_PIN_1_BXT
+ phy
;
3183 static u8
dg1_port_to_ddc_pin(struct drm_i915_private
*dev_priv
, enum port port
)
3185 return intel_port_to_phy(dev_priv
, port
) + 1;
3188 static u8
g4x_port_to_ddc_pin(struct drm_i915_private
*dev_priv
,
3195 ddc_pin
= GMBUS_PIN_DPB
;
3198 ddc_pin
= GMBUS_PIN_DPC
;
3201 ddc_pin
= GMBUS_PIN_DPD
;
3205 ddc_pin
= GMBUS_PIN_DPB
;
3211 static u8
intel_hdmi_ddc_pin(struct intel_encoder
*encoder
)
3213 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
3214 enum port port
= encoder
->port
;
3217 ddc_pin
= intel_bios_alternate_ddc_pin(encoder
);
3219 drm_dbg_kms(&dev_priv
->drm
,
3220 "Using DDC pin 0x%x for port %c (VBT)\n",
3221 ddc_pin
, port_name(port
));
3225 if (INTEL_PCH_TYPE(dev_priv
) >= PCH_DG1
)
3226 ddc_pin
= dg1_port_to_ddc_pin(dev_priv
, port
);
3227 else if (IS_ROCKETLAKE(dev_priv
))
3228 ddc_pin
= rkl_port_to_ddc_pin(dev_priv
, port
);
3229 else if (IS_GEN9_BC(dev_priv
) && HAS_PCH_TGP(dev_priv
))
3230 ddc_pin
= gen9bc_port_to_ddc_pin(dev_priv
, port
);
3231 else if (HAS_PCH_MCC(dev_priv
))
3232 ddc_pin
= mcc_port_to_ddc_pin(dev_priv
, port
);
3233 else if (INTEL_PCH_TYPE(dev_priv
) >= PCH_ICP
)
3234 ddc_pin
= icl_port_to_ddc_pin(dev_priv
, port
);
3235 else if (HAS_PCH_CNP(dev_priv
))
3236 ddc_pin
= cnp_port_to_ddc_pin(dev_priv
, port
);
3237 else if (IS_GEN9_LP(dev_priv
))
3238 ddc_pin
= bxt_port_to_ddc_pin(dev_priv
, port
);
3239 else if (IS_CHERRYVIEW(dev_priv
))
3240 ddc_pin
= chv_port_to_ddc_pin(dev_priv
, port
);
3242 ddc_pin
= g4x_port_to_ddc_pin(dev_priv
, port
);
3244 drm_dbg_kms(&dev_priv
->drm
,
3245 "Using DDC pin 0x%x for port %c (platform default)\n",
3246 ddc_pin
, port_name(port
));
3251 void intel_infoframe_init(struct intel_digital_port
*dig_port
)
3253 struct drm_i915_private
*dev_priv
=
3254 to_i915(dig_port
->base
.base
.dev
);
3256 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
3257 dig_port
->write_infoframe
= vlv_write_infoframe
;
3258 dig_port
->read_infoframe
= vlv_read_infoframe
;
3259 dig_port
->set_infoframes
= vlv_set_infoframes
;
3260 dig_port
->infoframes_enabled
= vlv_infoframes_enabled
;
3261 } else if (IS_G4X(dev_priv
)) {
3262 dig_port
->write_infoframe
= g4x_write_infoframe
;
3263 dig_port
->read_infoframe
= g4x_read_infoframe
;
3264 dig_port
->set_infoframes
= g4x_set_infoframes
;
3265 dig_port
->infoframes_enabled
= g4x_infoframes_enabled
;
3266 } else if (HAS_DDI(dev_priv
)) {
3267 if (intel_bios_is_lspcon_present(dev_priv
, dig_port
->base
.port
)) {
3268 dig_port
->write_infoframe
= lspcon_write_infoframe
;
3269 dig_port
->read_infoframe
= lspcon_read_infoframe
;
3270 dig_port
->set_infoframes
= lspcon_set_infoframes
;
3271 dig_port
->infoframes_enabled
= lspcon_infoframes_enabled
;
3273 dig_port
->write_infoframe
= hsw_write_infoframe
;
3274 dig_port
->read_infoframe
= hsw_read_infoframe
;
3275 dig_port
->set_infoframes
= hsw_set_infoframes
;
3276 dig_port
->infoframes_enabled
= hsw_infoframes_enabled
;
3278 } else if (HAS_PCH_IBX(dev_priv
)) {
3279 dig_port
->write_infoframe
= ibx_write_infoframe
;
3280 dig_port
->read_infoframe
= ibx_read_infoframe
;
3281 dig_port
->set_infoframes
= ibx_set_infoframes
;
3282 dig_port
->infoframes_enabled
= ibx_infoframes_enabled
;
3284 dig_port
->write_infoframe
= cpt_write_infoframe
;
3285 dig_port
->read_infoframe
= cpt_read_infoframe
;
3286 dig_port
->set_infoframes
= cpt_set_infoframes
;
3287 dig_port
->infoframes_enabled
= cpt_infoframes_enabled
;
3291 void intel_hdmi_init_connector(struct intel_digital_port
*dig_port
,
3292 struct intel_connector
*intel_connector
)
3294 struct drm_connector
*connector
= &intel_connector
->base
;
3295 struct intel_hdmi
*intel_hdmi
= &dig_port
->hdmi
;
3296 struct intel_encoder
*intel_encoder
= &dig_port
->base
;
3297 struct drm_device
*dev
= intel_encoder
->base
.dev
;
3298 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3299 struct i2c_adapter
*ddc
;
3300 enum port port
= intel_encoder
->port
;
3301 struct cec_connector_info conn_info
;
3303 drm_dbg_kms(&dev_priv
->drm
,
3304 "Adding HDMI connector on [ENCODER:%d:%s]\n",
3305 intel_encoder
->base
.base
.id
, intel_encoder
->base
.name
);
3307 if (INTEL_GEN(dev_priv
) < 12 && drm_WARN_ON(dev
, port
== PORT_A
))
3310 if (drm_WARN(dev
, dig_port
->max_lanes
< 4,
3311 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3312 dig_port
->max_lanes
, intel_encoder
->base
.base
.id
,
3313 intel_encoder
->base
.name
))
3316 intel_hdmi
->ddc_bus
= intel_hdmi_ddc_pin(intel_encoder
);
3317 ddc
= intel_gmbus_get_adapter(dev_priv
, intel_hdmi
->ddc_bus
);
3319 drm_connector_init_with_ddc(dev
, connector
,
3320 &intel_hdmi_connector_funcs
,
3321 DRM_MODE_CONNECTOR_HDMIA
,
3323 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
3325 connector
->interlace_allowed
= 1;
3326 connector
->doublescan_allowed
= 0;
3327 connector
->stereo_allowed
= 1;
3329 if (INTEL_GEN(dev_priv
) >= 10 || IS_GEMINILAKE(dev_priv
))
3330 connector
->ycbcr_420_allowed
= true;
3332 intel_connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
3334 if (HAS_DDI(dev_priv
))
3335 intel_connector
->get_hw_state
= intel_ddi_connector_get_hw_state
;
3337 intel_connector
->get_hw_state
= intel_connector_get_hw_state
;
3339 intel_hdmi_add_properties(intel_hdmi
, connector
);
3341 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
3342 intel_hdmi
->attached_connector
= intel_connector
;
3344 if (is_hdcp_supported(dev_priv
, port
)) {
3345 int ret
= intel_hdcp_init(intel_connector
, port
,
3346 &intel_hdmi_hdcp_shim
);
3348 drm_dbg_kms(&dev_priv
->drm
,
3349 "HDCP init failed, skipping.\n");
3352 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3353 * 0xd. Failure to do so will result in spurious interrupts being
3354 * generated on the port when a cable is not attached.
3356 if (IS_G45(dev_priv
)) {
3357 u32 temp
= intel_de_read(dev_priv
, PEG_BAND_GAP_DATA
);
3358 intel_de_write(dev_priv
, PEG_BAND_GAP_DATA
,
3359 (temp
& ~0xf) | 0xd);
3362 cec_fill_conn_info_from_drm(&conn_info
, connector
);
3364 intel_hdmi
->cec_notifier
=
3365 cec_notifier_conn_register(dev
->dev
, port_identifier(port
),
3367 if (!intel_hdmi
->cec_notifier
)
3368 drm_dbg_kms(&dev_priv
->drm
, "CEC notifier get failed\n");
3371 static enum intel_hotplug_state
3372 intel_hdmi_hotplug(struct intel_encoder
*encoder
,
3373 struct intel_connector
*connector
)
3375 enum intel_hotplug_state state
;
3377 state
= intel_encoder_hotplug(encoder
, connector
);
3380 * On many platforms the HDMI live state signal is known to be
3381 * unreliable, so we can't use it to detect if a sink is connected or
3382 * not. Instead we detect if it's connected based on whether we can
3383 * read the EDID or not. That in turn has a problem during disconnect,
3384 * since the HPD interrupt may be raised before the DDC lines get
3385 * disconnected (due to how the required length of DDC vs. HPD
3386 * connector pins are specified) and so we'll still be able to get a
3387 * valid EDID. To solve this schedule another detection cycle if this
3388 * time around we didn't detect any change in the sink's connection
3391 if (state
== INTEL_HOTPLUG_UNCHANGED
&& !connector
->hotplug_retries
)
3392 state
= INTEL_HOTPLUG_RETRY
;
3397 void intel_hdmi_init(struct drm_i915_private
*dev_priv
,
3398 i915_reg_t hdmi_reg
, enum port port
)
3400 struct intel_digital_port
*dig_port
;
3401 struct intel_encoder
*intel_encoder
;
3402 struct intel_connector
*intel_connector
;
3404 dig_port
= kzalloc(sizeof(*dig_port
), GFP_KERNEL
);
3408 intel_connector
= intel_connector_alloc();
3409 if (!intel_connector
) {
3414 intel_encoder
= &dig_port
->base
;
3416 mutex_init(&dig_port
->hdcp_mutex
);
3418 drm_encoder_init(&dev_priv
->drm
, &intel_encoder
->base
,
3419 &intel_hdmi_enc_funcs
, DRM_MODE_ENCODER_TMDS
,
3420 "HDMI %c", port_name(port
));
3422 intel_encoder
->hotplug
= intel_hdmi_hotplug
;
3423 intel_encoder
->compute_config
= intel_hdmi_compute_config
;
3424 if (HAS_PCH_SPLIT(dev_priv
)) {
3425 intel_encoder
->disable
= pch_disable_hdmi
;
3426 intel_encoder
->post_disable
= pch_post_disable_hdmi
;
3428 intel_encoder
->disable
= g4x_disable_hdmi
;
3430 intel_encoder
->get_hw_state
= intel_hdmi_get_hw_state
;
3431 intel_encoder
->get_config
= intel_hdmi_get_config
;
3432 if (IS_CHERRYVIEW(dev_priv
)) {
3433 intel_encoder
->pre_pll_enable
= chv_hdmi_pre_pll_enable
;
3434 intel_encoder
->pre_enable
= chv_hdmi_pre_enable
;
3435 intel_encoder
->enable
= vlv_enable_hdmi
;
3436 intel_encoder
->post_disable
= chv_hdmi_post_disable
;
3437 intel_encoder
->post_pll_disable
= chv_hdmi_post_pll_disable
;
3438 } else if (IS_VALLEYVIEW(dev_priv
)) {
3439 intel_encoder
->pre_pll_enable
= vlv_hdmi_pre_pll_enable
;
3440 intel_encoder
->pre_enable
= vlv_hdmi_pre_enable
;
3441 intel_encoder
->enable
= vlv_enable_hdmi
;
3442 intel_encoder
->post_disable
= vlv_hdmi_post_disable
;
3444 intel_encoder
->pre_enable
= intel_hdmi_pre_enable
;
3445 if (HAS_PCH_CPT(dev_priv
))
3446 intel_encoder
->enable
= cpt_enable_hdmi
;
3447 else if (HAS_PCH_IBX(dev_priv
))
3448 intel_encoder
->enable
= ibx_enable_hdmi
;
3450 intel_encoder
->enable
= g4x_enable_hdmi
;
3453 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
3454 intel_encoder
->power_domain
= intel_port_to_power_domain(port
);
3455 intel_encoder
->port
= port
;
3456 if (IS_CHERRYVIEW(dev_priv
)) {
3458 intel_encoder
->pipe_mask
= BIT(PIPE_C
);
3460 intel_encoder
->pipe_mask
= BIT(PIPE_A
) | BIT(PIPE_B
);
3462 intel_encoder
->pipe_mask
= ~0;
3464 intel_encoder
->cloneable
= 1 << INTEL_OUTPUT_ANALOG
;
3465 intel_encoder
->hpd_pin
= intel_hpd_pin_default(dev_priv
, port
);
3467 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3468 * to work on real hardware. And since g4x can send infoframes to
3469 * only one port anyway, nothing is lost by allowing it.
3471 if (IS_G4X(dev_priv
))
3472 intel_encoder
->cloneable
|= 1 << INTEL_OUTPUT_HDMI
;
3474 dig_port
->hdmi
.hdmi_reg
= hdmi_reg
;
3475 dig_port
->dp
.output_reg
= INVALID_MMIO_REG
;
3476 dig_port
->max_lanes
= 4;
3478 intel_infoframe_init(dig_port
);
3480 dig_port
->aux_ch
= intel_bios_port_aux_ch(dev_priv
, port
);
3481 intel_hdmi_init_connector(dig_port
, intel_connector
);