drivers/gpu/drm/i915/display/intel_vbt_defs.h

   1 /*
   2  * Copyright © 2006-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 /*
  29  * This information is private to VBT parsing in intel_bios.c.
  30  *
  31  * Please do NOT include anywhere else.
  32  */
  33 #ifndef _INTEL_BIOS_PRIVATE
  34 #error "intel_vbt_defs.h is private to intel_bios.c"
  35 #endif
  36
  37 #ifndef _INTEL_VBT_DEFS_H_
  38 #define _INTEL_VBT_DEFS_H_
  39
  40 #include "intel_bios.h"
  41
  42 /**
  43  * struct vbt_header - VBT Header structure
  44  * @signature:          VBT signature, always starts with "$VBT"
  45  * @version:            Version of this structure
  46  * @header_size:        Size of this structure
  47  * @vbt_size:           Size of VBT (VBT Header, BDB Header and data blocks)
  48  * @vbt_checksum:       Checksum
  49  * @reserved0:          Reserved
  50  * @bdb_offset:         Offset of &struct bdb_header from beginning of VBT
  51  * @aim_offset:         Offsets of add-in data blocks from beginning of VBT
  52  */
  53 struct vbt_header {
  54         u8 signature[20];
  55         u16 version;
  56         u16 header_size;
  57         u16 vbt_size;
  58         u8 vbt_checksum;
  59         u8 reserved0;
  60         u32 bdb_offset;
  61         u32 aim_offset[4];
  62 } __packed;
  63
  64 /**
  65  * struct bdb_header - BDB Header structure
  66  * @signature:          BDB signature "BIOS_DATA_BLOCK"
  67  * @version:            Version of the data block definitions
  68  * @header_size:        Size of this structure
  69  * @bdb_size:           Size of BDB (BDB Header and data blocks)
  70  */
  71 struct bdb_header {
  72         u8 signature[16];
  73         u16 version;
  74         u16 header_size;
  75         u16 bdb_size;
  76 } __packed;
  77
  78 /*
  79  * There are several types of BIOS data blocks (BDBs), each block has
  80  * an ID and size in the first 3 bytes (ID in first, size in next 2).
  81  * Known types are listed below.
  82  */
  83 enum bdb_block_id {
  84         BDB_GENERAL_FEATURES            = 1,
  85         BDB_GENERAL_DEFINITIONS         = 2,
  86         BDB_OLD_TOGGLE_LIST             = 3,
  87         BDB_MODE_SUPPORT_LIST           = 4,
  88         BDB_GENERIC_MODE_TABLE          = 5,
  89         BDB_EXT_MMIO_REGS               = 6,
  90         BDB_SWF_IO                      = 7,
  91         BDB_SWF_MMIO                    = 8,
  92         BDB_PSR                         = 9,
  93         BDB_MODE_REMOVAL_TABLE          = 10,
  94         BDB_CHILD_DEVICE_TABLE          = 11,
  95         BDB_DRIVER_FEATURES             = 12,
  96         BDB_DRIVER_PERSISTENCE          = 13,
  97         BDB_EXT_TABLE_PTRS              = 14,
  98         BDB_DOT_CLOCK_OVERRIDE          = 15,
  99         BDB_DISPLAY_SELECT              = 16,
 100         BDB_DRIVER_ROTATION             = 18,
 101         BDB_DISPLAY_REMOVE              = 19,
 102         BDB_OEM_CUSTOM                  = 20,
 103         BDB_EFP_LIST                    = 21, /* workarounds for VGA hsync/vsync */
 104         BDB_SDVO_LVDS_OPTIONS           = 22,
 105         BDB_SDVO_PANEL_DTDS             = 23,
 106         BDB_SDVO_LVDS_PNP_IDS           = 24,
 107         BDB_SDVO_LVDS_POWER_SEQ         = 25,
 108         BDB_TV_OPTIONS                  = 26,
 109         BDB_EDP                         = 27,
 110         BDB_LVDS_OPTIONS                = 40,
 111         BDB_LVDS_LFP_DATA_PTRS          = 41,
 112         BDB_LVDS_LFP_DATA               = 42,
 113         BDB_LVDS_BACKLIGHT              = 43,
 114         BDB_LFP_POWER                   = 44,
 115         BDB_MIPI_CONFIG                 = 52,
 116         BDB_MIPI_SEQUENCE               = 53,
 117         BDB_COMPRESSION_PARAMETERS      = 56,
 118         BDB_GENERIC_DTD                 = 58,
 119         BDB_SKIP                        = 254, /* VBIOS private block, ignore */
 120 };
 121
 122 /*
 123  * Block 1 - General Bit Definitions
 124  */
 125
 126 struct bdb_general_features {
 127         /* bits 1 */
 128         u8 panel_fitting:2;
 129         u8 flexaim:1;
 130         u8 msg_enable:1;
 131         u8 clear_screen:3;
 132         u8 color_flip:1;
 133
 134         /* bits 2 */
 135         u8 download_ext_vbt:1;
 136         u8 enable_ssc:1;
 137         u8 ssc_freq:1;
 138         u8 enable_lfp_on_override:1;
 139         u8 disable_ssc_ddt:1;
 140         u8 underscan_vga_timings:1;
 141         u8 display_clock_mode:1;
 142         u8 vbios_hotplug_support:1;
 143
 144         /* bits 3 */
 145         u8 disable_smooth_vision:1;
 146         u8 single_dvi:1;
 147         u8 rotate_180:1;                                        /* 181 */
 148         u8 fdi_rx_polarity_inverted:1;
 149         u8 vbios_extended_mode:1;                               /* 160 */
 150         u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1;                    /* 160 */
 151         u8 panel_best_fit_timing:1;                             /* 160 */
 152         u8 ignore_strap_state:1;                                /* 160 */
 153
 154         /* bits 4 */
 155         u8 legacy_monitor_detect;
 156
 157         /* bits 5 */
 158         u8 int_crt_support:1;
 159         u8 int_tv_support:1;
 160         u8 int_efp_support:1;
 161         u8 dp_ssc_enable:1;     /* PCH attached eDP supports SSC */
 162         u8 dp_ssc_freq:1;       /* SSC freq for PCH attached eDP */
 163         u8 dp_ssc_dongle_supported:1;
 164         u8 rsvd11:2; /* finish byte */
 165 } __packed;
 166
 167 /*
 168  * Block 2 - General Bytes Definition
 169  */
 170
 171 /* pre-915 */
 172 #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
 173 #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
 174 #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
 175 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 176
 177 /* Pre 915 */
 178 #define DEVICE_TYPE_NONE        0x00
 179 #define DEVICE_TYPE_CRT         0x01
 180 #define DEVICE_TYPE_TV          0x09
 181 #define DEVICE_TYPE_EFP         0x12
 182 #define DEVICE_TYPE_LFP         0x22
 183 /* On 915+ */
 184 #define DEVICE_TYPE_CRT_DPMS            0x6001
 185 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
 186 #define DEVICE_TYPE_TV_COMPOSITE        0x0209
 187 #define DEVICE_TYPE_TV_MACROVISION      0x0289
 188 #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
 189 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
 190 #define DEVICE_TYPE_TV_SCART            0x0209
 191 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
 192 #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
 193 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
 194 #define DEVICE_TYPE_EFP_DVI_I           0x6053
 195 #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
 196 #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
 197 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
 198 #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
 199 #define DEVICE_TYPE_LFP_PANELLINK       0x5012
 200 #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
 201 #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
 202 #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
 203 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
 204
 205 /* Add the device class for LFP, TV, HDMI */
 206 #define DEVICE_TYPE_INT_LFP             0x1022
 207 #define DEVICE_TYPE_INT_TV              0x1009
 208 #define DEVICE_TYPE_HDMI                0x60D2
 209 #define DEVICE_TYPE_DP                  0x68C6
 210 #define DEVICE_TYPE_DP_DUAL_MODE        0x60D6
 211 #define DEVICE_TYPE_eDP                 0x78C6
 212
 213 #define DEVICE_TYPE_CLASS_EXTENSION     (1 << 15)
 214 #define DEVICE_TYPE_POWER_MANAGEMENT    (1 << 14)
 215 #define DEVICE_TYPE_HOTPLUG_SIGNALING   (1 << 13)
 216 #define DEVICE_TYPE_INTERNAL_CONNECTOR  (1 << 12)
 217 #define DEVICE_TYPE_NOT_HDMI_OUTPUT     (1 << 11)
 218 #define DEVICE_TYPE_MIPI_OUTPUT         (1 << 10)
 219 #define DEVICE_TYPE_COMPOSITE_OUTPUT    (1 << 9)
 220 #define DEVICE_TYPE_DUAL_CHANNEL        (1 << 8)
 221 #define DEVICE_TYPE_HIGH_SPEED_LINK     (1 << 6)
 222 #define DEVICE_TYPE_LVDS_SIGNALING      (1 << 5)
 223 #define DEVICE_TYPE_TMDS_DVI_SIGNALING  (1 << 4)
 224 #define DEVICE_TYPE_VIDEO_SIGNALING     (1 << 3)
 225 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT  (1 << 2)
 226 #define DEVICE_TYPE_DIGITAL_OUTPUT      (1 << 1)
 227 #define DEVICE_TYPE_ANALOG_OUTPUT       (1 << 0)
 228
 229 /*
 230  * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the
 231  * system, the other bits may or may not be set for eDP outputs.
 232  */
 233 #define DEVICE_TYPE_eDP_BITS \
 234         (DEVICE_TYPE_INTERNAL_CONNECTOR |       \
 235          DEVICE_TYPE_MIPI_OUTPUT |              \
 236          DEVICE_TYPE_COMPOSITE_OUTPUT |         \
 237          DEVICE_TYPE_DUAL_CHANNEL |             \
 238          DEVICE_TYPE_LVDS_SIGNALING |           \
 239          DEVICE_TYPE_TMDS_DVI_SIGNALING |       \
 240          DEVICE_TYPE_VIDEO_SIGNALING |          \
 241          DEVICE_TYPE_DISPLAYPORT_OUTPUT |       \
 242          DEVICE_TYPE_ANALOG_OUTPUT)
 243
 244 #define DEVICE_TYPE_DP_DUAL_MODE_BITS \
 245         (DEVICE_TYPE_INTERNAL_CONNECTOR |       \
 246          DEVICE_TYPE_MIPI_OUTPUT |              \
 247          DEVICE_TYPE_COMPOSITE_OUTPUT |         \
 248          DEVICE_TYPE_LVDS_SIGNALING |           \
 249          DEVICE_TYPE_TMDS_DVI_SIGNALING |       \
 250          DEVICE_TYPE_VIDEO_SIGNALING |          \
 251          DEVICE_TYPE_DISPLAYPORT_OUTPUT |       \
 252          DEVICE_TYPE_DIGITAL_OUTPUT |           \
 253          DEVICE_TYPE_ANALOG_OUTPUT)
 254
 255 #define DEVICE_CFG_NONE         0x00
 256 #define DEVICE_CFG_12BIT_DVOB   0x01
 257 #define DEVICE_CFG_12BIT_DVOC   0x02
 258 #define DEVICE_CFG_24BIT_DVOBC  0x09
 259 #define DEVICE_CFG_24BIT_DVOCB  0x0a
 260 #define DEVICE_CFG_DUAL_DVOB    0x11
 261 #define DEVICE_CFG_DUAL_DVOC    0x12
 262 #define DEVICE_CFG_DUAL_DVOBC   0x13
 263 #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
 264 #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
 265
 266 #define DEVICE_WIRE_NONE        0x00
 267 #define DEVICE_WIRE_DVOB        0x01
 268 #define DEVICE_WIRE_DVOC        0x02
 269 #define DEVICE_WIRE_DVOBC       0x03
 270 #define DEVICE_WIRE_DVOBB       0x05
 271 #define DEVICE_WIRE_DVOCC       0x06
 272 #define DEVICE_WIRE_DVOB_MASTER 0x0d
 273 #define DEVICE_WIRE_DVOC_MASTER 0x0e
 274
 275 /* dvo_port pre BDB 155 */
 276 #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
 277 #define DEVICE_PORT_DVOB        0x01
 278 #define DEVICE_PORT_DVOC        0x02
 279
 280 /* dvo_port BDB 155+ */
 281 #define DVO_PORT_HDMIA          0
 282 #define DVO_PORT_HDMIB          1
 283 #define DVO_PORT_HDMIC          2
 284 #define DVO_PORT_HDMID          3
 285 #define DVO_PORT_LVDS           4
 286 #define DVO_PORT_TV             5
 287 #define DVO_PORT_CRT            6
 288 #define DVO_PORT_DPB            7
 289 #define DVO_PORT_DPC            8
 290 #define DVO_PORT_DPD            9
 291 #define DVO_PORT_DPA            10
 292 #define DVO_PORT_DPE            11                              /* 193 */
 293 #define DVO_PORT_HDMIE          12                              /* 193 */
 294 #define DVO_PORT_DPF            13                              /* N/A */
 295 #define DVO_PORT_HDMIF          14                              /* N/A */
 296 #define DVO_PORT_DPG            15                              /* 217 */
 297 #define DVO_PORT_HDMIG          16                              /* 217 */
 298 #define DVO_PORT_DPH            17                              /* 217 */
 299 #define DVO_PORT_HDMIH          18                              /* 217 */
 300 #define DVO_PORT_DPI            19                              /* 217 */
 301 #define DVO_PORT_HDMII          20                              /* 217 */
 302 #define DVO_PORT_MIPIA          21                              /* 171 */
 303 #define DVO_PORT_MIPIB          22                              /* 171 */
 304 #define DVO_PORT_MIPIC          23                              /* 171 */
 305 #define DVO_PORT_MIPID          24                              /* 171 */
 306
 307 #define HDMI_MAX_DATA_RATE_PLATFORM     0                       /* 204 */
 308 #define HDMI_MAX_DATA_RATE_297          1                       /* 204 */
 309 #define HDMI_MAX_DATA_RATE_165          2                       /* 204 */
 310
 311 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE         33
 312
 313 /* DDC Bus DDI Type 155+ */
 314 enum vbt_gmbus_ddi {
 315         DDC_BUS_DDI_B = 0x1,
 316         DDC_BUS_DDI_C,
 317         DDC_BUS_DDI_D,
 318         DDC_BUS_DDI_F,
 319         ICL_DDC_BUS_DDI_A = 0x1,
 320         ICL_DDC_BUS_DDI_B,
 321         TGL_DDC_BUS_DDI_C,
 322         ICL_DDC_BUS_PORT_1 = 0x4,
 323         ICL_DDC_BUS_PORT_2,
 324         ICL_DDC_BUS_PORT_3,
 325         ICL_DDC_BUS_PORT_4,
 326         TGL_DDC_BUS_PORT_5,
 327         TGL_DDC_BUS_PORT_6,
 328 };
 329
 330 #define DP_AUX_A 0x40
 331 #define DP_AUX_B 0x10
 332 #define DP_AUX_C 0x20
 333 #define DP_AUX_D 0x30
 334 #define DP_AUX_E 0x50
 335 #define DP_AUX_F 0x60
 336 #define DP_AUX_G 0x70
 337 #define DP_AUX_H 0x80
 338 #define DP_AUX_I 0x90
 339
 340 #define VBT_DP_MAX_LINK_RATE_HBR3       0
 341 #define VBT_DP_MAX_LINK_RATE_HBR2       1
 342 #define VBT_DP_MAX_LINK_RATE_HBR        2
 343 #define VBT_DP_MAX_LINK_RATE_LBR        3
 344
 345 /*
 346  * The child device config, aka the display device data structure, provides a
 347  * description of a port and its configuration on the platform.
 348  *
 349  * The child device config size has been increased, and fields have been added
 350  * and their meaning has changed over time. Care must be taken when accessing
 351  * basically any of the fields to ensure the correct interpretation for the BDB
 352  * version in question.
 353  *
 354  * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
 355  * space for the full structure below, and initialize the tail not actually
 356  * present in VBT to zeros. Accessing those fields is fine, as long as the
 357  * default zero is taken into account, again according to the BDB version.
 358  *
 359  * BDB versions 155 and below are considered legacy, and version 155 seems to be
 360  * a baseline for some of the VBT documentation. When adding new fields, please
 361  * include the BDB version when the field was added, if it's above that.
 362  */
 363 struct child_device_config {
 364         u16 handle;
 365         u16 device_type; /* See DEVICE_TYPE_* above */
 366
 367         union {
 368                 u8  device_id[10]; /* ascii string */
 369                 struct {
 370                         u8 i2c_speed;
 371                         u8 dp_onboard_redriver;                 /* 158 */
 372                         u8 dp_ondock_redriver;                  /* 158 */
 373                         u8 hdmi_level_shifter_value:5;          /* 169 */
 374                         u8 hdmi_max_data_rate:3;                /* 204 */
 375                         u16 dtd_buf_ptr;                        /* 161 */
 376                         u8 edidless_efp:1;                      /* 161 */
 377                         u8 compression_enable:1;                /* 198 */
 378                         u8 compression_method_cps:1;            /* 198 */
 379                         u8 ganged_edp:1;                        /* 202 */
 380                         u8 reserved0:4;
 381                         u8 compression_structure_index:4;       /* 198 */
 382                         u8 reserved1:4;
 383                         u8 slave_port;                          /* 202 */
 384                         u8 reserved2;
 385                 } __packed;
 386         } __packed;
 387
 388         u16 addin_offset;
 389         u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
 390         u8 i2c_pin;
 391         u8 slave_addr;
 392         u8 ddc_pin;
 393         u16 edid_ptr;
 394         u8 dvo_cfg; /* See DEVICE_CFG_* above */
 395
 396         union {
 397                 struct {
 398                         u8 dvo2_port;
 399                         u8 i2c2_pin;
 400                         u8 slave2_addr;
 401                         u8 ddc2_pin;
 402                 } __packed;
 403                 struct {
 404                         u8 efp_routed:1;                        /* 158 */
 405                         u8 lane_reversal:1;                     /* 184 */
 406                         u8 lspcon:1;                            /* 192 */
 407                         u8 iboost:1;                            /* 196 */
 408                         u8 hpd_invert:1;                        /* 196 */
 409                         u8 use_vbt_vswing:1;                    /* 218 */
 410                         u8 flag_reserved:2;
 411                         u8 hdmi_support:1;                      /* 158 */
 412                         u8 dp_support:1;                        /* 158 */
 413                         u8 tmds_support:1;                      /* 158 */
 414                         u8 support_reserved:5;
 415                         u8 aux_channel;
 416                         u8 dongle_detect;
 417                 } __packed;
 418         } __packed;
 419
 420         u8 pipe_cap:2;
 421         u8 sdvo_stall:1;                                        /* 158 */
 422         u8 hpd_status:2;
 423         u8 integrated_encoder:1;
 424         u8 capabilities_reserved:2;
 425         u8 dvo_wiring; /* See DEVICE_WIRE_* above */
 426
 427         union {
 428                 u8 dvo2_wiring;
 429                 u8 mipi_bridge_type;                            /* 171 */
 430         } __packed;
 431
 432         u16 extended_type;
 433         u8 dvo_function;
 434         u8 dp_usb_type_c:1;                                     /* 195 */
 435         u8 tbt:1;                                               /* 209 */
 436         u8 flags2_reserved:2;                                   /* 195 */
 437         u8 dp_port_trace_length:4;                              /* 209 */
 438         u8 dp_gpio_index;                                       /* 195 */
 439         u16 dp_gpio_pin_num;                                    /* 195 */
 440         u8 dp_iboost_level:4;                                   /* 196 */
 441         u8 hdmi_iboost_level:4;                                 /* 196 */
 442         u8 dp_max_link_rate:2;                                  /* 216 CNL+ */
 443         u8 dp_max_link_rate_reserved:6;                         /* 216 */
 444 } __packed;
 445
 446 struct bdb_general_definitions {
 447         /* DDC GPIO */
 448         u8 crt_ddc_gmbus_pin;
 449
 450         /* DPMS bits */
 451         u8 dpms_acpi:1;
 452         u8 skip_boot_crt_detect:1;
 453         u8 dpms_aim:1;
 454         u8 rsvd1:5; /* finish byte */
 455
 456         /* boot device bits */
 457         u8 boot_display[2];
 458         u8 child_dev_size;
 459
 460         /*
 461          * Device info:
 462          * If TV is present, it'll be at devices[0].
 463          * LVDS will be next, either devices[0] or [1], if present.
 464          * On some platforms the number of device is 6. But could be as few as
 465          * 4 if both TV and LVDS are missing.
 466          * And the device num is related with the size of general definition
 467          * block. It is obtained by using the following formula:
 468          * number = (block_size - sizeof(bdb_general_definitions))/
 469          *           defs->child_dev_size;
 470          */
 471         u8 devices[];
 472 } __packed;
 473
 474 /*
 475  * Block 9 - SRD Feature Block
 476  */
 477
 478 struct psr_table {
 479         /* Feature bits */
 480         u8 full_link:1;
 481         u8 require_aux_to_wakeup:1;
 482         u8 feature_bits_rsvd:6;
 483
 484         /* Wait times */
 485         u8 idle_frames:4;
 486         u8 lines_to_wait:3;
 487         u8 wait_times_rsvd:1;
 488
 489         /* TP wake up time in multiple of 100 */
 490         u16 tp1_wakeup_time;
 491         u16 tp2_tp3_wakeup_time;
 492 } __packed;
 493
 494 struct bdb_psr {
 495         struct psr_table psr_table[16];
 496
 497         /* PSR2 TP2/TP3 wakeup time for 16 panels */
 498         u32 psr2_tp2_tp3_wakeup_time;
 499 } __packed;
 500
 501 /*
 502  * Block 12 - Driver Features Data Block
 503  */
 504
 505 #define BDB_DRIVER_FEATURE_NO_LVDS              0
 506 #define BDB_DRIVER_FEATURE_INT_LVDS             1
 507 #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
 508 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS        3
 509
 510 struct bdb_driver_features {
 511         u8 boot_dev_algorithm:1;
 512         u8 block_display_switch:1;
 513         u8 allow_display_switch:1;
 514         u8 hotplug_dvo:1;
 515         u8 dual_view_zoom:1;
 516         u8 int15h_hook:1;
 517         u8 sprite_in_clone:1;
 518         u8 primary_lfp_id:1;
 519
 520         u16 boot_mode_x;
 521         u16 boot_mode_y;
 522         u8 boot_mode_bpp;
 523         u8 boot_mode_refresh;
 524
 525         u16 enable_lfp_primary:1;
 526         u16 selective_mode_pruning:1;
 527         u16 dual_frequency:1;
 528         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
 529         u16 nt_clone_support:1;
 530         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
 531         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
 532         u16 cui_aspect_scaling:1;
 533         u16 preserve_aspect_ratio:1;
 534         u16 sdvo_device_power_down:1;
 535         u16 crt_hotplug:1;
 536         u16 lvds_config:2;
 537         u16 tv_hotplug:1;
 538         u16 hdmi_config:2;
 539
 540         u8 static_display:1;
 541         u8 reserved2:7;
 542         u16 legacy_crt_max_x;
 543         u16 legacy_crt_max_y;
 544         u8 legacy_crt_max_refresh;
 545
 546         u8 hdmi_termination;
 547         u8 custom_vbt_version;
 548         /* Driver features data block */
 549         u16 rmpm_enabled:1;
 550         u16 s2ddt_enabled:1;
 551         u16 dpst_enabled:1;
 552         u16 bltclt_enabled:1;
 553         u16 adb_enabled:1;
 554         u16 drrs_enabled:1;
 555         u16 grs_enabled:1;
 556         u16 gpmt_enabled:1;
 557         u16 tbt_enabled:1;
 558         u16 psr_enabled:1;
 559         u16 ips_enabled:1;
 560         u16 reserved3:4;
 561         u16 pc_feature_valid:1;
 562 } __packed;
 563
 564 /*
 565  * Block 22 - SDVO LVDS General Options
 566  */
 567
 568 struct bdb_sdvo_lvds_options {
 569         u8 panel_backlight;
 570         u8 h40_set_panel_type;
 571         u8 panel_type;
 572         u8 ssc_clk_freq;
 573         u16 als_low_trip;
 574         u16 als_high_trip;
 575         u8 sclalarcoeff_tab_row_num;
 576         u8 sclalarcoeff_tab_row_size;
 577         u8 coefficient[8];
 578         u8 panel_misc_bits_1;
 579         u8 panel_misc_bits_2;
 580         u8 panel_misc_bits_3;
 581         u8 panel_misc_bits_4;
 582 } __packed;
 583
 584 /*
 585  * Block 23 - SDVO LVDS Panel DTDs
 586  */
 587
 588 struct lvds_dvo_timing {
 589         u16 clock;              /**< In 10khz */
 590         u8 hactive_lo;
 591         u8 hblank_lo;
 592         u8 hblank_hi:4;
 593         u8 hactive_hi:4;
 594         u8 vactive_lo;
 595         u8 vblank_lo;
 596         u8 vblank_hi:4;
 597         u8 vactive_hi:4;
 598         u8 hsync_off_lo;
 599         u8 hsync_pulse_width_lo;
 600         u8 vsync_pulse_width_lo:4;
 601         u8 vsync_off_lo:4;
 602         u8 vsync_pulse_width_hi:2;
 603         u8 vsync_off_hi:2;
 604         u8 hsync_pulse_width_hi:2;
 605         u8 hsync_off_hi:2;
 606         u8 himage_lo;
 607         u8 vimage_lo;
 608         u8 vimage_hi:4;
 609         u8 himage_hi:4;
 610         u8 h_border;
 611         u8 v_border;
 612         u8 rsvd1:3;
 613         u8 digital:2;
 614         u8 vsync_positive:1;
 615         u8 hsync_positive:1;
 616         u8 non_interlaced:1;
 617 } __packed;
 618
 619 struct bdb_sdvo_panel_dtds {
 620         struct lvds_dvo_timing dtds[4];
 621 } __packed;
 622
 623 /*
 624  * Block 27 - eDP VBT Block
 625  */
 626
 627 #define EDP_18BPP       0
 628 #define EDP_24BPP       1
 629 #define EDP_30BPP       2
 630 #define EDP_RATE_1_62   0
 631 #define EDP_RATE_2_7    1
 632 #define EDP_LANE_1      0
 633 #define EDP_LANE_2      1
 634 #define EDP_LANE_4      3
 635 #define EDP_PREEMPHASIS_NONE    0
 636 #define EDP_PREEMPHASIS_3_5dB   1
 637 #define EDP_PREEMPHASIS_6dB     2
 638 #define EDP_PREEMPHASIS_9_5dB   3
 639 #define EDP_VSWING_0_4V         0
 640 #define EDP_VSWING_0_6V         1
 641 #define EDP_VSWING_0_8V         2
 642 #define EDP_VSWING_1_2V         3
 643
 644
 645 struct edp_fast_link_params {
 646         u8 rate:4;
 647         u8 lanes:4;
 648         u8 preemphasis:4;
 649         u8 vswing:4;
 650 } __packed;
 651
 652 struct edp_pwm_delays {
 653         u16 pwm_on_to_backlight_enable;
 654         u16 backlight_disable_to_pwm_off;
 655 } __packed;
 656
 657 struct edp_full_link_params {
 658         u8 preemphasis:4;
 659         u8 vswing:4;
 660 } __packed;
 661
 662 struct bdb_edp {
 663         struct edp_power_seq power_seqs[16];
 664         u32 color_depth;
 665         struct edp_fast_link_params fast_link_params[16];
 666         u32 sdrrs_msa_timing_delay;
 667
 668         /* ith bit indicates enabled/disabled for (i+1)th panel */
 669         u16 edp_s3d_feature;                                    /* 162 */
 670         u16 edp_t3_optimization;                                /* 165 */
 671         u64 edp_vswing_preemph;                                 /* 173 */
 672         u16 fast_link_training;                                 /* 182 */
 673         u16 dpcd_600h_write_required;                           /* 185 */
 674         struct edp_pwm_delays pwm_delays[16];                   /* 186 */
 675         u16 full_link_params_provided;                          /* 199 */
 676         struct edp_full_link_params full_link_params[16];       /* 199 */
 677 } __packed;
 678
 679 /*
 680  * Block 40 - LFP Data Block
 681  */
 682
 683 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
 684 #define MODE_MASK               0x3
 685
 686 struct bdb_lvds_options {
 687         u8 panel_type;
 688         u8 panel_type2;                                         /* 212 */
 689         /* LVDS capabilities, stored in a dword */
 690         u8 pfit_mode:2;
 691         u8 pfit_text_mode_enhanced:1;
 692         u8 pfit_gfx_mode_enhanced:1;
 693         u8 pfit_ratio_auto:1;
 694         u8 pixel_dither:1;
 695         u8 lvds_edid:1;
 696         u8 rsvd2:1;
 697         u8 rsvd4;
 698         /* LVDS Panel channel bits stored here */
 699         u32 lvds_panel_channel_bits;
 700         /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
 701         u16 ssc_bits;
 702         u16 ssc_freq;
 703         u16 ssc_ddt;
 704         /* Panel color depth defined here */
 705         u16 panel_color_depth;
 706         /* LVDS panel type bits stored here */
 707         u32 dps_panel_type_bits;
 708         /* LVDS backlight control type bits stored here */
 709         u32 blt_control_type_bits;
 710
 711         u16 lcdvcc_s0_enable;                                   /* 200 */
 712         u32 rotation;                                           /* 228 */
 713 } __packed;
 714
 715 /*
 716  * Block 41 - LFP Data Table Pointers
 717  */
 718
 719 /* LFP pointer table contains entries to the struct below */
 720 struct lvds_lfp_data_ptr {
 721         u16 fp_timing_offset; /* offsets are from start of bdb */
 722         u8 fp_table_size;
 723         u16 dvo_timing_offset;
 724         u8 dvo_table_size;
 725         u16 panel_pnp_id_offset;
 726         u8 pnp_table_size;
 727 } __packed;
 728
 729 struct bdb_lvds_lfp_data_ptrs {
 730         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
 731         struct lvds_lfp_data_ptr ptr[16];
 732 } __packed;
 733
 734 /*
 735  * Block 42 - LFP Data Tables
 736  */
 737
 738 /* LFP data has 3 blocks per entry */
 739 struct lvds_fp_timing {
 740         u16 x_res;
 741         u16 y_res;
 742         u32 lvds_reg;
 743         u32 lvds_reg_val;
 744         u32 pp_on_reg;
 745         u32 pp_on_reg_val;
 746         u32 pp_off_reg;
 747         u32 pp_off_reg_val;
 748         u32 pp_cycle_reg;
 749         u32 pp_cycle_reg_val;
 750         u32 pfit_reg;
 751         u32 pfit_reg_val;
 752         u16 terminator;
 753 } __packed;
 754
 755 struct lvds_pnp_id {
 756         u16 mfg_name;
 757         u16 product_code;
 758         u32 serial;
 759         u8 mfg_week;
 760         u8 mfg_year;
 761 } __packed;
 762
 763 struct lvds_lfp_data_entry {
 764         struct lvds_fp_timing fp_timing;
 765         struct lvds_dvo_timing dvo_timing;
 766         struct lvds_pnp_id pnp_id;
 767 } __packed;
 768
 769 struct bdb_lvds_lfp_data {
 770         struct lvds_lfp_data_entry data[16];
 771 } __packed;
 772
 773 /*
 774  * Block 43 - LFP Backlight Control Data Block
 775  */
 776
 777 #define BDB_BACKLIGHT_TYPE_NONE 0
 778 #define BDB_BACKLIGHT_TYPE_PWM  2
 779
 780 struct lfp_backlight_data_entry {
 781         u8 type:2;
 782         u8 active_low_pwm:1;
 783         u8 obsolete1:5;
 784         u16 pwm_freq_hz;
 785         u8 min_brightness; /* Obsolete from 234+ */
 786         u8 obsolete2;
 787         u8 obsolete3;
 788 } __packed;
 789
 790 struct lfp_backlight_control_method {
 791         u8 type:4;
 792         u8 controller:4;
 793 } __packed;
 794
 795 struct lfp_brightness_level {
 796         u16 level;
 797         u16 reserved;
 798 } __packed;
 799
 800 struct bdb_lfp_backlight_data {
 801         u8 entry_size;
 802         struct lfp_backlight_data_entry data[16];
 803         u8 level[16]; /* Obsolete from 234+ */
 804         struct lfp_backlight_control_method backlight_control[16];
 805         struct lfp_brightness_level brightness_level[16];               /* 234+ */
 806         struct lfp_brightness_level brightness_min_level[16];   /* 234+ */
 807         u8 brightness_precision_bits[16];                                               /* 236+ */
 808 } __packed;
 809
 810 /*
 811  * Block 44 - LFP Power Conservation Features Block
 812  */
 813
 814 struct als_data_entry {
 815         u16 backlight_adjust;
 816         u16 lux;
 817 } __packed;
 818
 819 struct agressiveness_profile_entry {
 820         u8 dpst_agressiveness : 4;
 821         u8 lace_agressiveness : 4;
 822 } __packed;
 823
 824 struct bdb_lfp_power {
 825         u8 lfp_feature_bits;
 826         struct als_data_entry als[5];
 827         u8 lace_aggressiveness_profile;
 828         u16 dpst;
 829         u16 psr;
 830         u16 drrs;
 831         u16 lace_support;
 832         u16 adt;
 833         u16 dmrrs;
 834         u16 adb;
 835         u16 lace_enabled_status;
 836         struct agressiveness_profile_entry aggressivenes[16];
 837         u16 hobl; /* 232+ */
 838         u16 vrr_feature_enabled; /* 233+ */
 839 } __packed;
 840
 841 /*
 842  * Block 52 - MIPI Configuration Block
 843  */
 844
 845 #define MAX_MIPI_CONFIGURATIONS 6
 846
 847 struct bdb_mipi_config {
 848         struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
 849         struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
 850 } __packed;
 851
 852 /*
 853  * Block 53 - MIPI Sequence Block
 854  */
 855
 856 struct bdb_mipi_sequence {
 857         u8 version;
 858         u8 data[]; /* up to 6 variable length blocks */
 859 } __packed;
 860
 861 /*
 862  * Block 56 - Compression Parameters
 863  */
 864
 865 #define VBT_RC_BUFFER_BLOCK_SIZE_1KB    0
 866 #define VBT_RC_BUFFER_BLOCK_SIZE_4KB    1
 867 #define VBT_RC_BUFFER_BLOCK_SIZE_16KB   2
 868 #define VBT_RC_BUFFER_BLOCK_SIZE_64KB   3
 869
 870 #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value)    ((vbt_value) + 8) /* bits */
 871 #define VBT_DSC_MAX_BPP(vbt_value)              (6 + (vbt_value) * 2)
 872
 873 struct dsc_compression_parameters_entry {
 874         u8 version_major:4;
 875         u8 version_minor:4;
 876
 877         u8 rc_buffer_block_size:2;
 878         u8 reserved1:6;
 879
 880         /*
 881          * Buffer size in bytes:
 882          *
 883          * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes
 884          */
 885         u8 rc_buffer_size;
 886         u32 slices_per_line;
 887
 888         u8 line_buffer_depth:4;
 889         u8 reserved2:4;
 890
 891         /* Flag Bits 1 */
 892         u8 block_prediction_enable:1;
 893         u8 reserved3:7;
 894
 895         u8 max_bpp; /* mapping */
 896
 897         /* Color depth capabilities */
 898         u8 reserved4:1;
 899         u8 support_8bpc:1;
 900         u8 support_10bpc:1;
 901         u8 support_12bpc:1;
 902         u8 reserved5:4;
 903
 904         u16 slice_height;
 905 } __packed;
 906
 907 struct bdb_compression_parameters {
 908         u16 entry_size;
 909         struct dsc_compression_parameters_entry data[16];
 910 } __packed;
 911
 912 /*
 913  * Block 58 - Generic DTD Block
 914  */
 915
 916 struct generic_dtd_entry {
 917         u32 pixel_clock;
 918         u16 hactive;
 919         u16 hblank;
 920         u16 hfront_porch;
 921         u16 hsync;
 922         u16 vactive;
 923         u16 vblank;
 924         u16 vfront_porch;
 925         u16 vsync;
 926         u16 width_mm;
 927         u16 height_mm;
 928
 929         /* Flags */
 930         u8 rsvd_flags:6;
 931         u8 vsync_positive_polarity:1;
 932         u8 hsync_positive_polarity:1;
 933
 934         u8 rsvd[3];
 935 } __packed;
 936
 937 struct bdb_generic_dtd {
 938         u16 gdtd_size;
 939         struct generic_dtd_entry dtd[]; /* up to 24 DTD's */
 940 } __packed;
 941
 942 #endif /* _INTEL_VBT_DEFS_H_ */