drivers/gpu/drm/i915/display/intel_vdsc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
   6  *         Manasi Navare <manasi.d.navare@intel.com>
   7  */
   8
   9 #include <drm/i915_drm.h>
  10
  11 #include "i915_drv.h"
  12 #include "intel_display_types.h"
  13 #include "intel_vdsc.h"
  14
  15 enum ROW_INDEX_BPP {
  16         ROW_INDEX_6BPP = 0,
  17         ROW_INDEX_8BPP,
  18         ROW_INDEX_10BPP,
  19         ROW_INDEX_12BPP,
  20         ROW_INDEX_15BPP,
  21         MAX_ROW_INDEX
  22 };
  23
  24 enum COLUMN_INDEX_BPC {
  25         COLUMN_INDEX_8BPC = 0,
  26         COLUMN_INDEX_10BPC,
  27         COLUMN_INDEX_12BPC,
  28         COLUMN_INDEX_14BPC,
  29         COLUMN_INDEX_16BPC,
  30         MAX_COLUMN_INDEX
  31 };
  32
  33 #define DSC_SUPPORTED_VERSION_MIN               1
  34
  35 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
  36 static u16 rc_buf_thresh[] = {
  37         896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
  38         7744, 7872, 8000, 8064
  39 };
  40
  41 struct rc_parameters {
  42         u16 initial_xmit_delay;
  43         u8 first_line_bpg_offset;
  44         u16 initial_offset;
  45         u8 flatness_min_qp;
  46         u8 flatness_max_qp;
  47         u8 rc_quant_incr_limit0;
  48         u8 rc_quant_incr_limit1;
  49         struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
  50 };
  51
  52 /*
  53  * Selected Rate Control Related Parameter Recommended Values
  54  * from DSC_v1.11 spec & C Model release: DSC_model_20161212
  55  */
  56 static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = {
  57 {
  58         /* 6BPP/8BPC */
  59         { 768, 15, 6144, 3, 13, 11, 11, {
  60                 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
  61                 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
  62                 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
  63                 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
  64                 }
  65         },
  66         /* 6BPP/10BPC */
  67         { 768, 15, 6144, 7, 17, 15, 15, {
  68                 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
  69                 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
  70                 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
  71                 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
  72                 { 17, 18, -12 }
  73                 }
  74         },
  75         /* 6BPP/12BPC */
  76         { 768, 15, 6144, 11, 21, 19, 19, {
  77                 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
  78                 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
  79                 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
  80                 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
  81                 { 21, 22, -12 }
  82                 }
  83         },
  84         /* 6BPP/14BPC */
  85         { 768, 15, 6144, 15, 25, 23, 27, {
  86                 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
  87                 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
  88                 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
  89                 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
  90                 { 25, 26, -12 }
  91                 }
  92         },
  93         /* 6BPP/16BPC */
  94         { 768, 15, 6144, 19, 29, 27, 27, {
  95                 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
  96                 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
  97                 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
  98                 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
  99                 { 29, 30, -12 }
 100                 }
 101         },
 102 },
 103 {
 104         /* 8BPP/8BPC */
 105         { 512, 12, 6144, 3, 12, 11, 11, {
 106                 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 107                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 108                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
 109                 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 110                 }
 111         },
 112         /* 8BPP/10BPC */
 113         { 512, 12, 6144, 7, 16, 15, 15, {
 114                 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
 115                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 116                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 117                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 118                 }
 119         },
 120         /* 8BPP/12BPC */
 121         { 512, 12, 6144, 11, 20, 19, 19, {
 122                 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
 123                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 124                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 125                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 126                 { 21, 23, -12 }
 127                 }
 128         },
 129         /* 8BPP/14BPC */
 130         { 512, 12, 6144, 15, 24, 23, 23, {
 131                 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
 132                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 133                 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
 134                 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
 135                 { 24, 25, -12 }
 136                 }
 137         },
 138         /* 8BPP/16BPC */
 139         { 512, 12, 6144, 19, 28, 27, 27, {
 140                 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
 141                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 142                 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
 143                 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
 144                 { 28, 29, -12 }
 145                 }
 146         },
 147 },
 148 {
 149         /* 10BPP/8BPC */
 150         { 410, 15, 5632, 3, 12, 11, 11, {
 151                 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
 152                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 153                 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
 154                 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
 155                 }
 156         },
 157         /* 10BPP/10BPC */
 158         { 410, 15, 5632, 7, 16, 15, 15, {
 159                 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
 160                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 161                 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
 162                 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
 163                 }
 164         },
 165         /* 10BPP/12BPC */
 166         { 410, 15, 5632, 11, 20, 19, 19, {
 167                 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
 168                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 169                 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
 170                 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
 171                 { 19, 20, -12 }
 172                 }
 173         },
 174         /* 10BPP/14BPC */
 175         { 410, 15, 5632, 15, 24, 23, 23, {
 176                 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
 177                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 178                 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
 179                 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
 180                 { 23, 24, -12 }
 181                 }
 182         },
 183         /* 10BPP/16BPC */
 184         { 410, 15, 5632, 19, 28, 27, 27, {
 185                 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
 186                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 187                 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
 188                 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
 189                 { 27, 28, -12 }
 190                 }
 191         },
 192 },
 193 {
 194         /* 12BPP/8BPC */
 195         { 341, 15, 2048, 3, 12, 11, 11, {
 196                 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 197                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 198                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
 199                 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 200                 }
 201         },
 202         /* 12BPP/10BPC */
 203         { 341, 15, 2048, 7, 16, 15, 15, {
 204                 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
 205                 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 206                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 207                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 208                 }
 209         },
 210         /* 12BPP/12BPC */
 211         { 341, 15, 2048, 11, 20, 19, 19, {
 212                 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
 213                 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 214                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 215                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 216                 { 21, 23, -12 }
 217                 }
 218         },
 219         /* 12BPP/14BPC */
 220         { 341, 15, 2048, 15, 24, 23, 23, {
 221                 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
 222                 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 223                 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
 224                 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
 225                 { 22, 23, -12 }
 226                 }
 227         },
 228         /* 12BPP/16BPC */
 229         { 341, 15, 2048, 19, 28, 27, 27, {
 230                 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
 231                 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 232                 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
 233                 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
 234                 { 26, 27, -12 }
 235                 }
 236         },
 237 },
 238 {
 239         /* 15BPP/8BPC */
 240         { 273, 15, 2048, 3, 12, 11, 11, {
 241                 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
 242                 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
 243                 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
 244                 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
 245                 }
 246         },
 247         /* 15BPP/10BPC */
 248         { 273, 15, 2048, 7, 16, 15, 15, {
 249                 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
 250                 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
 251                 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
 252                 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
 253                 }
 254         },
 255         /* 15BPP/12BPC */
 256         { 273, 15, 2048, 11, 20, 19, 19, {
 257                 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
 258                 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
 259                 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
 260                 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
 261                 { 16, 17, -12 }
 262                 }
 263         },
 264         /* 15BPP/14BPC */
 265         { 273, 15, 2048, 15, 24, 23, 23, {
 266                 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
 267                 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
 268                 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
 269                 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
 270                 { 20, 21, -12 }
 271                 }
 272         },
 273         /* 15BPP/16BPC */
 274         { 273, 15, 2048, 19, 28, 27, 27, {
 275                 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
 276                 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
 277                 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
 278                 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
 279                 { 24, 25, -12 }
 280                 }
 281         }
 282 }
 283
 284 };
 285
 286 static int get_row_index_for_rc_params(u16 compressed_bpp)
 287 {
 288         switch (compressed_bpp) {
 289         case 6:
 290                 return ROW_INDEX_6BPP;
 291         case 8:
 292                 return ROW_INDEX_8BPP;
 293         case 10:
 294                 return ROW_INDEX_10BPP;
 295         case 12:
 296                 return ROW_INDEX_12BPP;
 297         case 15:
 298                 return ROW_INDEX_15BPP;
 299         default:
 300                 return -EINVAL;
 301         }
 302 }
 303
 304 static int get_column_index_for_rc_params(u8 bits_per_component)
 305 {
 306         switch (bits_per_component) {
 307         case 8:
 308                 return COLUMN_INDEX_8BPC;
 309         case 10:
 310                 return COLUMN_INDEX_10BPC;
 311         case 12:
 312                 return COLUMN_INDEX_12BPC;
 313         case 14:
 314                 return COLUMN_INDEX_14BPC;
 315         case 16:
 316                 return COLUMN_INDEX_16BPC;
 317         default:
 318                 return -EINVAL;
 319         }
 320 }
 321
 322 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 323                                 struct intel_crtc_state *pipe_config)
 324 {
 325         struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
 326         u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;
 327         u8 i = 0;
 328         int row_index = 0;
 329         int column_index = 0;
 330         u8 line_buf_depth = 0;
 331
 332         vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
 333         vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
 334         vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 335                                              pipe_config->dsc_params.slice_count);
 336         /*
 337          * Slice Height of 8 works for all currently available panels. So start
 338          * with that if pic_height is an integral multiple of 8.
 339          * Eventually add logic to try multiple slice heights.
 340          */
 341         if (vdsc_cfg->pic_height % 8 == 0)
 342                 vdsc_cfg->slice_height = 8;
 343         else if (vdsc_cfg->pic_height % 4 == 0)
 344                 vdsc_cfg->slice_height = 4;
 345         else
 346                 vdsc_cfg->slice_height = 2;
 347
 348         /* Values filled from DSC Sink DPCD */
 349         vdsc_cfg->dsc_version_major =
 350                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 351                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
 352         vdsc_cfg->dsc_version_minor =
 353                 min(DSC_SUPPORTED_VERSION_MIN,
 354                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 355                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
 356
 357         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
 358                 DP_DSC_RGB;
 359
 360         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 361         if (!line_buf_depth) {
 362                 DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
 363                 return -EINVAL;
 364         }
 365         if (vdsc_cfg->dsc_version_minor == 2)
 366                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
 367                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
 368         else
 369                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
 370                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
 371
 372         /* Gen 11 does not support YCbCr */
 373         vdsc_cfg->simple_422 = false;
 374         /* Gen 11 does not support VBR */
 375         vdsc_cfg->vbr_enable = false;
 376         vdsc_cfg->block_pred_enable =
 377                         intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
 378                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
 379
 380         /* Gen 11 only supports integral values of bpp */
 381         vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
 382         vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 383
 384         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 385                 /*
 386                  * six 0s are appended to the lsb of each threshold value
 387                  * internally in h/w.
 388                  * Only 8 bits are allowed for programming RcBufThreshold
 389                  */
 390                 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
 391         }
 392
 393         /*
 394          * For 6bpp, RC Buffer threshold 12 and 13 need a different value
 395          * as per C Model
 396          */
 397         if (compressed_bpp == 6) {
 398                 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
 399                 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
 400         }
 401
 402         row_index = get_row_index_for_rc_params(compressed_bpp);
 403         column_index =
 404                 get_column_index_for_rc_params(vdsc_cfg->bits_per_component);
 405
 406         if (row_index < 0 || column_index < 0)
 407                 return -EINVAL;
 408
 409         vdsc_cfg->first_line_bpg_offset =
 410                 rc_params[row_index][column_index].first_line_bpg_offset;
 411         vdsc_cfg->initial_xmit_delay =
 412                 rc_params[row_index][column_index].initial_xmit_delay;
 413         vdsc_cfg->initial_offset =
 414                 rc_params[row_index][column_index].initial_offset;
 415         vdsc_cfg->flatness_min_qp =
 416                 rc_params[row_index][column_index].flatness_min_qp;
 417         vdsc_cfg->flatness_max_qp =
 418                 rc_params[row_index][column_index].flatness_max_qp;
 419         vdsc_cfg->rc_quant_incr_limit0 =
 420                 rc_params[row_index][column_index].rc_quant_incr_limit0;
 421         vdsc_cfg->rc_quant_incr_limit1 =
 422                 rc_params[row_index][column_index].rc_quant_incr_limit1;
 423
 424         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 425                 vdsc_cfg->rc_range_params[i].range_min_qp =
 426                         rc_params[row_index][column_index].rc_range_params[i].range_min_qp;
 427                 vdsc_cfg->rc_range_params[i].range_max_qp =
 428                         rc_params[row_index][column_index].rc_range_params[i].range_max_qp;
 429                 /*
 430                  * Range BPG Offset uses 2's complement and is only a 6 bits. So
 431                  * mask it to get only 6 bits.
 432                  */
 433                 vdsc_cfg->rc_range_params[i].range_bpg_offset =
 434                         rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset &
 435                         DSC_RANGE_BPG_OFFSET_MASK;
 436         }
 437
 438         /*
 439          * BitsPerComponent value determines mux_word_size:
 440          * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
 441          * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
 442          * 48 bits
 443          */
 444         if (vdsc_cfg->bits_per_component == 8 ||
 445             vdsc_cfg->bits_per_component == 10)
 446                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
 447         else if (vdsc_cfg->bits_per_component == 12)
 448                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
 449
 450         /* RC_MODEL_SIZE is a constant across all configurations */
 451         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 452         /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
 453         vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 454                 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 455
 456         return drm_dsc_compute_rc_parameters(vdsc_cfg);
 457 }
 458
 459 enum intel_display_power_domain
 460 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 461 {
 462         struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
 463         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 464
 465         /*
 466          * On ICL VDSC/joining for eDP transcoder uses a separate power well,
 467          * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain.
 468          * For any other transcoder, VDSC/joining uses the power well associated
 469          * with the pipe/transcoder in use. Hence another reference on the
 470          * transcoder power domain will suffice.
 471          *
 472          * On TGL we have the same mapping, but for transcoder A (the special
 473          * TRANSCODER_EDP is gone).
 474          */
 475         if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
 476                 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 477         else if (cpu_transcoder == TRANSCODER_EDP)
 478                 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 479         else
 480                 return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 481 }
 482
 483 static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 484                                                 const struct intel_crtc_state *crtc_state)
 485 {
 486         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 487         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 488         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
 489         enum pipe pipe = crtc->pipe;
 490         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 491         u32 pps_val = 0;
 492         u32 rc_buf_thresh_dword[4];
 493         u32 rc_range_params_dword[8];
 494         u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
 495         int i = 0;
 496
 497         /* Populate PICTURE_PARAMETER_SET_0 registers */
 498         pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
 499                 DSC_VER_MIN_SHIFT |
 500                 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 501                 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
 502         if (vdsc_cfg->block_pred_enable)
 503                 pps_val |= DSC_BLOCK_PREDICTION;
 504         if (vdsc_cfg->convert_rgb)
 505                 pps_val |= DSC_COLOR_SPACE_CONVERSION;
 506         if (vdsc_cfg->simple_422)
 507                 pps_val |= DSC_422_ENABLE;
 508         if (vdsc_cfg->vbr_enable)
 509                 pps_val |= DSC_VBR_ENABLE;
 510         DRM_INFO("PPS0 = 0x%08x\n", pps_val);
 511         if (cpu_transcoder == TRANSCODER_EDP) {
 512                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
 513                 /*
 514                  * If 2 VDSC instances are needed, configure PPS for second
 515                  * VDSC
 516                  */
 517                 if (crtc_state->dsc_params.dsc_split)
 518                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
 519         } else {
 520                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
 521                 if (crtc_state->dsc_params.dsc_split)
 522                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
 523                                    pps_val);
 524         }
 525
 526         /* Populate PICTURE_PARAMETER_SET_1 registers */
 527         pps_val = 0;
 528         pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
 529         DRM_INFO("PPS1 = 0x%08x\n", pps_val);
 530         if (cpu_transcoder == TRANSCODER_EDP) {
 531                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
 532                 /*
 533                  * If 2 VDSC instances are needed, configure PPS for second
 534                  * VDSC
 535                  */
 536                 if (crtc_state->dsc_params.dsc_split)
 537                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
 538         } else {
 539                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
 540                 if (crtc_state->dsc_params.dsc_split)
 541                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
 542                                    pps_val);
 543         }
 544
 545         /* Populate PICTURE_PARAMETER_SET_2 registers */
 546         pps_val = 0;
 547         pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 548                 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 549         DRM_INFO("PPS2 = 0x%08x\n", pps_val);
 550         if (cpu_transcoder == TRANSCODER_EDP) {
 551                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
 552                 /*
 553                  * If 2 VDSC instances are needed, configure PPS for second
 554                  * VDSC
 555                  */
 556                 if (crtc_state->dsc_params.dsc_split)
 557                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
 558         } else {
 559                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
 560                 if (crtc_state->dsc_params.dsc_split)
 561                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
 562                                    pps_val);
 563         }
 564
 565         /* Populate PICTURE_PARAMETER_SET_3 registers */
 566         pps_val = 0;
 567         pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 568                 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 569         DRM_INFO("PPS3 = 0x%08x\n", pps_val);
 570         if (cpu_transcoder == TRANSCODER_EDP) {
 571                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
 572                 /*
 573                  * If 2 VDSC instances are needed, configure PPS for second
 574                  * VDSC
 575                  */
 576                 if (crtc_state->dsc_params.dsc_split)
 577                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
 578         } else {
 579                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
 580                 if (crtc_state->dsc_params.dsc_split)
 581                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
 582                                    pps_val);
 583         }
 584
 585         /* Populate PICTURE_PARAMETER_SET_4 registers */
 586         pps_val = 0;
 587         pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 588                 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 589         DRM_INFO("PPS4 = 0x%08x\n", pps_val);
 590         if (cpu_transcoder == TRANSCODER_EDP) {
 591                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
 592                 /*
 593                  * If 2 VDSC instances are needed, configure PPS for second
 594                  * VDSC
 595                  */
 596                 if (crtc_state->dsc_params.dsc_split)
 597                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
 598         } else {
 599                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
 600                 if (crtc_state->dsc_params.dsc_split)
 601                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
 602                                    pps_val);
 603         }
 604
 605         /* Populate PICTURE_PARAMETER_SET_5 registers */
 606         pps_val = 0;
 607         pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 608                 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 609         DRM_INFO("PPS5 = 0x%08x\n", pps_val);
 610         if (cpu_transcoder == TRANSCODER_EDP) {
 611                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
 612                 /*
 613                  * If 2 VDSC instances are needed, configure PPS for second
 614                  * VDSC
 615                  */
 616                 if (crtc_state->dsc_params.dsc_split)
 617                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
 618         } else {
 619                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
 620                 if (crtc_state->dsc_params.dsc_split)
 621                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
 622                                    pps_val);
 623         }
 624
 625         /* Populate PICTURE_PARAMETER_SET_6 registers */
 626         pps_val = 0;
 627         pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
 628                 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
 629                 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 630                 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 631         DRM_INFO("PPS6 = 0x%08x\n", pps_val);
 632         if (cpu_transcoder == TRANSCODER_EDP) {
 633                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
 634                 /*
 635                  * If 2 VDSC instances are needed, configure PPS for second
 636                  * VDSC
 637                  */
 638                 if (crtc_state->dsc_params.dsc_split)
 639                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
 640         } else {
 641                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
 642                 if (crtc_state->dsc_params.dsc_split)
 643                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
 644                                    pps_val);
 645         }
 646
 647         /* Populate PICTURE_PARAMETER_SET_7 registers */
 648         pps_val = 0;
 649         pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 650                 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 651         DRM_INFO("PPS7 = 0x%08x\n", pps_val);
 652         if (cpu_transcoder == TRANSCODER_EDP) {
 653                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
 654                 /*
 655                  * If 2 VDSC instances are needed, configure PPS for second
 656                  * VDSC
 657                  */
 658                 if (crtc_state->dsc_params.dsc_split)
 659                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
 660         } else {
 661                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
 662                 if (crtc_state->dsc_params.dsc_split)
 663                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
 664                                    pps_val);
 665         }
 666
 667         /* Populate PICTURE_PARAMETER_SET_8 registers */
 668         pps_val = 0;
 669         pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 670                 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 671         DRM_INFO("PPS8 = 0x%08x\n", pps_val);
 672         if (cpu_transcoder == TRANSCODER_EDP) {
 673                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
 674                 /*
 675                  * If 2 VDSC instances are needed, configure PPS for second
 676                  * VDSC
 677                  */
 678                 if (crtc_state->dsc_params.dsc_split)
 679                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
 680         } else {
 681                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
 682                 if (crtc_state->dsc_params.dsc_split)
 683                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
 684                                    pps_val);
 685         }
 686
 687         /* Populate PICTURE_PARAMETER_SET_9 registers */
 688         pps_val = 0;
 689         pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
 690                 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 691         DRM_INFO("PPS9 = 0x%08x\n", pps_val);
 692         if (cpu_transcoder == TRANSCODER_EDP) {
 693                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
 694                 /*
 695                  * If 2 VDSC instances are needed, configure PPS for second
 696                  * VDSC
 697                  */
 698                 if (crtc_state->dsc_params.dsc_split)
 699                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
 700         } else {
 701                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
 702                 if (crtc_state->dsc_params.dsc_split)
 703                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
 704                                    pps_val);
 705         }
 706
 707         /* Populate PICTURE_PARAMETER_SET_10 registers */
 708         pps_val = 0;
 709         pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
 710                 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
 711                 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 712                 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 713         DRM_INFO("PPS10 = 0x%08x\n", pps_val);
 714         if (cpu_transcoder == TRANSCODER_EDP) {
 715                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
 716                 /*
 717                  * If 2 VDSC instances are needed, configure PPS for second
 718                  * VDSC
 719                  */
 720                 if (crtc_state->dsc_params.dsc_split)
 721                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
 722         } else {
 723                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
 724                 if (crtc_state->dsc_params.dsc_split)
 725                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
 726                                    pps_val);
 727         }
 728
 729         /* Populate Picture parameter set 16 */
 730         pps_val = 0;
 731         pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
 732                 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
 733                                    vdsc_cfg->slice_width) |
 734                 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
 735                                         vdsc_cfg->slice_height);
 736         DRM_INFO("PPS16 = 0x%08x\n", pps_val);
 737         if (cpu_transcoder == TRANSCODER_EDP) {
 738                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
 739                 /*
 740                  * If 2 VDSC instances are needed, configure PPS for second
 741                  * VDSC
 742                  */
 743                 if (crtc_state->dsc_params.dsc_split)
 744                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
 745         } else {
 746                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
 747                 if (crtc_state->dsc_params.dsc_split)
 748                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
 749                                    pps_val);
 750         }
 751
 752         /* Populate the RC_BUF_THRESH registers */
 753         memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 754         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 755                 rc_buf_thresh_dword[i / 4] |=
 756                         (u32)(vdsc_cfg->rc_buf_thresh[i] <<
 757                               BITS_PER_BYTE * (i % 4));
 758                 DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
 759                          rc_buf_thresh_dword[i / 4]);
 760         }
 761         if (cpu_transcoder == TRANSCODER_EDP) {
 762                 I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
 763                 I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
 764                 I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
 765                 I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
 766                 if (crtc_state->dsc_params.dsc_split) {
 767                         I915_WRITE(DSCC_RC_BUF_THRESH_0,
 768                                    rc_buf_thresh_dword[0]);
 769                         I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
 770                                    rc_buf_thresh_dword[1]);
 771                         I915_WRITE(DSCC_RC_BUF_THRESH_1,
 772                                    rc_buf_thresh_dword[2]);
 773                         I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
 774                                    rc_buf_thresh_dword[3]);
 775                 }
 776         } else {
 777                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
 778                            rc_buf_thresh_dword[0]);
 779                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
 780                            rc_buf_thresh_dword[1]);
 781                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
 782                            rc_buf_thresh_dword[2]);
 783                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
 784                            rc_buf_thresh_dword[3]);
 785                 if (crtc_state->dsc_params.dsc_split) {
 786                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
 787                                    rc_buf_thresh_dword[0]);
 788                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
 789                                    rc_buf_thresh_dword[1]);
 790                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
 791                                    rc_buf_thresh_dword[2]);
 792                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
 793                                    rc_buf_thresh_dword[3]);
 794                 }
 795         }
 796
 797         /* Populate the RC_RANGE_PARAMETERS registers */
 798         memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
 799         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 800                 rc_range_params_dword[i / 2] |=
 801                         (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
 802                                 RC_BPG_OFFSET_SHIFT) |
 803                                (vdsc_cfg->rc_range_params[i].range_max_qp <<
 804                                 RC_MAX_QP_SHIFT) |
 805                                (vdsc_cfg->rc_range_params[i].range_min_qp <<
 806                                 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
 807                 DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
 808                          rc_range_params_dword[i / 2]);
 809         }
 810         if (cpu_transcoder == TRANSCODER_EDP) {
 811                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
 812                            rc_range_params_dword[0]);
 813                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
 814                            rc_range_params_dword[1]);
 815                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
 816                            rc_range_params_dword[2]);
 817                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
 818                            rc_range_params_dword[3]);
 819                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
 820                            rc_range_params_dword[4]);
 821                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
 822                            rc_range_params_dword[5]);
 823                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
 824                            rc_range_params_dword[6]);
 825                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
 826                            rc_range_params_dword[7]);
 827                 if (crtc_state->dsc_params.dsc_split) {
 828                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
 829                                    rc_range_params_dword[0]);
 830                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
 831                                    rc_range_params_dword[1]);
 832                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
 833                                    rc_range_params_dword[2]);
 834                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
 835                                    rc_range_params_dword[3]);
 836                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
 837                                    rc_range_params_dword[4]);
 838                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
 839                                    rc_range_params_dword[5]);
 840                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
 841                                    rc_range_params_dword[6]);
 842                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
 843                                    rc_range_params_dword[7]);
 844                 }
 845         } else {
 846                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
 847                            rc_range_params_dword[0]);
 848                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
 849                            rc_range_params_dword[1]);
 850                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
 851                            rc_range_params_dword[2]);
 852                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
 853                            rc_range_params_dword[3]);
 854                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
 855                            rc_range_params_dword[4]);
 856                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
 857                            rc_range_params_dword[5]);
 858                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
 859                            rc_range_params_dword[6]);
 860                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
 861                            rc_range_params_dword[7]);
 862                 if (crtc_state->dsc_params.dsc_split) {
 863                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
 864                                    rc_range_params_dword[0]);
 865                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
 866                                    rc_range_params_dword[1]);
 867                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
 868                                    rc_range_params_dword[2]);
 869                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
 870                                    rc_range_params_dword[3]);
 871                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
 872                                    rc_range_params_dword[4]);
 873                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
 874                                    rc_range_params_dword[5]);
 875                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
 876                                    rc_range_params_dword[6]);
 877                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
 878                                    rc_range_params_dword[7]);
 879                 }
 880         }
 881 }
 882
 883 static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
 884                                        const struct intel_crtc_state *crtc_state)
 885 {
 886         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 887         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 888         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
 889         struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
 890
 891         /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
 892         drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
 893
 894         /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
 895         drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
 896
 897         intel_dig_port->write_infoframe(encoder, crtc_state,
 898                                         DP_SDP_PPS, &dp_dsc_pps_sdp,
 899                                         sizeof(dp_dsc_pps_sdp));
 900 }
 901
 902 void intel_dsc_enable(struct intel_encoder *encoder,
 903                       const struct intel_crtc_state *crtc_state)
 904 {
 905         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 906         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 907         enum pipe pipe = crtc->pipe;
 908         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 909         u32 dss_ctl1_val = 0;
 910         u32 dss_ctl2_val = 0;
 911
 912         if (!crtc_state->dsc_params.compression_enable)
 913                 return;
 914
 915         /* Enable Power wells for VDSC/joining */
 916         intel_display_power_get(dev_priv,
 917                                 intel_dsc_power_domain(crtc_state));
 918
 919         intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
 920
 921         intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
 922
 923         if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
 924                 dss_ctl1_reg = DSS_CTL1;
 925                 dss_ctl2_reg = DSS_CTL2;
 926         } else {
 927                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
 928                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
 929         }
 930         dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
 931         if (crtc_state->dsc_params.dsc_split) {
 932                 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
 933                 dss_ctl1_val |= JOINER_ENABLE;
 934         }
 935         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
 936         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
 937 }
 938
 939 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 940 {
 941         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
 942         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 943         enum pipe pipe = crtc->pipe;
 944         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 945         u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
 946
 947         if (!old_crtc_state->dsc_params.compression_enable)
 948                 return;
 949
 950         if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
 951                 dss_ctl1_reg = DSS_CTL1;
 952                 dss_ctl2_reg = DSS_CTL2;
 953         } else {
 954                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
 955                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
 956         }
 957         dss_ctl1_val = I915_READ(dss_ctl1_reg);
 958         if (dss_ctl1_val & JOINER_ENABLE)
 959                 dss_ctl1_val &= ~JOINER_ENABLE;
 960         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
 961
 962         dss_ctl2_val = I915_READ(dss_ctl2_reg);
 963         if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
 964             dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
 965                 dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
 966                                   RIGHT_BRANCH_VDSC_ENABLE);
 967         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
 968
 969         /* Disable Power wells for VDSC/joining */
 970         intel_display_power_put_unchecked(dev_priv,
 971                                           intel_dsc_power_domain(old_crtc_state));
 972 }