2 * SPDX-License-Identifier: MIT
4 * Copyright © 2019 Intel Corporation
8 #include "i915_params.h"
9 #include "intel_engine_pm.h"
11 #include "intel_gt_pm.h"
13 #include "intel_wakeref.h"
15 static void pm_notify(struct drm_i915_private
*i915
, int state
)
17 blocking_notifier_call_chain(&i915
->gt
.pm_notifications
, state
, i915
);
20 static int __gt_unpark(struct intel_wakeref
*wf
)
22 struct intel_gt
*gt
= container_of(wf
, typeof(*gt
), wakeref
);
23 struct drm_i915_private
*i915
= gt
->i915
;
28 * It seems that the DMC likes to transition between the DC states a lot
29 * when there are no connected displays (no active power domains) during
32 * This activity has negative impact on the performance of the chip with
33 * huge latencies observed in the interrupt handler and elsewhere.
35 * Work around it by grabbing a GT IRQ power domain whilst there is any
36 * GT activity, preventing any DC state transitions.
38 gt
->awake
= intel_display_power_get(i915
, POWER_DOMAIN_GT_IRQ
);
39 GEM_BUG_ON(!gt
->awake
);
41 intel_enable_gt_powersave(i915
);
43 i915_update_gfx_val(i915
);
44 if (INTEL_GEN(i915
) >= 6)
47 i915_pmu_gt_unparked(i915
);
49 intel_gt_queue_hangcheck(gt
);
51 pm_notify(i915
, INTEL_GT_UNPARK
);
56 static int __gt_park(struct intel_wakeref
*wf
)
58 struct drm_i915_private
*i915
=
59 container_of(wf
, typeof(*i915
), gt
.wakeref
);
60 intel_wakeref_t wakeref
= fetch_and_zero(&i915
->gt
.awake
);
64 pm_notify(i915
, INTEL_GT_PARK
);
66 i915_pmu_gt_parked(i915
);
67 if (INTEL_GEN(i915
) >= 6)
70 /* Everything switched off, flush any residual interrupt just in case */
71 intel_synchronize_irq(i915
);
74 intel_display_power_put(i915
, POWER_DOMAIN_GT_IRQ
, wakeref
);
79 static const struct intel_wakeref_ops wf_ops
= {
82 .flags
= INTEL_WAKEREF_PUT_ASYNC
,
85 void intel_gt_pm_init_early(struct intel_gt
*gt
)
87 intel_wakeref_init(>
->wakeref
, >
->i915
->runtime_pm
, &wf_ops
);
89 BLOCKING_INIT_NOTIFIER_HEAD(>
->pm_notifications
);
92 static bool reset_engines(struct intel_gt
*gt
)
94 if (INTEL_INFO(gt
->i915
)->gpu_reset_clobbers_display
)
97 return __intel_gt_reset(gt
, ALL_ENGINES
) == 0;
101 * intel_gt_sanitize: called after the GPU has lost power
102 * @gt: the i915 GT container
103 * @force: ignore a failed reset and sanitize engine state anyway
105 * Anytime we reset the GPU, either with an explicit GPU reset or through a
106 * PCI power cycle, the GPU loses state and we must reset our state tracking
107 * to match. Note that calling intel_gt_sanitize() if the GPU has not
108 * been reset results in much confusion!
110 void intel_gt_sanitize(struct intel_gt
*gt
, bool force
)
112 struct intel_engine_cs
*engine
;
113 enum intel_engine_id id
;
117 intel_uc_sanitize(>
->uc
);
119 if (!reset_engines(gt
) && !force
)
122 for_each_engine(engine
, gt
->i915
, id
)
123 __intel_engine_reset(engine
, false);
126 int intel_gt_resume(struct intel_gt
*gt
)
128 struct intel_engine_cs
*engine
;
129 enum intel_engine_id id
;
133 * After resume, we may need to poke into the pinned kernel
134 * contexts to paper over any damage caused by the sudden suspend.
135 * Only the kernel contexts should remain pinned over suspend,
136 * allowing us to fixup the user contexts on their first pin.
139 for_each_engine(engine
, gt
->i915
, id
) {
140 struct intel_context
*ce
;
142 intel_engine_pm_get(engine
);
144 ce
= engine
->kernel_context
;
148 engine
->serial
++; /* kernel context lost */
149 err
= engine
->resume(engine
);
151 intel_engine_pm_put(engine
);
153 dev_err(gt
->i915
->drm
.dev
,
154 "Failed to restart %s (%d)\n",
164 void intel_gt_runtime_suspend(struct intel_gt
*gt
)
166 intel_uc_runtime_suspend(>
->uc
);
169 int intel_gt_runtime_resume(struct intel_gt
*gt
)
171 intel_gt_init_swizzling(gt
);
173 return intel_uc_runtime_resume(>
->uc
);