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ASoC: rockchip: add bindings for rk3368 i2s
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / gvt / cmd_parser.c
1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Kevin Tian <kevin.tian@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Ping Gao <ping.a.gao@intel.com>
31 * Tina Zhang <tina.zhang@intel.com>
32 * Yulei Zhang <yulei.zhang@intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
34 *
35 */
36
37 #include <linux/slab.h>
38 #include "i915_drv.h"
39 #include "gvt.h"
40 #include "i915_pvinfo.h"
41 #include "trace.h"
42
43 #define INVALID_OP (~0U)
44
45 #define OP_LEN_MI 9
46 #define OP_LEN_2D 10
47 #define OP_LEN_3D_MEDIA 16
48 #define OP_LEN_MFX_VC 16
49 #define OP_LEN_VEBOX 16
50
51 #define CMD_TYPE(cmd) (((cmd) >> 29) & 7)
52
53 struct sub_op_bits {
54 int hi;
55 int low;
56 };
57 struct decode_info {
58 char *name;
59 int op_len;
60 int nr_sub_op;
61 struct sub_op_bits *sub_op;
62 };
63
64 #define MAX_CMD_BUDGET 0x7fffffff
65 #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15)
66 #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9)
67 #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1)
68
69 #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20)
70 #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10)
71 #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2)
72
73 /* Render Command Map */
74
75 /* MI_* command Opcode (28:23) */
76 #define OP_MI_NOOP 0x0
77 #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */
78 #define OP_MI_USER_INTERRUPT 0x2
79 #define OP_MI_WAIT_FOR_EVENT 0x3
80 #define OP_MI_FLUSH 0x4
81 #define OP_MI_ARB_CHECK 0x5
82 #define OP_MI_RS_CONTROL 0x6 /* HSW+ */
83 #define OP_MI_REPORT_HEAD 0x7
84 #define OP_MI_ARB_ON_OFF 0x8
85 #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */
86 #define OP_MI_BATCH_BUFFER_END 0xA
87 #define OP_MI_SUSPEND_FLUSH 0xB
88 #define OP_MI_PREDICATE 0xC /* IVB+ */
89 #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */
90 #define OP_MI_SET_APPID 0xE /* IVB+ */
91 #define OP_MI_RS_CONTEXT 0xF /* HSW+ */
92 #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */
93 #define OP_MI_DISPLAY_FLIP 0x14
94 #define OP_MI_SEMAPHORE_MBOX 0x16
95 #define OP_MI_SET_CONTEXT 0x18
96 #define OP_MI_MATH 0x1A
97 #define OP_MI_URB_CLEAR 0x19
98 #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */
99 #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */
100
101 #define OP_MI_STORE_DATA_IMM 0x20
102 #define OP_MI_STORE_DATA_INDEX 0x21
103 #define OP_MI_LOAD_REGISTER_IMM 0x22
104 #define OP_MI_UPDATE_GTT 0x23
105 #define OP_MI_STORE_REGISTER_MEM 0x24
106 #define OP_MI_FLUSH_DW 0x26
107 #define OP_MI_CLFLUSH 0x27
108 #define OP_MI_REPORT_PERF_COUNT 0x28
109 #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */
110 #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */
111 #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */
112 #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */
113 #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */
114 #define OP_MI_2E 0x2E /* BDW+ */
115 #define OP_MI_2F 0x2F /* BDW+ */
116 #define OP_MI_BATCH_BUFFER_START 0x31
117
118 /* Bit definition for dword 0 */
119 #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8)
120
121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36
122
123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
125 #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U)
126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U)
127
128 /* 2D command: Opcode (28:22) */
129 #define OP_2D(x) ((2<<7) | x)
130
131 #define OP_XY_SETUP_BLT OP_2D(0x1)
132 #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3)
133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11)
134 #define OP_XY_PIXEL_BLT OP_2D(0x24)
135 #define OP_XY_SCANLINES_BLT OP_2D(0x25)
136 #define OP_XY_TEXT_BLT OP_2D(0x26)
137 #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31)
138 #define OP_XY_COLOR_BLT OP_2D(0x50)
139 #define OP_XY_PAT_BLT OP_2D(0x51)
140 #define OP_XY_MONO_PAT_BLT OP_2D(0x52)
141 #define OP_XY_SRC_COPY_BLT OP_2D(0x53)
142 #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54)
143 #define OP_XY_FULL_BLT OP_2D(0x55)
144 #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56)
145 #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57)
146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58)
147 #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59)
148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71)
149 #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72)
150 #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73)
151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74)
152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75)
153 #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76)
154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77)
155
156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
158 ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
159
160 #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03)
161
162 #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01)
163 #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02)
164 #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04)
165
166 #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B)
167
168 #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04)
169
170 #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0)
171 #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1)
172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2)
173 #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3)
174 #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4)
175
176 #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0)
177 #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2)
178 #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3)
179 #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5)
180
181 #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
182 #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
183 #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
184 #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
185 #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08)
186 #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09)
187 #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A)
188 #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B)
189 #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */
190 #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E)
191 #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F)
192 #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10)
193 #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11)
194 #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12)
195 #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13)
196 #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14)
197 #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15)
198 #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16)
199 #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17)
200 #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18)
201 #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
202 #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
203 #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
204 #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
205 #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
206 #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
207 #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
208 #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
209 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
211 #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
212 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
213 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
218 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
223 #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
224 #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
225 #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
226 #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
227 #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
228 #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
229 #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
230 #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
232 #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
233 #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
234 #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
235 #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
238 #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
239 #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
240 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
242 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
243 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
244 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
245 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
247
248 #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
249 #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
250 #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
251 #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
252 #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
253 #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
254 #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
255 #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
256 #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
257 #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
258 #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
259
260 #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
261 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02)
262 #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04)
263 #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05)
264 #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06)
265 #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07)
266 #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08)
267 #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A)
268 #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B)
269 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C)
270 #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D)
271 #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E)
272 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F)
273 #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10)
274 #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11)
275 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
280 #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17)
281 #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18)
282 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
283 #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
284 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
285 #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C)
286 #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00)
287 #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00)
288
289 /* VCCP Command Parser */
290
291 /*
292 * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
293 * git://anongit.freedesktop.org/vaapi/intel-driver
294 * src/i965_defines.h
295 *
296 */
297
298 #define OP_MFX(pipeline, op, sub_opa, sub_opb) \
299 (3 << 13 | \
300 (pipeline) << 11 | \
301 (op) << 8 | \
302 (sub_opa) << 5 | \
303 (sub_opb))
304
305 #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */
306 #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */
307 #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */
308 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */
309 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */
310 #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */
311 #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */
312 #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */
313 #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */
314 #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */
315 #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */
316
317 #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */
318
319 #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */
320 #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */
321 #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */
322 #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */
323 #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */
324 #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */
325 #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */
326 #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */
327 #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */
328 #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */
329 #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */
330 #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */
331
332 #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */
333 #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */
334 #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */
335 #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */
336 #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */
337
338 #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */
339 #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */
340 #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */
341 #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */
342 #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */
343
344 #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */
345 #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */
346 #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */
347
348 #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0)
349 #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2)
350 #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8)
351
352 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
353 (3 << 13 | \
354 (pipeline) << 11 | \
355 (op) << 8 | \
356 (sub_opa) << 5 | \
357 (sub_opb))
358
359 #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0)
360 #define OP_VEB_STATE OP_VEB(2, 4, 0, 2)
361 #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3)
362
363 struct parser_exec_state;
364
365 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
366
367 #define GVT_CMD_HASH_BITS 7
368
369 /* which DWords need address fix */
370 #define ADDR_FIX_1(x1) (1 << (x1))
371 #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
372 #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
373 #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
374 #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
375
376 struct cmd_info {
377 char *name;
378 u32 opcode;
379
380 #define F_LEN_MASK (1U<<0)
381 #define F_LEN_CONST 1U
382 #define F_LEN_VAR 0U
383
384 /*
385 * command has its own ip advance logic
386 * e.g. MI_BATCH_START, MI_BATCH_END
387 */
388 #define F_IP_ADVANCE_CUSTOM (1<<1)
389
390 #define F_POST_HANDLE (1<<2)
391 u32 flag;
392
393 #define R_RCS (1 << RCS)
394 #define R_VCS1 (1 << VCS)
395 #define R_VCS2 (1 << VCS2)
396 #define R_VCS (R_VCS1 | R_VCS2)
397 #define R_BCS (1 << BCS)
398 #define R_VECS (1 << VECS)
399 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
400 /* rings that support this cmd: BLT/RCS/VCS/VECS */
401 uint16_t rings;
402
403 /* devices that support this cmd: SNB/IVB/HSW/... */
404 uint16_t devices;
405
406 /* which DWords are address that need fix up.
407 * bit 0 means a 32-bit non address operand in command
408 * bit 1 means address operand, which could be 32-bit
409 * or 64-bit depending on different architectures.(
410 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
411 * No matter the address length, each address only takes
412 * one bit in the bitmap.
413 */
414 uint16_t addr_bitmap;
415
416 /* flag == F_LEN_CONST : command length
417 * flag == F_LEN_VAR : length bias bits
418 * Note: length is in DWord
419 */
420 uint8_t len;
421
422 parser_cmd_handler handler;
423 };
424
425 struct cmd_entry {
426 struct hlist_node hlist;
427 struct cmd_info *info;
428 };
429
430 enum {
431 RING_BUFFER_INSTRUCTION,
432 BATCH_BUFFER_INSTRUCTION,
433 BATCH_BUFFER_2ND_LEVEL,
434 };
435
436 enum {
437 GTT_BUFFER,
438 PPGTT_BUFFER
439 };
440
441 struct parser_exec_state {
442 struct intel_vgpu *vgpu;
443 int ring_id;
444
445 int buf_type;
446
447 /* batch buffer address type */
448 int buf_addr_type;
449
450 /* graphics memory address of ring buffer start */
451 unsigned long ring_start;
452 unsigned long ring_size;
453 unsigned long ring_head;
454 unsigned long ring_tail;
455
456 /* instruction graphics memory address */
457 unsigned long ip_gma;
458
459 /* mapped va of the instr_gma */
460 void *ip_va;
461 void *rb_va;
462
463 void *ret_bb_va;
464 /* next instruction when return from batch buffer to ring buffer */
465 unsigned long ret_ip_gma_ring;
466
467 /* next instruction when return from 2nd batch buffer to batch buffer */
468 unsigned long ret_ip_gma_bb;
469
470 /* batch buffer address type (GTT or PPGTT)
471 * used when ret from 2nd level batch buffer
472 */
473 int saved_buf_addr_type;
474
475 struct cmd_info *info;
476
477 struct intel_vgpu_workload *workload;
478 };
479
480 #define gmadr_dw_number(s) \
481 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
482
483 static unsigned long bypass_scan_mask = 0;
484
485 /* ring ALL, type = 0 */
486 static struct sub_op_bits sub_op_mi[] = {
487 {31, 29},
488 {28, 23},
489 };
490
491 static struct decode_info decode_info_mi = {
492 "MI",
493 OP_LEN_MI,
494 ARRAY_SIZE(sub_op_mi),
495 sub_op_mi,
496 };
497
498 /* ring RCS, command type 2 */
499 static struct sub_op_bits sub_op_2d[] = {
500 {31, 29},
501 {28, 22},
502 };
503
504 static struct decode_info decode_info_2d = {
505 "2D",
506 OP_LEN_2D,
507 ARRAY_SIZE(sub_op_2d),
508 sub_op_2d,
509 };
510
511 /* ring RCS, command type 3 */
512 static struct sub_op_bits sub_op_3d_media[] = {
513 {31, 29},
514 {28, 27},
515 {26, 24},
516 {23, 16},
517 };
518
519 static struct decode_info decode_info_3d_media = {
520 "3D_Media",
521 OP_LEN_3D_MEDIA,
522 ARRAY_SIZE(sub_op_3d_media),
523 sub_op_3d_media,
524 };
525
526 /* ring VCS, command type 3 */
527 static struct sub_op_bits sub_op_mfx_vc[] = {
528 {31, 29},
529 {28, 27},
530 {26, 24},
531 {23, 21},
532 {20, 16},
533 };
534
535 static struct decode_info decode_info_mfx_vc = {
536 "MFX_VC",
537 OP_LEN_MFX_VC,
538 ARRAY_SIZE(sub_op_mfx_vc),
539 sub_op_mfx_vc,
540 };
541
542 /* ring VECS, command type 3 */
543 static struct sub_op_bits sub_op_vebox[] = {
544 {31, 29},
545 {28, 27},
546 {26, 24},
547 {23, 21},
548 {20, 16},
549 };
550
551 static struct decode_info decode_info_vebox = {
552 "VEBOX",
553 OP_LEN_VEBOX,
554 ARRAY_SIZE(sub_op_vebox),
555 sub_op_vebox,
556 };
557
558 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
559 [RCS] = {
560 &decode_info_mi,
561 NULL,
562 NULL,
563 &decode_info_3d_media,
564 NULL,
565 NULL,
566 NULL,
567 NULL,
568 },
569
570 [VCS] = {
571 &decode_info_mi,
572 NULL,
573 NULL,
574 &decode_info_mfx_vc,
575 NULL,
576 NULL,
577 NULL,
578 NULL,
579 },
580
581 [BCS] = {
582 &decode_info_mi,
583 NULL,
584 &decode_info_2d,
585 NULL,
586 NULL,
587 NULL,
588 NULL,
589 NULL,
590 },
591
592 [VECS] = {
593 &decode_info_mi,
594 NULL,
595 NULL,
596 &decode_info_vebox,
597 NULL,
598 NULL,
599 NULL,
600 NULL,
601 },
602
603 [VCS2] = {
604 &decode_info_mi,
605 NULL,
606 NULL,
607 &decode_info_mfx_vc,
608 NULL,
609 NULL,
610 NULL,
611 NULL,
612 },
613 };
614
615 static inline u32 get_opcode(u32 cmd, int ring_id)
616 {
617 struct decode_info *d_info;
618
619 if (ring_id >= I915_NUM_ENGINES)
620 return INVALID_OP;
621
622 d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
623 if (d_info == NULL)
624 return INVALID_OP;
625
626 return cmd >> (32 - d_info->op_len);
627 }
628
629 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
630 unsigned int opcode, int ring_id)
631 {
632 struct cmd_entry *e;
633
634 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
635 if ((opcode == e->info->opcode) &&
636 (e->info->rings & (1 << ring_id)))
637 return e->info;
638 }
639 return NULL;
640 }
641
642 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
643 u32 cmd, int ring_id)
644 {
645 u32 opcode;
646
647 opcode = get_opcode(cmd, ring_id);
648 if (opcode == INVALID_OP)
649 return NULL;
650
651 return find_cmd_entry(gvt, opcode, ring_id);
652 }
653
654 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
655 {
656 return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
657 }
658
659 static inline void print_opcode(u32 cmd, int ring_id)
660 {
661 struct decode_info *d_info;
662 int i;
663
664 if (ring_id >= I915_NUM_ENGINES)
665 return;
666
667 d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
668 if (d_info == NULL)
669 return;
670
671 gvt_err("opcode=0x%x %s sub_ops:",
672 cmd >> (32 - d_info->op_len), d_info->name);
673
674 for (i = 0; i < d_info->nr_sub_op; i++)
675 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
676 d_info->sub_op[i].low));
677
678 pr_err("\n");
679 }
680
681 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
682 {
683 return s->ip_va + (index << 2);
684 }
685
686 static inline u32 cmd_val(struct parser_exec_state *s, int index)
687 {
688 return *cmd_ptr(s, index);
689 }
690
691 static void parser_exec_state_dump(struct parser_exec_state *s)
692 {
693 int cnt = 0;
694 int i;
695
696 gvt_err(" vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
697 " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
698 s->ring_id, s->ring_start, s->ring_start + s->ring_size,
699 s->ring_head, s->ring_tail);
700
701 gvt_err(" %s %s ip_gma(%08lx) ",
702 s->buf_type == RING_BUFFER_INSTRUCTION ?
703 "RING_BUFFER" : "BATCH_BUFFER",
704 s->buf_addr_type == GTT_BUFFER ?
705 "GTT" : "PPGTT", s->ip_gma);
706
707 if (s->ip_va == NULL) {
708 gvt_err(" ip_va(NULL)");
709 return;
710 }
711
712 gvt_err(" ip_va=%p: %08x %08x %08x %08x\n",
713 s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
714 cmd_val(s, 2), cmd_val(s, 3));
715
716 print_opcode(cmd_val(s, 0), s->ring_id);
717
718 /* print the whole page to trace */
719 pr_err(" ip_va=%p: %08x %08x %08x %08x\n",
720 s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
721 cmd_val(s, 2), cmd_val(s, 3));
722
723 s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
724
725 while (cnt < 1024) {
726 pr_err("ip_va=%p: ", s->ip_va);
727 for (i = 0; i < 8; i++)
728 pr_err("%08x ", cmd_val(s, i));
729 pr_err("\n");
730
731 s->ip_va += 8 * sizeof(u32);
732 cnt += 8;
733 }
734 }
735
736 static inline void update_ip_va(struct parser_exec_state *s)
737 {
738 unsigned long len = 0;
739
740 if (WARN_ON(s->ring_head == s->ring_tail))
741 return;
742
743 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
744 unsigned long ring_top = s->ring_start + s->ring_size;
745
746 if (s->ring_head > s->ring_tail) {
747 if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
748 len = (s->ip_gma - s->ring_head);
749 else if (s->ip_gma >= s->ring_start &&
750 s->ip_gma <= s->ring_tail)
751 len = (ring_top - s->ring_head) +
752 (s->ip_gma - s->ring_start);
753 } else
754 len = (s->ip_gma - s->ring_head);
755
756 s->ip_va = s->rb_va + len;
757 } else {/* shadow batch buffer */
758 s->ip_va = s->ret_bb_va;
759 }
760 }
761
762 static inline int ip_gma_set(struct parser_exec_state *s,
763 unsigned long ip_gma)
764 {
765 WARN_ON(!IS_ALIGNED(ip_gma, 4));
766
767 s->ip_gma = ip_gma;
768 update_ip_va(s);
769 return 0;
770 }
771
772 static inline int ip_gma_advance(struct parser_exec_state *s,
773 unsigned int dw_len)
774 {
775 s->ip_gma += (dw_len << 2);
776
777 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
778 if (s->ip_gma >= s->ring_start + s->ring_size)
779 s->ip_gma -= s->ring_size;
780 update_ip_va(s);
781 } else {
782 s->ip_va += (dw_len << 2);
783 }
784
785 return 0;
786 }
787
788 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
789 {
790 if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
791 return info->len;
792 else
793 return (cmd & ((1U << info->len) - 1)) + 2;
794 return 0;
795 }
796
797 static inline int cmd_length(struct parser_exec_state *s)
798 {
799 return get_cmd_length(s->info, cmd_val(s, 0));
800 }
801
802 /* do not remove this, some platform may need clflush here */
803 #define patch_value(s, addr, val) do { \
804 *addr = val; \
805 } while (0)
806
807 static bool is_shadowed_mmio(unsigned int offset)
808 {
809 bool ret = false;
810
811 if ((offset == 0x2168) || /*BB current head register UDW */
812 (offset == 0x2140) || /*BB current header register */
813 (offset == 0x211c) || /*second BB header register UDW */
814 (offset == 0x2114)) { /*second BB header register UDW */
815 ret = true;
816 }
817 return ret;
818 }
819
820 static int cmd_reg_handler(struct parser_exec_state *s,
821 unsigned int offset, unsigned int index, char *cmd)
822 {
823 struct intel_vgpu *vgpu = s->vgpu;
824 struct intel_gvt *gvt = vgpu->gvt;
825
826 if (offset + 4 > gvt->device_info.mmio_size) {
827 gvt_err("%s access to (%x) outside of MMIO range\n",
828 cmd, offset);
829 return -EINVAL;
830 }
831
832 if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
833 gvt_err("vgpu%d: %s access to non-render register (%x)\n",
834 s->vgpu->id, cmd, offset);
835 return 0;
836 }
837
838 if (is_shadowed_mmio(offset)) {
839 gvt_err("vgpu%d: found access of shadowed MMIO %x\n",
840 s->vgpu->id, offset);
841 return 0;
842 }
843
844 if (offset == i915_mmio_reg_offset(DERRMR) ||
845 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
846 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
847 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
848 }
849
850 /* TODO: Update the global mask if this MMIO is a masked-MMIO */
851 intel_gvt_mmio_set_cmd_accessed(gvt, offset);
852 return 0;
853 }
854
855 #define cmd_reg(s, i) \
856 (cmd_val(s, i) & GENMASK(22, 2))
857
858 #define cmd_reg_inhibit(s, i) \
859 (cmd_val(s, i) & GENMASK(22, 18))
860
861 #define cmd_gma(s, i) \
862 (cmd_val(s, i) & GENMASK(31, 2))
863
864 #define cmd_gma_hi(s, i) \
865 (cmd_val(s, i) & GENMASK(15, 0))
866
867 static int cmd_handler_lri(struct parser_exec_state *s)
868 {
869 int i, ret = 0;
870 int cmd_len = cmd_length(s);
871 struct intel_gvt *gvt = s->vgpu->gvt;
872
873 for (i = 1; i < cmd_len; i += 2) {
874 if (IS_BROADWELL(gvt->dev_priv) &&
875 (s->ring_id != RCS)) {
876 if (s->ring_id == BCS &&
877 cmd_reg(s, i) ==
878 i915_mmio_reg_offset(DERRMR))
879 ret |= 0;
880 else
881 ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0;
882 }
883 if (ret)
884 break;
885 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
886 }
887 return ret;
888 }
889
890 static int cmd_handler_lrr(struct parser_exec_state *s)
891 {
892 int i, ret = 0;
893 int cmd_len = cmd_length(s);
894
895 for (i = 1; i < cmd_len; i += 2) {
896 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
897 ret |= ((cmd_reg_inhibit(s, i) ||
898 (cmd_reg_inhibit(s, i + 1)))) ?
899 -EINVAL : 0;
900 if (ret)
901 break;
902 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
903 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
904 }
905 return ret;
906 }
907
908 static inline int cmd_address_audit(struct parser_exec_state *s,
909 unsigned long guest_gma, int op_size, bool index_mode);
910
911 static int cmd_handler_lrm(struct parser_exec_state *s)
912 {
913 struct intel_gvt *gvt = s->vgpu->gvt;
914 int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
915 unsigned long gma;
916 int i, ret = 0;
917 int cmd_len = cmd_length(s);
918
919 for (i = 1; i < cmd_len;) {
920 if (IS_BROADWELL(gvt->dev_priv))
921 ret |= (cmd_reg_inhibit(s, i)) ? -EINVAL : 0;
922 if (ret)
923 break;
924 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
925 if (cmd_val(s, 0) & (1 << 22)) {
926 gma = cmd_gma(s, i + 1);
927 if (gmadr_bytes == 8)
928 gma |= (cmd_gma_hi(s, i + 2)) << 32;
929 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
930 }
931 i += gmadr_dw_number(s) + 1;
932 }
933 return ret;
934 }
935
936 static int cmd_handler_srm(struct parser_exec_state *s)
937 {
938 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
939 unsigned long gma;
940 int i, ret = 0;
941 int cmd_len = cmd_length(s);
942
943 for (i = 1; i < cmd_len;) {
944 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
945 if (cmd_val(s, 0) & (1 << 22)) {
946 gma = cmd_gma(s, i + 1);
947 if (gmadr_bytes == 8)
948 gma |= (cmd_gma_hi(s, i + 2)) << 32;
949 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
950 }
951 i += gmadr_dw_number(s) + 1;
952 }
953 return ret;
954 }
955
956 struct cmd_interrupt_event {
957 int pipe_control_notify;
958 int mi_flush_dw;
959 int mi_user_interrupt;
960 };
961
962 static struct cmd_interrupt_event cmd_interrupt_events[] = {
963 [RCS] = {
964 .pipe_control_notify = RCS_PIPE_CONTROL,
965 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
966 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
967 },
968 [BCS] = {
969 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
970 .mi_flush_dw = BCS_MI_FLUSH_DW,
971 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
972 },
973 [VCS] = {
974 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
975 .mi_flush_dw = VCS_MI_FLUSH_DW,
976 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
977 },
978 [VCS2] = {
979 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
980 .mi_flush_dw = VCS2_MI_FLUSH_DW,
981 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
982 },
983 [VECS] = {
984 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
985 .mi_flush_dw = VECS_MI_FLUSH_DW,
986 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
987 },
988 };
989
990 static int cmd_handler_pipe_control(struct parser_exec_state *s)
991 {
992 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
993 unsigned long gma;
994 bool index_mode = false;
995 unsigned int post_sync;
996 int ret = 0;
997
998 post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
999
1000 /* LRI post sync */
1001 if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1002 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1003 /* post sync */
1004 else if (post_sync) {
1005 if (post_sync == 2)
1006 ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1007 else if (post_sync == 3)
1008 ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1009 else if (post_sync == 1) {
1010 /* check ggtt*/
1011 if ((cmd_val(s, 2) & (1 << 2))) {
1012 gma = cmd_val(s, 2) & GENMASK(31, 3);
1013 if (gmadr_bytes == 8)
1014 gma |= (cmd_gma_hi(s, 3)) << 32;
1015 /* Store Data Index */
1016 if (cmd_val(s, 1) & (1 << 21))
1017 index_mode = true;
1018 ret |= cmd_address_audit(s, gma, sizeof(u64),
1019 index_mode);
1020 }
1021 }
1022 }
1023
1024 if (ret)
1025 return ret;
1026
1027 if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1028 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1029 s->workload->pending_events);
1030 return 0;
1031 }
1032
1033 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1034 {
1035 set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1036 s->workload->pending_events);
1037 return 0;
1038 }
1039
1040 static int cmd_advance_default(struct parser_exec_state *s)
1041 {
1042 return ip_gma_advance(s, cmd_length(s));
1043 }
1044
1045 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1046 {
1047 int ret;
1048
1049 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1050 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1051 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1052 s->buf_addr_type = s->saved_buf_addr_type;
1053 } else {
1054 s->buf_type = RING_BUFFER_INSTRUCTION;
1055 s->buf_addr_type = GTT_BUFFER;
1056 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1057 s->ret_ip_gma_ring -= s->ring_size;
1058 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1059 }
1060 return ret;
1061 }
1062
1063 struct mi_display_flip_command_info {
1064 int pipe;
1065 int plane;
1066 int event;
1067 i915_reg_t stride_reg;
1068 i915_reg_t ctrl_reg;
1069 i915_reg_t surf_reg;
1070 u64 stride_val;
1071 u64 tile_val;
1072 u64 surf_val;
1073 bool async_flip;
1074 };
1075
1076 struct plane_code_mapping {
1077 int pipe;
1078 int plane;
1079 int event;
1080 };
1081
1082 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1083 struct mi_display_flip_command_info *info)
1084 {
1085 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1086 struct plane_code_mapping gen8_plane_code[] = {
1087 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1088 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1089 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1090 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1091 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1092 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1093 };
1094 u32 dword0, dword1, dword2;
1095 u32 v;
1096
1097 dword0 = cmd_val(s, 0);
1098 dword1 = cmd_val(s, 1);
1099 dword2 = cmd_val(s, 2);
1100
1101 v = (dword0 & GENMASK(21, 19)) >> 19;
1102 if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1103 return -EINVAL;
1104
1105 info->pipe = gen8_plane_code[v].pipe;
1106 info->plane = gen8_plane_code[v].plane;
1107 info->event = gen8_plane_code[v].event;
1108 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1109 info->tile_val = (dword1 & 0x1);
1110 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1111 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1112
1113 if (info->plane == PLANE_A) {
1114 info->ctrl_reg = DSPCNTR(info->pipe);
1115 info->stride_reg = DSPSTRIDE(info->pipe);
1116 info->surf_reg = DSPSURF(info->pipe);
1117 } else if (info->plane == PLANE_B) {
1118 info->ctrl_reg = SPRCTL(info->pipe);
1119 info->stride_reg = SPRSTRIDE(info->pipe);
1120 info->surf_reg = SPRSURF(info->pipe);
1121 } else {
1122 WARN_ON(1);
1123 return -EINVAL;
1124 }
1125 return 0;
1126 }
1127
1128 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1129 struct mi_display_flip_command_info *info)
1130 {
1131 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1132 u32 dword0 = cmd_val(s, 0);
1133 u32 dword1 = cmd_val(s, 1);
1134 u32 dword2 = cmd_val(s, 2);
1135 u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1136
1137 info->plane = PRIMARY_PLANE;
1138
1139 switch (plane) {
1140 case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1141 info->pipe = PIPE_A;
1142 info->event = PRIMARY_A_FLIP_DONE;
1143 break;
1144 case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1145 info->pipe = PIPE_B;
1146 info->event = PRIMARY_B_FLIP_DONE;
1147 break;
1148 case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1149 info->pipe = PIPE_C;
1150 info->event = PRIMARY_C_FLIP_DONE;
1151 break;
1152
1153 case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1154 info->pipe = PIPE_A;
1155 info->event = SPRITE_A_FLIP_DONE;
1156 info->plane = SPRITE_PLANE;
1157 break;
1158 case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1159 info->pipe = PIPE_B;
1160 info->event = SPRITE_B_FLIP_DONE;
1161 info->plane = SPRITE_PLANE;
1162 break;
1163 case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1164 info->pipe = PIPE_C;
1165 info->event = SPRITE_C_FLIP_DONE;
1166 info->plane = SPRITE_PLANE;
1167 break;
1168
1169 default:
1170 gvt_err("unknown plane code %d\n", plane);
1171 return -EINVAL;
1172 }
1173
1174 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1175 info->tile_val = (dword1 & GENMASK(2, 0));
1176 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1177 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1178
1179 info->ctrl_reg = DSPCNTR(info->pipe);
1180 info->stride_reg = DSPSTRIDE(info->pipe);
1181 info->surf_reg = DSPSURF(info->pipe);
1182
1183 return 0;
1184 }
1185
1186 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1187 struct mi_display_flip_command_info *info)
1188 {
1189 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1190 u32 stride, tile;
1191
1192 if (!info->async_flip)
1193 return 0;
1194
1195 if (IS_SKYLAKE(dev_priv)) {
1196 stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1197 tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) &
1198 GENMASK(12, 10)) >> 10;
1199 } else {
1200 stride = (vgpu_vreg(s->vgpu, info->stride_reg) &
1201 GENMASK(15, 6)) >> 6;
1202 tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1203 }
1204
1205 if (stride != info->stride_val)
1206 gvt_dbg_cmd("cannot change stride during async flip\n");
1207
1208 if (tile != info->tile_val)
1209 gvt_dbg_cmd("cannot change tile during async flip\n");
1210
1211 return 0;
1212 }
1213
1214 static int gen8_update_plane_mmio_from_mi_display_flip(
1215 struct parser_exec_state *s,
1216 struct mi_display_flip_command_info *info)
1217 {
1218 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1219 struct intel_vgpu *vgpu = s->vgpu;
1220
1221 set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),
1222 info->surf_val << 12);
1223 if (IS_SKYLAKE(dev_priv)) {
1224 set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),
1225 info->stride_val);
1226 set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),
1227 info->tile_val << 10);
1228 } else {
1229 set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(15, 6),
1230 info->stride_val << 6);
1231 set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(10, 10),
1232 info->tile_val << 10);
1233 }
1234
1235 vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1236 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1237 return 0;
1238 }
1239
1240 static int decode_mi_display_flip(struct parser_exec_state *s,
1241 struct mi_display_flip_command_info *info)
1242 {
1243 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1244
1245 if (IS_BROADWELL(dev_priv))
1246 return gen8_decode_mi_display_flip(s, info);
1247 if (IS_SKYLAKE(dev_priv))
1248 return skl_decode_mi_display_flip(s, info);
1249
1250 return -ENODEV;
1251 }
1252
1253 static int check_mi_display_flip(struct parser_exec_state *s,
1254 struct mi_display_flip_command_info *info)
1255 {
1256 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1257
1258 if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
1259 return gen8_check_mi_display_flip(s, info);
1260 return -ENODEV;
1261 }
1262
1263 static int update_plane_mmio_from_mi_display_flip(
1264 struct parser_exec_state *s,
1265 struct mi_display_flip_command_info *info)
1266 {
1267 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1268
1269 if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
1270 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1271 return -ENODEV;
1272 }
1273
1274 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1275 {
1276 struct mi_display_flip_command_info info;
1277 int ret;
1278 int i;
1279 int len = cmd_length(s);
1280
1281 ret = decode_mi_display_flip(s, &info);
1282 if (ret) {
1283 gvt_err("fail to decode MI display flip command\n");
1284 return ret;
1285 }
1286
1287 ret = check_mi_display_flip(s, &info);
1288 if (ret) {
1289 gvt_err("invalid MI display flip command\n");
1290 return ret;
1291 }
1292
1293 ret = update_plane_mmio_from_mi_display_flip(s, &info);
1294 if (ret) {
1295 gvt_err("fail to update plane mmio\n");
1296 return ret;
1297 }
1298
1299 for (i = 0; i < len; i++)
1300 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1301 return 0;
1302 }
1303
1304 static bool is_wait_for_flip_pending(u32 cmd)
1305 {
1306 return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1307 MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1308 MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1309 MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1310 MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1311 MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1312 }
1313
1314 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1315 {
1316 u32 cmd = cmd_val(s, 0);
1317
1318 if (!is_wait_for_flip_pending(cmd))
1319 return 0;
1320
1321 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1322 return 0;
1323 }
1324
1325 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1326 {
1327 unsigned long addr;
1328 unsigned long gma_high, gma_low;
1329 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1330
1331 if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8))
1332 return INTEL_GVT_INVALID_ADDR;
1333
1334 gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1335 if (gmadr_bytes == 4) {
1336 addr = gma_low;
1337 } else {
1338 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1339 addr = (((unsigned long)gma_high) << 32) | gma_low;
1340 }
1341 return addr;
1342 }
1343
1344 static inline int cmd_address_audit(struct parser_exec_state *s,
1345 unsigned long guest_gma, int op_size, bool index_mode)
1346 {
1347 struct intel_vgpu *vgpu = s->vgpu;
1348 u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1349 int i;
1350 int ret;
1351
1352 if (op_size > max_surface_size) {
1353 gvt_err("command address audit fail name %s\n", s->info->name);
1354 return -EINVAL;
1355 }
1356
1357 if (index_mode) {
1358 if (guest_gma >= GTT_PAGE_SIZE / sizeof(u64)) {
1359 ret = -EINVAL;
1360 goto err;
1361 }
1362 } else if ((!vgpu_gmadr_is_valid(s->vgpu, guest_gma)) ||
1363 (!vgpu_gmadr_is_valid(s->vgpu,
1364 guest_gma + op_size - 1))) {
1365 ret = -EINVAL;
1366 goto err;
1367 }
1368 return 0;
1369 err:
1370 gvt_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1371 s->info->name, guest_gma, op_size);
1372
1373 pr_err("cmd dump: ");
1374 for (i = 0; i < cmd_length(s); i++) {
1375 if (!(i % 4))
1376 pr_err("\n%08x ", cmd_val(s, i));
1377 else
1378 pr_err("%08x ", cmd_val(s, i));
1379 }
1380 pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1381 vgpu->id,
1382 vgpu_aperture_gmadr_base(vgpu),
1383 vgpu_aperture_gmadr_end(vgpu),
1384 vgpu_hidden_gmadr_base(vgpu),
1385 vgpu_hidden_gmadr_end(vgpu));
1386 return ret;
1387 }
1388
1389 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1390 {
1391 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1392 int op_size = (cmd_length(s) - 3) * sizeof(u32);
1393 int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1394 unsigned long gma, gma_low, gma_high;
1395 int ret = 0;
1396
1397 /* check ppggt */
1398 if (!(cmd_val(s, 0) & (1 << 22)))
1399 return 0;
1400
1401 gma = cmd_val(s, 2) & GENMASK(31, 2);
1402
1403 if (gmadr_bytes == 8) {
1404 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1405 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1406 gma = (gma_high << 32) | gma_low;
1407 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1408 }
1409 ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1410 return ret;
1411 }
1412
1413 static inline int unexpected_cmd(struct parser_exec_state *s)
1414 {
1415 gvt_err("vgpu%d: Unexpected %s in command buffer!\n",
1416 s->vgpu->id, s->info->name);
1417 return -EINVAL;
1418 }
1419
1420 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1421 {
1422 return unexpected_cmd(s);
1423 }
1424
1425 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1426 {
1427 return unexpected_cmd(s);
1428 }
1429
1430 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1431 {
1432 return unexpected_cmd(s);
1433 }
1434
1435 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1436 {
1437 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1438 int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1439 sizeof(u32);
1440 unsigned long gma, gma_high;
1441 int ret = 0;
1442
1443 if (!(cmd_val(s, 0) & (1 << 22)))
1444 return ret;
1445
1446 gma = cmd_val(s, 1) & GENMASK(31, 2);
1447 if (gmadr_bytes == 8) {
1448 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1449 gma = (gma_high << 32) | gma;
1450 }
1451 ret = cmd_address_audit(s, gma, op_size, false);
1452 return ret;
1453 }
1454
1455 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1456 {
1457 return unexpected_cmd(s);
1458 }
1459
1460 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1461 {
1462 return unexpected_cmd(s);
1463 }
1464
1465 static int cmd_handler_mi_conditional_batch_buffer_end(
1466 struct parser_exec_state *s)
1467 {
1468 return unexpected_cmd(s);
1469 }
1470
1471 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1472 {
1473 return unexpected_cmd(s);
1474 }
1475
1476 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1477 {
1478 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1479 unsigned long gma;
1480 bool index_mode = false;
1481 int ret = 0;
1482
1483 /* Check post-sync and ppgtt bit */
1484 if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1485 gma = cmd_val(s, 1) & GENMASK(31, 3);
1486 if (gmadr_bytes == 8)
1487 gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1488 /* Store Data Index */
1489 if (cmd_val(s, 0) & (1 << 21))
1490 index_mode = true;
1491 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1492 }
1493 /* Check notify bit */
1494 if ((cmd_val(s, 0) & (1 << 8)))
1495 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1496 s->workload->pending_events);
1497 return ret;
1498 }
1499
1500 static void addr_type_update_snb(struct parser_exec_state *s)
1501 {
1502 if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1503 (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1504 s->buf_addr_type = PPGTT_BUFFER;
1505 }
1506 }
1507
1508
1509 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1510 unsigned long gma, unsigned long end_gma, void *va)
1511 {
1512 unsigned long copy_len, offset;
1513 unsigned long len = 0;
1514 unsigned long gpa;
1515
1516 while (gma != end_gma) {
1517 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1518 if (gpa == INTEL_GVT_INVALID_ADDR) {
1519 gvt_err("invalid gma address: %lx\n", gma);
1520 return -EFAULT;
1521 }
1522
1523 offset = gma & (GTT_PAGE_SIZE - 1);
1524
1525 copy_len = (end_gma - gma) >= (GTT_PAGE_SIZE - offset) ?
1526 GTT_PAGE_SIZE - offset : end_gma - gma;
1527
1528 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1529
1530 len += copy_len;
1531 gma += copy_len;
1532 }
1533 return 0;
1534 }
1535
1536
1537 /*
1538 * Check whether a batch buffer needs to be scanned. Currently
1539 * the only criteria is based on privilege.
1540 */
1541 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1542 {
1543 struct intel_gvt *gvt = s->vgpu->gvt;
1544
1545 if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
1546 /* BDW decides privilege based on address space */
1547 if (cmd_val(s, 0) & (1 << 8))
1548 return 0;
1549 }
1550 return 1;
1551 }
1552
1553 static uint32_t find_bb_size(struct parser_exec_state *s)
1554 {
1555 unsigned long gma = 0;
1556 struct cmd_info *info;
1557 uint32_t bb_size = 0;
1558 uint32_t cmd_len = 0;
1559 bool met_bb_end = false;
1560 u32 cmd;
1561
1562 /* get the start gm address of the batch buffer */
1563 gma = get_gma_bb_from_cmd(s, 1);
1564 cmd = cmd_val(s, 0);
1565
1566 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1567 if (info == NULL) {
1568 gvt_err("unknown cmd 0x%x, opcode=0x%x\n",
1569 cmd, get_opcode(cmd, s->ring_id));
1570 return -EINVAL;
1571 }
1572 do {
1573 copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1574 gma, gma + 4, &cmd);
1575 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1576 if (info == NULL) {
1577 gvt_err("unknown cmd 0x%x, opcode=0x%x\n",
1578 cmd, get_opcode(cmd, s->ring_id));
1579 return -EINVAL;
1580 }
1581
1582 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1583 met_bb_end = true;
1584 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1585 if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0) {
1586 /* chained batch buffer */
1587 met_bb_end = true;
1588 }
1589 }
1590 cmd_len = get_cmd_length(info, cmd) << 2;
1591 bb_size += cmd_len;
1592 gma += cmd_len;
1593
1594 } while (!met_bb_end);
1595
1596 return bb_size;
1597 }
1598
1599 static int perform_bb_shadow(struct parser_exec_state *s)
1600 {
1601 struct intel_shadow_bb_entry *entry_obj;
1602 unsigned long gma = 0;
1603 uint32_t bb_size;
1604 void *dst = NULL;
1605 int ret = 0;
1606
1607 /* get the start gm address of the batch buffer */
1608 gma = get_gma_bb_from_cmd(s, 1);
1609
1610 /* get the size of the batch buffer */
1611 bb_size = find_bb_size(s);
1612
1613 /* allocate shadow batch buffer */
1614 entry_obj = kmalloc(sizeof(*entry_obj), GFP_KERNEL);
1615 if (entry_obj == NULL)
1616 return -ENOMEM;
1617
1618 entry_obj->obj =
1619 i915_gem_object_create(s->vgpu->gvt->dev_priv,
1620 roundup(bb_size, PAGE_SIZE));
1621 if (IS_ERR(entry_obj->obj)) {
1622 ret = PTR_ERR(entry_obj->obj);
1623 goto free_entry;
1624 }
1625 entry_obj->len = bb_size;
1626 INIT_LIST_HEAD(&entry_obj->list);
1627
1628 dst = i915_gem_object_pin_map(entry_obj->obj, I915_MAP_WB);
1629 if (IS_ERR(dst)) {
1630 ret = PTR_ERR(dst);
1631 goto put_obj;
1632 }
1633
1634 ret = i915_gem_object_set_to_cpu_domain(entry_obj->obj, false);
1635 if (ret) {
1636 gvt_err("failed to set shadow batch to CPU\n");
1637 goto unmap_src;
1638 }
1639
1640 entry_obj->va = dst;
1641 entry_obj->bb_start_cmd_va = s->ip_va;
1642
1643 /* copy batch buffer to shadow batch buffer*/
1644 ret = copy_gma_to_hva(s->vgpu, s->vgpu->gtt.ggtt_mm,
1645 gma, gma + bb_size,
1646 dst);
1647 if (ret) {
1648 gvt_err("fail to copy guest ring buffer\n");
1649 goto unmap_src;
1650 }
1651
1652 list_add(&entry_obj->list, &s->workload->shadow_bb);
1653 /*
1654 * ip_va saves the virtual address of the shadow batch buffer, while
1655 * ip_gma saves the graphics address of the original batch buffer.
1656 * As the shadow batch buffer is just a copy from the originial one,
1657 * it should be right to use shadow batch buffer'va and original batch
1658 * buffer's gma in pair. After all, we don't want to pin the shadow
1659 * buffer here (too early).
1660 */
1661 s->ip_va = dst;
1662 s->ip_gma = gma;
1663
1664 return 0;
1665
1666 unmap_src:
1667 i915_gem_object_unpin_map(entry_obj->obj);
1668 put_obj:
1669 i915_gem_object_put(entry_obj->obj);
1670 free_entry:
1671 kfree(entry_obj);
1672 return ret;
1673 }
1674
1675 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1676 {
1677 bool second_level;
1678 int ret = 0;
1679
1680 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1681 gvt_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1682 return -EINVAL;
1683 }
1684
1685 second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1686 if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1687 gvt_err("Jumping to 2nd level BB from RB is not allowed\n");
1688 return -EINVAL;
1689 }
1690
1691 s->saved_buf_addr_type = s->buf_addr_type;
1692 addr_type_update_snb(s);
1693 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1694 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1695 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1696 } else if (second_level) {
1697 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1698 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1699 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1700 }
1701
1702 if (batch_buffer_needs_scan(s)) {
1703 ret = perform_bb_shadow(s);
1704 if (ret < 0)
1705 gvt_err("invalid shadow batch buffer\n");
1706 } else {
1707 /* emulate a batch buffer end to do return right */
1708 ret = cmd_handler_mi_batch_buffer_end(s);
1709 if (ret < 0)
1710 return ret;
1711 }
1712
1713 return ret;
1714 }
1715
1716 static struct cmd_info cmd_info[] = {
1717 {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1718
1719 {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1720 0, 1, NULL},
1721
1722 {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1723 0, 1, cmd_handler_mi_user_interrupt},
1724
1725 {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1726 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1727
1728 {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1729
1730 {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1731 NULL},
1732
1733 {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1734 NULL},
1735
1736 {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1737 NULL},
1738
1739 {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1740 NULL},
1741
1742 {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1743 D_ALL, 0, 1, NULL},
1744
1745 {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1746 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1747 cmd_handler_mi_batch_buffer_end},
1748
1749 {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1750 0, 1, NULL},
1751
1752 {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1753 NULL},
1754
1755 {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1756 D_ALL, 0, 1, NULL},
1757
1758 {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1759 NULL},
1760
1761 {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1762 NULL},
1763
1764 {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1765 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1766
1767 {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1768 0, 8, NULL},
1769
1770 {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1771
1772 {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1773
1774 {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1775 D_BDW_PLUS, 0, 8, NULL},
1776
1777 {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1778 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1779
1780 {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1781 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1782
1783 {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1784 0, 8, cmd_handler_mi_store_data_index},
1785
1786 {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1787 D_ALL, 0, 8, cmd_handler_lri},
1788
1789 {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1790 cmd_handler_mi_update_gtt},
1791
1792 {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1793 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1794
1795 {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1796 cmd_handler_mi_flush_dw},
1797
1798 {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1799 10, cmd_handler_mi_clflush},
1800
1801 {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1802 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1803
1804 {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1805 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1806
1807 {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1808 D_ALL, 0, 8, cmd_handler_lrr},
1809
1810 {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1811 D_ALL, 0, 8, NULL},
1812
1813 {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1814 ADDR_FIX_1(2), 8, NULL},
1815
1816 {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1817 ADDR_FIX_1(2), 8, NULL},
1818
1819 {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1820 8, cmd_handler_mi_op_2e},
1821
1822 {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1823 8, cmd_handler_mi_op_2f},
1824
1825 {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1826 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1827 cmd_handler_mi_batch_buffer_start},
1828
1829 {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1830 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1831 cmd_handler_mi_conditional_batch_buffer_end},
1832
1833 {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1834 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1835
1836 {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1837 ADDR_FIX_2(4, 7), 8, NULL},
1838
1839 {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1840 0, 8, NULL},
1841
1842 {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1843 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1844
1845 {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1846
1847 {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1848 0, 8, NULL},
1849
1850 {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1851 ADDR_FIX_1(3), 8, NULL},
1852
1853 {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1854 D_ALL, 0, 8, NULL},
1855
1856 {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1857 ADDR_FIX_1(4), 8, NULL},
1858
1859 {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1860 ADDR_FIX_2(4, 5), 8, NULL},
1861
1862 {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1863 ADDR_FIX_1(4), 8, NULL},
1864
1865 {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1866 ADDR_FIX_2(4, 7), 8, NULL},
1867
1868 {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1869 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1870
1871 {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1872
1873 {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
1874 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
1875
1876 {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
1877 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1878
1879 {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
1880 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
1881 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1882
1883 {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
1884 D_ALL, ADDR_FIX_1(4), 8, NULL},
1885
1886 {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
1887 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1888
1889 {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
1890 D_ALL, ADDR_FIX_1(4), 8, NULL},
1891
1892 {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
1893 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1894
1895 {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
1896 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
1897
1898 {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
1899 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
1900 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1901
1902 {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
1903 ADDR_FIX_2(4, 5), 8, NULL},
1904
1905 {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
1906 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1907
1908 {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
1909 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
1910 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1911
1912 {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
1913 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
1914 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1915
1916 {"3DSTATE_BLEND_STATE_POINTERS",
1917 OP_3DSTATE_BLEND_STATE_POINTERS,
1918 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1919
1920 {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
1921 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
1922 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1923
1924 {"3DSTATE_BINDING_TABLE_POINTERS_VS",
1925 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
1926 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1927
1928 {"3DSTATE_BINDING_TABLE_POINTERS_HS",
1929 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
1930 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1931
1932 {"3DSTATE_BINDING_TABLE_POINTERS_DS",
1933 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
1934 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1935
1936 {"3DSTATE_BINDING_TABLE_POINTERS_GS",
1937 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
1938 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1939
1940 {"3DSTATE_BINDING_TABLE_POINTERS_PS",
1941 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
1942 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1943
1944 {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
1945 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
1946 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1947
1948 {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
1949 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
1950 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1951
1952 {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
1953 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
1954 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1955
1956 {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
1957 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
1958 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1959
1960 {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
1961 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
1962 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1963
1964 {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
1965 0, 8, NULL},
1966
1967 {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
1968 0, 8, NULL},
1969
1970 {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
1971 0, 8, NULL},
1972
1973 {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
1974 0, 8, NULL},
1975
1976 {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
1977 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1978
1979 {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
1980 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1981
1982 {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
1983 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1984
1985 {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
1986 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1987
1988 {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
1989 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1990
1991 {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
1992 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
1993
1994 {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
1995 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
1996
1997 {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
1998 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1999
2000 {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2001 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2002
2003 {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2004 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2005
2006 {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2007 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2008
2009 {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2010 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2011
2012 {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2013 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2014
2015 {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2016 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2017
2018 {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2019 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2020
2021 {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2022 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2023
2024 {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2025 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2026
2027 {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2028 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2029
2030 {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2031 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2032
2033 {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2034 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2035
2036 {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2037 D_BDW_PLUS, 0, 8, NULL},
2038
2039 {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2040 NULL},
2041
2042 {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2043 D_BDW_PLUS, 0, 8, NULL},
2044
2045 {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2046 D_BDW_PLUS, 0, 8, NULL},
2047
2048 {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2049 8, NULL},
2050
2051 {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2052 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2053
2054 {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2055 8, NULL},
2056
2057 {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2058 NULL},
2059
2060 {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2061 NULL},
2062
2063 {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2064 NULL},
2065
2066 {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2067 D_BDW_PLUS, 0, 8, NULL},
2068
2069 {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2070 R_RCS, D_ALL, 0, 8, NULL},
2071
2072 {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2073 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2074
2075 {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2076 R_RCS, D_ALL, 0, 1, NULL},
2077
2078 {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2079
2080 {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2081 R_RCS, D_ALL, 0, 8, NULL},
2082
2083 {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2084 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2085
2086 {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2087
2088 {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2089
2090 {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2091
2092 {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2093 D_BDW_PLUS, 0, 8, NULL},
2094
2095 {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2096 D_BDW_PLUS, 0, 8, NULL},
2097
2098 {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2099 D_ALL, 0, 8, NULL},
2100
2101 {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2102 D_BDW_PLUS, 0, 8, NULL},
2103
2104 {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2105 D_BDW_PLUS, 0, 8, NULL},
2106
2107 {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2108
2109 {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2110
2111 {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2112
2113 {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2114 D_ALL, 0, 8, NULL},
2115
2116 {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2117
2118 {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2119
2120 {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2121 R_RCS, D_ALL, 0, 8, NULL},
2122
2123 {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2124 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2125
2126 {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2127 0, 8, NULL},
2128
2129 {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2130 D_ALL, ADDR_FIX_1(2), 8, NULL},
2131
2132 {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2133 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2134
2135 {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2136 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2137
2138 {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2139 D_ALL, 0, 8, NULL},
2140
2141 {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2142 D_ALL, 0, 8, NULL},
2143
2144 {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2145 D_ALL, 0, 8, NULL},
2146
2147 {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2148 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2149
2150 {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2151 D_BDW_PLUS, 0, 8, NULL},
2152
2153 {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2154 D_ALL, ADDR_FIX_1(2), 8, NULL},
2155
2156 {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2157 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2158
2159 {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2160 R_RCS, D_ALL, 0, 8, NULL},
2161
2162 {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2163 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2164
2165 {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2166 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2167
2168 {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2169 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2170
2171 {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2172 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2173
2174 {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2175 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2176
2177 {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2178 R_RCS, D_ALL, 0, 8, NULL},
2179
2180 {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2181 D_ALL, 0, 9, NULL},
2182
2183 {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2184 ADDR_FIX_2(2, 4), 8, NULL},
2185
2186 {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2187 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2188 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2189
2190 {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2191 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2192
2193 {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2194 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2195 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2196
2197 {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2198 D_BDW_PLUS, 0, 8, NULL},
2199
2200 {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2201 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2202
2203 {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2204
2205 {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2206 1, NULL},
2207
2208 {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2209 ADDR_FIX_1(1), 8, NULL},
2210
2211 {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2212
2213 {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2214 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2215
2216 {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2217 ADDR_FIX_1(1), 8, NULL},
2218
2219 {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2220
2221 {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2222
2223 {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2224 0, 8, NULL},
2225
2226 {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2227 D_SKL_PLUS, 0, 8, NULL},
2228
2229 {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2230 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2231
2232 {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2233 0, 16, NULL},
2234
2235 {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2236 0, 16, NULL},
2237
2238 {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2239
2240 {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2241 0, 16, NULL},
2242
2243 {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2244 0, 16, NULL},
2245
2246 {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2247 0, 16, NULL},
2248
2249 {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2250 0, 8, NULL},
2251
2252 {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2253 NULL},
2254
2255 {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2256 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2257
2258 {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2259 R_VCS, D_ALL, 0, 12, NULL},
2260
2261 {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2262 R_VCS, D_ALL, 0, 12, NULL},
2263
2264 {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2265 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2266
2267 {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2268 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2269
2270 {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2271 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2272
2273 {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2274
2275 {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2276 R_VCS, D_ALL, 0, 12, NULL},
2277
2278 {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2279 R_VCS, D_ALL, 0, 12, NULL},
2280
2281 {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2282 R_VCS, D_ALL, 0, 12, NULL},
2283
2284 {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2285 R_VCS, D_ALL, 0, 12, NULL},
2286
2287 {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2288 R_VCS, D_ALL, 0, 12, NULL},
2289
2290 {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2291 R_VCS, D_ALL, 0, 12, NULL},
2292
2293 {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2294 R_VCS, D_ALL, 0, 6, NULL},
2295
2296 {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2297 R_VCS, D_ALL, 0, 12, NULL},
2298
2299 {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2300 R_VCS, D_ALL, 0, 12, NULL},
2301
2302 {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2303 R_VCS, D_ALL, 0, 12, NULL},
2304
2305 {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2306 R_VCS, D_ALL, 0, 12, NULL},
2307
2308 {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2309 R_VCS, D_ALL, 0, 12, NULL},
2310
2311 {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2312 R_VCS, D_ALL, 0, 12, NULL},
2313
2314 {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2315 R_VCS, D_ALL, 0, 12, NULL},
2316 {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2317 R_VCS, D_ALL, 0, 12, NULL},
2318
2319 {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2320 R_VCS, D_ALL, 0, 12, NULL},
2321
2322 {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2323 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2324
2325 {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2326 R_VCS, D_ALL, 0, 12, NULL},
2327
2328 {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2329 R_VCS, D_ALL, 0, 12, NULL},
2330
2331 {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2332 R_VCS, D_ALL, 0, 12, NULL},
2333
2334 {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2335 R_VCS, D_ALL, 0, 12, NULL},
2336
2337 {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2338 R_VCS, D_ALL, 0, 12, NULL},
2339
2340 {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2341 R_VCS, D_ALL, 0, 12, NULL},
2342
2343 {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2344 R_VCS, D_ALL, 0, 12, NULL},
2345
2346 {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2347 R_VCS, D_ALL, 0, 12, NULL},
2348
2349 {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2350 R_VCS, D_ALL, 0, 12, NULL},
2351
2352 {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2353 R_VCS, D_ALL, 0, 12, NULL},
2354
2355 {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2356 R_VCS, D_ALL, 0, 12, NULL},
2357
2358 {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2359 0, 16, NULL},
2360
2361 {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2362
2363 {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2364
2365 {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2366 R_VCS, D_ALL, 0, 12, NULL},
2367
2368 {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2369 R_VCS, D_ALL, 0, 12, NULL},
2370
2371 {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2372 R_VCS, D_ALL, 0, 12, NULL},
2373
2374 {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2375
2376 {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2377 0, 12, NULL},
2378
2379 {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2380 0, 20, NULL},
2381 };
2382
2383 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2384 {
2385 hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2386 }
2387
2388 #define GVT_MAX_CMD_LENGTH 20 /* In Dword */
2389
2390 static void trace_cs_command(struct parser_exec_state *s,
2391 cycles_t cost_pre_cmd_handler, cycles_t cost_cmd_handler)
2392 {
2393 /* This buffer is used by ftrace to store all commands copied from
2394 * guest gma space. Sometimes commands can cross pages, this should
2395 * not be handled in ftrace logic. So this is just used as a
2396 * 'bounce buffer'
2397 */
2398 u32 cmd_trace_buf[GVT_MAX_CMD_LENGTH];
2399 int i;
2400 u32 cmd_len = cmd_length(s);
2401 /* The chosen value of GVT_MAX_CMD_LENGTH are just based on
2402 * following two considerations:
2403 * 1) From observation, most common ring commands is not that long.
2404 * But there are execeptions. So it indeed makes sence to observe
2405 * longer commands.
2406 * 2) From the performance and debugging point of view, dumping all
2407 * contents of very commands is not necessary.
2408 * We mgith shrink GVT_MAX_CMD_LENGTH or remove this trace event in
2409 * future for performance considerations.
2410 */
2411 if (unlikely(cmd_len > GVT_MAX_CMD_LENGTH)) {
2412 gvt_dbg_cmd("cmd length exceed tracing limitation!\n");
2413 cmd_len = GVT_MAX_CMD_LENGTH;
2414 }
2415
2416 for (i = 0; i < cmd_len; i++)
2417 cmd_trace_buf[i] = cmd_val(s, i);
2418
2419 trace_gvt_command(s->vgpu->id, s->ring_id, s->ip_gma, cmd_trace_buf,
2420 cmd_len, s->buf_type == RING_BUFFER_INSTRUCTION,
2421 cost_pre_cmd_handler, cost_cmd_handler);
2422 }
2423
2424 /* call the cmd handler, and advance ip */
2425 static int cmd_parser_exec(struct parser_exec_state *s)
2426 {
2427 struct cmd_info *info;
2428 u32 cmd;
2429 int ret = 0;
2430 cycles_t t0, t1, t2;
2431 struct parser_exec_state s_before_advance_custom;
2432
2433 t0 = get_cycles();
2434
2435 cmd = cmd_val(s, 0);
2436
2437 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2438 if (info == NULL) {
2439 gvt_err("unknown cmd 0x%x, opcode=0x%x\n",
2440 cmd, get_opcode(cmd, s->ring_id));
2441 return -EINVAL;
2442 }
2443
2444 gvt_dbg_cmd("%s\n", info->name);
2445
2446 s->info = info;
2447
2448 t1 = get_cycles();
2449
2450 memcpy(&s_before_advance_custom, s, sizeof(struct parser_exec_state));
2451
2452 if (info->handler) {
2453 ret = info->handler(s);
2454 if (ret < 0) {
2455 gvt_err("%s handler error\n", info->name);
2456 return ret;
2457 }
2458 }
2459 t2 = get_cycles();
2460
2461 trace_cs_command(&s_before_advance_custom, t1 - t0, t2 - t1);
2462
2463 if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2464 ret = cmd_advance_default(s);
2465 if (ret) {
2466 gvt_err("%s IP advance error\n", info->name);
2467 return ret;
2468 }
2469 }
2470 return 0;
2471 }
2472
2473 static inline bool gma_out_of_range(unsigned long gma,
2474 unsigned long gma_head, unsigned int gma_tail)
2475 {
2476 if (gma_tail >= gma_head)
2477 return (gma < gma_head) || (gma > gma_tail);
2478 else
2479 return (gma > gma_tail) && (gma < gma_head);
2480 }
2481
2482 static int command_scan(struct parser_exec_state *s,
2483 unsigned long rb_head, unsigned long rb_tail,
2484 unsigned long rb_start, unsigned long rb_len)
2485 {
2486
2487 unsigned long gma_head, gma_tail, gma_bottom;
2488 int ret = 0;
2489
2490 gma_head = rb_start + rb_head;
2491 gma_tail = rb_start + rb_tail;
2492 gma_bottom = rb_start + rb_len;
2493
2494 gvt_dbg_cmd("scan_start: start=%lx end=%lx\n", gma_head, gma_tail);
2495
2496 while (s->ip_gma != gma_tail) {
2497 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2498 if (!(s->ip_gma >= rb_start) ||
2499 !(s->ip_gma < gma_bottom)) {
2500 gvt_err("ip_gma %lx out of ring scope."
2501 "(base:0x%lx, bottom: 0x%lx)\n",
2502 s->ip_gma, rb_start,
2503 gma_bottom);
2504 parser_exec_state_dump(s);
2505 return -EINVAL;
2506 }
2507 if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2508 gvt_err("ip_gma %lx out of range."
2509 "base 0x%lx head 0x%lx tail 0x%lx\n",
2510 s->ip_gma, rb_start,
2511 rb_head, rb_tail);
2512 parser_exec_state_dump(s);
2513 break;
2514 }
2515 }
2516 ret = cmd_parser_exec(s);
2517 if (ret) {
2518 gvt_err("cmd parser error\n");
2519 parser_exec_state_dump(s);
2520 break;
2521 }
2522 }
2523
2524 gvt_dbg_cmd("scan_end\n");
2525
2526 return ret;
2527 }
2528
2529 static int scan_workload(struct intel_vgpu_workload *workload)
2530 {
2531 unsigned long gma_head, gma_tail, gma_bottom;
2532 struct parser_exec_state s;
2533 int ret = 0;
2534
2535 /* ring base is page aligned */
2536 if (WARN_ON(!IS_ALIGNED(workload->rb_start, GTT_PAGE_SIZE)))
2537 return -EINVAL;
2538
2539 gma_head = workload->rb_start + workload->rb_head;
2540 gma_tail = workload->rb_start + workload->rb_tail;
2541 gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl);
2542
2543 s.buf_type = RING_BUFFER_INSTRUCTION;
2544 s.buf_addr_type = GTT_BUFFER;
2545 s.vgpu = workload->vgpu;
2546 s.ring_id = workload->ring_id;
2547 s.ring_start = workload->rb_start;
2548 s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2549 s.ring_head = gma_head;
2550 s.ring_tail = gma_tail;
2551 s.rb_va = workload->shadow_ring_buffer_va;
2552 s.workload = workload;
2553
2554 if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2555 gma_head == gma_tail)
2556 return 0;
2557
2558 ret = ip_gma_set(&s, gma_head);
2559 if (ret)
2560 goto out;
2561
2562 ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2563 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2564
2565 out:
2566 return ret;
2567 }
2568
2569 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2570 {
2571
2572 unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2573 struct parser_exec_state s;
2574 int ret = 0;
2575
2576 /* ring base is page aligned */
2577 if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, GTT_PAGE_SIZE)))
2578 return -EINVAL;
2579
2580 ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2581 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2582 PAGE_SIZE);
2583 gma_head = wa_ctx->indirect_ctx.guest_gma;
2584 gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2585 gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2586
2587 s.buf_type = RING_BUFFER_INSTRUCTION;
2588 s.buf_addr_type = GTT_BUFFER;
2589 s.vgpu = wa_ctx->workload->vgpu;
2590 s.ring_id = wa_ctx->workload->ring_id;
2591 s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2592 s.ring_size = ring_size;
2593 s.ring_head = gma_head;
2594 s.ring_tail = gma_tail;
2595 s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2596 s.workload = wa_ctx->workload;
2597
2598 ret = ip_gma_set(&s, gma_head);
2599 if (ret)
2600 goto out;
2601
2602 ret = command_scan(&s, 0, ring_tail,
2603 wa_ctx->indirect_ctx.guest_gma, ring_size);
2604 out:
2605 return ret;
2606 }
2607
2608 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2609 {
2610 struct intel_vgpu *vgpu = workload->vgpu;
2611 int ring_id = workload->ring_id;
2612 struct i915_gem_context *shadow_ctx = vgpu->shadow_ctx;
2613 struct intel_ring *ring = shadow_ctx->engine[ring_id].ring;
2614 unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2615 unsigned int copy_len = 0;
2616 int ret;
2617
2618 guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2619
2620 /* calculate workload ring buffer size */
2621 workload->rb_len = (workload->rb_tail + guest_rb_size -
2622 workload->rb_head) % guest_rb_size;
2623
2624 gma_head = workload->rb_start + workload->rb_head;
2625 gma_tail = workload->rb_start + workload->rb_tail;
2626 gma_top = workload->rb_start + guest_rb_size;
2627
2628 /* allocate shadow ring buffer */
2629 ret = intel_ring_begin(workload->req, workload->rb_len / 4);
2630 if (ret)
2631 return ret;
2632
2633 /* get shadow ring buffer va */
2634 workload->shadow_ring_buffer_va = ring->vaddr + ring->tail;
2635
2636 /* head > tail --> copy head <-> top */
2637 if (gma_head > gma_tail) {
2638 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2639 gma_head, gma_top,
2640 workload->shadow_ring_buffer_va);
2641 if (ret) {
2642 gvt_err("fail to copy guest ring buffer\n");
2643 return ret;
2644 }
2645 copy_len = gma_top - gma_head;
2646 gma_head = workload->rb_start;
2647 }
2648
2649 /* copy head or start <-> tail */
2650 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2651 gma_head, gma_tail,
2652 workload->shadow_ring_buffer_va + copy_len);
2653 if (ret) {
2654 gvt_err("fail to copy guest ring buffer\n");
2655 return ret;
2656 }
2657 ring->tail += workload->rb_len;
2658 intel_ring_advance(ring);
2659 return 0;
2660 }
2661
2662 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
2663 {
2664 int ret;
2665
2666 ret = shadow_workload_ring_buffer(workload);
2667 if (ret) {
2668 gvt_err("fail to shadow workload ring_buffer\n");
2669 return ret;
2670 }
2671
2672 ret = scan_workload(workload);
2673 if (ret) {
2674 gvt_err("scan workload error\n");
2675 return ret;
2676 }
2677 return 0;
2678 }
2679
2680 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2681 {
2682 int ctx_size = wa_ctx->indirect_ctx.size;
2683 unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2684 struct drm_i915_gem_object *obj;
2685 int ret = 0;
2686 void *map;
2687
2688 obj = i915_gem_object_create(wa_ctx->workload->vgpu->gvt->dev_priv,
2689 roundup(ctx_size + CACHELINE_BYTES,
2690 PAGE_SIZE));
2691 if (IS_ERR(obj))
2692 return PTR_ERR(obj);
2693
2694 /* get the va of the shadow batch buffer */
2695 map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2696 if (IS_ERR(map)) {
2697 gvt_err("failed to vmap shadow indirect ctx\n");
2698 ret = PTR_ERR(map);
2699 goto put_obj;
2700 }
2701
2702 ret = i915_gem_object_set_to_cpu_domain(obj, false);
2703 if (ret) {
2704 gvt_err("failed to set shadow indirect ctx to CPU\n");
2705 goto unmap_src;
2706 }
2707
2708 ret = copy_gma_to_hva(wa_ctx->workload->vgpu,
2709 wa_ctx->workload->vgpu->gtt.ggtt_mm,
2710 guest_gma, guest_gma + ctx_size,
2711 map);
2712 if (ret) {
2713 gvt_err("fail to copy guest indirect ctx\n");
2714 goto unmap_src;
2715 }
2716
2717 wa_ctx->indirect_ctx.obj = obj;
2718 wa_ctx->indirect_ctx.shadow_va = map;
2719 return 0;
2720
2721 unmap_src:
2722 i915_gem_object_unpin_map(obj);
2723 put_obj:
2724 i915_gem_object_put(wa_ctx->indirect_ctx.obj);
2725 return ret;
2726 }
2727
2728 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2729 {
2730 uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2731 unsigned char *bb_start_sva;
2732
2733 per_ctx_start[0] = 0x18800001;
2734 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2735
2736 bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2737 wa_ctx->indirect_ctx.size;
2738
2739 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2740
2741 return 0;
2742 }
2743
2744 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2745 {
2746 int ret;
2747
2748 if (wa_ctx->indirect_ctx.size == 0)
2749 return 0;
2750
2751 ret = shadow_indirect_ctx(wa_ctx);
2752 if (ret) {
2753 gvt_err("fail to shadow indirect ctx\n");
2754 return ret;
2755 }
2756
2757 combine_wa_ctx(wa_ctx);
2758
2759 ret = scan_wa_ctx(wa_ctx);
2760 if (ret) {
2761 gvt_err("scan wa ctx error\n");
2762 return ret;
2763 }
2764
2765 return 0;
2766 }
2767
2768 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2769 unsigned int opcode, int rings)
2770 {
2771 struct cmd_info *info = NULL;
2772 unsigned int ring;
2773
2774 for_each_set_bit(ring, (unsigned long *)&rings, I915_NUM_ENGINES) {
2775 info = find_cmd_entry(gvt, opcode, ring);
2776 if (info)
2777 break;
2778 }
2779 return info;
2780 }
2781
2782 static int init_cmd_table(struct intel_gvt *gvt)
2783 {
2784 int i;
2785 struct cmd_entry *e;
2786 struct cmd_info *info;
2787 unsigned int gen_type;
2788
2789 gen_type = intel_gvt_get_device_type(gvt);
2790
2791 for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2792 if (!(cmd_info[i].devices & gen_type))
2793 continue;
2794
2795 e = kzalloc(sizeof(*e), GFP_KERNEL);
2796 if (!e)
2797 return -ENOMEM;
2798
2799 e->info = &cmd_info[i];
2800 info = find_cmd_entry_any_ring(gvt,
2801 e->info->opcode, e->info->rings);
2802 if (info) {
2803 gvt_err("%s %s duplicated\n", e->info->name,
2804 info->name);
2805 return -EEXIST;
2806 }
2807
2808 INIT_HLIST_NODE(&e->hlist);
2809 add_cmd_entry(gvt, e);
2810 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2811 e->info->name, e->info->opcode, e->info->flag,
2812 e->info->devices, e->info->rings);
2813 }
2814 return 0;
2815 }
2816
2817 static void clean_cmd_table(struct intel_gvt *gvt)
2818 {
2819 struct hlist_node *tmp;
2820 struct cmd_entry *e;
2821 int i;
2822
2823 hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2824 kfree(e);
2825
2826 hash_init(gvt->cmd_table);
2827 }
2828
2829 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2830 {
2831 clean_cmd_table(gvt);
2832 }
2833
2834 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2835 {
2836 int ret;
2837
2838 ret = init_cmd_table(gvt);
2839 if (ret) {
2840 intel_gvt_clean_cmd_parser(gvt);
2841 return ret;
2842 }
2843 return 0;
2844 }
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